TW201104843A - A NAND based NMOS NOR flash memory cell, a NAND based NMOS NOR flash memory array, and a method of forming a NAND based NMOS NOR flash memory array - Google Patents

Abstract

A NOR flash nonvolatile memory device provides the memory cell size and a low current program process of a NAND flash nonvolatile memory device and the fast, asynchronous random access of a NOR flash nonvolatile memory device. The NOR flash nonvolatile memory device has an array of NOR flash nonvolatile memory circuits. Each NOR flash nonvolatile memory circuit includes a plurality of charge retaining transistors serially connected in a NAND string. A drain of a topmost charge retaining transistor is connected to a bit line associated with the serially connected charge retaining transistors and a source of a bottommost charge retaining transistor is connected to a source line associated with the charge retaining transistors. Each control gate of the charge retaining transistors on each row is commonly connected to a word line. The charge retaining transistors are programmed and erased with a Fowler-Nordheim tunneling process.

Description

201104843 l VI. INSTRUCTIONS DESCRIPTION: TECHNICAL FIELD OF THE INVENTION [0001] The present invention relates to a non-volatile memory array structure and operation, and more particularly to a NAND-based NOR flash memory structure and operation [Prior Art] [0002] Non-volatile memory is a well-known technique in the art. Non-volatile memory types include read-only memory (R0M), electronically programmable read-only memory (EPROM), electronically erasable programmable read-only memory (EEpR〇M), NOR flash memory, and NAND Flash memory. Flash memory has become one of the more popular non-volatile memories in applications such as personal digital assistants, cell phones, small laptops and portable computers, recorders, and global search systems. Flash memory has the advantages of high density, small footprint, low cost, and can be repeatedly programmed and erased with a single low voltage. [] The flash memory structure of the driver knows how to store the structure, such as charge storage and charge extraction. In the non-volatile floating gate memory, the charge storage, the charge representing the digital data in the structure is stored on the floating gate of the component. The stored charge changes the threshold voltage of the floating gate memory so that the digital data is stored. However, in the charge extraction structure in the silicon oxynitride (S0N0S) or gold oxynitride (M0N0S) type unit, the charge is taken up by the charge extraction layer between the double insulating layers. In the S0N0S and MONOS components, the charge of the layer is relatively high (KN) compared to silicon nitride (SiNx). [0004] 099113777

Non-volatile memory is divided into two categories: fast random access asynchronous NOR form number Aloi s Page 4 of 133 〇9! 201104843

[0005] 快 Flash memory and slow serial access synchronous NAND flash memory. The currently designed NOR flash memory has multiple external address and data pins and appropriate control signals. One disadvantage of this is that when the memory density is doubled, the addition of an external address pin will cause an increase in the number of external pins required. Conversely, the advantage of NAND flash memory is that it has fewer pins than NOR and has no address input pins. As the density increases, the number of NAND flash memory pins remains the same. As the two mainstream 'NAND and NOR flash memory cell structures in today's production, a one-time charge retention (charge storage or charge extraction) transistor memory cell is used to store one bit of data as a zero load. Thus, it is also commonly referred to as a single-order potential programming unit (SLC). The advantages of NAND and NOR flash memory are that they can be programmed and erased within the system and have a tolerance period of at least 100,000 times. In addition, because the cell size can be expanded south, 'single-chip NAND and NOR flash memory can provide giga megabyte density. For example, the current one-dimensional/single-crystal nand soap cell size is approximately maintained at 4:, 2 τ (λ is the smallest characteristic size in a semiconductor process) and the NOR cell size is approximately 10 λ2. In addition, single-crystal NAND and NOR flash memory can have four multi-potential threshold voltages (VtO) in a single unit, except for the single-stage potential programming unit with two threshold voltages (VtO and Vtl). For Vtl, Vt2, and Vt3), at least two bits may be stored in each cell or two cells may be stored in each transistor. At present, the maximum capacity of a single-chip double-layer polysilicon gate NAND flash memory is 64Gb. In contrast, a two-layer polysilicon gate N〇R flash memory has a 2Gb capacity. NAND flash memory and NOR flash memory between 099113777 Form nickname A0101 Page 5 / 133 pages 0992024278-0 [0006] 201104843 The large gap of the amount is due to the scalability ratio of NAND flash memory cells The N 0 R flash memory unit has excellent scalability. The voltage (Vds) from the drain to the source of a NOR flash memory cell must be 5.0 V to maintain the programming operation of the channel-Hot-Electron (CHE). Conversely, a low-current Fowler-Nordheim wear-through effect programming operation requires only a voltage between its drain and source of 0. 0V. The above results make the size of a single-element/single-crystal NAND cell only half that of a single-element/single-transistor NMOS cell, which makes NAND flash memory suitable for applications that require huge data storage, while NOR flashes. Memory is widely used as a programming code storage memory that requires a small amount of data storage but requires fast and asynchronous random reads. [0007] A dual transistor NOR flash memory cell is formed from two NMOS transistors, the construction of which is equivalent to a single order programming unit. The upper transistor in the transistor NOR cell is a floating gate transistor and the bottom transistor is a commonly used NMOS selective transistor. Only the upper transistor has the ability to store data. The dual transistor NOR flash memory cell has only one transistor to hold data, and in the NOR flash memory cell, each NAND cell corresponds to a select transistor. [0008] U.S. Patent No. 7,263,003 (Edahiro, et al.) describes a dual-cell flash memory using a replica cell array to control the pre-charge/discharge and sense amplifier circuits of the main cell array. [0009] U.S. Patent No. 5,596,523 (Endoh, et al.) provides a section of a NOR-type EEPROM memory cell array. Each two adjacent NOR cells are connected to a corresponding bit line, one of which is a memory cell transistor 099113777 Form No. A0101 Page 6 of 133 Page 0992024278-0 201104843 [0010]

[0011] [0012] The source of the 099113777 and the source of the other-cell transistor are connected in common to the _ bit. The source and drain of the other unit transistors are connected in common to one source line. The source line is provided by a selection transistor. U.S. Patent No. 6,765,825 (Scott) describes a differential NOR memory cell comprising a dual floating gate transistor. The terminal of each transistor is connected to the corresponding differential bit line. The source terminal of the dual transistor is connected to a common current source or sinker. Each control gate terminal is connected to a corresponding word line, which may be the same as or different from the corresponding word line to which the other control terminals are connected. "The floating gate transistor may be a five terminal element" which includes an increase The well terminal, in this case, the group bit line used to program the EEPRGM memory cell is different from the group bit line used to read the EEpR〇M memory cell. When the bungee terminal is connected to the differential read " - * λ ‘ 15 bit line, each well terminal is connected to a corresponding differential programming bit line. U.S. Patent Application No. 2006/0181 925 (Specht, et al.) is an arrangement of non-volatile memory cells in which memory cells are arranged in a row and straight. The source of the memory cell of the first row is the same as the terminal of the non-polar terminal and the wire of the metal surface different from the first source and the terminal of the second straight-line memory transistor. In this way, it is possible to bring the memory transistors in the memory adjacent to each other close to each other. SUMMARY OF THE INVENTION It is an object of the present invention to provide a NOR flash memory that combines the features of small size and low current programming operations of NAND with the features of NOR fast and asynchronous random read operations. In order to achieve the foregoing objectives, an embodiment of a NOR flash memory includes concatenating a form, a nickname A01Q1 % 7 I/* 133 I 0992024278-0 [0013] 201104843 number 'charge holding transistors into a NAND string. 'The pole of the transistor is connected to the string.> The electricity of the S is related to the storage of the transistor: the source of the lowest charge storage transistor is connected to the series of charge storage. The _ source line associated with the transistor. Each of the plurality of charge-preserving transistors in each row is connected to the same word line. The charge-contained transistor is in the - (10) type double well of the -type conductivity well. The first type of conductivity type well is formed within the second type of conductivity type well (the type well). The second type of conductivity type deep well is formed in a -first conductivity type substrate (P type substrate). [0015] The charge-preserving electro-cutter programming operation and the erasing operation are #Fowler_N〇rdheim« effect operating nozzles, which are selected in a purely stored transistor, a selected electrical storage crystal material - single order As the unit performs programming, the voltage of about +15_about +2() shoulder is applied in a gradually increasing manner between the selected charge cell __ gate and the base of the charge storage transistor. The unselected charge-storing transistors are blocked by the application of the unselected electrical charge control and the base between the base and the 0.0V. The size of the circuit layout is approximately four times the smallest feature size of the manufacturing-flash memory circuit process technology. To erase the selected charge storage transistor, a high voltage of approximately + 20. 0V is applied to approximately Between the base of the selected charge storage transistor and the control gate, by applying a bias voltage to the unselected charge holding transistor such that the unselected (four) transistor is controlled between the closed and the base (4) The big money UV, so that the unselected charge storage transistors can be prohibited. 099113777 Form No. A0101 Page 8 of 133 pages 0992024278-0 201104843 [0016] When programming from these single programming units The electric power is saved and stored in the crystal ceremony t-reading - the selected charge is stored in the memory crystal Zhao, the source line is connected to the sub-connection = - electric grinder follows the induction circuit. The gate of the selected electric charge storage electric crystal clock And the voltage of the drain is set to - the voltage source (VDD) The voltage of the gate of all the unselected charge-storing transistors in the charge-storing transistor is set to a first high-read voltage greater than 6.0 V. If the N〇R flash memory circuit is not selected to perform a read operation, the voltage of the control gate of the unselected charge holding transistor in the charge holding transistor is set to the ground reference voltage to turn off the charge storage. The voltage tracking follower circuit is a comparator circuit whose reference terminal is connected to a reference voltage source. The reference voltage source is set at about 2.0 V to distinguish the threshold voltage of the first logic level (〇) from the second logic level ( 1) The threshold voltage. [0017] 读取 When reading from the charge-preserving electrode body that is programmed from the first-order programming unit, the selected charge is stored, and the source line is connected with the voltage of the second one. Inductive circuit. The selected gate of the selected charge storage transistor is set to a high electrical potential of about 4 shoulders. All unselected H voltages in the charge holding transistor are set at a voltage greater than 7.0V. The idleth of the first _Τ4= The electric induction circuit includes a plurality of comparison circuits: reading: the number of threshold voltages representing the data within the body is reduced by -. Each of the reference voltage reference terminals is connected to the group of reference voltage sources. The reference voltage source is set to -voltage 'between the difference between the charge storage voltage and each of the differences. The data represented by the body towel (four) boundary voltage 099113777 form bat number ΑΟίοι 9 I 133 pages 201104843 _ .

[In another embodiment, a flash memory includes an array of flash memory circuits in which the charge-storing transistors of the flash memory circuit are arranged in a straight line and a horizontal row. Each--flash memory circuit includes a plurality of charge-storing transistors connected to the four-string series on a straight line to make at least one of the charge-holding transistors serve as a selective transistor. To avoid current leakage between the charge-storing transistors when the charge-storing transistors are not selected for a read operation. The bottom of the uppermost charge storage transistor in each of the NOR flash memory circuits is connected to a local bit line corresponding to the straight line where the NOR flash memory circuit is located, the local bit line and the straight line parallel. The most bleak, hard-to-charge (4) source in each _ flash (4) circuit is connected to a local source line corresponding to the NOR flash memory path, the local source line and the corresponding bit The lines are parallel. Each of the control gates of the charge-storing transistor on each column is commonly connected to a word line [0019]. The N0R flash memory includes control of the voltage per voltage. The straight line control circuit is coupled to the local bit line and source line corresponding to the straight line of each charge holding transistor, and provides a control signal to the local bit line associated with the straight line of each charge holding transistor (l 〇cal bit 1 i ne) and source line. Each of the status lines is connected to one of a set of global bit lines through a single line selection transistor, and each local source line is connected to a group through a source line selection transistor. One of the source lines of the whole domain. The global bit lines and the global source lines are connected to the straight line voltage control circuit to transmit control signals to the selected local bit lines and the selected local source lines to flash the N99 R099113777 form. No. A0101 Page 10 of 133 pages 0992024278-0 201104843 =: Load save _ perform read operation, edit [0020] Ο NOR flash memory includes - course voltage control circuit. The row voltage control circuit is coupled to the word line corresponding to each of the charge holding transistors and provides a control signal to the word tree associated with each row of charge holding transistors, while the local bits The gates of the line select transistor and the source line select transistor are connected to each local bit line. The row control circuit transfers the control word line in order to read, program, and erase the selected electro-acoustic memory U in the flash memory circuit. The horizontal voltage control circuit also transmits a bit line selection transistor that controls the money frequency selection to select a crystal "selective crystal" to control the bit line and the source line to control the local bit of the direct line voltage (four) circuit object. The source line and the selected source line. [0021] The programming and erasing of the charge-storing transistor relies on the _FQffle pass-through effect. The charge-preserving electron-crystal-selected charge-preserving transistor acts as a single-order potential When the programming unit is programmed, the horizontal voltage control circuit provides a programming voltage applied to the word line between the control gate and the base of the selected NMOS transistor, the programming voltage is approximately + 15.0V. Up to about + 20. 0 V. The horizontal voltage control circuit provides an intermediate voltage less than + 10. 0 V, and an intermediate voltage is applied between the control gate and the base of the unselected charge storage transistor to shield The selected charge holds the transistor. The layout of the NOR flash memory circuit requires that the size of each NOR flash memory circuit be approximately four times the size of the smallest feature of the N〇R flash memory circuit technology. 099113777 Such A selected charge is stored in the storage transistor. Form No. A0101 Page 11 of 133 Crystals 0992024278-0 [0022] 201104843 When the multi-level potential programming unit is programmed, the horizontal voltage control circuit is selected. The control gate of the charge-storing transistor and the base of the charge-storing transistor are applied in an increasing manner—about + 15·(10) to about 0.02 V. The programmed electricity is discarded to the character of the selected charge-preserving transistor. Line: verifying the data of the selected charge-preserving transistor read every time the program voltage is cut-to-high, reaching the front threshold voltage. The unselected transistors in the charge-preserving transistor are applied. The intermediate high voltage between the control gate and the base of the unselected charge storage transistor is less than + 10. [0023] To erase the selected charge storage transistor, the rank voltage control circuit applies a An erase voltage of about +15.0V to about +20.0V of the positive electrode to the selected electrode between the base of the storage transistor and the control room. The row voltage control circuit saves the electrolysis in the unselected charge. Applying a bias voltage such that there is an approximately 〇. 〇v voltage between the control gate and the base to shield the charge from holding the unselected transistor in the transistor? 1: ν :; r: [0024] NOR flash memory In the charge-preserving transistor of the body circuit, when the selected charge-preserving transistor is used as the Qin single-order potential programming unit for reading operation, the source line is connected to a voltage following sensing circuit in the straight-line voltage control circuit. The horizontal voltage control circuit sets the word line of the selected charge holding transistor, that is, the voltage of the voltage source (VDD) of the control gate to a voltage of about 1.8 V or about 3.0 V. The course voltage control starts local. The bit line selection transistor is connected to the global bit line and the local bit line corresponding to the selected charge holding transistor. Thereafter, the straight-through voltage control circuit sets the voltage of the global bit line, which is also the voltage of the local bit line connected to the drain of the selected charge storage transistor. 099113777 Form No. A0101 Page 12 of 133 Page 0992024278- 0 201104843 Voltage to voltage source (VDD) 'The voltage of this voltage source is about ν8ν or about 3·. The horizontal electric circuit setting circuit sets the word line and the voltage of the control gate of all unselected electric phase storage transistors in the charge storage transistor that is selected to be equal to or greater than 6. 〇ν雷= Read Μ. The voltage chasing circuit is a comparison circuit within the straight-line voltage control, and the JL — ^ reference is connected to the reference voltage source Ο [0025] Ο [0026]: the voltage of the reference power source is set to a large (10) to The difference represents the critical voltage of the criticality = level (8) and the four electrical repetitions representing the second logic level (1). The horizontal voltage (four) circuit sets the word recognition power, and also == selected _ flash memory circuit charge storage transistor does not select the charge to save the electric ink between the control of the electric crystal ship as the ground reference power' Thereby the charge holding transistor is turned off. 》

F reads the charge stored in the multi-level potential programming unit. When the crystal is selected - the charge is stored in the transistor, the source line is connected to the - voltage follower sensing circuit. The gate and the selected pole of the charge storage transistor are set to a moderately high voltage of approximately 4 ()V. The voltage of the gate of all unselected charge-storing transistors in the charge-storing transistor is set to a second read voltage greater than 7.. The voltage follower sensing circuit has a plurality of comparison circuits equal to the number of threshold voltages representing data stored in the charge storage transistor minus one. The reference terminal of each comparison circuit is connected to one of the reference voltage source groups. The reference voltage is set to a voltage between each of the threshold voltages to distinguish the data in the presence of the charge storage electromorphic threshold voltage. In another embodiment, the method of forming a flash memory includes: 099113777 Form No. A0101 Page 13 of 133 Page 0992024278-0 201104843 k for a substrate; an array of NOR flash memory circuits is placed on the substrate 'and the charge storage transistors of the NOR flash memory circuit are arranged Align and go straight. Each of the N 0 R flash memory circuits is formed by serially connecting charge-holding transistors on a line to a NAND string such that at least one of the charge-holding transistors acts as a select gate transistor To avoid current leakage between the charge-holding transistors when the charge-storing transistors are not selected for a read operation. The drain of the uppermost charge storage transistor in each N〇R flash memory circuit is connected to a local bit line corresponding to the straight line where the NOR flash memory circuit is located, the local bit line and the Straight line parallel. The source of the lowermost charge storage transistor in each N〇R flash memory circuit is connected to a local Zhurong 相对 corresponding to the NOR flash memory circuit, the local source line and the corresponding bit The lines are parallel. Each control gate of the complex charge-storing transistor on each row is connected in common to a word line. [0027] A method of forming an n 〇 R flash memory includes forming a continuous line voltage control circuit. The straight line voltage control circuit is operative to provide a pull signal to a local bit line and source line corresponding to a straight line of each charge holding transistor. Each local bit line is connected to one of the global bit line groups through a one-element selection transistor, and each local source line is connected to the global source line through a source line selection transistor. One of the groups. To read, program, and erase the selected charge-storing transistor within the NOR flash memory circuit, the global bit line and the global source line are connected to the straight-line voltage control circuit to transmit the control signal to the selected The local bit line and the selected local source line. [0028] A method of forming a NOR flash memory includes forming a horizontal voltage control circuit 099113777 Form No. A0101 Page 14 / 133 pages 0992024278-0 201104843 〇 ^ °Haiyang electric control circuit is used to provide control signals to And each of the electricity: the word line corresponding to the save transistor _ course and the local bit line connected to each local 曰疋 line select the idle pole of the transistor and the source line selection. To read, program, and erase the selected charge holding transistor within the NOR flash memory circuit, the row control circuit transmits a control signal to word line 70. The row voltage control circuit also transmits a control signal to the selected bit line to the transistor (4) to the source line of the source line to transfer the bit line and source line control signals from the straight line voltage control circuit. To the selected local bit line and the selected local source line 〇 [0029] and the isoelectric memory transistor programming operation and erase operation rely on a Fawler-Moi'dheim tunneling effect to complete the β When the selected charge-storing transistor in the charge-storing transistor group is programmed as a single-order potential programming unit, the course voltage control circuit provides a voltage of about 15.0 V to about 2 〇·0 V to the word line. This voltage is applied between the control gate and the base of the selected charge storage electrical body. The series voltage control circuit provides - intermediate power less than + 10. 〇 ν 'the intermediate voltage is applied between the control gate and the base region of the unselected electric 4 cast transistor to shield the unselected The charge holds the transistor. The size of the NOR flash memory circuit layout is approximately four times the smallest feature size of the N〇R fast memory system process technology. [0030] When the charge-preserving transistor is programmed as a multi-level potential programming unit, the row voltage control circuit controls the gate and charge-storing transistor of the selected charge-holding transistor The bases are applied in a gradually increasing manner _about + 15. just about 099113777 Form No. A0101 Page 15 / 133 pages 0992024278-0 201104843 The compilation of the levy V (four) pressure to the word of Wei _ electricity storage (four) Yuan line. The data of the selected selected charge holding transistor is verified every time the programming voltage is gradually increased, until the correct threshold voltage is reached. The non-selected transistors of the charge holding transistors t are masked by an intermediate high voltage applied between the control idle and base of the unselected charge storage transistors of less than +10.0V. [0032] To erase the selected charge holding transistor, the course electrical control circuit applies a positive erase voltage of approximately + 15.0V to approximately +20·0V to the selected charge storage clock. Between the base and the control gate. The row voltage control circuit also applies a bias on the unselected charge-storing transistor so that there is a voltage of "G. 〇v" between the control gate and the base, so that the shielded electricity saves the transistor from being selected. 'Electrocrystal: body. When reading the charge-holding transistor of the NOR flash memory circuit as a single-stage potential programming unit in the charge-holding transistor, the source line is connected to the straight-line voltage control circuit. A voltage follower sensing circuit. The horizontal voltage control circuit sets the word line of the selected charge holding transistor, that is, the voltage of the control gate is about 1.8 V or a voltage source (VDD) of about 3, 0 V. The voltage control circuit activates a local bit line selection transistor to connect the global bit line corresponding to the selected charge holding transistor to the local bit line. Thereafter, the straight line voltage control circuit sets the global The voltage of the bit line is connected to the voltage of the local bit line of the drain of the selected charge storage transistor to the voltage source (VDD), which is about 1.8 V or about 3.0 V. Voltage The circuit also sets the word line and the selected N 0 R flash memory circuit within the charge storage transistor. All of the unselected charge holding transistors in the control transistor are turned on. 099113777 Form No. A0101 Page 16 of 133 Page 0992024278-0 201104843 Voltage to a greater than 6. 〇ν Road sets the power of the word line. The horizontal voltage control powers the charge to save the crystal. The voltage between the intersystems of the selected bile flash memory circuit is grounded. 2 Select the charge to hold the transistor's control (10) reference voltage to off: follow the induction circuit for the straight-line voltage control two * ratio: 'it has - the reference terminal is connected to the reference „ source=two voltage source voltage is set to about 20ν , to " test level (〇) threshold voltage and. < Table - Logical water table - the threshold voltage of the first logic level (1). [0033] 读取 Reading the charge-storing transistor to program a single-crystal lens with multiple-order potentials. All unselected traits w are saved to - more than 7 stages. The voltage path of the first = electro-crystal _ pole includes plural Comparing the circuit, which represents a critical __ directory of the data, a reference end connection - reference _ is in the middle ... the parameter is set to a voltage between each - critical level to distinguish = The data represented by the critical electric hair stored in the charge storage transistor. [Embodiment] [0034] FIG. 1A is a top view of a _S N flash flash transistor ○ 0 is a cross-sectional view of the 浮动 快 快 浮动 。 。 。 。 。 。 。 。 。 。 。). Figure lc is a schematic diagram of the _S NAND fast inter-floating transistor. In the technical structure of the NAND cell string formed by the _s NA_ floating gate transistor 10, the _S N class flash floating gate transistor 的) of the pole 15^ 099113777 Form No. A0101 Page 17 of 133 0992024278-0 201104843 Source 20 does not require contacts. In a conventional NAND cell string, the uppermost transistor is connected to a top select transistor, and the lowest layer transistor is connected to a bottom select transistor. The tip of the top select transistor and the source of the bottom select transistor are connected to the bit line (Bitline, BL) and the source line. The structure of this conventional NAND cell string is such that the size of the N Μ 0 S N A N D flash floating gate transistor 1 是 is the smallest in the fast memory structure. [0035] The NMOS NAND flash floating gate transistor 10 is formed on the uppermost layer of the p-type substrate (psuB) 40. An N-profile oblique diffusion forms a deep N-well (DNW) 35 on the surface of the p-type baffle. Then a p-type material diffuses in the surface of the deep N well 35 to form a P well ^0 (generally referred to as triple p-well TPW). However, a broken type of material diffuses into the surface layer of the well 3 to form a dipole (D) 15 and a source (S) 20. A first polycrystalline layer forms a floating gate 45 above the base between the P well 30 and the drain 15 and the source 20. A second polycrystalline layer is formed over the floating gate 45 to form a control gate (G) 25 of the NMOS NAND flash floating gate transistor 10. The gate length of the NMOS NAND flash floating gate transistor 1 汲 is the channel of the base of the P well 30 between the drain 丨 5 and the source 20. The channel width of the NMOS NAND flash floating gate transistor 10 is determined by the width of the n-diffusion of the drain 15 and source 20. The NMOS NAND flash floating gate transistor has a typical cell size of about 4; 12, where the X axis is 2λ long and the Y axis is 2λ. Dimensions Lambda (again) is the smallest dimension that can achieve geometrical properties within the process. [0036] The floating gate 45 stores an electron charge to change the threshold voltage of the NMOS NAND flash floating gate transistor 10. The P-type substrate 40 is connected to a ground reference voltage source (GND) in operation. The deep N well 35 is connected to a voltage source (yj) D). 099113777 Form No. A0101 Page 18 of 133 0992024278-0 201104843 In the current design of NMOS NAND flash floating gate transistor 10, the supply voltage is 1.3V or 3.0V. The triple P well 30 is connected to a ground reference voltage source during normal read operations. [0037] The NMOS NAND flash floating gate transistors 1 are arranged in a row and a straight line in the array. The second polysilicon layer, ie, the control gate 25 of the NMOS NAND flash floating gate transistor 10, extends to form a word line that connects each NMOS NAND flash floating gate transistor 1 in the array of the array. Hey. [0038] A tunnel oxide 50 is painfully formed between the upper portion of the channel region 32 between the drain 15 and the source 20 and the floating gate 45 - the thickness of the tunnel oxide 50 is 100A. Electronic programming in fowier-Nprdheiip and ? 〇*161·-^^(11^111 channel erasing period 1^ soil ^^^ _'(^161*_ 5 · -3⁄4 馨参馨.Iff

The Nordheim channel wipe & is in the conventional HAND's work (the stored electrons are ejected from the floating gate 45 and pass through the tunnel oxide 5〇 to the cell channel region 32 and finally into the triple P well 30. [0039] Figure 1D is a single transistor floating sluice 0 SNA rib: double-voltage voltage distribution table of the programming potential and erase potential of the firing cell. Floating gate 45 after the erase operation, the electron charge is reduced so that the NMOS NAND flash floating gate The threshold voltage of the crystal 10 is lowered. Under normal conditions, the threshold voltage of the NMOS NAND flash floating gate transistor 10 after being erased is about -2.0 V. In contrast, during the Fowler-Nordheim channel programming process. The electrons are attracted to the floating gate 45, so that the threshold voltage of the NMOS NAND flash floating gate transistor 10 is increased to about +2.0 V. Conventionally, the threshold voltage (VtO) of about -2.0 V is erased after the erase operation. The logical data value "0", which is designated as the logical data value " Γ , the threshold voltage (Vtl) after programming + 2. 0V is designated as 0. 099113777 Form No. A0101 Page 19 / 133 pages 0992024278-0 201104843 [0040] The removal of electrons is more difficult to control, so it’s a while In the F〇wler_ Nordheim channel erase process, the removal of the electron charge from the floating gate is generally performed collectively in units of one page (512B) or one sector (64〇) and the threshold voltage (VtO) is erased. In contrast, the programming operation injects electrons into the floating gate in a controlled manner and performs on a one-bit one-bit basis (through the bit line connected to the drain 15 once, one NMOS NAND) The flash floating gate transistor is executed), so that the distribution of the threshold voltage (vti) is less than the distribution of the erase threshold voltage (Vt〇) and is controlled within 0.5 V. Since each unit is stored The widened threshold voltage (Vt〇) of the erased state and the narrowly distributed threshold voltage (vti) of the programmed state are two distinct threshold voltages, and only one or two of the s Nand flash slamming gate transistors 10 are stored. The bit-free bit is called a single-order potential programming or SLC (Single-Level-Cell); NMOS NAND flash floating gate transistor 1〇 stores a cone of data, which is called a unit. Single-single transistor (single_bit_〇ne_transi^〇r lblT NM0S NAND Flash Floating Gate: Unit [0041] Figure 1E is a four-voltage voltage distribution table with a erase potential and two programming potentials for a single transistor floating gate NM〇s NAND flash cell. In the technology, by changing the programming conditions, according to NM〇s “the number of floating secret charges in the rib flash floating gate transistor 1G can form more than two threshold voltages, generally refers to the multi-step of the NMOS NAND flash floating gate unit. Potential programming or MLC (multi-level cell). In this embodiment, there are four threshold voltages that can be programmed in the NM〇s NAND flash floating gate transistor 10. The most negative threshold voltage Vt0 is the erase voltage, which has an intermediate value of -2·〇ν for storing a logical data value "u,,. Since the most negative 099113777 form number A0101 page 20 / 133 pages 0992024278-0 201104843 The threshold voltage vto of the bungee is the only erased state, that is, the electron charge is removed, so the threshold voltage vto of the most negative electrode has the widest distribution among the threshold voltages (VtO, Vtl, Vt2 and Vt3). The threshold voltages (Vtl, Vt2, and Vt3) add electrons to the floating gate in a controlled manner from the erased state. They have a relatively narrow distribution in the programmed state. The three positive, narrow programming threshold voltages are sufficiently separated. Detected. In this embodiment, the first Vtl of the three threshold voltages has a normal value of approximately +1.0V for storing a logical data value of "10". The second of the three threshold voltages Each Vt2 has a standard value of approximately +2.00V for storing a logical data value of "0". The third Vt3 of the three threshold voltages has a standard value of approximately +3.00 V for storing a logical data value "00". Because each NMOS NAND flash floating gate transistor 10 stores four distinct threshold voltage states, each NMOS NAND flash floating gate transistor 10 also stores two binary data bits and is referred to as a two-bit binary. Single transistor NMOS NAND flash unit (2b/lT). [0042] The standard values of the threshold voltages (vtO, Vtl 〇 , Vt2, and Vt3) of the NMOS NAND flash floating gate transistor 10 may vary by more than i. 〇v in different designs. The distribution between the data values of the two bits and the state of the four threshold voltages can also vary between different NMOS NAND flash floating gate cell designs. For example, some NMOS NAND flash floating gate cell designs assign a logical data value of "01" to a first positive threshold voltage Vtl, a logical data value of "10" to a second positive threshold voltage Vt2, or a negative value to erase a threshold voltage. Vto can be assigned to the logical data value "00", and the third positive threshold voltage Vt3 can be assigned to the logical data value "11". 2A is a top plan view of an NMOS NOR flash floating gate transistor 11A. Figure 099113777 Form No. A0101 Page 21 of 133 0992024278-0 201104843 ^ This is a cross-sectional view of the closed 05 1^01? flash floating gate transistor 11〇. 20 is a schematic diagram of the NMOS NOR flash floating gate transistor 110. The NMOS NOR flash floating gate transistor 11 is formed in the uppermost surface layer of the triple p-type substrate 14A to be formed in a triple P well. An N-type material diffuses into the surface layer of the P-type substrate 140 to form a deep N well 135. A P-type material is then diffused into the surface of the deep N-well 135 to form a P-well 130 (generally referred to as a triple-P well). The N-type material is then diffused into the surface of the P-well 130 to form a drain (D) 115 and a self-aligned source (S) 120. The first polysilicon layer forms a floating gate 145 over the P well 130, above the base between the drain 115 and the source 120. A second polysilicon layer :::::: __ ::. ' : ' is formed over the floating gate 145 to form a control gate (G) 125 of the NMOS NOR flash floating gate transistor 11 . The self-aligned source 120 is self-aligned between the adjacent two handles of the two control gates 125 of the two NMOS NOR flash floating gate transistors 110. The self-aligned source 120 is generally used to reduce the pitch of the source line of the NMOS NOR flash floating gate transistor 110. [0044] The gate length of the NMOS NOR flash floating gate crystal game is equal to that of the p well. The channel region 132 of the base between the drain 115 and the source 120. The channel width of the NMOS f, .. ..... ί β NOR flash floating gate transistor 11 0 is determined by the width of the drain diffusion of the drain π 5 and the source 120. The NMOS NOR flash floating gate transistor 110 has a typical cell size of about 10 and 2, wherein the X-axis length is 2. 5λ and the x-axis length is 4 λ. [0045] The floating gate 145 stores electronic charge to change the threshold voltage of the NMOS NOR flash floating gate transistor 110. The P-type substrate 140 is operatively connected to a ground reference voltage source (GND). Deep N well 135 is connected to the voltage source (VDD) during read and program operations. 'Right' its voltage in Fowler-Nordheim channel eraser 099113777 Form No. A0101 Page 22 of 133 page 0992024278-0 201104843 + 10V or so. In the current design of the NMOS NOR, the power supply voltage is 1. 3V or 3. 0V. The triple p well 130 is connected to the ground reference voltage during normal read and program operations, however, its voltage during the erase operation is approximately +10V. In other words, during the Fowler-Nordheim channel erase operation, the deep n well 135 and the = heavy P well 130 have the same bias voltage 'which is approximately +' to avoid P/ between the deep n well 135 and the triple P well 130. Forward leakage current of the N node. [0046] NMOS NMOS NOR flash floating gate transistors 11 are arranged in a matrix in a row and straight. The second polycrystalline layer, i.e., the control gate 125 of the _s N0R flash floating inter-cell transistor, extends to form a word line that is connected to each of the -_S臓 flashes on the column of the array [0047]

A channel oxide 15 is formed between the channel region i32 between the secret 115 and the source 12 and the floating gate 145. The warmth oxide 15 〇-like thickness is 100 A. The electron charge passes through the accompanying oxide (10) during the high-cost channel _ sub-programming process and the low-power _FQWlendheim_ erase process. In conventional dirty operation, the F〇wWheim channel erase operation ejects female electrons from the axis _5 through the tunnel oxide 150 to the cell channel region 132 and finally into the triple 1 > well 130. 0伏。 [0048] 099113777 after the erase operation, stored in the floating gate 145 (four) sub-charge reduction caused by the NM 〇 S_ flash floating gate transistor transistor's first critical tilt vt0) reduced to about less than 2. 5V. In contrast, ^ π under 'in the channel hot electron programming operation, electrons are drawn into the floating gate 14 and (7)' so that NM〇s Ν〇Ι ^ ^ flash floating gate transistor 11 〇 second critical 厐 I 0伏。 The pressure (vtl) is set to be greater than about 4. 0V. The narrow distribution of the -^ & boundary voltage (Vt0) and the second threshold voltage Utl) in the programmed state are set to the form number_1 page 23/133 pages 0992024278-0 201104843 positive pole to avoid any mis-reading operation caused by the NMOS NOR flash floating gate transistor 11〇 having the negative voltage of the negative pole. 2D is a dual threshold voltage distribution table of a single transistor floating gate NM〇s N〇R flash cell having a single-order programming potential. [0049] FIG. After the erase gate 145 is erased, the electron charge is reduced such that the threshold voltage of the NMOS NOR flash floating gate transistor 11 降低 is lowered. Under normal conditions, the maximum value of the threshold voltage of the N Μ 0 S N 0 R flash floating gate transistor 110 after being erased is approximately + 2. 5V. In contrast, in the channel hot electron programming, electrons are drawn into the floating gate 145' so that the threshold voltage of the NMOS NOR flash floating gate transistor ι10 is increased to at least about +4.00 V. Conventionally, the threshold voltage (VtO) of approximately +2.5V after the erase operation is specified as the logical value 丨 "丨,,, the threshold voltage of + 4.0V after the programming operation: < VU > is designated as logic The data value is “0.” The same as the NMOS NAND flash floating gate transistor, the NMOS NOR flash floating gate transistor that stores the unit metadata is called the single-element single-transistor NMOS NOR flash floating gate unit. (iblT) [0050] FIG. 2 shows four threshold voltage distribution tables of a single transistor floating gate NMOS NOR flash cell having an erase potential and three .program potentials. In the prior art, By varying the programming conditions and according to the amount of charge on the floating gate 14 5 of the NMOS NOR flash floating gate transistor 110, more than two threshold voltages can be formed, which is generally referred to as an NMOS NOR flash floating gate unit. Potential programming or multi-step potential programming unit. In this embodiment, there are four threshold voltages that can be programmed in the NMOS NOR flash floating idler 110. The minimum positive width distribution threshold voltage Vt0 is the erase voltage, which has a maximum value. + 2· 5V for storing a logic According to the value "u". The other three positive polarity narrow programming threshold voltages are sufficiently separated to allow the correct 099113777 form number Α0101 page 24 / total 133 page 0992024278-0 201104843 heart detection. In this embodiment, three critical The first Vtl of the voltage has a standard value of approximately +3.5 V to store a logical data value of "10". The second of the three threshold voltages Vt2 has a standard value of approximately +4.5V for storage. A logical data value of "01". The third Vt3 of the three threshold voltages has a standard value of approximately +5.5 V to store a logical data value of "00". Since each NMOS NOR flashes the floating gate transistor 110 Four distinct positive threshold voltage states are stored. Each NMOS NOR flash floating gate transistor 110 stores two binary data bits, so it is called a dual-bit single-crystal NMOS NOR flash unit (2b). /lT) The standard values of the threshold voltages Vtl and Vt2 of the NMOS NOR flash floating inter-cell transistor 110 may exceed i. 0W in different designs: variation '. The standard values of the threshold voltages VtO and Vt3 may have a wider value. The distribution of electric power. For example, The voltage of the fourth threshold voltage Vt3 may have a wider distribution, but it must be greater than about 4.5 V to ensure that the NMOS NOR floats rapidly. 1 i 0 in a non-conducting s I state. As mentioned above, the NMOS NAND flash floating il unit corresponds to the two-bit number of the four threshold voltage states: the distribution of values can also be fast in different NMOS NORs Flash floating gate unit design changes. [0052] wIntel StrataFlash (Memory Technology Overview), published by Atwood, Intel Technical Journal, Volume 2, Q4 1997, wamv. intei.com, April 23, 2007, Intel Strst^F 13>sh( Memory Technology De — velopment and Implementation”, Fazio et al., Intel Technical Journal, Vol. 1, No. 2, Q4 1997, www.intel.com 'April 21, 2009, ETOX (Flash 099113777 Form No. A0101, 25th Page / Total 133 pages 0992024278-0 201104843

Memory Technology: Scaling and Integration Challenges", Fazio et al., Intel Technical Journal, Vol. 6, No. 2, May 2002 'www.intel.com, April 21, 2009, discusses a floating gate ET0X (flash memory) The transistor has a structure to form an NMOS NOR flash cell as shown in Figures 3A-3E. Figure 3A is a top view of a double crystal body floating gate NMOS NOR flash cell. Figure 3B is the double transistor floating gate NMOS. A cross-sectional view of the NOR flash cell. Figure 2C is a schematic diagram of the dual transistor floating gate NMOS NOR flash cell. The dual transistor floating gate NMOS NOR flash cell 210 is formed in the uppermost surface layer of the p-type substrate 240. The type of material diffuses into the surface layer of the p-type substrate 24A to form double floating gate transistors 205a, 205t> fishing rod (D) sides 15a, 215b and self-aligned source (S, SAS) 22Q, self-aligned The source (s) 220 is shared by the double floating gate transistors 205a and 2〇5b. A first polysilicon layer is at the base 23 between the drains 215a and 215b and the self-aligned source 22〇 (^ and Floating gates 245a and 245b are formed over 230b. A second polysilicon layer is in floating closures 245a and 245b The square forms a double _ eye crystal 2〇5& and 2〇51) control rooms (G) 225a and 225b. The self-aligned source 220 in the double floating f-1 transistors 205a and 205b two control gates 225a and Self-aligned between two adjacent second polycrystalline layers in 225b, self-aligned source 220 is commonly used for dual transistor floating gates 2〇53 and 2〇51) to reduce the source line [0054] Each of the poles 215a and 215b has a metal contact 250a and 250b, respectively. The two metal contacts 250a and 25B are commonly connected to a metal bit line 255. FIG. 3D is the double power. Crystal floating gate NM〇s N〇R flash unit 2丨〇 has a 099113777 Form No. A0101 Page 26 of 133 Page 0992024278-0 Double-threshold voltage distribution table for single-order programming potential. Floating gate 245 after erase operation The electron charge is reduced, causing the threshold voltages of the dual floating gate transistors 205a and 205b to decrease. Conversely, during channel hot electron programming, electrons are drawn into the floating gates 245a and 245b such that the threshold voltages of the dual floating gate transistors 205a and 205b Increased. Conventionally, the threshold voltage (VtO) after erasing is specified as logic According to the value "1", the programmed threshold voltage (Vtl) is designated as a logical data value. The dual floating gate transistors 205a and 205b store two bits of data, which is called a two-bit dual-crystal NMOS NOR flash floating. Gate unit (2b2T). Figure 3E is a four threshold voltage distribution table for a dual transistor floating gate NMOS NOR flash cell 210 having an erase potential and three programming potentials. In the prior art, by changing the programming conditions and according to the amount of charge on the floating gate 245 in the double transistor floating gate NMOS NOR flash unit 210, more than two threshold voltages can be formed, generally referred to as a double crystal floating gate. Multi-level potential programming or multi-order potential programming unit of NMOS NOR flash unit 210. In this embodiment, there are four threshold voltages that can be programmed in the dual floating gate transistors 205a and 205b. The minimum positive threshold voltage VtO is the erase voltage for storing a logic data value of "1". The other three positive programming The threshold voltage is sufficiently separated in order to allow correct detection. In this embodiment, the first voltage Vtl of the three threshold voltages stores a logical data value "10". The second voltage Vt2 of the three threshold voltages stores one. The logical data value "01". The third voltage Vt3 of the three threshold voltages stores a logical data value "〇〇" ^ Since each dual transistor floating gate NMOS NOR flash unit 210 stores four distinct threshold voltages State, each double crystal floating gate NMOS NOR flash unit 210 stores a binary form number A0101 page 27 / 133 pages 201104843 bit data double bit, so it is called double bit single crystal NM0S N0R flash Unit (2b/lT) [0056] The standard values of the threshold voltages vu and Vt2 of the double transistor floating gate _〇5 Ν〇_flash unit 21〇 may also vary in different designs. The criteria for the threshold voltages VtO and Vt3 Value can have Wide threshold voltage distribution. The distribution of the two-bit data values corresponding to the four threshold voltage states of the NMOS NAND flash floating gate unit as described above can also vary between different NMOS NOR flash floating gate unit designs. 4A is a schematic diagram of an NM0S n〇R flash memory unit 4〇〇 of the present invention. FIGS. 4B-1 and 4C-1 are top views of an NMOS NOR flash memory unit 4〇〇. FIG. 2 and 4C-2 are cross-sectional views of the NMOS NOR flash memory cell unit 4A. The floating gate type NMOS NOR flash memory cell unit 4 is formed on the uppermost surface layer of the p-type substrate 440. An n-type material is absent. Dispersed into the surface layer of the p-type substrate 440 to form a deep n-well 435. Then, a p-type material diffuses into the surface layer of the deep N-well 435 to form a p-well 430 (generally referred to as a triple-p well). Then 'N The type of material diffuses into the surface layer of the P well 430 to form the drain (D) 415 of the NM〇s NAND flash floating gate transistor 405a, the source and self-aligned source of the NMOS NAND flash floating gate transistor 405b. Pole/dipole (S/D) 420. Source/drain 420 is the source of NMOS NAND flash floating gate transistor 405a and NMOS NAND flash floating The drain of the gate transistor 4〇5b. The first polysilicon layer is at the drain 415 and the source 420 of the NMOS NAND flash floating gate transistor 405a of the P well 430 and the NMOS NAND flash floating gate transistor 40 Floating gates 445a and 445b are formed above the base between the 5b 0 and the source 4 2 2 of 5 b. The second polysilicon layer forms NMOS NAND flash floating gate transistors 405a and 099113777 over floating gates 445a and 445b. Form No. A0101 Page 28 of 133 pages 0992024278-0 201104843 405b Control Gates (G) 425a and 425b » The self-aligned source/drain 420 is self-aligned between the second polysilicon layers adjacent to the two control gates 425a and 425b of the NMOS NAND flash floating gate transistors 405a and 405b. Self-aligned source 420 is commonly used for NMOS NAND flash floating gate transistors 405a and 405b to reduce the pitch of the source lines. [0058] The gate length of the NMOS NAND flash floating gate transistors 405a and 405b is the drain 415 and the source 4 2 0 and the N Μ 0 SNAND of the NMOS NAND flash floating gate transistor 405a in the P well 430. The channel of the base between the drain 420 and the source 422 of the floating floating gate transistor 4 0 5 b. The channel width of the NMOS NAND flash floating gate transistors 405a and 405b is determined by the width of the drain 415, the source 422, and the source/drain 420 N diffusion. Double crystal: Body: NM0S NOR Fast flash memory unit 400 The general unit size is between 2, 12 and approximately 14 λ 2 . Therefore, the effective size of a one-dimensional NOR unit is about 6 and 2. The effective size (6 λ2) of the one-bit NOR cell is slightly larger than the size of a NAND cell of the prior art. However, the effective size of the one-dimensional nor cell is much smaller than the conventional n〇R cell size (1 into 2) of semiconductor process technology greater than 50 nm. Due to the expansion factor of the semiconductor process less than 5〇nm, the structure size of the aforementioned NOR cell is expected to increase to 15 λ 2 ^ The effective unit cell/single transistor size of the NMOS NOR flash memory cell unit 4 remains approximately 6 The effective unit size of 2 is unchanged. The constant cell size is due to its scalability being the same as that of the conventional NMOS NAND flash memory cell. Floating gates 445a and 445b store electron charges to change the threshold voltage of NM〇s NANI) flash floating gate transistors 405a and 405b, respectively. In all such operations as read, program, and erase, the p-type substrate 44 is always connected. 099113777 Form No. A0101 Page 29 of 133 0992024278-0 [0059] 201104843 Connected to ground reference (GND). Deep N is connected to the supply voltage (_) during read operations and programming operations. However, its voltage at the F〇wier_ N〇rdheim channel erase operation is approximately +20V. In the current design of the _S NOR flash memory cell unit 4, the ink source is 1.8V or 3.0V. The same as the bias condition of the deep N well, the triple p well 43 is connected to the reduced reference voltage source during the normal read transition and the braided wipe, but the voltage connected in the Fowler-Nordheim channel erase operation is approximately + 20V. [0062] 099113777 NMOS NAND flash floating closed crystals 4〇50〇4〇5b are arranged in a straight row and a row in their array - a second polysilicon layer is off (10) NAND flash floating gate The control closures 425a and 425b of the crystals 405a and 405b extend to form a sub-element line that is connected to each of the nm 〇S NAND flash floating gate transistors 4〇5a and 405b on a column in the array. A tunnel oxide is in the NMOS N AND flash floating gate transistor 4〇5a, the drain 415 and the source 4 2 0 and the NM:0 SNAND fast floating gate transistor 405b, the pole 420 and the source 42: 3⁄4^ It is formed between the upper side of the 'Using' areas 432a and 432b and the lower side of the floating gates 445a and 445b. The tunnel oxide is typically 100 A thick. During the Fowler-Nordheim channel programming operation and erase operation, electron charges flow through the tunnel oxide. In conventional NOR operation, the Fowler-Nordheim channel erase operation ejects stored electrons from floating gates 445a and 445b and through the associated oxide to cell channel regions 432a and 432b, and finally into triple P well 430. After the erase operation, the reduced electron charge stored in the floating gates 445a and 445b causes the first threshold voltage (VtO) of the NMOS NAND flash floating gate transistors 405a and 405b to decrease. In contrast, in a Fowler-form number A0101, page 30 / 133 pages 0992024278 201104843

During the Nordheim channel programming operation, electrons are drawn into the floating gates .445a and 445b such that the second threshold voltage level (Vtl) of the NMOS NAND flash floating gate transistors 405a and 405b is set to a relatively high voltage. [0063] Ο

5A-5E are top plan views of line connections of a portion of an array formed by a series connection of a dual transistor floating gate NMOS NOR flash cell. The portion includes four horizontal double crystal NMOS NOR flash memory cells 400 and twelve inline dual transistor NMOS NOR flash memory cells 400, or eight horizontal NMOS NAND flash floating gate transistors 405a and 405b . Each of the NMOS NOR flash memory cells 400 has an N+ diffusion dipole 415, a source/drain 420, and a source 422 as shown in FIGS. 4A, 4B-1, 4B-2, 4C-1, and 4C-2. Control blocks 425a and 4251) are connected to word lines WL0 450a and WL1 450b. The bit lines 455a and 455b and the source lines 460a and 460b are formed as the first layer metal (455a and 460b) or the second layer metal (455b and 460a) of Figs. 4B-2 and 4C-2. The bit lines 455a and 455b pass through the via holes 457a and 457b and the NMOS NAND ·"" I iji _ .- ., . . . . . . . . . . . . . . . . . . 5 y :... The drain 415 of the flash floating gate transistor 405a is connected. The source line 460a ϋ; : 1 · ; ί : Ψ · · 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 In Figure 5B, the connection of the local Metal 1 bit line to the local Metal 2 bit line and the connection of the local Metal 1 source line to the local Metal 2 source line are via vias (Vial). In Figure 5C, the connection between the local Metal 2 bit line of the next layer to the local Metal 3 bit line and the connection of the local Metal 2 source line to the local Metal 3 source line is through the via (VIA2). ) achieved. In Figure 5D, the connection of the local Metal 3 bit line of the next layer to the local Metal 4 bit line and the Metal 3 source line connection of this 099113777 Form No. A0101 Page 31 / 133 page 0992024278-0 201104843 The connection to the local Metal 4 source line is via the via (VIA3); in Figure 5E, the next layer of the local Metal 4 bit line is connected to the local Metal 5 bit line and the local Metal 4 source line to the local "1 ^ 1 5 source line connection through the via (VIA4). Twelve local bit lines 455a, 455b and twelve local source lines 460a, 46 The matrix of the NMOS NOR flash memory cell 400 of 〇i) can be successfully connected using only five layers of metal with an effective cell size of approximately 6 λ 2. Each global bit line and each global domain The source lines are shared by the two local bit lines 455a and 455b and the local source lines 460a and 460b, respectively. [0065] In the structure depicted in Figures 5A-5E, there are five layers of gold ridge lines generated. A unit is constructed such that the effective size of a unit cell transistor 〇R unit is approximately 6 λ2. The spacing between the lines may be larger in the horizontal or X-axis direction, or the NAND string may include three or more floating gate transistors to reduce the metal layer to less than five layers. The number of metal layers and the number of NAND strings There is a trade-off between the metal line spacing in the horizontal or X-axis direction. The more NAND string numbers and the looser in the X-axis direction, the more the gold: genus layer.. less [0066] Figures 6A-6D are double pairs of the present invention The threshold voltage diagram of various embodiments of a single transistor of a transistor floating gate NMOS NAND flash cell is shown in FIG. 6A as an NMOS NAND flash floating in FIGS. 4A, 4B-1, 4B-2, 4C-1, and 4C-2. The gate transistors 405a and 40b perform a threshold voltage level diagram of an embodiment of a program operation and an erase operation. In this embodiment, a positive programming threshold voltage (Vtl) has a narrow distribution representing logical data "〇 , , , A negative programming threshold voltage (VtO) also has a narrow distribution, which represents logical data 1 . VtO and Vtl are superior in programming state. 099113777 Form No. A0101 Page 32 of 133 Page 0992024278-0 201104843 Distribution threshold voltage. In the erase operation of the NMOS NAND flash floating gate transistors 405a and 405b, a voltage of +2〇v is applied to the triple P well 430 where the NMOS NAND flash floating gate transistors 4〇5a and 405b are located, and grounded. A reference voltage (()V) is applied to selected control gates 425a and 425b of the selected NMOS NAND flash floating gate transistor for selection of NMOS NAND flash/floating gate transistors 405a and 405b A voltage difference of 20 V is formed between the control gates 425a and 425b and the channel regions 432a and 432b to produce a Fowler-Nordheim channel tunneling effect of the negative electrode. Since the NOR flash memory array erase operation is customarily performed in the n〇r flash memory [0067] in the memory array block, the threshold voltage (V10) of the negative electrode is generally considered to be considered. It is a collective wipe〗 _ Weng. 々- . · ί _ 响; . -13⁄43⁄4 ^ Snow -: '广-' In the conventional technology, the NAND flash memory array of the pressure (vtO) :- >-i -= - <·ϊ has a wide voltage distribution. Conventionally, the negative voltage threshold (Vto) has a voltage range of approximately V [0068] of 2.0V, i.e., varies from -2.0V to about 0.0V. The programming voltage for the threshold voltage (Vtl) is approximately +2.5V, which varies between +2,0 V and +3.00V. The positive gull dust (vtl) does not require a narrow 0. 5V minutes #' as long as it is less than the unselected word line in the selected NAND flash memory array block during the page programming operation. 6. 0V pass voltage can be. A slower 20us linear read speed specification than a one-page 512-bit NAND flash memory array. The fast, random, and asynchronous read speeds of NOR flash memory components are less than 10 ns. In view of the above-mentioned speed requirement of the double/dual transistor of the NMOS NOR flash memory cell 400, when the NMOS NAND flash floating gate transistors 4〇5a and 405b are connected in series, the negative threshold voltage (VtO) and the positive electrode are connected. The ideal threshold voltage (vti) 099113777 Form No. A0101 Page 33 / 133 pages 0992024278-0 201104843 The critical t-pressure distribution is within about 0.5V. The threshold voltage (Vt〇) of the negative electrode has a standard voltage of about -0.5 V, and the threshold voltage (Vtl) of the positive electrode is about +3. The standard voltage of 〇V. In order to make the threshold voltage (VtO) of the negative electrode have a narrow threshold voltage distribution, the threshold voltage (VtO) of the negative electrode and the threshold voltage (Vtl) of the positive electrode can be transmitted through one-bit-bit. The positive Fowler-Nordheim channel programming operation is achieved. The threshold voltage (VtO) state of the negative terminals of the NMOS NAND flash floating gate transistors 405a and 405b can be achieved in two steps. The first step is to perform a collective erase of the Fowler-Nordheim channel of the negative electrode with a wide negative voltage threshold (VtO) distribution in one page or one block. The second step is to use one bit of the positive electrode. One element Fowler~Nor (iheim channel programming to obtain a narrow negative critical dust (Vt0)" according to the integrated circuit process, the selected NMOS NAND asks the threshold voltage of the positive gate of the floating gate transistors 405a and 405b (Vtl) can be narrowed by a single step of gradually increasing the programming voltages of the selected control gates 425a and 425b from about + 15.0V to about +20V. For NMOS NAND flash floating gate transistors 405a and 405b The threshold voltage (VtO) of the negative electrode and the threshold voltage (Vtl) of the positive electrode all have a narrow programming state distributed at about V5V.

6B is a second embodiment of the programming and erase operations of the NMOS NAND flash floating gate transistors 405a and 405b of FIGS. 4A, 4B-1, 4B-2, 4C-1, and 4C-2. Critical voltage map. In the single potential cell (SLC) embodiment, the first threshold voltage (vto) and the second threshold voltage (Vtl) are all positive and have a critical voltage distribution of about 0.5V. The first threshold voltage (VtO) of the positive electrode is also completed in two steps: the first step is to perform a collective erase operation of the Fowler-Nordheim channel of the negative electrode, the second step 099113777 Form No. A0101 Page 34 / 133 pages 0992024278-0 201104843 Yes A one-dimensional one-bit programming operation of the Fowler_Nordheim channel of the positive electrode as described in Figure 6a is performed. The first threshold voltage (VtO) and the second threshold voltage (V11) are both programmed states rather than an erased state and a programmed state. [〇〇7〇] The first threshold voltage (VtO) is set to the positive electrode, which has a standard value of 〇5V and a narrow 0.5V distribution, that is, from about +0.75V to about +1.25V for storage. A logical data "1". The second threshold voltage (Vtl) is a positive electrode having a standard value of 3.0 V and a narrow distribution from about + 2.75 V to about + 3.25 V for storing a logical data '', _, _. In some embodiments, the NOR flash memory needs to have a wider critical voltage distribution from +2.5V to +3.5V depending on the speed considerations in some applications.

6C is a critical diagram of another embodiment of the programming and erase operations of the NMOS NAND flash floating gate transistors 405a and 405b of FIGS. 4A, 4B-1, 4B-2, 4C-1, and 4C-2. Voltage map. This implementation is about a multi-potential cell (MLC) in which all four threshold voltages are r, r, ', , ....., Vt2, and Vt3), whether positive or negative. There is a narrow 〇 distribution of about 〇5V. In this implementation, the first front-end voltage (ντο) is the negative electrode and

The programming state is entered by using a two-step writing method as described above, which means that the first threshold voltage level (ντο) has a standard value of about 0.5 V and is from about -0.25 V to about - 〇. 75 V. The varying distribution is used to store a logical data "1". The second threshold voltage (VT1) is the second data state stored in the NMOS NAND flash floating gate transistors 405a and 405b, which has a standard of approximately + 1. Ον The value of the second threshold voltage (ντί) varies from approximately +0.75V to approximately +1.50V and is used to store a logical data "10". The third threshold voltage (Vt2) is NM0S 099113777 Form No. A0101 Page 35 of 133 pages 0992024278-0 201104843 The third data state of the NAND flash floating gate transistors 405a and 405b has a standard value of approximately +2.0 V. The distribution of the third threshold voltage (Vt2) is approximately + 1 Between 75V and about + 2.25V, and for storing a logical data "01". The fourth threshold voltage (Vt3) is the fourth data state of the NMOS NAND flash floating gate transistors 405a and 405b, and A standard value of approximately + 3. 0V. Fourth Pro The distribution of the boundary voltage level (vt3) varies between approximately +2.75V to approximately + 3.25V and is used to store logical data "00, [0072] Figure 6D is Figure 4A, Figure 4B-1, Figure 4B-2, FIG. 4C-1 and FIG. 4C-2 NMOS flash floating gate transistors 4〇5a and 405b perform a threshold voltage diagram of another embodiment of a program operation and an erase operation. The first temporary voltage ^·^), the second threshold voltage (VT1), the third threshold voltage (Vt2), and the fourth threshold voltage (Vt3) are both positive and the threshold voltage distribution is relatively narrow. In this embodiment, the first threshold voltage (VT0> has a standard value of about +1.0 V and is used to store the logical data "u" ^the first threshold voltage (ντ〇) is distributed at + 〇. 7 5 V to Between +1 and 2 5 V. The second threshold voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A logical data "ίο". The second threshold voltage (VT1) varies between approximately +1.75V and approximately +2.25V. The third threshold voltage (Vt2) has a standard value of approximately + 3. 〇v and is used for storage - Logic data "01". The distribution of the third threshold voltage (Vt2) varies from approximately + 2.75V to approximately + 3.25V. The fourth threshold voltage (Vt3) has a standard value of approximately 3. 〇v, and is used The logic data "〇〇" is stored. The distribution of the fourth threshold voltage (vt3) varies from about +3 75 V to about + 4.25 V. Figures 7A-7D show the dual transistor floating gate NM〇s N0R of the present invention. 099113777 of flash unit No. A0101 Page 36 of 133 page 0992024278-0 201104843 Threshold voltage diagram of other embodiments. Fig. 6A_6D is abbreviated with Fig. 1, Fig. 4B-2, Fig. 4 (> Figure 4 (:_2 _ nand flash floating floating crystals 405a and 405b perform a conventional threshold voltage diagram of a program operation and an erase operation. The erase and program threshold voltage diagrams opposite to those in FIGS. 6A-6D are described in FIGS. 7A-7D. In Fig. 7A, the first threshold voltage (ντ〇) second critical value (νΤ1) is divided into data "" and logical data 1 and has a standard value of approximately - 5 V and approximately + 3 · 0 V, respectively. In the graph, the 'threshold voltage (10) represents the logical data Ο the second threshold voltage (VT1) represents the logical data "丨" and has a standard value of about H.0V and about +3, respectively. In Fig. 7c The knife-threshold voltage (ντο) has an approximate - standard value for storing = series data "00"; the second critical electric bribe T1) has approximately + 1. 2 standard values and is used to store logical data "10"; The three threshold voltage Ο (eight 2) has a standard value of approximately + 2. 0V and is used to store the logical data "〇1, the fourth threshold voltage (Vt3) has a standard value of approximately +3. Of, and is used for storage - logical data "GO". In the coffee, the first critical value; (VT0) has a standard value of about + 1.0V, For storing logical data "°°; the second threshold voltage (VT1) has a standard value of about +2.0V, and stores the logical data "ίο"; the third threshold voltage (vt2) has a standard value of about +3.0V, And used to store the logical value "〇1"; the fourth voltage (10)) has a standard value of about +4. 〇V, and is used to store the logical data _ the highest threshold voltage of the 电位 step potential unit, that is, the fourth threshold voltage (7) state or single The second threshold voltage of the step potential unit (V(1) is designated as the state of the erase operation. First threshold voltage (vt〇) and 099113777 of single-stage potential unit Form No. A0101 Page 37 of 133 Page 0992024278-0 201104843 First threshold voltage (vto) and second threshold voltage (Vtl) of multi-level potential unit The third threshold voltage (vt2) is a programmed state. Erasing the threshold voltage (the threshold voltage Vt3 of the multi-step potential unit or the threshold voltage Vtl of the single-order potential unit) is obtained by tunneling the positive Fowler-Nordheim channel of a page on the NOR flash memory device, which is fast The flash memory device applies a voltage of approximately +20.0V to the selected NMOS NAND flash floating gate transistors 405a and 405b of FIGS. 4A, 4B-1, 4B-2, 4C-1, and 4C-2. The selected control gates 425a and 425b are applied as well as a ground reference voltage (〇. 0V) at the selected base. It should be noted that Figure 7C,? The fourth threshold voltage (Vt3) of the multi-level power unit of D# and the second threshold voltage (VT1) of the single-stage r-potential unit of FIGS. 7A and 7B are set to the real-time p0wpeΓ-Nordheim channel collective effect a voltage value. Since the threshold voltage of the erase state is checked by the minimum acceptable erase state threshold voltage, and the maximum erase state voltage does not need to be noted, the distribution of the threshold voltage is more varied. [0075] After the erase operation, 'the one-to-one bit F〇wler_N〇rdheim boundary programming process is used to program the cells to be programmed to other logical data states'. In the process, an approx. -1 〇 is applied. The voltage of the negative terminal of V is at a selected word line of one page in the NOR flash memory device and a voltage of about + 5 V to about +1 〇v is applied to the selected nm 〇 S NAND flash floating gate transistor 405a. And the bungee of 405b. The sources of the selected NM0S NAND flash floating gate transistors 405a and 405b are then turned off to a floating state. As mentioned earlier, the programming operation of the NMOS NAND flash floating gate transistors 4〇5a and 405b has two steps, the first of which is to use the positive 099113777 Form No. A0101 Page 38 of 133 Page 0992024278-0 201104843

The Fowler-Nordheim channel operates to erase the block of the selected NOR flash memory element. The second step is to trim the maximum threshold voltage to the desired voltage using a one-bit one-dimensional Fowler-Nordheim boundary tunnel programming operation. 8 is a schematic diagram of a NOR flash memory component 500 including various embodiments of a dual transistor floating gate NM0S n〇R flash cell 510 of the present invention. [0077] FIG. The NOR flash memory component 500 includes an array 505 of dual-electric crystal floating gate NMOS NOR flash cells 510 arranged in straight and horizontal rows. Each dual transistor floating gate NMOS NOR flash cell 510 includes two NMOS NAND flash floating gate transistors 515a and 515b. Two NMOS NAND flash floating gate transistors 5153 and 5151) are configured to operate the _%4, Figure 46-1, Figure 4C-2, Figure 4C-1, and Figure 4C-2. Transistors 405a and 405b. The drain of the NMOS NAND flash floating gate transistor 515a is connected to one of the local bit lines 520a, 520b, ..., 520n-1, and 520n. The source of the NMOS NAND floating gate transistor 515b is connected to one of the source lines 530a, 53Q|, ..., 530n-1, and 530n. The source of the NMOS NAND flash floating gate transistor 515 a is connected to N Μ 0 S Ν 0 R fast * j ψ * t (> The flip-flop of the floating floating gate transistor 515b. The double transistor floating gate adjacent to the straight line The local bit lines 520a, 520b, ..., 520n-1, and 520n associated with the NMOS NOR flash cell 510 are connected to the global bit by the bit line selection transistors 560a.....

Line 525a..... 525η. Local source lines 530a, 530b, ..., 530n-1, and 530n associated with adjacent straight-line dual transistor floating gate NMOS NOR flash cells 510 are connected to the global domain through source line selection transistors 565a.....565n Source lines 540a, ..., 540n. Global bit line 099113777 Form number Α0101 Page 39/133 page 0992024278-0 201104843 525a,...,525η and global source lines 540a,...,540η are connected to the column voltage control circuit (COLUMN VOLTAGE) CTL) 555. The straight line voltage control circuit 555 generates an appropriate voltage to selectively read, program, and erase the dual crystal floating gate NMOS NOR flash unit 510. [007S] Each control gate of the NMOS NAND flash floating gate transistors 515a and 515b of the dual transistor floating gate SNOF flash unit 510 on each of the arrays 505 is coupled to word lines 545a, 545b. One of ..., 545m. In the horizontal voltage control circuit (1"〇¥飞:〇1技术轻6.00111:1'〇1(^1·- cuit, ROW V CTL CKT) 550, the word lines 545a, 545b, ..., 545m are connected to the character A line voltage control circuit (WOKD LINE VOLTAGE CTL) 552. [0079] Each gate of the bit line selection transistors 560a..... 560n is coupled to the course voltage control circuit 550. A bit line select control sub-circuit (BL SEL CTL) 551 ′ is provided to select a signal to activate the bit line selection transistor 56〇a .....56〇n, thereby selecting one The local bit lines 520a, 520b.....520n-1 and 520n are connected to their corresponding global bit lines 525a, ..., 525n. The source line selection transistors 565a.....565n Each gate is connected to a source line voltage control sub-circuit (SOURCE LINE VOLTAGE CTL) 553 > to the local source line 53〇a, 53〇b, ..., 53〇n-i and 53〇n are connected to their corresponding global source lines 54〇a, ..., 54〇n. 099113 777 Form No. A0101 Page 40 of 133 Page 0992024278-0 201104843 [0080] Each gate of the source line selection transistor 565a.....565n is connected to the source within the row voltage control circuit 550 The pole select control sub-circuit 5 $ 3 is operative to provide a select signal to activate the source line select transistor 565a, ..., ' so that a selected local source line 530a, 530b..... 530n-l And 530n are connected to their corresponding global source lines 54A & .... 540n. Each gate of the source line selection transistors 565a.....565n is connected to the course voltage control circuit 55. The source line selection control sub-circuit 553 within the 〇 to local source lines 53〇a, 53〇b, ...,

530Π-1 and 530n are connected to their corresponding global source lines “Μ, ..., 540η. Figure 9 is a schematic diagram of the horizontal voltage control circuit 55{). The course voltage control circuit 550 includes a control decoder ( Ccmuol decoder·, DCDR) 6G5, used to receive programming timing and control signals 61(), erase timing and control signals 615, and read timing and control signals 62. This control decodes the decoding of the programming timing and control signals. 6] 〇, erase timing and control signals 615 and read timing and control signals to establish the operation of the memory component 500. The horizontal electrical circuit 550 includes a bit address decoder Uddress dec〇der , ADDRDCDR) 625, for receiving and decoding the address signal 63 〇 to provide the position of the selected dual-electro-optic floating gate _s surface flash unit 51 待 to be programmed, erased or read. 099113777 [0082] The bit line selection control sub-circuit 551 receives timing and control information from the control numerator (10) that has been edited, erased, and read by p: also from the address address H 625 Receive the address that has been decoded. Bit line selection The path 551 selects the bit (10) to select the signal 570a, ..., 570n, the form 鹄 Α Ι Ι 41 41 41 41 41 41 41 2011 2011 2011 2011 2011 2011 2011 2011 2011 2011 2011 2011 2011 2011 2011 2011 2011 2011 2011 2011 2011 2011 2011 2011 2011 2011 2011 2011 2011 2011 2011 2011 2011 2011 2011 The local bit lines 520a' 520b..... 52 〇 nl and 520 η connected to the NOR flash memory device 5 连接 are connected to the corresponding global bit lines 525a, ..., 525 n. The source line selection control sub-circuit 553 receives the timing and control signals of the programmed operation, the erase operation, and the read operation that have been decoded from the control decoder 605, and also receives the decoded bits from the address decoder 625. The source line selection control sub-circuit 535 selects one of the source line selection signals 575a.....575n to activate the source line selection transistor 565a..... 565n

The local source lines 530a, 530b, ... connected to the N0U flash memory cell are connected to the corresponding global source lines 540a, ..., 540n.

The word line voltage control sub-circuit 552 includes a program voltage generator 635, an erase voltage generator 640'-read voltage generator 645, and a column select switch 650. The programming voltage generator includes a pulse increasing voltage generator 636 to provide a pulsed fiber from about 15 (^ gradually increasing to about + 20. 0V) so that the NMOS NAND floating of FIG. 8 can be more accurately and stably set. The threshold voltage values of the gate transistors 515a and 515b. In the first embodiment, a positive programming voltage generator 637 is used to provide a voltage of about +0.5 V; in the second embodiment, the positive programming voltage generator 637 is A programming operation to provide a voltage of approximately +2.5V to prevent unselected NMOS NAND flash floating gate transistors 5153 and 5151 in FIG. 8 is limited. In the second embodiment, the erase and program conditions are reversed as described in Figures 7a-7d. According to the voltage distribution relationship in FIG. 7 &_7 (1), the negative programming voltage generator 638 provides a negative voltage of about _1 〇 〇 以 以 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 表单 表单 表单 表单 表单 表单 表单 对 对 对 对 对 对 对 对 对 对 对 对 对 对 对 对The unselected NMOS NAND flash floating gate transistors 515a and 515b are programmed to operate. - The ground reference voltage source 639 is used to cause all of the dual nm 〇S NAND flash floating gates within a NOR flash memory component 500. The transistors 515a and 515b are insulated from each other to prevent the established programming in the NMOS NAND flash floating gate transistors 515a and 515b of Fig. 8 from being damaged. [0085] The erase voltage generator 640 includes a positive erase The voltage generator 642 is configured to provide a necessary positive voltage to erase the N 〇 R flash memory element 5 未被 unselected word line in the first embodiment, thereby preventing the unselected NMOS in FIG. 8 . The programming in the NAND flash floating gate transistors 5丨5& and 5丨5b is damaged. In the second embodiment, the Bay Series is used to provide the required voltage to flash the Figure 8 Floating brake power ϋΊ.ϋΊ: .:乂'寒.13⁄4 crystals 515a and 5 15b performs an erase operation. In the first embodiment, the erase voltage generator 640 includes a negative erase voltage generator 643 for the NMOS NAND flash floating gate transistors 5 丨 53 and 5 图 of FIG. 5b performs a [0086] erase operation. In the second embodiment, the voltage of the unselected word line is set to the ground reference voltage source 644. To read the single-order unit data, the read voltage generator 645 includes a first high read voltage generator 646 for providing the necessary read voltage VH to the selected ones of the NMOS NAND flash floating gate transistors 515a and 515b of FIG. The word line control gate. To read the multi-level cell data, the read voltage generator 645 further includes a second and third high read voltage generators 647 and 648 for generating the second and third high read voltages. 647 and 648 are respectively used to supply the necessary read voltages VH1 and VH2 to the NMOS NAND flash floating gate transistor 5 of FIG. 8 and the 5 ribs of the 099113777 form number A0101, page 43, total 133 Page 0992024278-0 201104843 [0087] [0089] 099113777 Select control gate. The voltage generator 645 also provides a voltage gate generator 649 to the control gate of the NMOS NAND flash floating gate transistor 515b of Figure 8 to read the single-order cell data. The row voltage control circuit includes a row selection A switch is applied to transfer the programming voltage generator 635, the erase voltage generator 640, and the read voltage generator 645 programming voltage, erase voltage, and read voltage to the selected word line 545a, 545b, ..., 545m. Referring to Figure 10', a straight-line voltage control circuit 555 is described. The straight line voltage control circuit 55 5 includes a control code coder 5 〇 5 for receiving a programming timing and control signal 710, an erase timing and control signal 715, a read timing, and a control signal 720. The control numerator 7〇5 is also used to decode the programming timing and control signals 710, erase timing and control signals 715, read timing and control signals 720, and to operate the NOR flash memory component 500. The straight line voltage control circuit 555 also includes a bit address decoder 725 for receiving and decoding the address number 730' to provide a selected dual crystal thyristor floating gate NMOS NAND flash The 51 〇 address is programmed, erased or read. The straight line voltage control circuit 555 further includes a program voltage generator 735, an erase voltage generator 74, and a read voltage generator 745. And the row select switch 750 °. The program voltage generator 735 includes a program voltage source 736. In the first embodiment, the program voltage source 736 is used to provide a program inhibit voltage of about + 10.0V to the The selected NM〇s NANd flash drain gates 515a and 515b are drained and sourced to suppress the unselected NMOS NAND flash floating gate transistors 515a and 515b. Form No. A0101 Page 44 of 133 Programming operation of page 201104843. In a second embodiment, during a programming operation, the programming source 736 is used to provide a voltage of approximately +5.0 V to the selected NMOS NAND flash floating gate transistors 515a and 515b of FIG. Bungee jumping. In the first embodiment, a ground reference voltage source 737 is also provided to the drain and source of the selected NMOS NAND flash floating gate transistors 515a and 515b of FIG. 8 during a programming operation. For some of the unselected NMOS NAND flash floating gate transistors 515a and 515b of FIG. 8, the ground reference voltage source 737 is also provided to the unselected NMOS NAND flash floating gate transistors 515a and 515b to suppress Programming shakes. The erase voltage generator 740 includes a wipe voltage source 742 for providing the necessary positive voltage to effect the erase of the NOR flash memory device 500 in the first embodiment. The drain and source voltages of the unselected NMOS NAND flash floating gate transistors 515a and 515b of Figure 8 are then set to ground reference voltage source 743. [0091] To read multi-level potential cell data, the read electroacoustic generator 745 includes a moderately high read voltage source 747 for providing the necessary read voltage VHD to The drains of the selected NMOS NAND flash floating gate transistors 515a and 515b. To read the single-order cell data, the read voltage generator 745 further includes a voltage source generator for supplying a voltage to the drain of the NMOS NAND flash floating gate transistors 515a and 515b of FIG. . [0092] The straight line voltage control circuit 555 includes a row select switch 75A for erasing the program voltages of the program voltage generator 735, the erase voltage generator 740, and the read voltage generator 745. The voltage and read voltage are transferred to selected bit lines 525a, 525b..... 525n 099113777 Form No. A0101 page 45/133 pages 0992024278-0 201104843 and source lines 540a, 540b, ..., 540n. 11 is a schematic diagram of a single-stage potential programming voltage following sensing circuit in various embodiments of the NMOS NOR flash memory cell 400 of FIG. The illustration is directed to two NMOS NAND flash floating gate transistors 405a and 405b in an NMOS NAND flash floating gate transistor. The drain 415 of the uppermost transistor of the NAND flash floating gate transistor 4 0 5 a and 4 0 5 b is connected to the local bit line 805 and then connected to the global bit line through the bit line selection transistor 810. 815. The global bit line 815 is coupled to the straight line voltage control circuit 555 of FIG. The gate of the bit line selection transistor 810 is connected to the bit line selection control sub-circuit 51 of FIG. 8 to receive the enable signal enable bit line select transistor 810, so that the uppermost flash floating gate The sum terminal 415 of the transistor 40 5a is connected to the voltage source VDD. [0094] The source 422 of the lowermost NMOS NAND flash floating gate transistor 4〇5b is connected to the local source line 825. The local source line 825 is coupled to the global bit line 835 through the source line select transistor 830. The global bit line 835 is coupled to the sense amplifier 755 in the straight line voltage control circuit 555 of FIG. The sense amplifier 755 includes a comparison circuit 850 having one end coupled to a global source line 835 and the other end coupled to a reference voltage source 855. The voltage of the reference voltage source 855 is set between a threshold voltage representing a logic "Γ and a logic "0". The gate of the source line selection transistor 830 is connected to the straight line voltage control circuit 555 of FIG. a source line voltage control sub-circuit 553. The source line voltage control sub-circuit 553 is configured to provide a voltage necessary to activate the source line select transistor 83, thereby connecting the local source line 825 to the global bit line 835, that is, the source 422 of the NMOS NOR flash memory cell 4 。. When the 099113777 form number A0101 page 46 / 133 pages 0992024278-0 201104843 NMOS NAND flash floating gate transistors 4〇5a and 405b are At startup, its operational behavior is similar to that of a voltage follower. The voltage of the source line capacitor 845 is equal to the voltage source minus the programming threshold voltage of the NMOS NAND flash gate transistor 4〇5a or 405b (Vs = VDD-VtMSEL). The selected NMOS NAND asks the floating gate transistor 405a or 405b to be driven such that it has a minimum voltage drop. Depending on the programmed threshold voltage of the selected NMOS ΝΑΟ flash floating gate transistor 405a or 405b, Than the output voltage of the circuit 850 represents a logical "Gamma] or a logical" square. " [0095] Referring to FIG. 11B, in order to read the single-order potential programming unit storage value of the uppermost transistor in the NMOS NANIX flash floating gate transistors 405a and 405b, the electric potential of the first word line fLO 450a is set to , : 3⁄4 source VDD voltage. The voltage of the voltage source VDD is about +1, .8V or about +3.00V. · .....; .. :.....·· . ο The voltage of the second word line WL1 450b is set to a higher read voltage greater than +6. ον to turn on NMOS NAND fast Flash floating gate transistor 405b. The voltage of the drain of the uppermost NMOS NAND flash floating gate body 405a is set to the voltage of the voltage source VDD through the local bit line 805 and the global bit line 815. If the voltage of the NMOS NAND flash floating gate transistor 405a is set at the first threshold voltage Vt0 (from about -0.75V to about -0.25V), the source of the lowermost NMOS NAND flash floating gate transistor 405b The pole 422, that is, the voltage value VS0 of the first input of the comparison circuit 850 is approximately equal to the voltage value of the voltage source VDD. If the voltage of the floating gate transistor 405a is set at the second threshold voltage Vtl (greater than +3.00V), the source 422 of the lower NMOS NAND flash floating gate transistor 405b, that is, the first input of the comparison circuit 850 The voltage value VS1 of the terminal is approximately equal to the voltage value of the ground reference voltage (0. 0V). Thus, the comparison circuit 099113777 Form No. A0101 Page 47 of 133. 0992024278-0 201104843 The logic value of the output of the 850 is specified by the threshold voltage value programmed by the uppermost NMOS NAND flash floating gate transistor 405a. [0096] In order to read the SLC storage value of the lowermost transistor in the NMOS NAND flash floating gate transistors 405a and 405b, the voltage value of the second word line WL1 450b is set to the voltage value of the voltage source VDD. The voltage value of the first word line WLO 450a is set to a higher read voltage greater than +6.0V to turn on the NMOS NAND flash floating gate transistor 405a. The voltage of the drain of the lowermost NMOS NAND flash floating gate transistor 405b is set to the voltage source VDD through the uppermost NMOS NAND flash floating gate transistor 405a, the global bit line 815, and the local bit line 805. If the voltage of the lowermost NMOS NAND flash floating well transistor 4053⁄4 is set at the first threshold voltage VtO (from about -Q.75Y to about -0.25 V), the lowermost NMOS NAND flash floating gate transistor 4_b The source 422, that is, the voltage value VS0 of the first input of the comparison circuit 850 is approximately equal to the voltage value of the voltage source VDD. Since the gate voltage Vi)D of the NMOS NAND flash floating gate transistor 405b is less than Vtl, if the power of the NMOS NAND flash floating gate transistor 405b is set to the second threshold voltage Vtl (greater than +3.00V) The source 422 of the 405b of the lowermost NMOS NAND flash floating gate transistor, that is, the voltage value VS1 of the first input terminal of the comparison circuit 850 is approximately equal to the voltage value of the ground reference voltage (0. 0V). Thus, the lowermost NMOS NAND flash floating gate transistor 405b is in a non-conducting state, and the local bit line 805, i.e., no voltage, is transferred to the local source line select transistor 830, so VS1 = 0V. Thus, the output logic value of the comparison circuit 850 is specified by the threshold voltage value programmed by the lowermost NMOS NAND flash floating gate transistor 405b. 099113777 Form No. A0101 Page 48 / Total 133 Page 0992024278-0 201104843 [0097] In an array of NMOS NOR flash memory cells 400, if a nm 〇s NOR flash memory cell unit 4 is not selected for reading When the other (10) N 〇 R flash memory cell is selected for reading, the unselected (10) (10) Ν〇Ι ^ ^ flash memory cell 400 in the non-selected 〇 5 NAND flash floating gate transistor 405a And the voltage of the control gate of 405b is set to the ground reference voltage to turn off the charge holding transistor. [0098] FIG. 11C is a multi-step potential programming voltage following induction of the NMOS NOR flash memory cell 400 of FIG. 4A. A schematic diagram of a specific embodiment of the circuit. The NMOS NAND flash floating gate transistor as described in FIG. 11A illustrates that the voltages of the two NMOS NAND flash floating gate transistors 405a and 405b are both fiberized except for the global bit lines. A first higher read voltage source VHD. [0099] In the particular embodiment, the global bit line 835 is coupled to the sense amplifier 755 in the straight voltage control circuit 555 of FIG. In this embodiment, the sense amplifier 755 includes three comparison circuits 860, 870, and 880. A first input of each of the three comparison circuits 860, 870, and 8 is coupled to a global bit line 835, the second input being coupled to a reference voltage source, wherein the second comparison circuit 860 is second The input is coupled to a first reference voltage source 865 REFV0; the second input of the second comparison circuit 870 is coupled to a second reference voltage source 875 REFV1 ; the second input of the third comparison circuit 880 is coupled to a third reference voltage source 885 REFV2. The voltage values of the three reference voltage sources 865, 875, and 885 are set between the threshold voltage values representing the logical values of the data ("00", "01", "10", "11"). The gate of the source line selection transistor 830 is connected to the source line voltage control sub-circuit 553 in the horizontal voltage control circuit of FIG. 099113777 Form Number Α0101 Page 49 of 133 Page 0992024278-0 201104843 The source line voltage control sub-circuit 553 is used to provide the necessary voltage to connect the source line select transistor 830 to the local source line 825, That is, the source 422 of the NMOS NOR flash memory cell 400 is connected to the global bit line 835. When the NMOS NAND flash floating gate transistors 405a and 405b are activated, they are similar to a voltage follower. The voltage on source line capacitance 845 is equal to the voltage source minus the programmed threshold voltage (Vs = VDD - VtMSEL) of the selected NMOS NAND flash floating gate transistor 405a or 405b. The unselected NMOS NAND flash floating gate transistor 405a or 405b is driven to have a minimum voltage drop. Depending on the programmed threshold voltage level of the selected NMOS NAND flash floating gate transistor 405a or 405b, the output voltage of the comparison circuit 850 will represent the data logic value ("00", "01", "10", with the programmed threshold voltage. "11"). It should be noted that the structure described in this embodiment is applicable to one two-dimensional multi-order unit. It will be appreciated that any number of data logic values may be preserved by NMOS NAND flash floating gate transistors 405a and 405b without departing from the spirit of the present invention.

[0100] FIG. 11D discusses reading the bias voltage of the multi-stage potential programming of the NM Of N OR flash memory cell unit 400. The voltage of the first word line WL0 450a is set to a first higher read voltage VH0 to read the uppermost transistor of the NMOS NAND flash floating gate transistors 405a and 405b. 0伏。 The first higher read voltage VH0 is about 4. 0V. The voltage of the second word line WL1 450b is set to a second higher read voltage VH1 greater than +7.0V to turn on the NMOS NAND flash floating gate transistor 405b. The voltage of the drain of the uppermost NMOS NAND flash floating gate transistor 405a is set to a third higher voltage source VHD 099113777 through the local bit line 805 and the global bit line 815. Form No. A0101 Page 50 / Total 133 pages 0992024278-0 201104843 04. 0V) 〇[0101] ο ο If the voltage of the NMOS NAND flash floating gate transistor 405a is set to the first threshold voltage VtO (from about -0.75V to about -0.25V), then The source 422 of the lowermost NMOS NAND flash floating gate transistor 405b, that is, the voltage VS0 of the first input of the comparison circuit 850 is approximately the third highest read voltage VHD. If the voltage of the NMOS NAND flash floating gate transistor 405a is set to the second threshold voltage Vtl (about + 1.0 V), the voltage VS1 ' of the source 422 of the lowermost NMOS NAND flash floating gate transistor 405b is also compared. The voltage at the first input of the circuit 850 is approximately 3. 〇v. If the voltage of the NMOS NAND flash floating gate transistor 4〇5a is set to the third threshold voltage Vt2 (about 2.0 V), the voltage VS2 of the source 422 of the lowermost NMOS NAND flash floating gate transistor 405b is also That is, the voltage at the first input terminal of the comparison circuit 850 is about 2. OV » If the voltage of the NMOS NAND flash floating gate transistor 405a is set to the second threshold voltage Vt3 (about + 3. 0V), the lowermost MOS NAND is fast. The voltage VS3 of the source 422 of the flash floating gate transistor 405b, that is, the voltage at the first input of the comparison circuit 850 is approximately the ground reference voltage (1.0 V). Thereafter, the logic state set by the output of the comparison circuit 850 is determined by the threshold voltage at which the uppermost NMOS NAND flash floating gate transistor 40 5a is programmed. [0102] To read the multi-level potential programming of the lowermost transistor in the NMOS NAND flash floating gate transistors 405a and 405b, the voltage of the second word line WL1 450b is set to the voltage of the VHD. The voltage of the first word line WL0 450a is set to a higher read voltage greater than +6.00V to turn on the NMOS NAND flash floating gate transistor 405a. By SLG [η] 099113777 Form No. 1010101 Page 51 / Total 133 Page 0992024278-0 201104843 [0103] The lowermost terminal of the gate control selects the voltage of the global source line of the transistor. The GSL is transmitted through the lowermost NMOS NAND. The flash floating gate transistor 405b, the uppermost NMOS NAND flash floating gate transistor 405a, the local bit line 805, the uppermost selection transistor Msel controlled by the BLG [[η] gate, and the global bit line 815 are provided. The gate voltage of the top and bottom select transistors must be coupled to the high sum of the read voltage and the threshold voltage (VHD + Vt) to fully transfer sufficient VHD voltage from GBL to GSL. If the voltage of the NMOS NAND flash floating gate transistor 4 〇 ib is set at the first threshold voltage VtO (from _about -0.75 V to about -0.25 V), the lowermost NMOS NAND flash floating flash power #a body The voltage VS0' of the source 422 of 4051), that is, the voltage at the first wheel input of the comparison circuit 850 is approximately equal to a third high read voltage source VHD. If the voltage of the NMOS NAND flash floating gate transistor 405b is set to the second threshold voltage Vtl (about + 1·0V)' and the VHD is approximately equal to 4.0V, the lowermost NMOS NAND flash floating gate transistor 40 0伏。 The voltage VS1 of the voltage 422, that is, the voltage of the first input of the comparison circuit 850 is approximately equal to 3. 0V. If the voltage of the NMOS NAND flash floating gate transistor 405b is set to the third threshold voltage Vt2 (about 2.0 V), the voltage VS2 of the source 422 of the lowermost NMOS NAND flash floating gate transistor 405b is also compared. The voltage at the first input of the circuit 850 is approximately 2.0 V. If the voltage of the NMOS NAND flash floating gate transistor 4 0 5 b is set to the sth threshold voltage Vt3 (about +3.0 V), the voltage of the source 422 of the lowermost NMOS NAND flash floating gate transistor 405b.伏之间。 The voltage of the first input terminal of the comparator circuit 850 is about 1. 0V. Thus, the input of the comparison circuit 850 099113777 Form No. A0101 Page 52 of 133 099 201104843 The output shows the logic value represented by the threshold voltage of the lowest NMOS NAND flash floating gate transistor. [0104] In FIGS. 11A and 11C, the triple p well 430 in FIGS. 4B-2 and 4C-2 is connected to the ground reference voltage (0.0 V), and the deep n well 435 is connected to the voltage source VDD 〇 [0105]. [0106] In an array of NMOS NOR flash memory early 4 ,, if one nm 〇 S NOR flash memory cell 400 is not selected for read operation, another NMOS is selected for read operation When the unselected NM〇s N〇R flash memory cell 400 is not selected, the NM0S NAND flash floating gate transistors 4 0 5 a and 4 0 5 b are controlled to be closed; The ground reference voltage is set to turn off the charge to save the electric crystal. Figure 12A-12E is the erase bias voltage meter of the double crystal floating gate NMOS NOR flash unit in Figures 4A and 4B-1. Referring to Figures 12B-12E, the erase bias voltages of the four tables are used to provide an erase condition such that the drains 415, 420 and source 420 of Figures 4A, 4B-1, 4B-2 '4C-1 and 4CM2 The voltage drop between the base channel 432a and 432b and the control gate 4258 or 4251) between 422 is set to one approximately + 20·0V during the channel erasing period of ^?0|161^01" In Fig. 12A, the selected word line 450a or 450b', that is, the voltage of the control gate 425a or 425b, is set to a negative erase voltage of about -10·0 V. The drains 415 and 420, the source The voltages of 420 and 422, triple ρ well 43 〇 and deep WELL 435 are set to a positive erase voltage of approximately + 10. 0 V. The unselected word line 450a or 450b, that is, unselected control The voltage of gate 425a or 425b is set to a masking erase voltage of approximately + 10. 〇v. 099113777 Form No. 1010101 Page 53 of 133 Page 0992024278-0 201104843 [0107] In Figure 12B, the negative erase voltage Approximately -15 〇V, the positive erase voltage is approximately + 5. 0V, and the positive shield voltage is approximately + 5. 0V. In Figure 12c, the negative eraser is Approx. _2〇. 〇v, positive erase is about 0. 0V 'The positive blocking voltage is about 〇· 〇v. In Figure 12]), the voltage level is reversed, and the negative erase voltage is about 〇 〇v, the positive erase voltage is approximately + 20.0V. Each of the voltages in Figures 12A-12D produces a Fowler-Nordheim channel tunneling effect to reduce the threshold voltage of the selected _〇s NAND flash floating gate transistor 4〇5a or 405b. [0108] The unselected double transistor floating gate NMOS NAND fast interrogation units of FIGS. 4A, 4B-1, 4B-2, 4C-1, and 4C-2 do not share the same triple p well 43 〇 and deep N well 435 . The voltage of the unselected word line 450a or 450b, i.e., the control gate 425a or 425b, the drains 415 and 420, the sources 420 and 422, and the triple P well 430 are set to be approximately equal to the ground reference voltage. The voltage of the deep N well 435 is set to the voltage of the voltage source VDD. [0109] For a sub-array in an array of floating gate NMOS NAND flash cells (often 512Kb or 4Kb.), the voltage of the deep N well of the un-erased sub-array is set to + At 20V, the voltage of the word line, drain, source, and triple P diffusion well is set to the ground reference voltage. The voltages of the word lines, the wave poles, the source poles, the = heavy P wells, and the deep N diffusion wells of the sub-arrays that are not selected in the different deep N wells are set to the ground reference voltage. [〇11〇] The erasing operation when another erase and programming threshold voltage is inverted is discussed in Fig. 12E. In this case, the selected word line 45A or 450b, that is, the voltage of the control gate 425a or 425b is set to a positive programming voltage of about +20. (^). The control gate 4 2 5 a Or 4 2 5 b, no pole 415 and 4 2 〇, source 420 and 422, triple P well 430 voltage is set to ground reference 099113777 Form No. A0101 Page 54 / 133 pages 201104843 Pressure (0. OV) The voltage of the deep N well 435 is set to the voltage of the voltage source. The conditions for setting the erased threshold voltage to the positive voltage and setting the programmed threshold voltage to the negative voltage are as shown in FIGS. 7A-7D. Figure 13A and Figure 13B are the programming biases for programming the dual transistor floating gate NMOS NOR flash cell in Figure 4Α, 4Β-1, 4Β-2, 4C-1, and 4C-2. The selected _〇s NAND flash floating gate transistor 405a or 405b in the dual transistor floating gate NMOS NAND flash cell in 4A, 4B-1, 4B_2, 4C-1, and 4C-2 is programmed before the cell is programmed. Must be erased. In an array of a double transistor floating gate NMOS NAND flash cell as shown in Figure 8, the erase operation is Performed on a page or a block of cells. [0112] The NM0S NAND flash floating gate transistor 405a selected from FIGS. 4A, 4B-1, 4B-2, 4C-1, and 4G-2 When the programming operation is performed by 405b, the selected word line 450a or 450b, that is, the voltage of the control gate 425a or 425b is set to a positive programming voltage of about + 15 > 0.V to + 20: 0V. The voltages of 415 and 420, _ poles 420 and 422, and channel regions 432a and 432b are freshly set to ground reference voltage (0. 0 V) through triple P well 430. Unselected NMOS NAND flash floating gate transistor 4 〇 5a Or word line 450a or 450b of 405b is coupled to its control gate 425a or 425b to set its voltage to a masking programming voltage of approximately +0.5 V. Within an array as shown in Figure 8, located in the selected character The drain and source voltages of the unselected floating gate NMOS NAND flash cells on line 450a or 450b are set to a positive programming masking voltage from about +7.00V to about +10 〇v. In the array shown in 8, the common bit line 455a, 455b having the positive blocking voltage and the source line 460a, 460b are 099113777 Form No. A 0101 Page 55 of 133 0992024278-0 201104843 The voltage of word lines 450a and 450b of the unselected floating gate NMOS NAND flash cell is set to a positive blocking programming voltage of + 5. 0V. The voltages of the unselected floating gate NMOS NOR flash cells that are not connected to the positive programming voltage or the positive programming masking voltage are not included in the word lines 450a, 450b or the bit lines 455a, 455b or the source lines 460a, 46 Ob. Set to ground reference voltage (O.OV). It is conventionally known that the higher the positive programming voltage applied to the control gate 425a or 425b, the higher the threshold voltage Vt after the programming operation. During the programming operation, in order to maintain the precise control of the threshold voltage of the NM0S NAND flash cell, the gate is applied with an initial positive programming from approximately + 15.0V to approximately + 16.0V. The positive programming voltage is incremented by a small amount over time. The above programming voltage is suitable for programming a single-order potential unit or a multi-level potential unit. The threshold voltage is shown in Figures 6A-6D. [0114] As the gate voltage of the selected programming cell in the selected block and the voltage of the floating source gradually increase by a small amount of negative gate voltage, this is an iterative programming operation and a program verifying step. For example, the drain (BL of ground) voltage is coupled to a fixed +5V and the local SL is floating. Fig. 8F is a preferred bias condition for programming a selected cell M0. A gate voltage of -10 V is applied to WL0 of the selected cell M0. The -10V gate voltage can start from -5V and then gradually drop to -10V. In other words, the voltage value Vt of the unit can be accurately controlled to a desired voltage value. Referring to Figure 13B, the programming voltage for the reverse programming and erase conditions as shown in Figures 7A-7B is depicted. In this embodiment, the voltage of the selected word line 450a or 450b of the selected NMOS NAND flash floating gate transistor 405a or 405b is set to about -10. ov of the negative programming voltage bungee 099113777 Form Compilation A0101 Page 56 of 133 pages 0992024278-0 201104843 Ο [0115]

[0116] G

[0117] The voltages of 415 and 420 gradually drop to a positive drain voltage of approximately + 5. ον. The voltage of source 420 stops floating. The selected NM〇s N〇R flash cell is repeatedly programmed and tested so that the cell threshold voltage can be accurately reached after the programming operation. In this embodiment, the programming conditions are based on the FoWler-Nordheim boundary tunnel programming operation. A common FN boundary programming operation is used to reduce the voltage Vt of the selected cell after programming. However, the final voltage Vt of the selected programming unit after (4) boundary programming is to be positive to avoid being misread due to leakage of bl through the unselected cells in the selected block. The FN boundary occurs at the boundary between the drain point and the gate point of the selected NAND cell in the selected block of the present invention. In addition, the negative programming voltage can be gradually increased from about -7. 〇V to about -10· Ο » » The middle positive drain voltage is fixed at about + 5 · 〇v » In this embodiment, each iterative step is about 〇 3V gradually breaks the negative programming voltage 〇 sets the power of the unselected word line i5〇a or 450b to a positive illuminating power of about +2.5V to prevent the unselected NMOS NAND from flashing. Gate transistor 405a or 405b is not programmed to operate. The voltages of the drain 415 and the triple P well 430 of the unselected NMOS NAND flash floating gate transistor 405a or 405b are set to the ground reference voltage (o.ov), and the voltage of the deep N well 435 is set to Voltage source VDD. The electrons in the floating compartment of the selected floating gate NMOS NOR flash cell are evicted from the floating gate 445a or 445b. Therefore, the threshold voltage of the selected floating gate NM0S NOR flash cell can be controlled very accurately in single-order cells and multi-level cells. 099113777 Form No. A0101 Page 57 of 133 0992024278-0 201104843 [0118] Figure 14 is a flow chart for forming a NOR flash memory component using the present invention. An array of floating gate transistors is formed on a substrate (as indicated by block 905). The floating gate transistor is arranged in a matrix of rows and columns. At least two adjacent floating gate transistors are connected in series (block 910) in a row to form a NOR memory cell θ ΝΑΝΙ string. The drain of the uppermost floating gate transistor in each of the NAND-based NOR flash memory cells is connected to a corresponding bit line (block 915). The source of the lowermost floating gate transistor in each row of the NAND-based NOR flash memory cell is connected to a corresponding source line (block 920) 〇[0119] local bit line The transistor is connected to a corresponding global bit line (square 柩% 5 ) through an uppermost bit line selection layer » the source of the uppermost bit line selection transistor is connected to the local bit line, the uppermost The bit line select transistor has a gate connected to the global bit line. The local source line is coupled to a corresponding global source line through a lowermost source line select transistor (block 930). The lowermost & line selects the transistor's ... source connected to the local source line'. The lowermost source line selects the drain of the transistor to be connected to the global source line. [0120] A one-bit gate select control line is connected to the uppermost bit line select gate of the transistor (square stick 935). The source line gate selection control line is connected to the gate of the lower source line selection transistor (block 94A). In each row of a NAND-based NOR flash memory array, the control gate of each floating gate transistor is coupled to a corresponding word line (block 945). Each word line in each floating gate transistor row is connected to a word line voltage controller (block 950)' to provide a base for the base (4). Form number A0101 Page 58 of 133 201104843 峨 flashing e'lt body array for the bias required for the splicing, erasing and reading operations. The per-bit line select control line is coupled to the _ bit line select controller (block 955) such that the bit line select transistor can be selectively connected - the selected local bit (4) - global bit Similarly, the per-source line select control line is coupled to a source line select control gs (block 960) such that the source line select transistor can be selectively coupled to the selected local source line. To the _ global source line.

[0121] G-to-global bit it and straight bit lines are connected to a straight-through voltage controller (block 965). As described above, the word line voltage controller and the straight line voltage controller are used to supply an appropriate voltage to the NAND-based N〇R flash memory unit, and the N 〇R flash memory unit is programmed by α. Operation, Erase Operation, and Read Operation, [0122] Figure 15 is a schematic diagram of a NAND-based multi-crystal floating gate NM〇sn〇r flash memory array. In Figure 8 of a NAND-based NMOS NOR flash memory array, each floating gate NMOS NOR flash cell includes two floating gate transistors. In Fig. 15, 'each floating gate NMOS NOR flash unit 1; at least two of the floating gate transistors 1010a, l〇l〇b, ..., l〇i〇n in 〇〇5 are connected in series with each other 'An embodiment of the double transistor series as described in Fig. 8. The drain of the uppermost floating gate transistor 1010a is connected to the local bit line 1015, and the source of the lowermost floating gate transistor 1 〇 1 〇n is connected to the local source line 1 020. On a related NAND-based NMOS NOR flash memory array, each word line l〇25a, 1 025b.....1025η is connected to the floating gate transistor ιοί〇a, 101 〇 b.....101 On the control gate. The single-order unit is stored in the floating gate NMOS NOR flash unit. 099113777 Form No. A0101 Page 59 / 133 pages 0992024278-0 201104843 The number of bits stored is one bit per transistor, so the floating gate NMOS N0R is fast. The flash cell can be designated as a clamp/n transistor unit. In a multi-level cell, the number of bits depends on the number of threshold voltages stored in each of the floating gate transistors 1010a, 1010b, ..., ι〇ι〇η. [0123] The need for NOR flash to use the memory element technology is that the read time is between about 20 uS and about 100 ns. The number of transistors determines the performance of the NAND-based NOR flash memory unit. For example, Figure 4A,

The double-crystal floating gates NM〇s(10) in 4B-2, 4C-1 and 4C-2 are in the form of strobe units; 5&s examples are based on NAND based on NAND from 1 Gb to 4 Gb capacity. Flash memory wants the array to read for approximately l〇〇nS. In addition, the read time of the Dragon (10) 臓 flash memory array based on NAND of 1Mb to 4Mb capacity is 2〇ns. In the array, the random read operation is a one-tuple (8-bit). , - character (1 hex) or a pair of 疋 (32 το) for reading operations; programming unit is a page of 512-bit 或 group or half-page 256-bit group for programming operations The divide operation is performed in units of sectors (-small section 4K bytes or _large section 64K bytes). Port 0 [0124] 099113777 In other embodiments, the _s N(10) flash memory unit based on the biliary (four) has 16 or 32 transistors in series. The read time for a longer array of capacities from 1Gb to 32Gb is reduced to approximately Mm. In this embodiment, the read operation is half page (256 bytes) or one page (512 bits read). The unit is continuously read. Similarly, a programming operation such as a full page of 512 bytes or a half page of 256 bytes is performed in units. The erase operation is erased in units of - segment 51 te group or 519 "four" bit ytes X 32 (16K bytes) ^

Form 鱿Α0101 Page 6 of 133 pages 0992024278-0 201104843 [0126] 0 [0127] Ο [0128]. In various embodiments, the NAND-based floating gate NMOS NOR flash memory cell can include any number of transistors as previously described. However, in order to ensure compliance with current performance requirements for floating NMOS NMOS NOR flash memory cells, up to 15 transistors are typically used in a NAND-based floating gate NMOS NOR flash memory cell. As described above, the NAND-based NMOS NOR flash memory cell includes a floating gate transistor for storing charge "Floating gate NMOS NOR in each NAND string of the NOR flash memory cell. Flash memory cell-based NANDs all include a S0N0S charge operation NAND transistor. An integrated circuit comprising a flash memory unit based on N A N D may comprise a NAND flash memory array and a NAND-based NMOS NOR flash memory cell array using the inventive concept. The NAND-based NMOS NOR flash memory unit is further integrated with volatile memory to form a memory function on a single-integrated circuit. Furthermore, the NAND-based NMOS NOR flash memory cell can include peripheral circuitry to enable NAND-based (10) (10) NOR flash memory cells for applications such as pLj or fpga. In summary, the present invention complies with the requirements of the invention patent, and proposes a patent declaration according to law. However, the above description is only the preferred embodiment of the present invention, and equivalent modifications or variations made by those skilled in the art of the present invention in the spirit of the present invention should be covered by the following claims. [Simple description of the drawing] 099113777 Form No. A0101 Page 61 of 133 Page 0992024278-0 201104843 [0129] FIG. 1A is a top view of a single transistor floating gate OS NAND flash unit [0130] FIG. 1B is a single Sectional view of a transistor floating gate NMOS NAND flash cell 013 [0131] FIG. 1C is a schematic diagram of a single transistor floating gate NMOS NAND flash cell [0132] FIG. 1D is a single transistor floating gate NMOS NAND flash cell A distribution map of threshold voltages. [0133] FIG. 1E is a distribution diagram of four threshold voltages of a single transistor floating gate NMOS NAND flash cell. 2A is a top plan view of a single transistor floating gate NMOS NOR flash cell. 2B is a cross-sectional view of a single transistor floating gate NMOS NOR flash cell. 2C is a schematic diagram of a single transistor floating gate NMOS NOR flash unit. 2D is a distribution diagram of two threshold voltages of a single transistor floating gate NMOS NOR flash cell. 2E is a distribution diagram of four threshold voltages of a single transistor floating gate NMOS NOR flash cell. [0139] FIG. 3A is a top plan view of a dual transistor floating gate NMOS NOR flash unit of the prior art. [0140] FIG. 3B is a cross-sectional view of the dual transistor floating gate NMOS NOR flash cell of FIG. 3A. 3C is a schematic diagram of a unit of the dual transistor floating gate NMOS NOR flash in the prior art FIG. 3A. 099113777 Form No. A0101 Page 62 of 133 0992024278-0 201104843 Unit. 3D is a distribution diagram of two threshold voltages of a dual transistor floating gate NMOS NOR flash cell of the prior art. 3E is a distribution diagram of four threshold voltages of a prior art dual transistor floating gate NMOS NOR flash unit. 4A is a schematic diagram of an embodiment of a dual transistor floating gate NMOS NOR flash cell of the present invention.

4B-1, 4B-2, 4C-1, and 4C-2 are top and cross-sectional views of an embodiment of a dual transistor floating gate NMOS NOR flash cell of the present invention. 5A-5E are connection diagrams of a segment of the dual transistor floating gate NMOS NOR flash cell array of the present invention. 6A-6D are threshold voltage diagrams of various embodiments of a single transistor floating gate NMOS NOR flash cell of the present invention. 7A-7D are threshold voltage diagrams of other embodiments of a dual transistor floating gate NMOS NOR flash cell of the present invention. 8 is a schematic diagram of a NOR flash memory component including a dual transistor floating gate NMOS NOR flash cell in accordance with various embodiments of the present invention. 9 is a circuit diagram of a course voltage control circuit of the N 0 R flash memory of FIG. 8. 10 is a circuit diagram of a straight-line voltage control circuit of the N 0 R flash memory of FIG. 8. 11A is a schematic diagram of a single-stage potential programming voltage following induction circuit in the double transistor floating gate NMOS NOR flash unit of the present invention. 099113777 Form No. A0101 Page 63 of 133 0992024278-0 201104843 11B is a single-order potential programming read bias table in the dual transistor floating gate NMOS NOR flash cell of the present invention. 11C is a schematic diagram of a multi-level potential programming voltage following sensing circuit in the dual transistor floating gate NMOS NOR flash unit of the present invention. 11D is a multi-level potential programming read offset table in a dual transistor floating gate NMOS NOR flash cell of the present invention. 12A-12E are eraser bias tables of the dual transistor floating-to-space NMOS NOR flash cell of the present invention. 1A-1 3B are programming bias tables of the dual transistor floating gate NMOS NOR flash cell of the present invention. [0158] FIGS. 14A-14B are flowcharts showing the formation of a NOR flash memory. Figure 15 is a schematic illustration of an embodiment of a polymorphic floating gate NMOS NOR flash cell of the present invention. [Main component symbol description] [0160] NMOS NAND flash floating gate transistor: 1 0 [0161] NMOS NOR flash floating gate transistor: 110 [0162] Bungee: 15, 115, 215a, 215b, 415 [0163] Source: 20, 120, 220, 422 [0164] Control gate: 25, 125, 225a, 225b, 425a, 425b [0165] P well: 30, 130, 430 099113777 Form number A0101 Page 64 of 133 0992024278-0 201104843 [0166] Channel area: 32, 132, 432a, 432b [0167] Deep N well: 35, 135, 435 [0168] P-type substrate: 40, 140, 240, 440 [0169] Floating gate: 45 , 145, 245a, 245b, 445a, 445b [0170] Tunnel oxide: 50, 150 [0171] Double transistor floating gate NMOS NOR flash unit: 210 [0172] Floating gate transistor: 205a, 205b 〇 [0173] Base · 2 3 0 〇, 2 3 0.b ^ ' [0174] Metal contact: 250a, 250b [0175] Metal bit line: 255 [0176] NMOS NOR flash memory unit: 400 [0177] NMOS NAND flash floating gate transistor, .: 40.5a, 40:5 b, 515a, i . i .·'"· : \, is' .: g J !| 515b rfVVi:. 〇[0178] Source /Bungee: 420 i [0179] Word line: 4 50a, 450b, 1 025a, 1025b...l 025n, 545 [0180] Bit lines: 455a, 455b, 520a, 520b...520n, 525a, 525b...525n, 805, 815, 1015 [0181] Source line: 460a, 460b, 540a, 540b...540n, 530a, 530b...530n, 825, 1020 [0182] NOR flash memory component: 500 099113777 Form number A0101 Page 65 of 133 page 0992024278-0 201104843 [0183] Crystal Floating Gate NMOS NOR Flash Unit: 510 [0184] Array: 505 [0185] Horizontal Voltage Control Circuit: 5 5 0 [0186] Bit Line Select Control Subcircuit: 551 [0187] Word Line Voltage Control Subcircuit :552 [0188] Source line selection control subcircuit: 553 [0189] Straight line voltage control circuit: 555 [0190] Bit line selection transistor: 560a, 560b...560η, 810 [0191] Source line selection transistor: 565a, 565b...565η, 830 [0192] Bit line selection signal: 57Ga..... 570η [0193] Source line selection signal: 575a, 575b [0194] Control decoder: 605, 705 [0195] Programming timing And control signals: 610, 710 .. ......

[0196] Erase Timing and Control Signals: 615, 715 [0197] Read Timing and Control Signals: 620, 720 [0198] Address Decoder: 625, 725 [0199] Address Signals: 630, 730 [0200] Programming voltage generator: 635, 735 [0201] Pulse increasing voltage generator: 636 0992024278-0 099113777 Form number A0101 Page 66 / 133 pages 201104843 [0202] Positive programming voltage generator: 637 [0203] Negative programming voltage Generator: 638 [0204] Ground reference voltage source: 639, 644, 737, 743 [0205] Erase voltage generator: 640, 740 [0206] Positive erase voltage generator: 642 [0207] Negative erase voltage generation Device: 643 [0208] Read Voltage Generator: 645, 745 〇 ^ [0209] First High Read Voltage Generator: 646 [0210] Second High Read Voltage Generator: 647 [0211] Third High Read Take voltage generator: 648 [0212] Electric waste source generator: 649 [0213] Horizontal selection switch: 650 [0214] Straight line selection switch: 750 ❹ [0215] Programming voltage source: 736 [0216] Erase voltage source: 742 [0217] Moderate high read voltage source: 747 [0218] sense amplifier: 755 [0219] Pole capacitance: 845 [0220] Comparison circuit: 850, 860, 870, 880 099113777 Form number A0101 Page 67 / 133 page 0992024278-0 201104843 [0221] Reference voltage source: 865, 875, 885, 855 [0222] Floating Gate NMOS NOR Flash Unit: 1005 [0223] Floating Gate Crystal: 1010a, 1010b...1010η 099113777 Form No. A0101 Page 68 of 133 C) 0992024278-0

Claims (1)

201104843 Ο G VII. Patent application scope: • A N0R flash memory circuit, including: = number of charge-holding transistors are continuously connected into a -NAND string, where: - the uppermost charge holds the transistor, and its anode is connected a bit line associated with the charge-holding transistor; the lowermost charge-preserving transistor, the secret charge-connecting charge-holding transistor-related source line; and ^ the charge-preserving Each control gate of the transistor is connected to a word line. Such as the dirty flash memory circuit of the first paragraph of the patent scope, the charge storage transistor is formed in the well of the -type conductivity type. , such as the collision and fast __ circuit i of the scope of the patent scope of the application of the fourth type of conductivity type well formed in the first class of the type of guide type _ well. As stated in the third paragraph of the Shenqing patent scope N0R fast The flash-poor body circuit, the second type of conductive deep well is formed in a first conductivity type substrate. For example, the stupid flash memory circuit described in claim 1 of the patent scope, wherein the charge storage transistor of S is subjected to a tunneling effect for a programming operation and an erase operation. An N〇R flash memory circuit as described in claim 1, wherein a programming voltage of +15·0V to +2.00V is applied to a control of a selected charge-storing body and Between the bases, a programming operation is performed with a selected charge holding transistor in the charge holding transistors, wherein the programmed electrical waste is applied to the selected charge holding transistor in a gradually increasing manner. Between the control gate and the base. • The N〇R flash memory Zhao circuit as described in claim 6 of the patent scope, wherein a voltage less than 10·0 V is applied to the other of the charge-storage transistors. Among them, 099113777 Form No. A0101, page 69/ A total of 133 pages 0992024278-0 201104843 The unselected charge holds between the control gate and the base of the transistor to shield the unselected charge from holding the transistor. 8. The NOR flash memory circuit according to claim 1, wherein the layout of the NOR flash memory circuit requires the size of the NOR flash memory circuit to be a manufacturing process of the NOR flash memory circuit. Four to six times the smallest feature size. 9. The NOR flash memory circuit of claim 1, wherein a positive erase voltage of + 15. Ον to + 20. 0V is applied to the base of the selected charge storage transistor and the control gate In between, an erase operation is performed on the selected charge storage transistor. C1 10. The NOR flash memory circuit of claim 6, wherein a bias voltage of 0 V is applied to a control gate of the other unselected charge storage transistor in the charge storage transistor. Between the base and the base, the transistor is held to shield the unselected charges. 11. The NOR flash memory circuit of claim 1, wherein the selected charge holding transistor of the charge holding transistors that are programmed by a single order programming unit performs a read operation. The method includes: connecting a source line to a voltage following sensing circuit; U setting the voltage of the drain and gate of the selected charge holding transistor in the N 0 R flash memory circuit as a voltage source; The voltage of the gate of the unselected charge-storing transistor in the transistor is set to a first high read voltage; and the voltage is compared to the voltage generated at the source line and the reference voltage source in the sensing circuit, the reference voltage The source is set to 2.0 V to distinguish between a threshold voltage at a first logic value and a threshold voltage at a second logic value. 12. The NOR flash memory circuit of claim 11 is 099113777 Form No. A0101, and the first high read voltage is greater than 6.〇v. 13. The N〇R flash memory circuit of claim 2, wherein the reference voltage source is 2, 〇V. ', 14. The N〇R flash memory circuit as described in the scope of the patent application, wherein if the NOR flash memory circuit is not selected for the read operation, and the other N0R flash memory circuit is When the read operation is selected, the voltage of the control gate of the charge-holding transistor that is not selected in the charge-holding transistors in the unselected NOR flash memory circuit is set to the ground reference voltage to turn off the The charge holds the transistor. N15. The NOR flash memory circuit of claim 1, wherein the charge-preserving transistor in the charge-storing transistor in a program operation by a multi-level programming unit performs a read operation And including: connecting the source line to an electric waste following the sensing circuit; setting the voltage of the drain and the gate of the selected charge holding transistor to an intermediate high voltage; storing the electric charge in the transistor · setting the voltage of the gate of all unselected charge-storing transistors to a second high read voltage; and comparing the voltage to the voltage generated at the source line and the complex reference voltage source in the sensing circuit to determine A threshold voltage value is used to represent the data stored in the charge holding transistor. 16. The N〇R flash memory circuit as described in claim 15 wherein the intermediate high voltage is + 4. 〇V ° 17. The flash memory is as described in claim 15 The circuit 'where the second high read voltage is greater than 7.0V. 18. The NOR flash memory circuit of claim 15, wherein the reference voltage source is set between each threshold voltage to be stored separately at 0992024278-0 099113777 Form No. A0101 Page 71 / Total Page 133, 201104843 The charge holds the threshold voltage of the data in the transistor. 19. The NOR flash memory circuit of claim 15, wherein if the NOR flash memory circuit is not selected for reading, and when another NOR flash memory circuit is selected for reading, The voltages of the control gates of the unselected charge-storing transistors in the unselected NOR flash memory circuits in the unselected NOR flash memory circuit are set to a ground reference voltage to turn off the power and save the transistor. 20. An N0R flash memory, comprising: an array comprising a plurality of NOR flash memory circuits arranged in a row and a straight line, wherein each flash memory circuit comprises: €1 every line The plurality of charge-storing transistors are connected in series to form a NAND string; the drain of the uppermost charge-storing transistor in each of the N 0 R flash memory circuits is connected to a straight line corresponding to each N 0 R flash memory circuit a local bit line; the source of the lowest charge holding transistor in each NOR flash memory circuit is connected to a local source corresponding to the straight line where each N 0 R flash memory circuit is located Each of the control gates of the charge holding transistor on each row of _D is commonly connected to a word line. 21. The NOR flash memory of claim 20, wherein the bit line and the source line correspond to a straight line in which the NOR flash memory circuit is located and are parallel. 22. The NOR flash memory of claim 20, further comprising a continuous voltage control circuit for providing a control signal to a local bit line and source corresponding to each row of charge holding transistors Polar line. 099113777 Form No. A0101 Page 72 of 133 Page 0992024278-0 201104843 23 . As claimed in the 22nd paragraph of the patent application, only the flash memory is selected, and each bit of the local bit is selected by a bit line. The crystal is connected to a plurality of global bit lines of 24 25 〇 26 27 〇 28 29 099113777. The NOR flash memory of claim 23, wherein each local source line is selected through a source line. The crystal is connected to one of the plurality of global source lines, such as the Κ0Κ flash memory described in claim 24, wherein the global bit line and the global source line are connected to the straight line voltage control circuit for transmitting The control signal to the selected local bit edge and the selected local source line 'for reading, programming, and wiping the selected charge holding device in the NOR flash memory circuit In addition to the operation. The NOR flash memory described in claim 20 of the patent scope further includes a course voltage control circuit for providing a control signal to a word line corresponding to each row of charge storage transistors. The NOR flash memory according to claim 26, wherein the queue control circuit transmits a control signal to the word line to read the charge handle storage transistor of the NOR flash memory circuit (4) Take operations, program operations, and erase operations. The flash memory described in the second paragraph of the patent, including a 70-line selection control circuit, connecting all local bit line selection gates of the transistor; and a plurality of source line selection transistors, Secret (4) Select electricity (4) Connect to each local bit line. The N〇R flash memory according to claim 20, wherein the row control circuit is configured to transmit a word control signal to the word line, and a form number is 1^73 133 1 to the 09920242, 201104843 30 _Selected fine-grained, programmed operation and erase operation in the flash memory circuit, ::Electric 仃 仃 · · · · · (3) Book 3 (four) control circuit to choose the money and secret line to choose Wei _ The location of the thief selects the transistor and the selected source line transistor to transfer the bit line ^: line: signal from the straight-line voltage control circuit to the selected local: several lines and the selected local source Polar line. ~ 31 32 33 The _ flash memory described in item 20 of the scope of application, in which the electric storage transistor uses a F〇wler_Lim wear-through effect for programming operation and erasing operation. _ flash memory as described in claim 20, wherein a 15.0Vfj + 2G, the programming power of the GV is applied to the control gate and the base of the selected charge-storing electrode In between, to program the selected charge protection transistor. The N〇R flash memory as described in claim 31, wherein - a voltage less than 10.0 V is applied to the control gates of the other unselected charge-preserving transistors in the charge-holding transistors Between the base and the base, the transistor is held to shield the unselected charges. " N0R flash memory as described in claim 20, wherein the N 0 R flash memory circuit layout requires the size of the N 〇 R flash memory circuit to be a NOR flash memory circuit process The technology's smallest feature size is four to six times the size. 34 . 35 . 099113777 NOR flash memory according to claim 20, wherein a positive erase voltage of +1.5 0V to + 2 〇. 0V is applied to the base of the selected charge storage transistor Between the control gate and the control gate, an erase operation is performed on the selected charge storage transistor. For example, the NOR flash memory described in claim 20, wherein _ form number. A0101 page 74 / 133 pages 0992024278-0 201104843 36 . Ο 37 . 38 . ❹ 39 . 40 . 099113777 〇. 〇 A V bias is applied between the other unselected charge holding transistor miscellaneous gates and bases in the charge holding transistor group to mask the unselected charge holding transistors. The ceramic flash memory according to claim 20, wherein the selected charge storage transistor in the charge storage transistor in which the lung operation is performed by the single-stage coding element performs a reading operation, including: Connecting the source line to the _ voltage tracking sensing circuit; setting the voltage of the drain and gate of the selected charge holding transistor in the memory circuit to be the voltage of the voltage source; the charge is not selected in the holding transistor The charge-holding transistor's closed-pole voltage is set to a first high-read voltage; and the voltage is generated at the source line and the reference source is compared to the voltage in the sense circuit, where the reference voltage is set to 2. 〇v to distinguish between a threshold voltage at the first-logic value and a critical electrosurgical pressure at the second logic value. A flash memory as described in claim 36, wherein the first read voltage is greater than 6 〇v. ·: As described in the application for patent verse 36, the reference voltage source is 2. 〇Γ. " 'Eight in the 'Zhezhong' patents NGR flash memory, the unlined and unselected flash memory circuits of the unselected charge-preserving transistor Complex 5r, the sub-electricity is set to the ground reference ", to save the electric voltage with the off charge, as the patent application __ rhyme _ _ = - multi-level programming unit for the operation of the charge protection ^, the selected charge When the save transistor performs a read operation, the source line is connected to a voltage follow-up induction circuit in the crystal; Form number page 75/133 pages 0992024278-0 201104843 Set the selected charge to hold the transistor 汲The voltage of the pole and the gate is an intermediate high voltage; the voltage of the gate of all the unselected electricity and the holding transistor stored in the transistor is set to a second high reading voltage; The voltage follows the voltage developed at the source line and the complex reference voltage source in the sensing circuit to determine a threshold voltage value representative of the data stored in the charge holding transistor. 41. The N0R flash memory of claim 40, wherein the middle high voltage is +4. 0V. 42. The NOR flash memory of claim 40, wherein the second high read voltage is greater than 7.0V » 43. The NOR flash memory of claim 40, wherein A reference voltage source is provided between each threshold voltage to distinguish a threshold voltage of data stored in the charge holding transistor. 44. The NOR flash memory of claim 40, wherein the word line and the unselected NOR flash memory circuit save the unselected charge in the transistor to preserve the transistor The voltage of the complex control gate is set to the ground reference voltage to turn off the charge holding transistor. 45. A method of forming a NOR flash memory, comprising the steps of: providing a substrate; and forming a plurality of N 0 R flash memory circuits into an array comprising a horizontal and a straight line, wherein the NOR flash memory circuit Forming includes the steps of: placing a plurality of charge-preserving transistors in a straight row and a row; linearly connecting the plurality of charge-holding transistors in a straight row to form a NAND string to connect the topmost charge-storing transistor in each NOR flash memory circuit 099113777 Form No. A0101 Page 76 / 133 pages 0992024278-0 201104843 46 . Ο 47 . 48 . ❹ 49 , 50 51 The bungee to a local line corresponding to the straight line where each N 〇 L ^ flash memory circuit is located Bit line; connecting the source of the lowermost charge holding transistor in each NOR flash memory circuit to a local source line corresponding to the straight line where each NOR flash memory circuit is located; and connecting each The complex charge on one column holds each control gate of the transistor to a word line. The method of claim 45, further comprising: the NOR flash memory circuit has a corresponding bit line and source line in each line; and the bit line and the source line are arranged in parallel. . The method of claim 45, wherein the NDR flash memory circuit layout requires that the λ small of the NOR flash memory circuit is the minimum characteristic size of the NOR flash memory circuit. Up to six times, as in the method of claim 45, the method further includes: forming a line voltage control circuit; and, Λ connecting the straight line voltage control circuit to provide a control signal to save power with each line charge The local bit line and source line corresponding to the crystal. The method of claim 45, further comprising: connecting each local bit line to one of the plurality of global bit lines through a one-bit selection transistor. The method of claim 45, further comprising: connecting each local source line to one of the plurality of global source lines through a source line select transistor. For example, the method described in claim 46 includes: 099113777 Form No. Α0101 Page 77/133 Page 0992024278-0 201104843 52 . 53 . 54 . 55 . 56 · 57 . 58 ' 099113777 Will King 7L Line and global source de-connection (4) straight-forward control transmission control signal to selected local bit line and selected source line 'for transistor selected in the _ flash memory circuit Read operations, program operations, and erase operations. How to save The method of applying for the full-time section 46 includes: Forming a horizontal voltage control circuit. The method of applying the patent _52 further includes: ???said the horizontal voltage control circuit ‘to provide at least a control signal to a row of charge storage transistors corresponding to the word line. For example, the method of applying for the scope of patent application 52 also includes: The local source of the 83⁄4 body connected to the foot of the local peach tester. The gate of the transistor connected to each local bit line. The method of claim 54, further comprising: transmitting a signal from the horizontal voltage control circuit to the word line to perform a read operation on the selected charge holding transistor in the flash memory circuit , programming operations and erase operations. The method of claim 55, wherein: the selection control signal is transmitted from the row control circuit to the selected bit line selection transistor and the selected source line selection transistor for using the bit element The line and source line control signals are transmitted from the straight line voltage control circuit to the selected local bit line and the selected local source line. The method of claim 45, wherein the charge storage transistors employ a F〇wier_Nordheim tunneling effect for programming and erasing operations. A method as claimed in claim 45, wherein a programming voltage of + 15.0 V to + 20. 0 V is applied to the charge holding transistors - by 0992024278-0 Form No. A0101 Page 78 of 133 Page 201104843 59 60❹ 61 62G 099113777 The selected charge-holding transistor is between the control gate and the base 'to program the selected charge-storing transistor', wherein the programming voltage is applied to the The selected charge holds between the control gate and the base of the transistor. The method of claim 45, wherein one of the methods is less than 10. The programming mask voltage of 〇v is applied between the control gate and the base of the other unselected charge-storing transistors in the charge-storing transistors. To conserve the unselected charge to hold the transistor. The method of claim 45, wherein applying a negative electrode of + 15. 〇v to + 20. 〇ν erases electricity between the base of the selected charge-preserving transistor and the control gate, The selected charge holding transistor performs an erase operation. The method of claim 45, wherein a bias voltage of two 0.0V is applied between the other unselected charge storage transistor control gates and the bases of the charge storage transistors to shield the same The unselected charge holds the transistor. The method of claim 45, wherein the selected charge-storing transistor in the complex charge-storing transistor in which the single-stage programming unit is programmed is read by the following steps: cation connection source line to one a voltage follow-up sensing circuit; setting a voltage of the drain and gate of the selected charge-holding transistor in the flash memory circuit to a voltage source; the charge-preserving transistor has an unselected charge-preserving transistor The closed-pole voltage is set to a first high read voltage; and the comparison of the electric gate follows the induction circuit to cause the voltage generated at the source line and a reference voltage source 'the reference f noisy setting GV, simplification| Form No. _1 Page 79 / Total (3) Page 0992024278-0 201104843 The threshold voltage of the value and a threshold voltage at the second logic value. 63. The method of claim 62, wherein the first high read voltage is greater than 6.0V. 64. The method of claim 62, wherein the reference voltage source is 2. 0V. 65. The method of claim 62, wherein the word line, that is, the voltage of the unselected NOR flash memory circuit, of the unselected charge storage transistor, the voltage of the plurality of control gates of the transistor. It is set to the ground reference voltage to turn off the charge holding transistor. 66. The method of claim 45, wherein the selected one of the plurality of stages (the % of the plurality of charge-storing transistors selected to save the transistor is read by the following steps: connecting the source a line-to-voltage follow-up sensing circuit; setting the voltage of the drain and gate of the selected charge-storing transistor to an intermediate high voltage; all the unselected electricity within the cell 4 holding the transistor The gate voltage is set to a second high read voltage; and the comparison voltage follows the voltage generated at the source line and the complex reference U voltage source in the sense circuit to determine a threshold voltage value for use in the charge storage transistor The method of claim 66, wherein the high voltage of the standard is +4.0 V. 68. The method of claim 66, wherein the second high read voltage More than 7. 0V ^ 69. The method of claim 66, wherein the reference voltage source is set between each threshold voltage to be separately stored in the charge storage transistor 0991 13777 Form No. A0101 Page 80 of 133 Page 0992024278-0 201104843 70 . 71 · Ο ❹ 72. The threshold voltage of the data. For example, the method described in claim 66, wherein the word line, that is, The voltage of the complex control gate of the unselected charge-storing transistor in the charge-storing transistor of the selected NOR flash memory circuit is set to the ground reference voltage* to turn off the current and save the transistor. The method includes: an array comprising a plurality of NAND flash memory circuits, each NAND flash memory circuit comprising: a plurality of charge-storing transistors arranged in a row and a straight line, wherein the charge on each of the lines preserves the transistor to be linear Connected into a NAND string, each NAND string has an upper selection transistor and a lower selection transistor; an array comprising a plurality of NOR flash memory circuits, wherein each NOR flash memory circuit comprises: a plurality of charge storage transistors, Arranged into a horizontal row and a straight line, wherein each row of charge-holding transistor groups is linearly connected into a NAND string, wherein the dance-N0R flashes The drain of the uppermost charge-preserving transistor in the memory circuit is connected to a corresponding local bit line in the straight line where each of the NOR flash memory circuits is located, wherein the lowest end of each of the NOR flash memory circuits The source of the charge-storing transistor is connected to a corresponding local source line in a straight row in which each N 0 R flash memory circuit is located, wherein each of the plurality of charge-preserving transistors in each row holds the control The gate is connected to a word line. The integrated circuit device according to claim 71, wherein in each of the NOR flash memory circuits, the bit line and the source line and the NOR flash memory circuit are The straight line in which it is located corresponds and is parallel. The integrated circuit device of claim 71, wherein each of the NOR flash memory circuits comprises a line voltage control circuit for providing 099113777 form number A0101 page 81 / page 133 0992024278-0 73 . 201104843 74 . 75 . 76 . 77 . 78 · 79 80 Control signals to the local bit line and source line corresponding to the charge holding transistor in each row. The integrated circuit device of claim 71, wherein in each of the NOR flash memory circuits, each local bit line is connected to the plurality of global bit lines through a one-element selection transistor. one. The integrated circuit device of claim 74, wherein in each of the NOR flash memory circuits, each local source line is connected to the plurality of global source lines through a source line selection transistor. one. The integrated circuit device of claim 75, wherein in each of the NOR flash memory circuits, the global bit line and the global source line are connected to the 直 straight-line voltage control circuit for transmitting the control signal to The selected local bit line and the selected local source line are used to perform read operations, program operations, and erase operations on the selected charge holding transistors in the NOR flash memory circuit. The integrated circuit device of claim 74, wherein each of the NOR flash memory circuits includes a horizontal voltage control circuit for providing a control signal to correspond to each of the row charge storage transistors. Word line. The integrated circuit device of claim 77, wherein in each CJ NOR flash memory circuit, the row control circuit transmits a signal to a word line to be used in the NOR flash memory circuit. The selected charge holding transistor performs a read operation, a program operation, and an erase operation. The integrated circuit device of claim 78, wherein each of the NOR flash memory circuits further comprises a bit line selection control circuit, and the bit line selection control circuit is connected to all local bit lines to select electricity. The gate of the crystal, the complex source line select transistor is connected to each local bit line. The integrated circuit device as described in claim 71, wherein each 099113777 form number A0101 page 82 / 133 page 0992024278-0 201104843 81 · G 82 . 83 .Ο 84 · 099113777 NOR flash memory In the circuit, the row control circuit transmits the word line control signal to the word line “fast” (four), and the charge storage transistor performs the read operation, the programming operation and the erase operation, and the row control circuit further The transfer bit line selection signal and the source line selection signal are respectively selected to the selected bit it line selection transistor and the selected source line transistor to reduce the bit line and the impurity line (4) from the straight line voltage (four) electric material It is the turn of the selected local bit line and the selected local source line. The integrated circuit device according to claim 71, wherein in each of the hidden flash memory circuits, the charge storage transistors are subjected to a Powler^ordheim tunneling effect for programming operation and erasing operation. For example, in the application of the patent scope, item 71, in which the integrated circuit is installed, in each NOR flash memory circuit, a +15 .〇v to the ship shouting programming voltage is applied to the plurality of charge bribes - The selected charge holds between the control gate and the base of the transistor to program the charge transistor into a single-order programming unit' wherein the programming voltage is applied to the selected charge scale transistor in a stepwise increasing step (four) _ secret between. For example, in the circuit device of claim 82, wherein in each R-flashing circuit, the programming masking voltage of less than -1Q.GV is applied to the plurality of f-charged electric crystal (four) towels. Other unselected charges preserve the control of the electro-lumps between the bases to shield the unsupported charges from preserving the transistors. The apparatus circuit of claim 71, wherein in each of the flash memory circuits, the NOR flash memory circuit layout requires the size of the paste R flash memory circuit to be N 〇 The R flash flash memory circuit technology is four to six times the smallest feature size. The integrated circuit device as described in claim 71, wherein in each form number A0101, page 83 / page 0992024278-0 85 . 201104843 NOR flash memory circuit, one + 15. 0V to + 20 A negative erase voltage of 0 V is applied between the base of the selected charge holding transistor and the control gate to perform an erase operation on the selected charge holding transistor. 86. The integrated circuit device of claim 71, wherein in each of the NOR flash memory circuits, a bias of 0.0 V is applied to the other unselected ones of the charge holding transistors. A charge is held between the control gate and the base of the transistor to shield the unselected charge from holding the transistor. 87. The integrated circuit device of claim 71, wherein in each of the NOR flash memory circuits, a selected charge-storing device programmed into a single-order programming unit in the plurality of charge-storing transistors The crystal is read by the following steps: connecting the source line to a voltage follow-up sensing circuit; setting the voltage of the drain and gate of the selected charge-holding transistor in the N 0 R flash memory circuit to a voltage source a voltage; the voltage of the gate of the unselected electrical and holding transistor is set to a first high read voltage; and comparing the voltage to the voltage generated at the source line in the sensing circuit And a reference voltage source, the reference voltage source is set to 2.0V to distinguish a threshold voltage at the first logic value and a threshold voltage at the second logic value. The first high-reading voltage is greater than 6.0V in each of the NOx flash memory circuits, as described in claim 87. The voltage of the reference voltage source is 2.0 V in each of the NOR flash memory circuits. 90. The integrated circuit device of claim 87, wherein the word line, that is, the unselected N 0 R flash memory circuit, of the uncharged charge in the charge holding transistor The voltage of the complex control gate of the transistor is 099113777 Form No. A0101 Page 84 / Total 133 Page 0992024278-0 201104843 91 ❹ 92 93 Ο 94 . Such as 95 House 099113777, to close the charge to save the crystal form number Α 0101 set to the ground reference voltage To save the transistor by turning off the charge. The integrated circuit device of claim 71, wherein in each of the flash memory circuits, the selected charge-preserving transistor in the plurality of charge-preserving transistors programmed into a multi-level programming unit It is read by the following steps: connecting the source line to a voltage following sensing circuit; setting the voltage of the drain and gate of the selected charge holding transistor to an intermediate high voltage; storing the charge in the transistor group (10) The voltage of the idle pole of the unselected _charge-storing transistor is set to a second high-reading power; and the comparison of the inductive-inductive power is made. In the secret line, the voltage and the complex reference voltage source 'mosquito-critical Electricity (4) is used to represent the data stored in the charge-storing transistor. η~ As in the circuit device described in item 91 of the patent application, the voltage in the NOR flash memory circuit is +4.0V». In the flash memory circuit of the patent described in Item 91, the first '2' is placed in each of the applications such as Shenjing's patent voltage is greater than 7.〇v. The integrated circuit device described in the flash flash/physical item, wherein between each (four) (four), the reference voltage source is set at each threshold. The screaming of the electric power of the electric storage (10) _ data, such as the scope of the patent application, that is, the selection of the circuit device is not selected, in which the word 1 is in the unselected 峋 flash memory # The charge of the unselected "luster in the crystal is saved to the grounding parameter/the complex control of the holding transistor_Electric-repeat body page 85/133 pages 0992024278-0