TWI868192B - Reduced resistivity traces in multilayered printed circuit boards and methods of forming - Google Patents

Abstract

The disclosure relates to methods for forming multilayered printed circuit boards (PCBs), flexible printed circuits (FPCs) and high-density interconnect (HDI) printed circuits and methods of forming these. Specifically, the disclosure relates to methods for direct inkjet printing of traces having predetermined resistivity for use in multilayered printed circuit boards (PCBs), flexible printed circuits (FPCs) and high-density interconnect (HDI) printed circuits, by printing intermediate traces coupled to the external trace with a plurality of blind and/or buried vias.

Description

Traces with reduced resistivity in multi-layer printed circuit boards and methods of forming the same

The present disclosure relates to methods for forming multi-layer printed circuit boards (PCBs), flexible printed circuits (FPCs), and high density interconnect (HDI) printed circuits, collectively referred to as multi-layer fabricated electronic devices (AMEs), and methods for forming such AMEs. Specifically, the present disclosure relates to methods for inkjet printing traces having a predetermined resistivity for use in multi-layer printed circuit boards (PCBs), flexible printed circuits (FPCs), and high density interconnect (HDI) printed circuits.

High-power electronic components such as central processing units (CPUs) and graphics processing units (GPUs) as well as power supply units (PSUs) generate a lot of heat during operation. In order to increase computing performance, for example by overclocking (in other words, increasing the clock frequency above the standard frequency used by the manufacturer) within strict packaging constraints, many of these components generate additional heat that the provided cooling systems (e.g., cooling fans) cannot adequately dissipate.

Additionally, there is an increasing need for electronic devices with small form factors in all of the following fields, such as: manufacturing, commercial, consumer, military, aviation, Internet of Things, etc. Products with these smaller form factors rely on compact PCBs with closely spaced digital and analog circuits placed very closely on the outer surface. Increased device complexity may also cause the number of PCB layers to increase significantly to account for, for example, increased functionality requirements and the need for smaller footprints and form factors, such as those required in mobile communication devices and computing devices.

Furthermore, as active devices continue to shrink in size and packaged in advanced packages and chip scale packages (CSPs) increase the complexity and problems associated with small form factor PCBs, OEMs require fewer "parasitic" or "bleeding" interconnects and better yields associated with these (small form factor) designs. All of these requirements require minimizing the connection length between these active devices without compromising resistivity and robustness to various temperature changes during operation.

The following disclosure solves these shortcomings.

In various exemplary implementations, methods and systems for collectively forming multi-layer printed circuit boards (PCBs), flexible printed circuits (FPCs), and high density interconnect (HDI) printed circuits (possibly together with additional integrated circuits, collectively referred to as interlayer fabricated electronic devices (AMEs)) and methods of forming such AMEs are disclosed. Specifically, the disclosure relates to methods for inkjet printing traces having a predetermined resistivity for use in multi-layer AMEs.

In an exemplary implementation, a method of reducing trace resistivity between at least two connected components in a multi-layered electronic device (AME) is provided herein, comprising: forming at least one trace on an intermediate layer, thereby forming an intermediate trace; forming a trace sized and configured to operably couple at least two components on at least one of: an external top layer and an external base layer of the multi-layered AME, thereby forming at least one external trace; and forming a predetermined number of at least one of: a blind via and a buried via, the predetermined number of vias sized and configured to electrically couple at least one intermediate trace and a corresponding external trace of the multi-layered AME.

In another embodiment, a multi-layer AME is provided herein, comprising: at least one intermediate trace on an intermediate layer; an external trace sized and configured to operably couple at least two components on at least one of: an external top layer and an external base layer of the multi-layer AME; and at least one of a predetermined number of: a blind via and a buried via, the blind via and the buried via electrically coupling the at least one intermediate trace and the external trace.

In yet another embodiment, a computerized method for using an inkjet printer to fabricate a trace with reduced resistivity between at least two connected components in a multi-layer printed circuit board (PCB) is provided herein, comprising: providing an inkjet printing system, comprising: a first print head operable to dispense a dielectric ink composition; a second print head operable to dispense a conductive ink composition; a conveyor operably coupled to the first print head and the second print head, the conveyor configured to transport a substrate to each of the first print head and the second print head; and a computer-aided manufacturing ("CAM") module including a central processing module (CPM), the CAM being coupled to one of the first print head and the second print head. each, wherein the CPM further comprises: at least one processor in communication with a non-transitory storage medium, a set of executable instructions stored on the non-transitory storage medium being configured to cause the CPM to perform the following steps when executed: receiving a 3D visualization file representing multiple layers of AME having traces with reduced resistivity; and generating a file library having a plurality of files, each file representing a substantially 2D layer for printing LPF and a meta file representing at least a printing order; wherein the CAM module is configured to control each of the conveyor, the first print head and the second print head; providing the dielectric ink composition and the conductive ink composition; using the CAM module, obtaining from the library a file representing a plurality of layers of AME having traces with reduced resistivity; and A first file of a first layer of the multi-layer AME having traces with reduced resistivity, the first file comprising print instructions representing a pattern of at least one of the following: the dielectric ink and the conductive ink; using the first print head to form the pattern corresponding to the dielectric ink; using an electromagnetic radiation source to cure the pattern represented by the dielectric ink in the 2D layer corresponding to the multi-layer PCB; using the second print head to form the pattern corresponding to the conductive ink; using heat to sinter the pattern corresponding to the conductive ink; using the CAM module, obtaining from the library a subsequent file representing a subsequent layer of the multi-layer AME having traces with reduced resistivity, the subsequent file comprising print instructions representing a pattern of at least one of the following: the dielectric ink and the conductive ink; The method comprises the steps of: forming a first print head and a second ...

These and other features of the method for forming traces with selectively reduced resistivity in a multi-layer printed circuit board will become apparent from the following detailed description when read in conjunction with the drawings and examples, which are intended to be illustrative and not limiting.

Exemplary implementations of methods for forming traces with selectively reduced resistivity in multi-layer printed circuit boards are provided herein.

Typically, calculating the resistance of a PCB trace is as simple as using Ohm's law (V=I/R) with known parameters. Additionally, the resistance of the final trace on the board can be estimated by providing the desired manufacturing outline and calculating the resistance using the standard formula: (Equation 1) Where - R is the resistivity in ohm∙m; - ρ is the material specific resistivity coefficient; - L is the trace length; - h is the trace thickness; - W is the trace width; - a is the (material specific) resistivity temperature coefficient; and - ΔT is the temperature difference between the operating temperature and the reference temperature, typically 25°C.

Table I provides some examples of r and a for some commonly used trace materials: Table I : Material specific resistivity parameters: Material ρ (ohm∙m) α (℃ ^-1 ) Copper ^1.6x10-8 0.0039 Silver ^1.7x10-8 0.0038 gold ^2.2x10-8 0.0034

Therefore, in the case of high component densities, which are sometimes accompanied by high temperature generating components such as PSUs and GPUs and the requirement to shorten trace lengths, it is reasonable to expect higher trace resistivity. In addition, these calculations can only determine approximate values. The actual values after production will vary to some extent.

High power components such as converters (e.g. A/D, D/A) and the circuits that couple these components are greatly affected by these constraints and any unexpected changes in resistivity, which may result in power loss. In such power circuits, uncompensated AME trace resistance may act as a fuse and burn the trace under power surge conditions, causing permanent damage to the circuit. In addition, in high-speed digital board PCBs, trace resistance and parasitic capacitance may generate oscillations and generate electromagnetic (EM) interference to the circuit system.

The method described herein can be used to form a multi-layer AME with selectively reduced resistivity traces using an inkjet printing device in a continuous process or using several passes. Typically, the dielectric material used to form the board is formed separately and provided as a substrate for further printing of conductive and dielectric layers on top of the substrate. Using the printing method described herein, it is possible to achieve selectively reduced resistivity traces, allowing for increased component density and increased design flexibility.

Conventional methods for forming the multi-layer AME disclosed herein are well-known methods for producing electronic components such as RFID antennas and circuit boards, and involve multi-step subtractive processes involving etching or stamping of copper/silver films. Additionally or alternatively, the systems, methods, and compositions described herein can be used to form/fabricate multi-layer AMEs with traces whose resistivity is selectively reduced (in other words, calculated without affecting other components in outer or intermediate layers) using a combination of a print head and a conductive and dielectric ink composition in a continuous process (in other words, in a single pass) or in a semi-continuous additive manufacturing (AM) process using an inkjet printing device or using several passes.

Although reference is made to inkjet inks and dispensing systems thereof, other additive manufacturing (AM) methods are also contemplated in the implementation of the disclosed methods. In an exemplary embodiment, a multi-layer PCB having traces with selectively reduced resistivity may likewise be manufactured by a selective laser sintering (SLS) process, but any other suitable additive manufacturing process (also known as rapid prototyping, rapid manufacturing, and 3D printing methods) may also be used, alone or in combination. Such processes may be, for example, direct metal laser sintering (DMLS), electron beam melting (EBM), selective thermal sintering (SHS), or stereolithography (SLA).

Multi-layer PCBs with traces having optionally reduced resistivity can be made from any suitable laminated fabrication material, such as metal powders (e.g., silver, gold, cobalt chromium, steel, aluminum, titanium and/or nickel alloys), gas atomized metal powders, thermoplastic plastic powders (e.g., polylactic acid (PLA), acrylonitrile butadiene styrene (ABS) and/or high-density polyethylene (HDPE)), photopolymer resins (e.g., UV-curable photopolymers such as PMMA), thermosetting resins, thermoplastic resins, or any other suitable material that achieves the functionality described herein.

Depending on the type of metal particles (e.g., silver, copper, gold, platinum, aluminum, etc.) and the aspect ratio (the ratio between the length of the metal particles and their respective thickness or diameter), the maximum theoretical conductivity achievable in a conductive ink composition for inkjet printing can be a fraction of the bulk conductivity of the same metal, for example, between about 10% and about 90%, or between about 20% and about 80%, or in another example, between about 30% and about 70%, or 50%, compared to a pure bulk metal.

For example, the conductive material used to form the traces is silver nanoparticles. Silver (Ag) has the highest electrical conductivity among conductive metals such as silver, copper, gold, aluminum, and nickel (see, e.g., Table I). In addition, silver remains conductive when oxidized, while copper does not. In the context of the present disclosure, nanoparticles are defined particles having a volume average particle size (D _3,2 , which may be important for obtaining a proper aspect ratio) of less than 1 micron, e.g., less than about 0.5 micron or less than about 0.2 micron. Nanoparticles can benefit inkjet printing applications by enabling low ink viscosity even at very high conductive material content or loading (thus ensuring that 2D (on a single layer) and 3D (for trace-on-trace) bond percolation thresholds are exceeded), as well as preventing nozzle clogging on inkjet printhead dispensers.

In practice, it has been observed that the thicker the trace is printed, the more difficult it is to achieve particle-specific (i.e., metal type [e.g., silver] and geometry [e.g., aspect ratio of at least 2:1]) theoretical conductivity. In one example, a typical trace formed using a conductive ink with silver nanoparticles achieved 30% conductivity (relative to bulk silver) at a layer thickness ( h ) of 17 µm (for a trace length that yielded 0.5 Oz of total bulk silver weight), and the resistance of the trace was measured to be 1.0 Ohm. Using the same geometry and Equation 1 to reduce the resistance to 0.25 ohms or less, typically the trace thickness would increase by at least 4 times to approximately 68 to 71µm (2.0 Oz Silver for the same trace length). However, when the trace thickness was increased to a thickness of 68 to 71µm, the observed resistance was higher than the calculated (using Equation 1) 0.25 ohms (Ω>0.25 ohms).

Without theoretical constraints, it is assumed that the geometry of the nanoparticles affects the 2D bond penetration threshold (which can be distinguished from the pore penetration threshold), especially when the aspect ratio is r >> 1 ( r >> 1), so that the higher the aspect ratio, the lower the 2D bond penetration threshold. For example, the 2D bond spread threshold for silver nanoparticles (having an aspect ratio, e.g., between about 2:1 and 5:1 or 10:1) is about 80 wt% based on the total solids in the sintered traces (which corresponds to a fractional concentration of about 28% (v/v) in the ink), while for carbon nanotubes/nanoribbons (having much higher aspect ratios, e.g., in the range of 15:1 to 1,000:1), the spread threshold may already be a few wt% (and even lower fractional volume). When the 2D bond penetration threshold is reached (or exceeded), the resistivity of the sintered trace decreases significantly and tends to be stable as the conductive material loading is further increased (e.g., the nanoparticle fraction volume concentration increases). In the context of the present disclosure, the 2D bond penetration threshold is defined as the point where the conductive materials in the trace touch and form a continuous trace in the XY plane of the trace.

Again without theoretical constraints, while exceeding the 2D bond penetration threshold at a given trace thickness will be sufficient to reduce the resistivity to a given value (e.g., 30% of bulk metal conductivity), increasing the thickness will produce traces with a fractional volume concentration of metal nanoparticles greater than the 2D bond penetration threshold but less than the 3D bond penetration threshold (which is defined as the fractional volume concentration at which the conductive material (particles) in the trace touch and form a continuous bulk in the trace in any direction).

Therefore, and in an exemplary implementation, and to address some of the deficiencies in the current state of multi-layer AMEs formed by either reduction methods or layered fabrication methods, a method of reducing the resistivity of a trace between at least two connected components in an AME is provided herein, comprising: forming at least one trace on an intermediate layer (thereby forming an intermediate trace); forming at least one trace sized and configured to be between: At least two components are operably coupled on at least one of: an external top layer and an external base layer of the AME; and a predetermined number of at least one of the following: a blind via and a buried via are formed, the predetermined number of vias being sized and configured to electrically couple at least one trace on the intermediate layer (intermediate trace) with a trace formed on at least one of the following (in other words, corresponding to the external trace): the external top layer and the external base layer of the AME. For components having an AME coupled to any side plane, wall or side of the AME, the disclosed methods and systems can be used to similarly reduce trace resistivity, thereby coupling such side-mounted components with the remainder of the AME topology.

In a typical extraction method, a through hole is first formed in a copper laminated plate, such as a copper foil, and the substrate is continuously subjected to an electrodeless copper (or other metal, such as silver) electroplating process to form the plated through hole. Then, a trace pattern is formed by etching the surface of the metal-plated substrate with a predetermined pattern, and then the surface of the trace pattern is roughened by electroless plating or etching and the like. Continuously, a resin insulating layer is formed on the trace pattern having a rough surface, and then subjected to exposure and development treatment to form an opening portion of a through hole (through hole, buried via or blind via), and thereafter, an interlayer resin insulating layer is formed by depositing a dielectric resin, UV curing and optionally main curing. After the interlayer resin insulating layer (in other words, the intermediate layer) is generally subjected to a roughening treatment by an acid or an oxidizing agent, an electroless plating film is formed on the electroless plating film, and then the electroless plating film is thickened by electroplating. After separating the plating resist, etching can be performed to form a trace pattern connected to the under-level trace pattern through a through hole. When all the intermediate layers are finally formed in this way, a solder resist layer is formed to protect the conductor circuit, and the portion of the trace pattern exposed for connection with the electronic part (e.g., IC chip or motherboard and the like) is electroplated, and then solder bumps are formed by depositing (e.g., by printing or otherwise dispensing) solder paste to complete the manufacture of the assembled multi-layer PCB.

Alternatively, in another example, through holes may be formed in a metal clad laminate having a metal foil carried thereon, and then subjected to electroless metal plating to provide plated through holes therein. The surface of the substrate is then etched imagewise (in other words, according to a grating file) to provide a trace pattern thereon. By performing electroless plating or etching on this trace pattern, the trace pattern has a rough surface, and an intermediate resin insulation layer including epoxy resin, acrylic resin, fluororesin or a mixed resin thereof is constructed on the rough surface. Then, through holes are formed by exposure and development or laser treatment, and the resin is UV cured and, if necessary, post-cured to provide a target interlayer resin insulation layer. This interlayer resin insulation layer is also subjected to surface roughening treatment, and then, a thin metal layer by electrodeless plating is formed on the interlayer resin insulation layer. Thereafter, an anti-plating agent is placed on the electrodeless plated metal layer, and then a thick plating layer is formed. The anti-plating agent is then stripped off and etching is performed to provide a trace pattern connected to the underlying trace pattern by means of a through hole. Here, the sequence of the above steps is also repeated, and then, a solder resist layer for protecting the trace pattern is formed as the outermost layer (in other words, an external top layer or an external base layer). This solder resist layer is formed with an opening, and the conductive trace layer in the area corresponding to the opening is electroplated to provide a contact pad. Solder bumps can then be formed or otherwise deposited on and/or around the contact pad to complete the manufacture of this example of a modular multi-layer AME.

In another embodiment, inkjet printing is used to form a multi-layer AME having traces with selectively lower resistivity. For example, a computerized method of using an inkjet printer to manufacture traces with reduced resistivity between at least two connected components in a multi-layer AME is disclosed, comprising: providing an inkjet printing system, comprising: a first print head operable to dispense a dielectric ink composition; a second print head operable to dispense a conductive ink composition; a conveyor operably coupled to the first print head and the second print head, the conveyor configured to transport a substrate to each of the first print head and the second print head; and a computer-aided manufacturing ("CAM") module, comprising a central processing module (CPM), the CAM communicating with each of the first print head and the second print head, wherein The CPM further comprises: at least one processor in communication with a non-transitory storage medium, a set of executable instructions stored on the non-transitory storage medium configured to cause the CPM to perform the following steps when executed: receiving a 3D visualization file representing multiple layers of AME with traces having reduced resistivity; and generating a file library having a plurality of files, each file representing a substantially 2D layer for printing LPF and a metafile representing at least a printing order; wherein the CAM module is configured to control each of the conveyor, the first print head, and the second print head; providing a dielectric ink composition and a conductive ink composition; using the CAM module, obtaining from the library a 3D visualization file representing a trace for printing LPF with reduced resistivity; A first file of a first layer of a multi-layer AME having traces with a resistivity-reduced pattern, the first file including printing instructions for patterns representing at least one of the following: dielectric ink and conductive ink; using a first print head to form a pattern corresponding to the dielectric ink; using an electromagnetic radiation source to cure the pattern represented by the dielectric ink in a 2D layer corresponding to the multi-layer PCB; using a second print head to form a pattern corresponding to the conductive ink; using heat to sinter the pattern corresponding to the conductive ink; using a CAM module to obtain from a library a subsequent file representing a subsequent layer of a multi-layer AME having traces with reduced resistivity, the subsequent file including printing instructions for patterns representing at least one of the following: dielectric ink and conductive ink ; repeating the following steps: using a first print head to form a pattern corresponding to the dielectric ink until a subsequent substantially 2D layer is obtained from a 2D file library using a CAM module, wherein after the conductive ink pattern is sintered in the final substantially 2D layer, the multi-layer AME is configured to include: at least one intermediate trace, which is on an intermediate layer; at least one external trace, which is sized and configured to operably couple at least two components on at least one of the following: an external top layer and an external base layer of the multi-layer AME; and a predetermined number of at least one of the following: a blind via and a buried via, the blind via and the buried via electrically coupling at least one intermediate trace with the external trace; and removing the substrate.

In one exemplary embodiment, the term "dispensing" is used to refer to the operation of a device from which ink droplets are dispensed, such as a print head acting as a dispenser. A dispenser may be, for example, a device used to dispense small amounts of liquid, including microvalves, piezoelectric dispensers, continuous jet print heads, boiling (bubble jet) dispensers, and other devices that affect the temperature and properties of the fluid flowing through the dispenser. In one exemplary embodiment, the term "print head" and the term "dispenser" are interchangeable.

In addition, an exemplary implementation of a multi-layer AME is also provided herein, which includes: at least one trace on an intermediate layer; a trace that is sized and configured to operably couple at least two components on at least one of the following: an external top layer and an external base layer of a PCB; and a predetermined number of at least one of the following: a blind via and a buried via, the blind via and the buried via electrically coupling at least one trace on the intermediate layer with a trace on at least one of the following: an external top layer and an external base layer of the multi-layer AME.

In the context of the present disclosure, it should be understood that a through hole that spans multiple layers of AME, across all layers, such as from a top external layer to an external base layer (e.g., "Z direction") is referred to as a "through hole", which may be plated or filled (using a conductive metal such as silver, copper, gold, aluminum, nickel, etc.), and starts at a top external layer or a base external layer; and a through hole that terminates at any intermediate layer is referred to as a "blind via"; and a through hole between any two intermediate layers (whether adjacent to each other or not) is referred to as a "buried via".

A more comprehensive understanding of the components, methods, and devices disclosed herein may be obtained by reference to the accompanying drawings. These drawings (also referred to herein as "figures") are schematic representations based on the convenience and simplicity of illustrating the present disclosure, and therefore are not intended to indicate the relative size and dimensions of the device or its components, their relative size relationships, and/or to define or limit the scope of the exemplary implementation. Although specific terms are used in the following description for clarity, these terms are only intended to refer to the specific structures of the exemplary implementations selected for the illustration of the drawings, and are not intended to define or limit the scope of the present disclosure. In the drawings and the following description, it should be understood that the same numerical designations refer to components with the same functions. Likewise, reference is made to a cross section on a normal orthogonal coordinate device having XYZ axes, such that the Y axis refers to front and back, the X axis refers to side to side, and the Z axis refers to up and down.

Turning now to Figures 1 and 2, Figure 1 shows the current state when two conductive external traces 103i are above a grounded external base plane 101 of a multi-layer PCB 100. Also shown are contact pads 104j, which are coupled to the external base (ground) plane 101 by a plurality of through-holes 107k. It should be noted that dielectric/insulating intermediate layers are not shown in Figures 1 and 2, thus implying the number of intermediate layers that would result in a thickness h (see, e.g., Figure 2) of the multi-layer PCB 100 in the Z direction, and assuming that the external traces 103i (Figure 1) and 203i (Figure 2) are deposited on external top layers 102, 202 and/or external base layers 101, 201. In addition, the conductive external traces 103i are each shown as terminating in a coupled contact pad 104j, in which solder bumps may be disposed. As indicated (see, e.g., Equation 1), in conventional manufacturing processes, the resistivity may be reduced by increasing the surface area of the traces 103i, by increasing the width W of the traces 103i (see, e.g., FIG. 1 ), or by increasing the length of the traces as shown in 303i of FIG. 3 . Similarly, separate contact pads 106q are also shown as being very close to the termination contact pads 104j, and coupled to the substrate external layer 102 along with through-holes 107k.

However, there are some situations where either option (e.g., increasing the length and/or width of the trace) is not feasible, such as when the traces between components need to be kept as short as possible (e.g., placing bypass capacitors as close as possible to their corresponding ICs) so that the lengths shown in Figure 3 do not increase, and/or when a high density of component surfaces is required, such as in cell phones or high density interconnect PCBs (HDI), where portability (demanding miniaturization), performance (demanding increased processing speeds, thereby shortening traces), and components (demanding more leads in a smaller footprint) all require denser interconnects, shorter trace and gap sizes, smaller diameter vias, and more buried vias.

Thus, a method provided herein for forming a multi-layer AME 200 having a trace having a selectively lower resistivity (compared to a trace of the same length made without the methods disclosed herein) includes (see, e.g., FIG. 2 ): forming at least one middle trace 213 i on a middle layer; forming outer traces 203 i sized and configured to operably couple at least two components on at least one of the following: the multi-layer AME 200; and forming a predetermined number of at least one of the following: blind vias 224k, 233k and buried vias 225k, 226k, the predetermined number of vias being sized and configured to electrically couple at least one intermediate trace 213i with an external trace 203i formed on at least one of the following: the external top layer 202 and the external base layer 201 of the multi-layer AME 200.

In addition, the method includes forming at least one contact pad 204j at a terminal end (end) of an external trace 203i, the contact pad being adapted, sized and configured to be operably coupled to a component 500n, the external trace being sized and configured to be operably coupled to at least two components 500n (not shown). The component 500n may be, for example, at least one of a quad flat package (QFP) package, a thin small outline package (TSOP), a small outline integrated circuit (SOIC) package, a small outline J-lead (SOJ) package, a plastic leaded chip carrier (PLCC) package, a wafer level chip scale package (WLCSP), a mold array process-ball grid array (MAPBGA) package, a quad flat no-lead (QFN) package, a land grid array (LGA) package, and a bypass capacitor.

Therefore, the combined resistivity Ω of a predetermined number of blind vias 224k, 233k and buried vias 225k, 226k; at least one intermediate trace 213i; and at least one of the external traces 203i is configured to provide a resistivity Ω that is a predetermined fraction of the resistivity Ω of the external traces 103i, 203i only in the absence of at least one of the following being coupled: blind vias 224k, 233k and buried vias 225k, 226k; and at least one intermediate trace 213i. Without being bound by theory, it is estimated that the initial thickness of the outer traces 103i, 203i produces a fixed and known resistivity for a given length, which when substantially repeated in the middle trace 213i and coupled with the blind vias 224k, 233k and buried vias 225k, 226k, will produce a selectable and predictable resistivity of the resulting enhanced trace 253i.

For example, the method provided herein for forming a multi-layer PCB 200 having traces with selectively low resistivity further includes forming a plurality of (2 or more) intermediate traces 213i, each of which is disposed in a separate layer along a vertical axis Z of the multi-layer PCB 200. In addition, each of the plurality of intermediate traces 213i is coupled to an adjacent intermediate trace, thereby forming a plurality of buried vias 225k, 226k between the adjacent intermediate traces 213i. It should be noted that the intermediate trace 213i may have a width W that is different from any adjacent intermediate trace 213i and may be wider or narrower based on other parameters and factors associated with trace packaging. In addition, the buried vias 225k, 226k and the blind vias 224k, 233k are not necessarily vertical, but can be tilted at non-vertical angles (e.g., the Z direction, see FIG. 2). Similarly, the grid 253 (also referred to as a lattice in some examples) formed by the coupled traces is not formed with uniform openings throughout the process.

As shown in FIG2 , the intermediate traces 213i each terminate in a terminal buried via 226k, and the intermediate traces 213i are immediately coupled to the external traces 203i through the terminal blind via 233k. When there are a large number of intermediate traces 213i, and in order not to hinder the conductivity with the contact pad 204j or the external trace 203i, it may be advantageous to form the terminal blind via 233k (and/or the non-terminal blind via 224k) to have a cross-section that is larger in area (e.g., larger in diameter) than each non-terminal buried via 225k. Similarly, in an example, the terminal buried via 226k will also be formed to have a cross-section that is larger in area (e.g., larger in diameter) than each non-terminal buried via 225k. Furthermore, in another example, as the middle trace 213i gets closer to the outer trace 203i, the cross-section of each non-terminal buried via 225k will increase, thereby actually forming a single conical blind via with the substrate outer trace 203i.

As shown in FIG. 2 , the method provided herein for forming a multi-layer PCB 200 having traces with optionally lower resistivity is configured such that when a lattice 253i extending vertically (in the Z direction) from the external traces 203i is completed, at least one of the following is formed: a predetermined number of non-end blind vias 224k, non-end buried vias 225k, end buried vias 226k, and end blind vias 233k and at least one of a plurality of intermediate traces 213i. As used herein, the term "lattice" refers to an open frame made of metal strips (e.g., middle trace 213i and outer traces 203i) that are overlapped or interlaced in a regular pattern and connected by a regular pattern of vertical components (e.g., buried vias 225k, 226k and blind vias 224k, 233k).

A method of forming a PCB using a computerized inkjet printing system disclosed herein may include the step of providing a substrate (e.g., a peelable substrate such as a film). A print head (and its derivatives; which should be understood to refer to any device or technology that deposits, transfers, or produces material on a surface in a controlled manner) that deposits dielectric ink can be configured to provide ink droplets on demand, in other words, as a function of various process parameters such as conveyor speed, desired PCB sublayer thickness (whether vias or heat pipes are filled or plated), or combinations thereof. It should be noted that the intermediate traces 213i are not disposed at the same PCB sublayer thickness determined by the process specific sublayer thickness, and can be disposed at the same or different thickness as the sublayer.

In one exemplary implementation, a software feature is added that will allow conductive traces to be selected in, for example, a Gerber file before starting fabrication. The software feature will generate an additional embedded spacer signal layer with the selected external traces, as well as a buried/blind via drill head (e.g., in Excellon format) file with vias connecting the duplicate layer containing the repeated traces with the original trace layer on the external signal layer. The input parameters for forming the reduced resistivity traces may be, for example, at least one of the following: height of the conductive layer in which the traces are embedded; height of the dielectric layer between the embedded layers (replicas); number of replicas (in other words, number of embedded spacer signal layers); via diameter, width of the embedded traces in the replicas (referring to traces disposed on an internal embedded signal layer where the coupled traces are substantially wider than the external traces to which they are coupled), and via spacing (in other words, vias that are not perpendicular to the surface of the PCB but are tilted at a predetermined angle to compensate for other component routing vias or other parameters). The replicas may then be configured as internal signal layers and internal vias in a print operation.

The substrate used in the computerized inkjet printing system disclosed herein may be, for example, removable or peelable, or may be a relatively rigid material, such as glass or a crystal (e.g., sapphire). Alternatively, the substrate may be a flexible (e.g., rollable) substrate (or film) to facilitate the substrate to be peeled off from a PCB such as polyethylene naphthalate (PEN), polyimide (e.g., DuPont's ^ketone® ), silicone polymer, polyethylene terephthalate (PET), polytetrafluoroethylene (PTFE) film, etc.

When using the computerized inkjet printing system disclosed herein before or after a first print head or a second print head (e.g., for sintering a conductive layer), other functional steps (and therefore components for affecting such steps) may be employed. Such steps may include (but are not limited to): heating steps (under the influence of heating elements such as chucks and/or hot air); photobleaching (using, for example, a UV light source and a photomask); drying (for example, using a vacuum zone or a heating element); (reactive) plasma deposition (for example, using a pressurized plasma gun and a plasma beam controller); crosslinking (for example, by selectively initiating by adding a photoacid such as {4-[(2-hydroxytetradecyl)-hydroxyl]-phenyl}-phenyl iodonium hexafluorosulfonate to the polymer solution before coating or using it as a dispersant with metal precursors or nanoparticles); annealing or promoting redox reactions.

When using the computerized inkjet printing system disclosed herein, the conductive and/or dielectric ink compositions may be formulated taking into account the requirements imposed by the deposition tool (if any) and the surface properties of the substrate (e.g., at least one of hydrophilicity or hydrophobicity and surface energy) (which may be removed as appropriate). For example, in the case of inkjet printing using a piezo head, the viscosity of the conductive ink and/or dielectric ink (measured at 20° C.) may be, for example, not less than about 5 cP, such as not less than about 8 cP, or not less than about 10 cP, and not more than about 30 cP, such as not more than about 20 cP, or not more than about 15 cP. The conductive ink and/or the dielectric ink may each be configured (e.g., formulated) to have a dynamic surface tension (referring to the surface tension when a jetted ink droplet is formed at the print head aperture) between about 25 mN/m and about 35 mN/m, such as between about 29 mN/m and about 31 mN/m, as measured by a maximum bubble pressure tensiometer at a surface age of 50 ms and 25° C. The dynamic surface tension may be adjusted so that the contact angle with the strippable substrate or dielectric layer is between about 100° and about 165°.

In an exemplary implementation, an inkjet ink system composition and method for forming a multi-layer AME with traces having optionally low resistivity can be patterned by expelling droplets of a liquid ink provided herein from an orifice one at a time, for example, in two (X-Y) dimensions (it should be understood that the print head can also move in the Z axis) at a predetermined distance above the substrate or any subsequent layer while manipulating the print head (or substrate/chuck). The provided inkjet print heads used in the methods described herein can provide a minimum layer film thickness equal to or less than about 3 μm to 10,000 μm.

In an exemplary implementation, the volume of each droplet of the conductive ink and/or dielectric ink may be in the range of 0.5 to 300 picoliters (pL), such as 1 to 4 pL and depending on the strength of the drive pulse and the properties of the ink. The waveform used to eject a single droplet may be a 10 V to about 70 V pulse, or about 16 V to about 20 V, and may be ejected at a frequency between about 5 kHz and about 500 kHz.

The dielectric ink compositions described herein may additionally have a continuous phase comprising: a crosslinking agent, a comonomer, a co-oligomer, a copolymer, or a composition comprising one or more of the foregoing. Likewise, the oligomer and/or polymer backbone may be induced to form crosslinks by contacting the polymer with an agent that will form free radicals on the backbone, thereby allowing crosslinking sites. In an exemplary implementation, the crosslinking agent, comonomer, co-oligomer, copolymer, or a composition comprising one or more of the foregoing may be part of or configured to form a solution, emulsion, gel, or suspension within the continuous phase.

In an exemplary embodiment, the continuous phase used in an AME (PCB, FPC, and HDI circuits) fabricated using the disclosed method for forming a multi-layer AME having traces with optionally low resistivity may include: a multifunctional acrylate monomer, oligomer, polymer, or a combination thereof; a crosslinking agent; and a free radical photoinitiator, and may be partially or completely dissolved in the continuous phase.

An initiator may be used to initiate polymerization of the dielectric resin backbone, such as benzoyl peroxide (BP) and other peroxide-containing compounds. As used herein, the term "initiator" generally refers to a substance that initiates a chemical reaction, particularly any compound that initiates polymerization, or produces reactive species that initiate polymerization, including, for example and without limitation, co-initiators and/or photoinitiators.

In another embodiment, the dielectric resin used in the described ink composition comprises a reactive and/or active component of a polymer capable of being photo-triggered using a photoinitiator. For example, such a reactive monomer, reactive oligomer, reactive polymer, or combination thereof capable of being photo-triggered can be, for example, a multifunctional acrylate, for example, a multifunctional acrylate selected from the group consisting of 1,2-ethylene glycol diacrylate, 1,3-propylene glycol diacrylate, 1,4-butylene glycol diacrylate, 1,6-hexanediol diacrylate, dipropylene glycol diacrylate, neopentyl glycol diacrylate, ethoxylated neopentyl glycol diacrylate, propoxylated neopentyl glycol diacrylate, tripropylene glycol diacrylate, bisphenol-A-diglycidyl ether diacrylate, hydroxypivalate neopentyl glycol ... The present invention also includes pentylene glycol diacrylate, ethoxylated bisphenol-A-diglycidyl ether diacrylate, polyethylene glycol diacrylate, trihydroxymethylpropane triacrylate, ethoxylated trihydroxymethylpropane triacrylate, propoxylated trihydroxymethylpropane triacrylate, propoxylated glycerol triacrylate, tris(2-acryloxyethyl)isocyanurate, pentaerythritol triacrylate, ethoxylated pentaerythritol triacrylate, pentaerythritol tetraacrylate, ethoxylated pentaerythritol tetraacrylate, di(trihydroxymethylpropane)tetraacrylate, dipentaerythritol pentaacrylate and dipentaerythritol hexaacrylate.

The photoinitiators that can be used with the multifunctional acrylates described herein can be, for example, free radical photoinitiators. Such free radical photoinitiators can be, for example, Irgacure® 500 from CIBA SPECIALTY CHEMICAL, as well as Darocur® 1173, Irgacure® 819, Irgacure® 184, TPO-L (ethyl (2,4,6, trimethylbenzoyl)phenylphosphinate), benzophenone and acetophenone compounds, and the like. For example, the free radical photoinitiator can be a cationic photoinitiator, such as triaryl iron salts of hexafluoroantimonate. Another example of a free radical photoinitiator used in the active continuous phase described herein can be 2-isopropylthiazolone.

The terms "living monomer", "living oligomer", "polymer" or their equivalents (e.g., comonomer) in combination refer in an exemplary embodiment to a monomer, short monomer group, or polymer having at least one functional group capable of forming a free radical reaction (in other words, the reaction can continue and is not otherwise terminated by an end group).

The crosslinking agent used in the compositions, systems and methods described herein for forming a multilayer AME having traces with optionally low resistivity can be, for example, a primary or secondary polyamine and its adducts, or in another example, an anhydride, a polyamide, a _C4 - _C30 polyoxyalkylene wherein the alkylene groups each independently contain 2 to 6 carbon atoms, or a combination comprising one or more of the foregoing.

Conductive and/or dielectric ink compositions may each require the presence of a surfactant and, if appropriate, an auxiliary surfactant. The surfactant and/or auxiliary surfactant may be a cationic surfactant, an anionic surfactant, a nonionic surfactant, and an amphiphilic copolymer, such as a block copolymer.

In addition, the dielectric (insulating) layer portion may have a substantially uniform thickness throughout, thereby forming a substantially planar (e.g., flat) surface for receiving additional conductive circuit patterns. The dielectric layer may be a UV curable adhesive or other polymer material. For example, the dielectric ink includes a UV curable polymer. Other dielectric polymers include polyester (PES), polyethylene (PE), polyvinyl alcohol (PVOH) and polymethyl methacrylate (PMMA), poly (vinyl pyrrolidone) (PVP, which is water soluble and can be helpful in avoiding clogging the print head orifice). Other dielectric materials may be photoresist polymers, such as SU-8 based polymers, and polymer-derived ceramics or combinations and copolymers thereof may also be used.

The inkjet system for implementing the methods provided herein may further include a computer-aided manufacturing ("CAM") module including a data processor, a non-volatile memory, and a set of executable instructions stored in the non-volatile memory, wherein the executable instructions, when executed, are configured to cause at least one processor to perform the following operations: receive a 3D visualization file representing a printed circuit board including basic architectural components; generate a library of files, each file representing at least one The method further comprises: receiving a plurality of substantially 2D layers of AME having traces with selectively low resistivity, receiving a series of parameters related to the plurality of substantially 2D layers of AME having traces with selectively low resistivity, and modifying a file representing at least one substantially 2D layer based on at least one of the series of parameters, wherein the CAM module is configured to control each of the first print head and the second print head. Thus, the set of executable instructions is further configured to cause the processor to generate a library of files of a plurality of subsequent layers from the 3D visualization file when executed. Each subsequent file represents a substantially two-dimensional (2D) subsequent layer for printing a subsequent portion of a PCB including a plurality of embedded passive and active components, wherein each subsequent layer file is indexed by a printing order. In addition, the set of executable instructions can be configured to parse out the conductive and dielectric portions of each 2D layer and generate a unique pattern for each layer starting from the first layer, which will instruct the appropriate print head to print that portion of the 2D layer.

Thus, the CAM module may include: a 2D file library storing files converted from a 3D visualization file of a printed circuit board including built-in passive and embedded active components. As used herein, the term "library" refers to a collection of 2D layer files derived from a 3D visualization file, which contains the information required to print each conductive and dielectric pattern, which can be accessed and used by a data collection application that can be executed by a computer readable medium. Each file contains at least a print order for a conductive ink (CI) and a dielectric ink (DI). A layer file in the library will have print instructions for both CI and DI in the same layer, however, the print order for each pattern corresponding to CI and BI may vary from layer to layer and form part of the file library. The CAM further includes: a processor communicating with the library; a non-transitory storage device storing a set of operating instructions for execution by the processor; a micro-mechanical inkjet print head communicating with the processor and the library; and a print head interface circuit communicating with the 2D file library, the non-transitory storage device and the micro-mechanical inkjet print head, wherein the 2D file library is configured to provide printer operating parameters specific to the functional (printed) layer.

Therefore, the step of using the first print head is preceded by the following step: using a CAM module, obtaining a generated file from a library, the first file representing a first substantially 2D layer for printing of a multi-layer AME having traces with optionally lower resistivity, the 2D layer comprising patterns representing dielectric ink and conductive ink, wherein the parameters used in a series of parameters related to the multi-layer AME having traces with optionally lower resistivity include, for example: the required resistivity, the number of intermediate traces 213i, the number of end blind through holes 233k (related to the number of coupled contact pads 204j), the number of non-end buried through holes 225k, the number of end buried through holes 226k, their respective diameters and combinations thereof.

The 3D visualization file representing a multi-layer AME with traces with optionally lower resistivity may be: ODB, ODB++, .asm, STL, IGES, STEP, Catia, SolidWorks, Autocad, ProE, 3D Studio, Gerber, Rhino, Altium, Orcad or a file comprising one or more of the foregoing; and the file representing at least one substantially 2D layer (and uploaded to the library) may be, for example, a JPEG, GIF, TIFF, BMP, PDF file or a combination comprising one or more of the foregoing.

In addition, the computer program may include program code components for performing the steps of the method described herein, and a computer program product containing the program code components stored on a medium that can be read by a computer. The non-transitory storage device used in the method described herein can be any of various types of non-volatile memory devices or storage devices (in other words, a memory device that does not lose information when there is no power). The term "memory device" is intended to cover installation media, such as CD-ROM, floppy disk or tape devices or non-volatile memory, such as magnetic media, such as hard drives, optical storage, or ROM, EPROM, FLASH, etc. The memory device may also include other types of memory or combinations thereof. In addition, the memory medium may be located in a first computer (e.g., a provided 3D inkjet printer) executing a program, and/or may be located in a second different computer connected to the first computer via a network such as the Internet. In the latter case, the second computer may further provide the program instructions to the first computer for execution. The term "memory device" may also include two or more memory devices that may reside in different locations, such as two or more memory devices that may reside in different computers connected via a network. Thus, for example, a bitmap library may reside on a memory device remote from a CAM module coupled to a provided 3D inkjet printer, and may be accessed by the provided 3D inkjet printer (e.g., via a wide area network).

The use of the term "module" does not imply that the components or functionality described or claimed as part of the module are all configured in a (single) common package. Rather, any or all of the various components of the module (whether control logic or other components) may be combined in a single package or maintained separately, and may further be distributed in multiple groups or packages or across multiple (remote) locations and devices. Furthermore, in certain exemplary implementations, the term "module" refers to an integrated or distributed hardware unit.

As used herein, the term "comprise" and its derivatives are intended to be open terms that specify the presence of stated features, elements, components, groups, integers and/or steps but do not exclude the presence of other unstated features, elements, components, groups, integers and/or steps. The foregoing also applies to words with similar meanings, such as the terms "include", "have" and their derivatives.

Unless otherwise specifically stated, it should be understood as apparent from the following discussion that throughout this specification, discussions utilizing terms such as "processing," "loading," "communication," "detection," "computing," "determining," "analysis," or the like, refer to actions and/or processes of a computer or computing system or similar electronic computing device that manipulate and/or transform data represented as physical objects, such as transistor structures, into other data similarly represented as physical structures (in other words, resin or metal/metallic properties) layers.

The computer-aided design/computer-aided manufacturing (CAD/CAM) generated information associated with the AME including the reduced resistivity traces herein to be manufactured used in the methods, procedures and libraries can be based on a converted CAD/CAM data package, which can be, for example, IGES, DXF, DWG, DMIS, NC files, GERBER® files, EXCELLON®, STL, EPRT files, ODB, ODB++, .asm, STL, IGES, STEP, Catia, SolidWorks, Autocad, ProE, 3D Studio, Gerber, Rhino, Altium, Orcad, Eagle files, or a package containing one or more of the foregoing. In addition, the attributes associated with the graphic objects convey the meta-information required for manufacturing and can accurately define the PCB. Therefore and in one exemplary implementation, GERBER®, EXCELLON®, DWG, DXF, STL, EPRT ASM and the like as described herein are converted into 2D files using a pre-processing algorithm.

All ranges disclosed herein are inclusive of endpoints, and the endpoints are independently combinable with each other. "Combination" includes blends, mixtures, alloys, reaction products, and the like. Unless otherwise indicated herein or clearly contradicted by context, the terms "a", "an", and "the" herein do not indicate a limitation of number and should be interpreted as covering both the singular and the plural. As used herein, the suffix "(s)" is intended to include both the singular and the plural of the term it modifies, thereby including one or more of the term (e.g., a trace includes one or more traces). When present, references throughout this specification to "one embodiment," "another embodiment," "an exemplary implementation," etc. mean that particular elements (e.g., features, structures, and/or characteristics) described in connection with that embodiment are included in at least one embodiment described herein, and may or may not be present in other exemplary implementations. In addition, it should be understood that the described elements may be combined in any suitable manner in the various exemplary implementations.

All ranges disclosed herein include endpoints, and each endpoint can be independently combined with each other. In addition, in this article, the terms "first", "second" and similar terms do not represent any order, number or importance, but are used to indicate one element and another element.

Similarly, the term "about" means that amounts, dimensions, formulations, parameters, and other quantities and characteristics are not and need not be exact, but may be approximate and/or larger or smaller as necessary, reflecting tolerances, conversion factors, rounding, measurement errors, and the like, as well as other factors known to those skilled in the art. In general, amounts, dimensions, formulations, parameters, or other numbers or characteristics are "about" or "approximate", whether or not expressly stated.

Thus, in an exemplary implementation, a method of reducing the resistivity of a trace between at least two connected components in a multi-layer fabricated electronic device (AME) is provided herein, comprising: forming at least one trace on an intermediate layer, thereby forming an intermediate trace; forming a trace sized and configured to operably couple at least two components on at least one of: an external top layer and an external base layer of the multi-layer AME, thereby forming at least one external trace; and forming a predetermined number of at least one of: a blind via and a buried via, the predetermined number a plurality of through holes sized and configured to electrically couple at least one intermediate trace and a corresponding external trace of the multi-layer AME, wherein the method further (i) comprises: forming at least one contact pad at one of the ends of the external trace, the contact pad being adapted, sized and configured to be operably coupled to a component, wherein (ii) the combined resistivity of at least one of the predetermined number of the blind vias and the buried vias; the at least one intermediate trace; and the external trace is configured to provide a resistivity that is a predetermined fraction of the resistivity of the external trace in the absence of the intermediate traces. The method further comprises (iii) forming a plurality of intermediate traces, each intermediate trace being disposed in a single layer along a vertical axis of the multi-layer AME, (iv) coupling each of the plurality of intermediate traces to an adjacent intermediate trace, thereby forming a plurality of buried vias between the adjacent intermediate traces, (v) forming an end buried via at the end of each of the intermediate traces, each end buried via being formed to have a cross-section having an area larger than that of each of the non-end buried vias, (vi) forming an end buried via at each end of the intermediate trace adjacent to the outer trace. An end blind via hole, the end blind via hole is formed to have a cross-section having an area larger than each of a non-end buried via hole, wherein (vii) the outer trace, the predetermined number of the blind via holes and at least one of the buried via holes, the end buried via holes, the end blind via holes and at least one of the plurality of intermediate traces are formed to extend vertically from the outer trace to a lattice in the multi-layer AME, wherein (viii) a width of the intermediate trace is formed to be wider than a width of the outer trace, and wherein (ix) at least one of the plurality of buried via holes between the adjacent intermediate traces is tilted.

In another exemplary implementation, a multi-layer fabricated electronic device (AME) is provided herein, comprising: at least one intermediate trace on an intermediate layer; at least one external trace sized and configured to operably couple at least two components on at least one of: an external top layer and an external base layer of the AME; and a predetermined number of at least one of: a blind via and a buried via, the blind via and the buried via being connected to each other. wherein (x) the outer trace terminates at least one end in a contact pad adapted, sized and configured to be operably coupled to a component, (xi) at least one of the predetermined number of the blind vias and the buried vias is configured to provide a resistivity that is a fraction of the resistivity of the outer trace in the absence of the at least one intermediate trace, and (xii) the multi-layer AME comprises a plurality of a plurality of intermediate traces, each intermediate trace disposed in a single intermediate layer along a vertical axis of the multi-layer AME, (xiii) each intermediate trace of the plurality of intermediate traces is coupled to an adjacent intermediate trace, wherein there are a plurality of buried vias between the adjacent intermediate traces, (xiv) each intermediate trace of the plurality of intermediate traces terminates in an end buried via, the end buried via having a cross-section having an area greater than each of the non-end buried vias, (xv) the intermediate layer adjacent to the outer trace terminates in a terminal blind via formed to have a cross-section having an area greater than each of the non-terminal buried vias, and wherein (xvi) the outer trace, the predetermined number of the blind vias and at least one of the buried vias, the terminal buried vias, the terminal blind vias and at least one of the plurality of intermediate traces form a lattice extending vertically from the outer trace to the multi-layer AME.

In yet another exemplary implementation, a computerized method for using an inkjet printer to fabricate a trace with reduced resistivity between at least two connected components in a multi-layer fabricated electronic device (AME) is provided herein, comprising: providing an inkjet printing system, comprising: a first print head operable to dispense a dielectric ink composition; a second print head operable to dispense a conductive ink composition; a conveyor operably coupled to the first print head and the second print head, the conveyor being configured to transport a substrate to the first print head and the second print head; each of the print heads; and a computer-aided manufacturing ("CAM") module including a central processing module (CPM), the CAM communicating with each of the first print head and the second print head, wherein the CPM further comprises: at least one processor communicating with a non-transitory storage medium, a set of executable instructions stored on the non-transitory storage medium configured to cause the CPM to perform the following steps when executed: receiving a 3D visualization file representing the multi-layer AME having traces with reduced resistivity; and generating a file library having a plurality of files, Each file represents a substantially 2D layer for printing an LPF and a meta file represents at least a printing order; wherein the CAM module is configured to control each of the conveyor, the first print head and the second print head; provide the dielectric ink composition and the conductive ink composition; using the CAM module, obtain from the library a first file representing a first layer of the multi-layer AME having the traces with reduced resistivity, the first file including print instructions representing a pattern of at least one of the following: the dielectric ink and the conductive ink; using the first print head, forming the pattern corresponding to the dielectric ink; curing the pattern represented by the dielectric ink in the 2D layer corresponding to the multi-layer AME using an electromagnetic radiation source; forming the pattern corresponding to the conductive ink using the second print head; sintering the pattern corresponding to the conductive ink using heat; obtaining from the library, using the CAM module, a subsequent file representing a subsequent layer of the multi-layer AME having the traces with reduced resistivity, the subsequent file including print instructions representing a pattern of at least one of the following: the dielectric ink and the conductive ink; repeating the following steps: Using the first print head, forming the pattern corresponding to the dielectric ink until the step of obtaining a subsequent substantially 2D layer from the 2D file library using the CAM module, wherein after sintering the conductive ink pattern in the final substantially 2D layer, the multi-layer AME is configured to include: at least one intermediate trace, which is on an intermediate layer; at least one external trace, which is sized and configured to operably couple at least two components on at least one of the following: an external top layer and an external base layer of the multi-layer AME; and a predetermined number of at least one of the following: a blind through hole and a a buried via, the blind via and the buried via electrically coupling the intermediate trace with the outer trace; and removing the substrate, wherein (xvii) the outer trace terminates at least one end in a contact pad, the contact pad being adapted, sized and configured to be operably coupled to a component, (xviii) at least one of the predetermined number of the blind vias and the buried vias is configured to provide a resistivity that is a fraction of the resistivity of the outer trace, wherein after sintering the conductive ink in the final substantially 2D layer (xix), the multi-layer AME is configured to include a plurality of intermediate traces and the outer traces; traces, each intermediate trace being disposed in a single layer along a vertical axis of the multi-layer AME, (xx) each of the plurality of intermediate traces is coupled to an adjacent intermediate trace, wherein there are a plurality of buried vias between the adjacent intermediate traces, (xxi) each of the plurality of intermediate traces terminates in an end buried via having a cross-section with an area greater than each of the non-end buried vias, (xxii) the intermediate layer adjacent to the outer trace terminates in an end blind via formed to have an area greater than each of the non-end buried vias. a cross-section of the non-terminal buried vias, (xxiii) the outer trace, at least one of the predetermined number of the blind vias and the buried via, the terminal buried vias, the terminal blind vias and at least one of the plurality of intermediate traces are from extending vertically from the outer trace to a lattice in the multi-layer AME, (xxiv) a width of the intermediate trace formed is wider than a width of the outer trace, and (xxv) wherein after firing the conductive ink pattern in the final substantially 2D layer, at least one of the plurality of buried vias between the adjacent intermediate traces is tilted.

Of course, the above examples and descriptions are provided for illustrative purposes only and are not intended to limit the disclosed technology in any way. As will be appreciated by those skilled in the art, the disclosed technology can be implemented in a variety of ways, which employ more than one of the techniques described above, all of which are within the scope of the present invention.

100: Multilayer printed circuit board (PCB) 101: External base layer 102: External top layer 103i: External trace 104j: Contact pad 106q: Contact pad 107k: Through hole 200: Multilayer Amplitude-Added Electronic Device (AME)/Multilayer PCB 201: External base layer 20 2: External top layer 203i: External trace 204j: Contact pad 213i: Middle trace 224k: Blind via 225k: Buried via 226k: Buried via 233k: Blind via 253i: Lattice/enhanced trace 303i: Trace 500n: Component h: Trace thickness W: Trace width

In order to better understand the method for forming traces with selectively reduced resistivity in multi-layer printed circuit boards (PCBs), flexible printed circuits (FPCs), and high density interconnect printed circuits (HDI circuits) using direct inkjet printing, for example, reference is made to the accompanying examples and drawings for exemplary implementations thereof, in which:

FIG1 shows a perspective schematic diagram of a trace with a fixed area;

FIG. 2 shows a perspective schematic diagram of a reduced resistivity trace formed using the disclosed method; and

FIG. 3 shows a top plan view of a wiring board formed using prior art techniques.

100:Multi-layer printed circuit board (PCB)

101: External base layer

102: External top layer

103i: External trace

104j:Contact pad

106q: Contact pad

107k:Through hole

h: trace thickness

W: trace width

Claims (28)

A method of reducing the resistivity of a trace between at least two connected components in a multi-layered electronic device (AME), comprising: a. forming at least one trace on an intermediate layer, thereby forming an intermediate trace; b. forming a trace sized and configured to operably couple at least two components on at least one of: an external top layer and an external base layer of the multi-layered AME, thereby forming at least one external trace; and c. forming a predetermined number of at least one of: a blind via and a buried via, the predetermined number of vias being sized and configured to electrically couple the at least one middle trace and a corresponding outer trace of the multi-layer AME, wherein an end blind via between the at least one outer trace and the at least one middle trace has a cross-sectional diameter that is greater than a diameter of a cross-sectional area of at least one non-end buried via. The method of claim 1, further comprising: forming at least one contact pad at the end of the external trace, the contact pad being adapted, sized and configured to be operably coupled to a component. The method of claim 2, wherein the combined resistivity of the predetermined number of at least one of the blind vias and the buried vias; the at least one intermediate trace; and the outer trace is configured to provide a resistivity that is a predetermined fraction of the resistivity of the outer trace in the absence of the intermediate traces. The method of claim 3 further comprises forming a plurality of intermediate traces, each intermediate trace being disposed in a single layer along a vertical axis of the multi-layer AME. The method of claim 4 further comprises coupling each of the plurality of intermediate traces to an adjacent intermediate trace, thereby forming a plurality of buried vias between the adjacent intermediate traces. The method of claim 5 further comprises forming an end buried via at the end of each of the intermediate traces, each end buried via being formed to have a cross-section having an area larger than each of the at least one non-end buried via. The method of claim 6 further comprises forming the terminal blind via at each end of the middle trace adjacent to the outer trace, the terminal blind via being formed to have a cross-section having an area larger than each of the at least one non-terminal buried via. The method of claim 7, wherein: the external trace, the predetermined number of the blind vias and at least one of the buried vias, the terminal buried vias, the terminal blind vias and at least one of the plurality of intermediate traces form a lattice extending vertically from the external trace to the multi-layer AME. A method as claimed in claim 4, wherein a width of the intermediate trace formed is wider than a width of the outer trace. The method of claim 5, wherein at least one of the plurality of buried vias between the adjacent intermediate traces is tilted. A multi-layer AME, comprising: a. at least one middle trace on a middle layer; b. at least one external trace sized and configured to operably couple at least two components on at least one of: an external top layer and an external base layer of the AME; and c. a predetermined number of at least one of: a blind via and a buried via, the blind via and the buried via electrically coupling the middle trace with the external trace, wherein an end blind via between the at least one external trace and the at least one middle trace has a cross-sectional diameter that is greater than a diameter of a cross-sectional area of at least one non-end buried via. A multi-layer AME as claimed in claim 11, wherein the external trace terminates at least one end in a contact pad adapted, sized and configured to be operably coupled to a component. The multi-layer AME of claim 12, wherein at least one of the predetermined number of the blind vias and the buried vias is configured to provide a resistivity that is a fraction of the resistivity of the outer trace in the absence of the at least one intermediate trace. A multi-layer AME as claimed in claim 13, wherein the multi-layer AME comprises a plurality of intermediate traces, each of which is disposed in a separate intermediate layer along a vertical axis of the multi-layer AME. A multi-layer AME as claimed in claim 14, wherein each of the plurality of intermediate traces is coupled to an adjacent intermediate trace, wherein there are a plurality of buried vias between the adjacent intermediate traces. A multi-layer AME as claimed in claim 15, wherein each of the plurality of intermediate traces terminates in a terminal buried via, the terminal buried via having a cross-section having an area greater than each of the at least one non-terminal buried via. A multi-layer AME as claimed in claim 16, wherein the intermediate layer adjacent to the outer trace terminates in the terminal blind via hole, the terminal blind via hole being formed to have a cross-section having an area larger than each of the at least one non-terminal buried via hole. A multi-layer AME as claimed in claim 17, wherein the external trace, the predetermined number of the blind vias and at least one of the buried vias, the terminal buried vias, the terminal blind vias and at least one of the plurality of intermediate traces form a lattice extending vertically from the external trace to the multi-layer AME. A computerized method for using an inkjet printer to produce a trace with reduced resistivity between at least two connected components in a multi-layer fabricated electronic device (AME), comprising: a. providing an inkjet printing system, comprising: i. a first print head operable to dispense a dielectric ink composition; ii. a second print head operable to dispense a conductive ink composition; iii. a conveyor operably coupled to the first print head and the second print head, the conveyor configured to convey a substrate to each of the first print head and the second print head; and iv. a computer-aided manufacturing ("CAM") module, comprising a central processing module (CPM), the CAM communicating with each of the first print head and the second print head, wherein the CPM further comprises: to at least one processor in communication with a non-transitory storage medium, a set of executable instructions stored on the non-transitory storage medium configured to, when executed, cause the CPM to perform the following steps: receiving a 3D visualization file representing the multi-layer AME having traces with reduced resistivity; and generating a file library having a plurality of files, each file representing a substantially 2D layer for printing LPF and a meta file At least representing a printing order; wherein the CAM module is configured to control each of the conveyor, the first print head and the second print head; b. providing the dielectric ink composition and the conductive ink composition; c. using the CAM module, obtaining from the library a first file representing a first layer of the multi-layer AME having the traces with reduced resistivity, the first file comprising print instructions representing a pattern of at least one of the following: the dielectric ink and the conductive ink; d. using the first print head, forming the pattern corresponding to the dielectric ink; e. using an electromagnetic radiation source, curing the pattern represented by the dielectric ink in the 2D layer corresponding to the multi-layer AME; f. using the second print head, forming the pattern corresponding to the conductive ink; g. using heat to sinter the pattern corresponding to the conductive ink ; h. using the CAM module, obtaining from the library a subsequent file representing a subsequent layer of the multi-layer AME having the traces with reduced resistivity; the subsequent file includes print instructions representing a pattern of at least one of the following: the dielectric ink and the conductive ink; i. repeating the following steps: using the first print head to form the pattern corresponding to the dielectric ink until the CAM module is used The step of obtaining a subsequent substantially 2D layer from the 2D file library, wherein after sintering the conductive ink pattern in the final substantially 2D layer, the multi-layer AME is configured to include: i. at least one intermediate trace on an intermediate layer; ii. at least one external trace sized and configured to operably couple at least two components on at least one of: an external top layer and an external layer of the multi-layer AME; base layer; and iii. a predetermined number of at least one of: a blind via and a buried via, the blind via and the buried via electrically coupling the middle trace and the outer trace; wherein an end blind via between the at least one outer trace and the at least one middle trace has a cross-sectional diameter that is greater than a diameter of a cross-sectional area of at least one non-end buried via; and j. removing the substrate. The method of claim 19, wherein the external trace terminates at least one end in a contact pad that is adapted, sized, and configured to be operably coupled to a component. The method of claim 20, wherein at least one of the predetermined number of the blind vias and the buried vias is configured to provide a resistivity that is a fraction of the resistivity of the external trace. The method of claim 19, wherein after sintering the conductive ink in the final substantially 2D layer, the multi-layer AME is configured to include a plurality of intermediate traces, each intermediate trace being disposed in a separate layer along a vertical axis of the multi-layer AME. The method of claim 22, wherein after sintering the conductive ink pattern in the final substantially 2D layer, each of the plurality of intermediate traces is coupled to an adjacent intermediate trace, wherein there are a plurality of buried vias between the adjacent intermediate traces. The method of claim 23, wherein after sintering the conductive ink pattern in the final substantially 2D layer, each of the plurality of intermediate traces terminates in a terminal buried via having a cross-section having an area greater than each of the at least one non-terminal buried via. The method of claim 24, wherein after firing the conductive ink pattern in the final substantially 2D layer, the intermediate layer adjacent to the outer trace terminates in the terminal blind via, the terminal blind via being formed to have a cross-section having an area greater than each of the at least one non-terminal buried via. The method of claim 25, wherein after sintering the conductive ink pattern in the final substantially 2D layer, the outer trace, at least one of the predetermined number of the blind vias and the buried vias, the terminal buried vias, the terminal blind vias, and at least one of the plurality of intermediate traces are from extending vertically from the outer trace to a lattice in the multi-layer AME. The method of claim 22, wherein after firing the conductive ink pattern in the final substantially 2D layer, a width of the middle trace formed is wider than a width of the outer trace. The method of claim 23, wherein after firing the conductive ink pattern in the final substantially 2D layer, at least one of the plurality of buried vias between the adjacent intermediate traces is tilted.