TWI865199B - Continuous Approximation Analog-to-Digital Converter for PAM-(2^N-2) Receiver - Google Patents

Abstract

A continuous approximation analog-to-digital converter for converting an analog input signal in a ( ^2N -2)-level pulse amplitude modulation format into an N-bit wide digital output signal includes a switch circuit, a conversion circuit, a comparison circuit, a register, and a controller. The switch circuit is used to receive a first input voltage and a second input voltage that jointly represent the analog input signal. The conversion circuit outputs a first comparison voltage and a second comparison voltage. The comparison circuit compares the first comparison voltage and the second comparison voltage to generate a comparison output. The register generates the digital output signal according to the comparison output. The controller selectively provides one of a reference voltage or a ground voltage to the conversion circuit according to the comparison output.

Description

Continuous Approximation Analog-to-Digital Converter for PAM-(2^N-2) Receiver

The present invention is a continuous approximation analog-to-digital converter, and more particularly, is a continuous approximation analog-to-digital converter for a (2 ^N -2)-level [PAM-(2 ^N -2)] pulse amplitude modulation receiver.

In a receiver for decoding 6-level pulse amplitude modulation (PAM-6) format data, a conventional analog-to-digital converter requires seven comparators and seven reference voltages, which has the disadvantages of occupying a large area of hardware space and consuming high power.

Therefore, an object of the present invention is to provide a continuous approximation analog-to-digital converter (ADC) suitable for a (2 ^N -2)-level pulse amplitude modulation receiver, wherein the continuous approximation analog-to-digital converter (ADC) can solve at least one drawback of the prior art.

The continuous approximation analog-to-digital converter of the present invention is suitable for converting an analog input signal in a (2 ^N -2)-level pulse amplitude modulation format into a digital output signal with an N-bit width, wherein N ≥ 3. The continuous approximation analog-to-digital converter comprises a switch circuit, a conversion circuit, a comparison circuit, a register and a controller. The switch circuit is used to receive a first input voltage and a second input voltage that jointly represent the analog input signal. The switch circuit operates between an on state and a off state, and is configured to allow the first input voltage and the second input voltage to pass when operating in the on state, and not allow the first input voltage and the second input voltage to pass when operating in the off state. The conversion circuit includes a first capacitor group and a second capacitor group. The first capacitor group has a first common node and N first capacitors, each of which has a first end and a second end. The first common node is connected to the first ends of the first capacitors and is connected to the switch circuit to receive the first input voltage. The first capacitors jointly output a first comparison voltage at the first common node. When the switch circuit operates in the open state, the first comparison voltage is equal to the first input voltage. When the switch circuit operates in the closed state, the first comparison voltage changes with the voltage of the second ends of the first capacitors. The second capacitor group has a second common node and N second capacitors, each of which has a first end and a second end. The second common node is connected to the first ends of the second capacitors and is connected to the switch circuit to receive the second input voltage. The second capacitors output a second comparison voltage at the second common node. When the switch circuit is operated in the open state, the second comparison voltage is equal to the second input voltage. When the switch circuit is operated in the closed state, the second comparison voltage changes with the voltage of the second ends of the second capacitors. The comparison circuit is connected to the first common node and the second common node to receive the first comparison voltage and the second comparison voltage, and is configured to compare the first comparison voltage and the second comparison voltage to generate a comparison output, the comparison output includes a first comparison signal and a second comparison signal with a width of N bits, and the least significant bit of the first comparison signal and the least significant bit of the second comparison signal are generated in relation to the two first capacitors and the two second capacitors. The register is connected to the comparison circuit to receive the comparison output, and is configured to generate the digital output signal according to the comparison output. The controller is connected to the comparison circuit to receive the comparison output, and is also connected to the second ends of the first capacitors and the second ends of the second capacitors, and is configured to selectively provide one of a reference voltage or a ground voltage to the second ends of the first capacitors and the second ends of the second capacitors according to the comparison output for each of the first capacitors and each of the second capacitors. When the N-1 most significant bits of the first comparison signal have the same logical value, the controller provides the reference voltage and the ground voltage to the two first capacitors associated with the lowest bit of the first comparison signal and the lowest bit of the second comparison signal, respectively. The controller also provides the reference voltage and the ground voltage to the lowest bit of the first comparison signal and the lowest bit of the second comparison signal, respectively. On the contrary, the controller provides one of the reference voltage and the ground voltage to the two first capacitors associated with the lowest bit of the first comparison signal and the lowest bit of the second comparison signal, and the controller also provides the reference voltage and the ground voltage, which have not yet been provided, to the two second capacitors associated with the lowest bit of the first comparison signal and the lowest bit of the second comparison signal.

Before the present invention is described in detail, it should be noted that similar components are represented by the same reference numerals in the following description.

Referring to FIGS. 1 and 2 , an embodiment of the continuous approximation analog-to-digital converter of the present invention is applicable to a (2 ^N -2)-stage pulse amplitude modulation receiver, and converts an analog input signal in a pulse amplitude modulation format of PAM-(2 ^N -2) into a digital output signal of N bits wide, where N ≥ 3. For the convenience of explanation, N = 3 in this embodiment. (That is, the receiver in the embodiment is a PAM-6 receiver, the analog input signal is in the PAM-6 format, and the digital output signal B<2:0> is 3 bits wide.) The continuous approximation analog-to-digital converter of this embodiment includes a switch circuit 1, a conversion circuit 2, a comparison circuit 3, a register 4, and a controller 5. It should be noted that the following description of the continuous approximation analog-to-digital converter of this embodiment is based on the premise of ignoring the gain loss of the conversion circuit 2.

The switch circuit 1 is used to receive a first input voltage Vip and a second input voltage Vin that jointly represent the analog input signal, and is also used to receive a clock signal Φs, and operates in an on state and a off state according to the clock signal Φs. The switch circuit 1 is configured to allow the first input voltage Vip and the second input voltage Vin to pass when operating in the on state, and not allow the first input voltage Vip and the second input voltage Vin to pass when operating in the off state.

In this embodiment, the voltage of the analog input signal is equal to the voltage difference between the first input voltage Vip and the second input voltage Vin (e.g., Vip-Vin, hereinafter referred to as the input voltage difference (Vip-Vin)). In addition, 0≤Vip≤Vref, 0≤Vin≤Vref, so -Vref≤Vip-Vin≤Vref, where Vref is a reference voltage. In addition, the switch circuit 1 includes a first sampling switch 11 and a second sampling switch 12. The first sampling switch 11 has a first terminal and a second terminal for receiving the first input voltage Vip. The second sampling switch 12 has a first terminal and a second terminal for receiving the second input voltage Vin. The first sampling switch 11 and the second sampling switch 12 also receive the clock signal Φs and switch between conduction and non-conduction according to the clock signal Φs. When the clock signal Φs is a logic value "1", the first sampling switch 11 and the second sampling switch 12 are both conducted, and the switch circuit 1 operates in the conduction state. When the clock signal Φs is a logic value "0", the first sampling switch 11 and the second sampling switch 12 are both non-conducting, and the switch circuit 1 operates in the off state.

The conversion circuit 2 includes a first capacitor group 21 and a second capacitor group 22 .

The first capacitor group 21 includes a first common node n1 and N first capacitors (including three first capacitors 211 ₁ -211 ₃ in this embodiment), each of which has a first end and a second end. The first common node n1 is connected to the first ends of the first capacitors 211 ₁ -211 ₃ , and is also connected to the second end of the first sampling switch 11 to receive the first input voltage Vip. The first capacitors 211 ₁ -211 ₃ jointly output a first comparison voltage Vcp at the first common node n1. When the switch circuit 1 operates in the on state, the first input voltage Vip is transmitted to the first capacitors 211 ₁ -211 ₃ through the on first sampling switch 11 for charging and discharging, so the first comparison voltage Vcp is equal to the first input voltage Vip. When the switch circuit 1 operates in the off state, the first input voltage Vip cannot be transmitted through the non-conducting first sampling switch 11, so the first comparison voltage Vcp changes with the voltage of the second ends of the first capacitors 211 ₁ -211 ₃ . In this embodiment, the capacitance value of the first capacitor 211 ₁ is 0.25×C, the capacitance value of the first capacitor 211 ₂ is 0.75×C, and the capacitance value of the first capacitor 211 _n is 2 ^(n-2) ×C, where C is a predetermined capacitance value, and 3≤n≤N (n=3 in this embodiment). Therefore, the capacitance value ratio of the first capacitors 211 ₁ -211 ₃ is 1:3:8.

Similarly, the second capacitor group 22 includes a second common node n2 and N second capacitors (including three second capacitors 221 ₁ -221 ₃ in this embodiment), each of which has a first end and a second end. The second common node n2 is connected to the first ends of the second capacitors 221 ₁ -221 ₃ and is also connected to the second end of the second sampling switch 12 to receive the second input voltage Vin. The second capacitors 221 ₁ -221 ₃ jointly output a second comparison voltage Vcn at the second common node n2. When the switch circuit 1 is operated in the on state, the second input voltage Vin is transmitted to the second capacitors 221 ₁ -221 ₃ through the on second sampling switch 12 for charging and discharging, so the second comparison voltage Vcn is equal to the second input voltage Vin. When the switch circuit 1 is operated in the off state, the second input voltage Vin cannot be transmitted through the non-conducting second sampling switch 12, so the second comparison voltage Vcn changes with the voltage of the second ends of the second capacitors 221 ₁ -221 ₃ . In this embodiment, the capacitance value of the second capacitor 221 ₁ is 0.25×C, the capacitance value of the second capacitor 221 ₂ is 0.75×C, and the capacitance value of the second capacitor 221 _n is 2 ^(n-2) ×C, where C is a predetermined capacitance value, and 3≤n≤N (n=3 in this embodiment). Therefore, the capacitance value ratio of the second capacitors 221 ₁ -221 ₃ is 1:3:8.

The comparison circuit 3 is connected to the first common node n1 and the second common node n2 to receive the first comparison voltage Vcp and the second comparison voltage Vcn, and is configured to compare the first comparison voltage Vcp and the second comparison voltage Vcn to generate a comparison output, which includes an N-bit wide first comparison signal (in this embodiment, the first comparison signal BP＜2:0＞ is 3 bits wide) and an N-bit wide second comparison signal (in this embodiment, the second comparison signal BN＜2:0＞ is 3 bits wide). The generation of the least significant bit BP＜0＞ of the first comparison signal and the least significant bit BN＜0＞ of the second comparison signal is related to the two first capacitors 211 ₁ , 211 ₂ and the two second capacitors 221 ₁ , 221 ₂ , and the generation of the bit BP＜n＞ of the first comparison signal and the bit BN＜n＞ of the second comparison signal is related to the first capacitor 211 _(n+2) and the second capacitor 221 _(n+2) , where 1≤n≤N-2 (n＝1 in this embodiment).

In this embodiment, the comparison circuit 3 includes N comparators (there are three comparators 31 ₁ - 31 ₃ in this embodiment) and a clock generator 32. The comparators _31n are connected to the first common node n1 and the second common node n2 to receive the first comparison voltage Vcp and the second comparison voltage Vcn. When operating in an enable mode, the comparison result between the first comparison voltage Vcp and the second comparison voltage Vcn is used to generate the bit BP＜n-1＞ of the first comparison signal and the bit BN＜n-1＞ of the second comparison signal. When operating in a disable mode, the comparison result between the first comparison voltage Vcp and the second comparison voltage Vcn will not be used, where 1≤n≤N (in the present embodiment, 1≤n≤3). The clock generator 32 is connected to the comparators 31 ₁ -31 ₃ , receives the N-1 most significant bits of the first comparison signal (in the present embodiment, the two most significant bits BP＜ ₂ :1 _＞ of the first comparison signal) and the N-1 most significant bits of the second comparison signal (in the present embodiment, the two most significant bits BN＜2:1＞ of the first comparison signal) from the comparators 31 2 , 31 3 , and also receives the clock signal Φs. The clock generator 32 is configured to control the comparators 31 1 - 31 3 to switch between the enable mode and the disable mode according to the two most significant bits BP<2:1> of the first comparison signal, the two most significant bits (BN< ₂ :1> ₎ of the second comparison signal, and the clock signal Φs.

In the present embodiment, the clock generator 32 generates an N-bit wide timing signal (in the present embodiment, the timing signal Φ＜2:0＞ is 3 bits wide) to control the comparators 31 ₁ -31 ₃ to switch between the enable mode and the disable mode. When the bit Φ＜n-1＞ of the timing signal is a logical value "1", the comparator 31 _n operates in the enable mode, and when the bit Φ＜n-1＞ of the timing signal is a logical value "0", the comparator 31 _n operates in the disable mode, where 1≤n≤N (in the present embodiment, 1≤n≤3). Initially, the timing signal Φ<2:0> is a logic value of "000", the comparators 31 ₁ -31 ₃ are all operated in the disable mode, the first comparison signal BP<2:0> is a logic value of "000", and the second comparison signal BN<2:0> is a logic value of "000". Then, at the falling edge of the clock signal Φs, the bit Φ<2> of the timing signal becomes a logic value "1", the comparator 31 ₃ switches to the enable mode and starts to compare the first comparison voltage Vcp and the second comparison voltage Vcn. If the comparison result is that the first comparison voltage Vcp is greater than the second comparison voltage Vcn, the bit BP＜2＞ of the first comparison signal becomes a logical value "1"; if the comparison result is that the first comparison voltage Vcp is less than the second comparison voltage Vcn, the bit BN＜2＞ of the second comparison signal becomes a logical value "1". Then, when the comparator ₃₁₃ completes the comparison between the first comparison voltage Vcp and the second comparison voltage Vcn (at this time, the voltage difference between the bit BP＜2＞ of the first comparison signal and the bit BN＜2＞ of the second comparison signal reaches a predetermined threshold), the bit Φ＜1＞ of the timing signal becomes a logical value "1", and the comparator ₃₁₂ switches to the enable mode and starts to compare the first comparison voltage Vcp and the second comparison voltage Vcn. When the first comparison voltage Vcp is greater than the second comparison voltage Vcn, the bit BP＜1＞ of the first comparison signal becomes a logical value “1”; when the first comparison voltage Vcp is less than the second comparison voltage Vcn, the bit BN＜1＞ of the second comparison signal becomes a logical value “1”. Finally, when the comparator ₃₁₂ completes the comparison between the first comparison voltage Vcp and the second comparison voltage Vcn (at this time, the voltage difference between the bit BP＜1＞ of the first comparison signal and the bit BN＜1＞ of the second comparison signal reaches the predetermined threshold), the bit Φ＜0＞ of the timing signal becomes a logical value "1", and the comparator ₃₁₁ switches to the enable mode and starts to compare the first comparison voltage Vcp and the second comparison voltage Vcn. When the first comparison voltage Vcp is greater than the second comparison voltage Vcn, the bit BP<0> of the first comparison signal becomes a logical value "1"; when the first comparison voltage Vcp is less than the second comparison voltage Vcn, the bit BN<0> of the second comparison signal becomes a logical value "1". It should be noted that the present embodiment adopts an asynchronous timing control scheme.

It should be noted that in other embodiments, the comparison circuit 3 may include only one comparator, which can replace the three comparators 31 ₁ -31 ₃ . The comparator 31 compares the first comparison voltage Vcp with the second comparison voltage Vcn three times, and can sequentially generate each bit BP<2:0> of the first comparison signal and each bit BN<2:0> of the second comparison signal.

The register 4 is connected to the comparators 31 ₁ -31 ₃ to receive the comparison output, and is configured to generate the digital output signal B<2:0> according to the comparison output. In this embodiment, the register 4 is implemented by a D flip-flop, and also receives the clock signal Φs, and reads the comparison output at each rising edge of the clock signal Φs as the digital output signal B<2:0>.

The controller 5 is connected to the comparison circuit 3 to receive the comparison output, and is also connected to the second ends of the first capacitors 211 ₁ -211 ₃ and the second ends of the second capacitors 221 ₁ -221 3, and is configured to selectively provide one of the reference _{voltage Vref or the ground voltage to the second ends of the first capacitors 211 1 -211 3 and the second ends of the second capacitors 221 1 / 221 2 / 221 3} for each of the first capacitors 211 ₁ -211 ₃ and each of the second capacitors 221 ₁ -221 ₃ .

In this embodiment, the controller 5 includes a first switch group 51, a second switch group 52, a mutually exclusive gate 53 and a control logic circuit 54. The first switch group 51 includes N first switches (three first switches 511 ₁ -511 ₃ in this embodiment). The first switch 511 _n has a first end connected to the second end of the first capacitor 211 _n , a second end for receiving the reference voltage Vref, and a third end for receiving the ground voltage, wherein 1≤n≤N (1≤n≤3 in this embodiment). The second switch group 52 includes N second switches (three second switches 521 ₁ -521 ₃ in this embodiment). The second switch 521 _n has a first end connected to the second end of the second capacitor 221 _n , a second end for receiving the reference voltage Vref, and a third end for receiving the ground voltage, wherein 1≤n≤N (1≤n≤3 in the present embodiment). Each of the first switches 511 ₁ -511 ₃ and each of the second switches 521 ₁ -521 ₃ can be operated in a first state in which the first end and the second end of each of the first switches are electrically connected and the first end and the second end of each of the second switches are electrically connected, and can also be operated in a second state in which the first end and the third end of each of the first switches are electrically connected and the first end and the third end of each of the second switches are electrically connected. The exclusive OR gate 53 has N-1 input terminals (two input terminals in the present embodiment) respectively connected to the comparators 31 ₂ -31 ₃ to respectively receive the two most significant bits BP<2:1> of the first comparison signal, and an output terminal providing a control signal Ctrl. When the two most significant bits BP<2:1> of the first comparison signal have the same logical value, the control signal Ctrl is a logical value "0", otherwise the control signal Ctrl is a logical value "1". The control logic circuit 54 is connected to the output terminal of the exclusive OR gate 53 to receive the control signal Ctrl, is also connected to the comparators 31 ₂ -31 ₃ to receive the two most significant bits BP<2:1> of the first comparison signal and the two most significant bits BN<2:1> of the second comparison signal, and is also connected to the first switches 511 ₁ -511 ₃ and the second switches 521 ₁ -521 ₃ . The control logic circuit 54 is configured to generate a first conversion control signal with a width of N bits (in the present embodiment, the first conversion control signal Cp<2:0> is 3 bits wide) and a second conversion control signal (in the present embodiment, the second conversion control signal Cn<2:0> is 3 bits wide) according to the control signal Ctrl, the two most significant bits BP<2:1> of the first comparison signal, and the two most significant bits BN<2:1> of the second comparison signal to control the first switches 511 ₁ -511 ₃ and the second switches 521 ₁ -521 ₃ to switch between the first state and the second state. The first switch 511 _n receives the bit Cp<n-1> of the first conversion control signal. When the bit Cp<n-1> of the first conversion control signal is at a logical value "1", the first switch 511 _n operates in the first state. When the bit Cp<n-1> of the first conversion control signal is at a logical value "0", the first switch 511 _n operates in the second state. The second switch 521 _n receives the bit Cn<n-1> of the second conversion control signal. When the bit Cn<n-1> of the second conversion control signal is at a logical value "1", the second switch 521 n operates in the first state. When the bit Cn<n-1> of the second conversion control signal is at a logical value "0", the second switch 521 _n operates in the first state. _n operates in the second state, where 1≤n≤N (in this embodiment, 1≤n≤3).

Initially, the first conversion control signal Cp<2:0> is a logical value "000", the second conversion control signal Cn<2:0> is a logical value "000", and the ground voltage is provided to the second ends of the first capacitors 211 ₁ -211 ₃ and the second ends of the second capacitors 221 ₁ -221 ₃ . Next, when the comparator ₃₁₃ completes the comparison of the first comparison voltage Vcp and the second comparison voltage Vcn, one of the following situations will occur: (a) if the bit BP<2> of the first comparison signal is a logical value "0", and the bit BN<2> of the second comparison signal is a logical value "1", then the bit Cp<2> of the first conversion control signal becomes a logical value "1", and the reference voltage Vref is provided to the first capacitor 211. ₃ , and the first comparison voltage Vcp increases by (8/12)×Vref; (b) if the bit BP＜2＞ of the first comparison signal is a logical value "1", and the bit BN＜2＞ of the second comparison signal is a logical value "0", then the bit Cn＜2＞ of the second conversion control signal becomes a logical value "1", the reference voltage Vref is provided to the second end of the second capacitor 221 ₃ , and the second comparison voltage Vcn increases by (8/12)×Vref. Finally, when the comparator ₃₁₂ completes comparing the first comparison voltage Vcp and the second comparison voltage Vcn, if the control signal Ctrl is a logical value "1", one of the following situations will occur: (a) If the bit BP<1> of the first comparison signal is a logical value "0", and the bit BN<1> of the second comparison signal is a logical value "1", then the bits Cp<1:0> of the first conversion control signal become a logical value "11", and the reference voltage Vref is provided to the first capacitors _2111-211 . ₂ , and the first comparison voltage Vcp increases by (4/12)×Vref; (b) if the bit BP<1> of the first comparison signal is a logical value "1", and the bit BN<1> of the second comparison signal is a logical value "0", then the bits Cn<1:0> of the second conversion control signal become a logical value "11", and the reference voltage Vref is provided to the second capacitors 221 ₁ -221 ₂ , and the second comparison voltage Vcn increases by (4/12)×Vref; if the control signal Ctrl is a logical value "0", one of the following situations will occur: (a) if the bit BP＜1＞ of the first comparison signal is a logical value "0", and the bit BN＜1＞ of the second comparison signal is a logical value "1", then the bit Cp＜1＞ of the first conversion control signal becomes a logical value "1", the bit Cn＜0＞ of the second conversion control signal becomes a logical value "1", and the reference voltage Vref is provided to the second end of the first capacitor 211 ₂ and the second capacitor 221 ₁ , and the first comparison voltage Vcp increases by (3/12)×Vref, and the second comparison voltage Vcn increases by (1/12)×Vref; (b) if the bit BP＜1＞ of the first comparison signal is a logical value “1”, and the bit BN＜1＞ of the second comparison signal is a logical value “0”, then the bit Cp＜0＞ of the first conversion control signal becomes a logical value “1”, and the bit Cn＜1＞ of the second conversion control signal becomes a logical value “1”, and the reference voltage Vref is provided to the second end of the first capacitor 211 ₁ and the second capacitor 221 ₂ , and the first comparative voltage Vcp increases by (1/12)×Vref, and the second comparative voltage Vcn increases by (3/12)×Vref.

Therefore, the relationship between the analog input signal (having a voltage equal to the input voltage difference (Vip-Vin)) and the digital output signal B<2:0>, and a binary search method of an embodiment of the continuous approximation analog-to-digital converter of the present invention are shown in FIG. 3.

It should be noted that when the digital output signal B<2:0> is one of the logical values "000", "001", "110" and "111", the bit B<0> of the digital output signal can be used as an error correction bit and can be used for automatic correction of the receiver to enhance the performance of the receiver.

The continuous approximation analog-to-digital converter of this embodiment can operate in a sampling phase, a first conversion phase, a second conversion phase, and a third conversion phase. Taking the input voltage difference (Vip-Vin) equal to (9/12)×Vref as an example, the following Table 1 describes the sampling phase, the first conversion phase, the second conversion phase, and the third conversion phase in detail. Table 1 Stage Sampling stage Φs=1 Φ＜2:0＞=000 Cp＜2:0＞=000 Cn＜2:0＞=000 Vcp=Vip Vcn=Vin Vcp-Vcn=(9/12)×Vref BP＜2:0＞=000 BN＜2:0＞=000 First conversion stage Φs=0 Φ＜2:0＞=100 Cp＜2:0＞=000 Cn＜2:0＞=000 Vcp=Vip Vcn=Vin Vcp-Vcn=(9/12)×Vref BP＜2:0＞=100 BN＜2:0＞=000 Second conversion stage Φs=0 Φ＜2:0＞=110 Cp＜2:0＞=000 Cn＜2:0＞=100 Vcp=Vip Vcn=Vin+(8/12)×Vref Vcp-Vcn=(1/12)×Vref BP＜2:0＞=110 BN＜2:0＞=000 The third conversion stage Φs=0 Φ＜2:0＞=111 Ctrl=0 Cp＜2:0＞=001 Cn＜2:0＞=110 Vcp=Vip+(1/12)×Vref Vcn=Vin+(8/12)×Vref +(3/12)×Vref Vcp-Vcn=(-1/12)×Vref BP＜2:0＞=110 BN＜2:0＞=001

In the sampling stage, the clock signal Φs is a logical value "1", the timing signal Φ＜2:0＞ is a logical value "000", the first conversion control signal Cp＜2:0＞ is a logical value "000", the second conversion control signal Cn＜2:0＞ is a logical value "000", the first comparison signal BP＜2:0＞ is a logical value "000", and the second comparison signal BN＜2:0＞ is a logical value "000". Therefore, the first comparison voltage Vcp is equal to the first input voltage Vip, the second comparison voltage Vcn is equal to the second input voltage Vin, and the difference between the first comparison voltage Vcp and the second input voltage Vin (eg, Vcp-Vcn, hereinafter referred to as the comparison voltage difference) is equal to (9/12)×Vref.

In the first conversion stage, the clock signal Φs becomes a logical value "0", the bit Φ＜2＞ of the timing signal becomes a logical value "1", the bits Φ＜1:0＞ of the timing signal remain unchanged, the first conversion control signal Cp＜2:0＞ remains unchanged, and the second conversion control signal Cn＜2:0＞ remains unchanged. Therefore, the first comparison voltage Vcp remains unchanged, the second comparison voltage Vcn remains unchanged, and the comparison voltage difference (Vcp-Vcn) remains unchanged. Since the comparison voltage difference (Vcp-Vcn) is greater than zero, the bit BP＜2＞ of the first comparison signal becomes a logical value "1", the bit BP＜1:0＞ of the first comparison signal remains unchanged, and the second comparison signal BN＜2:0＞ remains unchanged.

In the second conversion phase, the clock signal Φs remains unchanged, the bit Φ＜1＞ of the timing signal becomes a logical value "1", and the bits Φ＜2＞ and Φ＜0＞ of the timing signal remain unchanged. Therefore, the first conversion control signal Cp＜2:0＞ remains unchanged. Since the bit BP＜2＞ of the first comparison signal is a logical value "1" and the bit BN＜2＞ of the second comparison signal is a logical value "0", the bit Cn＜2＞ of the second conversion control signal becomes a logical value "1", the bits Cn＜1:0＞ of the second conversion control signal remain unchanged, the first comparison voltage Vcp remains unchanged, and the second comparison signal Cp＜2:0＞ remains unchanged. The comparison voltage Vcn increases by (8/12)×Vref, and the comparison voltage difference (Vcp-Vcn) is equal to (1/12)×Vref. Since the comparison voltage difference (Vcp-Vcn) is greater than zero, the bit BP＜1＞ of the first comparison signal becomes a logical value "1", the bit BP＜2＞ and the bit BP＜0＞ of the first comparison signal remain unchanged, and the second comparison signal BN＜2:0＞ remains unchanged.

In the third conversion stage, the clock signal Φs remains unchanged, the bit Φ＜0＞ of the timing signal becomes a logical value "1", and the bits Φ＜2:1＞ of the timing signal remain unchanged. Therefore, since the bits BP＜2:1＞ of the first comparison signal are the same logical value, the control signal Ctrl is the logical value "0", since the control signal Ctrl is the logical value "0", the bit BP＜1＞ of the first comparison signal is the logical value "1", and the bit BN＜1＞ of the second comparison signal is the logical value "0", the bit Cp＜0＞ of the first conversion control signal becomes the logical value "1" and the bit Cn＜1＞ of the second conversion control signal becomes the logical value "1", the bits Cp＜2:1＞ of the first conversion control signal remain unchanged, and the The bit Cn<2> and the bit Cn<0> of the second conversion control signal remain unchanged, the first comparison voltage Vcp increases by (1/12)×Vref, the second comparison voltage Vcn increases by (3/12)×Vref, the comparison voltage difference (Vcp-Vcn) is equal to (-1/12)×Vref, the first comparison signal BP<2:0> remains unchanged, and since the comparison voltage difference (Vcp-Vcn) is less than zero, the bit BN<0> of the second comparison signal becomes a logical value "1", and the bit BN<2> and the bit BN<0> of the second comparison signal remain unchanged. At the end of this stage, the digital output signal B<2:0> changes to a logical value "110".

Taking the input voltage difference (Vip-Vin) equal to (-6/12)×Vref as another example, the following Table 2 describes the sampling phase, the first conversion phase, the second conversion phase, and the third conversion phase in detail. Table 2 Stage Sampling stage Φs=1 Φ＜2:0＞=000 Cp＜2:0＞=000 Cn＜2:0＞=000 Vcp=Vip Vcn=Vin Vcp-Vcn=(-6/12)×Vref BP＜2:0＞=000 BN＜2:0＞=000 First conversion stage Φs=0 Φ＜2:0＞=100 Cp＜2:0＞=000 Cn＜2:0＞=000 Vcp=Vip Vcn=Vin Vcp-Vcn=(-6/12)×Vref BP＜2:0＞=000 BN＜2:0＞=100 Second conversion stage Φs=0 Φ＜2:0＞=110 Cp＜2:0＞=100 Cn＜2:0＞=000 Vcp=Vip+(8/12)×Vref Vcn=Vin Vcp-Vcn=(2/12)×Vref BP＜2:0＞=010 BN＜2:0＞=100 The third conversion stage Φs=0 Φ＜2:0＞=111 Ctrl=1 Cp＜2:0＞=100 Cn＜2:0＞=011 Vcp=Vip+(8/12)×Vref Vcn=Vin+(4/12)×Vref Vcp-Vcn=(-2/12)×Vref BP＜2:0＞=010 BN＜2:0＞=101

In the sampling phase, the clock signal Φs is a logical value "1", the timing signal Φ＜2:0＞ is a logical value "000", the first conversion control signal Cp＜2:0＞ is a logical value "000", the second conversion control signal Cn＜2:0＞ is a logical value "000", the first comparison signal BP＜2:0＞ is a logical value "000". The second comparison signal BN＜2:0＞ is a logical value "000". Therefore, the first comparative voltage Vcp is equal to the first input voltage Vip, the second comparative voltage Vcn is equal to the second input voltage Vin, and the comparative voltage difference (Vcp-Vcn) is equal to (-6/12)×Vref.

In the first conversion stage, the clock signal Φs becomes a logical value "0", the bit Φ＜2＞ of the timing signal becomes a logical value "1", the bits Φ＜1:0＞ of the timing signal remain unchanged, the first conversion control signal Cp＜2:0＞ remains unchanged, and the second conversion control signal Cn＜2:0＞ remains unchanged. Therefore, the first comparison voltage Vcp remains unchanged, the second comparison voltage Vcn remains unchanged, the comparison voltage difference (Vcp-Vcn) remains unchanged, and the first comparison signal BP＜2:0＞ remains unchanged. Since the comparison voltage difference (Vcp-Vcn) is less than zero, the bit BN＜2＞ of the second comparison signal becomes a logical value "1", and the bits BN＜1:0＞ of the second comparison signal remain unchanged.

In the second conversion stage, the clock signal Φs remains unchanged, the bit Φ＜1＞ of the timing signal becomes a logical value "1", and the bits Φ＜2＞ and Φ＜0＞ of the timing signal remain unchanged. Therefore, since the bit BP＜2＞ of the first comparison signal is a logical value "0", and the bit BN＜2＞ of the second comparison signal is a logical value "1", the bit Cp＜2＞ of the first conversion control signal becomes a logical value "1", the bits Cp＜1:0＞ of the first conversion control signal remain unchanged, the second conversion control signal Cn＜2:0＞ remains unchanged, and the first comparison voltage Vcp increases by (8/1 2)×Vref, the second comparison voltage Vcn remains unchanged, the comparison voltage difference (Vcp-Vcn) is equal to (2/12)×Vref, since the comparison voltage difference (Vcp-Vcn) is greater than zero, the bit BP＜1＞ of the first comparison signal becomes a logical value "1", the bit BP＜2＞ and the bit BP＜0＞ of the first comparison signal remain unchanged, and the second comparison signal BN＜2:0＞ remains unchanged.

In the third conversion stage, the clock signal Φs remains unchanged, the bit Φ＜0＞ of the timing signal becomes a logical value "1", and the bits Φ＜2:1＞ of the timing signal remain unchanged. Therefore, since the bits BP＜2:1＞ of the first comparison signal are different logical values, the control signal Ctrl is the logical value "1", and the first conversion control signal Cp＜2:0＞ remains unchanged. Since the control signal Ctrl is the logical value "1", the bit BP＜1＞ of the first comparison signal is the logical value "1", and the bit BN＜1＞ of the second comparison signal is the logical value "0", the bits Cn＜1:0＞ of the second conversion control signal become the logical value "11", and the second conversion control signal Cp＜2:0＞ remains unchanged. The bit Cn＜2＞ of the control signal remains unchanged, the first comparison voltage Vcp remains unchanged, the second comparison voltage Vcn increases by (4/12)×Vref, the comparison voltage difference (Vcp-Vcn) is equal to (-2/12)×Vref, the first comparison signal BP＜2:0＞ remains unchanged, and since the comparison voltage difference (Vcp-Vcn) is less than zero, the bit BN＜0＞ of the second comparison signal becomes a logical value "1", and the bit BN＜2＞ and the bit BN＜0＞ of the second comparison signal remain unchanged. At the end of this stage, the digital output signal B＜2:0＞ changes to a logical value "010".

In summary, when the continuous approximation analog-to-digital converter of the present embodiment is used in a 6-level pulse amplitude modulation receiver, three comparators 31 ₁ -31 ₃ and the reference voltage Vref are required, and the converter has the advantages of small footprint and low power consumption.

However, the above is only an example of the implementation of the present invention, and it should not be used to limit the scope of the implementation of the present invention. All simple equivalent changes and modifications made according to the scope of the patent application of the present invention and the content of the patent specification are still within the scope of the patent of the present invention.

1: Switching circuit 11: First sampling switch Vip: First input voltage 12: Second sampling switch Vin: Second input voltage 2: Converting circuit 21: First capacitor group 211 ₁ -211 ₃ : First capacitor n1: First common node Vcp: First comparison voltage 22: Second capacitor group 221 ₁ -221 ₃ : Second capacitor n2: Second common node Vcn: Second comparison voltage 3: Comparator circuit 31 ₁ -31 ₃ : Comparator 32: Clock generator Φs: Clock signal Φ＜2:0＞: Timing signal 4: Register B＜2:0＞: Digital output signal 5: Controller 51: First switching group 511 ₁ -511 ₃ : First switch 52: Second switching group 521 ₁ -521 ₃ : Second switch Cp＜2:0＞: First conversion control signal Cn＜2:0＞: Second conversion control signal 53: Mutex OR gate 54: Control logic circuit BP＜2:0＞: First comparison signal BN＜2:0＞: Second comparison signal Ctrl: Control signal Vref: Reference voltage

Other features and effects of the present invention will be clearly presented in the embodiments with reference to the drawings, and it should be noted that various features may not be drawn to scale. FIG. 1 is a circuit block diagram illustrating an embodiment of the continuous approximation analog-to-digital converter of the present invention for a ( ^2N -2)-stage pulse amplitude modulation receiver; FIG. 2 is a circuit block diagram illustrating a controller in the embodiment; and FIG. 3 is a schematic diagram illustrating the relationship between the analog input signal and the digital output signal in the embodiment, and the binary search method used in the embodiment.

1: Switching circuit

11: First sampling switch

Vip: First input voltage

12: Second sampling switch

Vin: Second input voltage

2:Conversion circuit

21: First capacitor group

211 ₁ -211 ₃ : First capacitor

n1: first common node

Vcp: first comparison voltage

22: Second capacitor group

221 ₁ -221 ₃ : Second capacitor

n2: The second common node

Vcn: Second comparison voltage

3: Comparison circuit

31 ₁ -31 ₃ : Comparator

32: Pulse generator

Φs: clock signal

Φ<2:0>: Timing signal

4: Register

B<2:0>: digital output signal

5: Controller

BP<2:0>: first comparison signal

BN<2:0>: Second comparison signal

Claims (5)

A continuous approximation analog-to-digital converter is used to convert an analog input signal in a pulse amplitude modulation format of PAM-(2 ^N -2) into a digital output signal with a width of N bits, wherein N ≥ 3. The continuous approximation analog-to-digital converter comprises: a switching circuit for receiving a first input voltage and a second input voltage that jointly represent the analog input signal, the switching circuit operating between an on state and a off state, allowing the first input voltage and the second input voltage to pass when operating in the on state, and not allowing the first input voltage and the second input voltage to pass when operating in the off state; a conversion circuit, comprising: A first capacitor group has a first common node and N first capacitors, each of the first capacitors has a first end and a second end, the first common node is connected to the first ends of the first capacitors, and is connected to the switch circuit to receive the first input voltage, the first capacitors jointly output a first comparison voltage at the first common node, when the switch circuit operates in the open state, the first comparison voltage is equal to the first input voltage, when the switch circuit operates in the closed state, the first comparison voltage changes with the voltage of the second ends of the first capacitors, and a second capacitor group having a second common node and N second capacitors, each of the second capacitors having a first end and a second end, the second common node being connected to the first ends of the second capacitors and connected to the switch circuit to receive the second input voltage, the second capacitors jointly output a second comparison voltage at the second common node, when the switch circuit operates in the on state, the second comparison voltage is equal to the second input voltage, and when the switch circuit operates in the off state, the second comparison voltage changes with the voltages of the second ends of the second capacitors; a comparison circuit connected to the first common node and the second common node to receive the first comparison voltage and the second comparison voltage, the comparison circuit is used to compare the first comparison voltage and the second comparison voltage to generate a comparison output, the comparison output includes a first comparison signal and a second comparison signal with a width of N bits, and the least significant bit of the first comparison signal and the least significant bit of the second comparison signal are generated in association with the two first capacitors and the two second capacitors; a register connected to the comparison circuit to receive the comparison output and generate the digital output signal according to the comparison output; and a controller connected to the comparison circuit, the second terminals of the first capacitors, and the second terminals of the second capacitors, and configured to selectively provide one of a reference voltage or a ground voltage to the second terminals of the first capacitors and the second terminals of the second capacitors according to the comparison output for each of the first capacitors and each of the second capacitors; When the N-1 most significant bits of the first comparison signal have the same logical value, the controller provides the reference voltage and the ground voltage to the two first capacitors, respectively, and the two first capacitors are related to the lowest bit of the first comparison signal and the lowest bit of the second comparison signal. The controller also provides the reference voltage and the ground voltage to the two second capacitors, respectively, and the two second capacitors are related to the lowest bit of the first comparison signal and the lowest bit of the second comparison signal. The controller provides one of the reference voltage and the ground voltage to the two first capacitors, the two first capacitors are related to the lowest bit of the first comparison signal and the lowest bit of the second comparison signal, and the controller also provides the reference voltage and the ground voltage which have not been provided to the two second capacitors, the two second capacitors are related to the lowest bit of the first comparison signal and the lowest bit of the second comparison signal. A continuous approximation analog-to-digital converter as described in claim 1, wherein the controller further includes a first switch group, a second switch group, a mutex gate, and a control logic circuit, the first switch group has N first switches, each of the first switches has a first end, a second end, and a third end, the first ends of the first switches are respectively connected to the second ends of the first capacitors, the second ends of the first switches are used to receive the reference voltage, and the third ends of the first switches are used to receive the The second switch group has N second switches, each of which has a first end, a second end and a third end. The first ends of the second switches are connected to the second ends of the second capacitors, respectively. The second ends of the second switches are used to receive the reference voltage, and the third ends of the second switches are used to receive the ground voltage. When the first end and the second end of each of the first switches are connected to each other and the first end and the second end of each of the second switches are connected to each other, the first The first switch and the second switches are operated in a first state, the first end of each of the first switches is connected to the third end and the first end of each of the second switches is connected to the third end, the first switches and the second switches are operated in a second state, the exclusive OR gate has (N-1) input ends connected to the comparison circuit and used to respectively receive the (N-1) most significant bits of the first comparison signal, and an output end for providing a control signal, the control logic circuit is connected to receive the (N-1) most significant bits of the first comparison signal. The output end of the mutually exclusive OR gate of the control signal, the comparison circuit for receiving the (N-1) most significant bits of the first comparison signal and the (N-1) most significant bits of the second comparison signal, the first switches and the second switches, and the control logic circuit controls the conversion of the first switches and the second switches between the first state and the second state according to the control signal, the (N-1) most significant bits of the first comparison signal and the (N-1) most significant bits of the second comparison signal. A continuous approximation analog-to-digital converter as described in claim 1, wherein the comparator circuit includes N comparators and a timing generator, each of the comparators is connected to the first common node for receiving the first comparison voltage and the second common node for receiving the second comparison voltage, and each of the comparators can be switched between an enable mode and a disable mode, the enable mode generates a corresponding bit of the first comparison signal and a corresponding bit of the second comparison signal by comparing the first comparison voltage and the second comparison voltage. The disable mode is generated by not comparing the first comparison voltage and the second comparison voltage, the timing generator is connected to the comparators for receiving the (N-1) most significant bits of the first comparison signal and the (N-1) most significant bits of the second comparison signal, and a clock signal, and the timing generator controls the comparators to switch between the enable mode and the disable mode according to the (N-1) most significant bits of the first comparison signal, the (N-1) most significant bits of the second comparison signal and the clock signal. A continuous approximation analog-to-digital converter as described in claim 1, wherein the switching circuit includes a first sampling switch and a second sampling switch, the first sampling switch having a first end for receiving the first input voltage and a second end connected to the first common node, the second sampling switch having a first end for receiving the second input voltage and a second end connected to the second common node, the first sampling switch and the second sampling switch switching between conduction and non-conduction according to a clock signal, when the first sampling switch and the second sampling switch are both conducted, the switching circuit operates in the on state, and when the first sampling switch and the second sampling switch are both non-conducting, the switching circuit operates in the off state. A continuous approximation analog-to-digital converter as described in claim 1, wherein the capacitance value ratio of the first capacitor associated with the least significant bit of the first comparison signal and the first capacitor associated with the least significant bit of the second comparison signal is 3:1, and the capacitance value ratio of the second capacitor associated with the least significant bit of the first comparison signal and the second capacitor associated with the least significant bit of the second comparison signal is 3:1.

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