TWI864949B - Electronic component and manufacturing method thereof - Google Patents

Abstract

An electronic component including a substrate and an electronic device layer is provided. The substrate has a first surface and a second surface opposite to the first surface. The electronic device layer is disposed on the first surface of the substrate. A stress relief structure is disposed on the second surface of the substrate.

Description

Electronic component and method for manufacturing the same

The present invention relates to an electronic component and a manufacturing method thereof, and in particular to an electronic component with a stress release structure and a manufacturing method thereof.

The manufacturing process and/or application of electronic components often include a corresponding heating step. However, during the aforementioned heating process, due to the mismatch of the coefficient of thermal expansion (CTE) between materials, the overall stress of the structure may be too large, resulting in unexpected warping, and then causing corresponding deviation, cracking and/or delamination, thereby affecting the product yield and/or quality.

In general electronic components, additional reinforcement structures or reinforcement films are often used to reduce warp. However, the aforementioned methods often increase the corresponding thickness, require additional forming steps and/or components, and increase costs and/or manufacturing complexity. Therefore, how to adjust the warp and/or reduce the overall warp while reducing the corresponding cost and/or reducing the use of components has become a research topic.

The present invention provides an electronic component and a manufacturing method thereof, which can adjust the possible direction of warp and/or reduce the overall warp.

The manufacturing method of the electronic component of the present invention comprises the following steps: providing a substrate having a first surface and a second surface opposite to the first surface, and the first surface of the substrate has an electronic component layer; forming a stress release structure on the second surface of the substrate.

In one embodiment of the present invention, the stress relief structure is formed by removing a portion of the substrate from the second surface.

In one embodiment of the present invention, the method of removing a portion of the substrate includes laser scribing.

In one embodiment of the present invention, after forming the stress relief structure, at least a heating step is performed.

In one embodiment of the present invention, the electronic device has a first region and a second region separated from each other, wherein the conductor density in the first region is greater than the conductor density in the second region, and the stress relief structure density in the first region is greater than the stress relief structure density in the second region.

The electronic component of the present invention comprises a substrate and an electronic component layer. The substrate has a first surface and a second surface opposite to the first surface. The electronic component layer is located on the first surface of the substrate. The second surface of the substrate has a stress release structure.

In one embodiment of the present invention, the electronic device has a first region and a second region separated from each other, wherein the conductor density in the first region is greater than the conductor density in the second region, and the stress relief structure density in the first region is greater than the stress relief structure density in the second region.

In one embodiment of the present invention, the electronic component is a chip.

In one embodiment of the present invention, the electronic component is a wafer having a plurality of chip regions.

In one embodiment of the present invention, the stress relief structure patterns of each chip region are substantially the same.

Based on the above, the stress release structure on the second surface of the substrate can adjust the possible direction of warp and/or reduce the overall warp in the electronic component and/or its manufacturing process, thereby improving the product yield and/or quality.

Unless expressly stated otherwise, directional terms used herein (eg, up, down, top, bottom) are used only with reference to the drawings and are not intended to imply an absolute orientation.

Unless otherwise expressly stated, it is in no way intended that any method described herein be construed as requiring that its steps be performed in a specific order.

The present invention is more fully described with reference to the drawings of the present embodiment. However, the present invention may be embodied in various forms and should not be limited to the embodiments described herein. The thickness, size or size of the layers or regions in the drawings may be exaggerated for clarity. The same or similar reference numbers represent the same or similar elements, and the following paragraphs will not be repeated one by one.

1A to 1D are partial schematic diagrams of a partial manufacturing method of an electronic component according to the first embodiment of the present invention. FIG. 1E is a three-dimensional schematic diagram of an electronic component according to the first embodiment of the present invention.

1A , a substrate 110 is provided. In the present embodiment, the substrate 110 may include a semiconductor substrate. In the present embodiment, the substrate 110 may include a silicon wafer. In the present embodiment, the coefficient of thermal expansion (CTE) of the substrate 110 is substantially smaller than the coefficient of thermal expansion of metals (such as copper, aluminum, tin, gold or silver) commonly used in general semiconductor processes.

In one embodiment, the substrate 110 may be a substrate suitable for use in semiconductor processes. In one possible embodiment, a substrate similar to the substrate 110 may include but is not limited to: a silicon carbide substrate, a gallium nitride substrate or a glass plate.

The substrate 110 has a first surface 110a and a second surface 110b. The second surface 110b is opposite to the first surface 110a.

The first surface 110a of the substrate 110 has a corresponding electronic component layer 120. The electronic component layer 120 may include a corresponding conductive layer, a semiconductor layer, an insulating layer or a dielectric layer. The aforementioned film layer may be patterned or unpatterned, which is not limited in the present invention. The film layer in the electronic component layer 120 may constitute a corresponding active element (such as a transistor), a passive element (such as an electrolyte, a resistor or an inductor) and/or a wire.

In one embodiment, the electronic component layer 120 may include corresponding conductive terminals 128, but the present invention is not limited thereto. The conductive terminals 128 may include corresponding conductive posts and/or conductive materials (such as solder), but the present invention is not limited thereto. In addition, for simplicity, not all conductive terminals 128 are indicated one by one in the drawings.

1A and 1B , in one embodiment, the substrate 110 may be thinned according to the process and/or design requirements. In one embodiment, the substrate 110 may be thinned by polishing or other appropriate methods.

The thinned substrate 110 can still be referred to as the substrate 110 and the same symbol can be used. In addition, the second surface 110 b of the thinned substrate 110 can be a flat surface.

Referring to FIG. 1B to FIG. 1C , a stress release structure 150 is formed on a substrate 110. In addition, for the sake of distinction, the second surface 110c having the stress release structure 150 thereon is represented by a different symbol. In other words, the symbol 110c represents the second surface having the stress release structure 150 formed thereon, and the symbol 110b represents the second surface not having the stress release structure 150 formed thereon. In addition, for the sake of clarity, not all release structures 150 are marked one by one in the drawings.

In this embodiment, the stress release structure 150 may be formed on the second surface 110b (as shown in FIG. 1B ) of the thinned substrate 110. In an embodiment not shown, a similar stress release structure 150 may be formed on the second surface 110b (as shown in FIG. 1A ) of the unthinned substrate 110.

In this embodiment, a portion of the substrate 110 may be removed from the second surface 110 b to form a corresponding stress release structure 150 (ie, the second surface 110 c having the stress release structure 150 ).

In one embodiment, a portion of the substrate 110 may be removed from the second surface 110 b by laser scribing to form a corresponding stress release structure 150 (ie, the second surface 110 c having the stress release structure 150 ).

In one embodiment, a portion of the substrate 110 may be removed from the second surface 110 b by etching, mechanical grinding and/or other appropriate methods to form a corresponding stress release structure 150 (ie, the second surface 110 c having the stress release structure 150 ).

In this embodiment, the stress release structure 150 located on the second surface 110c can make the second surface 110c present a corresponding structural discontinuity, thereby making the surface stress discontinuous.

For example, the stress release structure 150 can make the second surface 110c present a corresponding concave-convex pattern instead of a continuous concave pattern or a continuous convex pattern.

For another example, in cross-section, the outer edge of the stress release structure 150 has a corresponding turning point (ie, discontinuity in slope) P1 (marked in FIG. 1D ).

In one embodiment, similar to FIG. 1E , the structure shown in FIG. 1C may be a wafer 101 (or a portion of the wafer) having a plurality of chip regions 102, and may be sufficient to be referred to as an electronic device 100. The electronic device 100 includes a substrate 110 and an electronic device layer 120. The electronic device layer 120 is located on a first surface 110 a of the substrate 110. The second surface 110 c of the substrate 110 has a stress relief structure 150 thereon.

In addition, for simplicity, not all chip regions 102 are marked one by one in FIG 1E , and the stress release structures 150 on the chip regions 102 are directly marked. Referring to FIG 1E , the pattern of the stress release structure 150 on the chip region 102 may correspond to the corresponding chip 103 shown.

1C and 1E , the chip regions 102 can be separated or distinguished by corresponding sealing rings and/or scribe lanes. For example, the wafer 101 can be cut along the corresponding scribe lanes to form a corresponding plurality of chips 103. Moreover, the pattern of the stress release structure 150 of each chip region 102 is substantially the same.

Referring to FIG. 1C , in a cross-sectional view, a wafer 101 (a type of electronic device 100 ) may be divided into a first region R1 and a second region R2 separated from each other. The conductor density in the first region R1 is greater than that in the second region R2, and the density of the stress relief structure 150 in the first region R1 is greater than that in the second region R2. The aforementioned conductor may include, but is not limited to: a portion of a conductive layer (e.g., a source, a drain, or a gate formed in a chip front end of line (FEOL); an interconnect or a line in a redistribution layer (RDL) formed in a chip back end of line (BEOL)) or a conductive terminal 128.

In one embodiment, the structure shown in FIG. 1C (which may be referred to as: electronic component 100; a wafer 101) may be suitable for being heated later. Moreover, since the second surface 110c of the substrate 110 has a stress release structure 150. Therefore, in the subsequent heating step, the possible direction of warpage and/or the overall warpage may be adjusted by the stress release structure 150 corresponding to the metal conductor in position (e.g.: the metal conductor and the stress release structure 150 are respectively on two opposite surfaces). In this way, the quality and/or yield of the structure shown in FIG. 1C in the subsequent process may be improved.

1C to 1D , a singulation process may be performed on the structure shown in FIG. 1C to form at least one structure shown in FIG. 1D .

It is worth noting that after the singulation process, similar component symbols will be used for the singulated components. For example, the substrate 110 (as shown in FIG. 1C ) can be the substrate 110 (as shown in FIG. 1D ) after singulation, the stress release structure 150 (as shown in FIG. 1C ) can be the stress release structure 150 (as shown in FIG. 1D ) after singulation, the electronic component layer 120 can be the electronic component layer 120 (as shown in FIG. 1D ) after singulation, and so on. Other components after singulation will follow the same component symbol rules as above and will not be described in detail here.

It is worth noting that in this embodiment, the substrate 110 may be thinned first, and then the corresponding stress release structure 150 is formed, and then a singulation process is performed. In an embodiment not shown, a singulation process may be performed first, and then the corresponding stress release structure 150 is formed. In an embodiment not shown, the substrate 110 may be thinned first, and then a singulation process may be performed first, and then the corresponding stress release structure 150 is formed. In an embodiment not shown, a singulation process may be performed first, and then the singulated substrate 110 is thinned, and then the corresponding stress release structure 150 is formed.

1D and 1E , the structure shown in FIG. 1D may correspond to a single chip region 102 (marked in FIG. 1E ), may be a chip 103 , and may be referred to as an electronic device 100 .

In one embodiment, the chip 103 shown in FIG. 1D may be suitable for subsequent heating. For example, the chip 103 may be fixed and/or electrically connected to other components (e.g., the conductive terminal 128 may be soldered to the circuit board, but not limited thereto) by a corresponding heating step. In addition, since the second surface 110c of the substrate 110 has a stress release structure 150. Therefore, in the subsequent heating step, the possible direction of warpage and/or the overall warpage may be adjusted by the stress release structure 150 corresponding to the metal conductor in position (e.g., the metal conductor and the stress release structure 150 are respectively on two opposite surfaces). In this way, the quality and/or yield of the structure shown in FIG. 1C in the subsequent process may be improved. In addition, corresponding heat energy may be generated during the operation of the electronic component 100, and the second surface 110c having the stress release structure 150 can also increase the heat dissipation area, thereby improving the heat dissipation efficiency.

Referring to FIG. 1C , in cross-sectional view, the chip 103 (a type of electronic device 100 ) can be divided into a first region R1 and a second region R2 separated from each other. The conductor density in the first region R1 is greater than the conductor density in the second region R2, and the density of the stress relief structure 150 in the first region R1 is greater than the density of the stress relief structure 150 in the second region R2. The aforementioned conductor may include but is not limited to: a source, a drain or a gate formed in a portion of a conductive layer (e.g., a chip front-end process); an internal connection or a line in a redistribution line formed in a chip back-end process) or a conductive terminal 128.

In one embodiment, the first region R1 is substantially the same as the second region R2 in cross-section. The vertical position and vertical distance of the first region R1 are substantially the same as the vertical position and vertical distance of the second region R2, and at least include the entire thickness of the electronic component 100. In one embodiment, the first region R1 may further include at least a plurality of conductive terminals 128 in cross-section.

Referring to FIG. 1E , when viewed from above (e.g., in the direction facing the second surface 110 c ), the stress release structure 150 may be a plurality of stripe structures. In one embodiment, the stripe structures may be formed by continuous or dense laser scribing, but the present invention is not limited thereto. The form, quantity, pattern and/or position of the stress release structure 150 may be adjusted according to the corresponding metal conductor.

Please refer to FIG. 1E , from above, the pattern of the stress release structure 150 may be slightly cross-shaped, but the present invention is not limited thereto.

FIG. 2 is a three-dimensional schematic diagram of an electronic component according to a second embodiment of the present invention.

The manufacturing method of the electronic component 200 of this embodiment is similar to the manufacturing method of the electronic component 100 of the aforementioned embodiment. Similar components are represented by the same reference numerals and have similar functions, materials or formation methods, and the description is omitted. For example, the electronic component 200 includes a substrate 110 and an electronic component layer 120. The second surface 110c of the substrate 110 has a stress relief structure 250. The formation method of the stress relief structure 250 can be the same or similar to the stress relief structure 150 of the aforementioned embodiment.

Please refer to FIG. 2 and FIG. 1D/FIG. 1E simultaneously. The electronic component 200 of this embodiment is similar to the electronic component 100 of the aforementioned embodiment. The difference between the two is that when viewed from above (eg, facing the direction of the second surface 110c), the stress release structure 250 can have different patterns.

2 , when viewed from above (eg, in the direction facing the second surface 110 c ), the stress release structure 250 may be a plurality of point structures. When viewed from above, the distribution of the stress release structure 250 may be slightly cross-shaped, but the present invention is not limited thereto.

In one embodiment, the electronic component 200 shown in FIG. 2 may be a portion of a wafer; or, a chip.

FIG3 is a three-dimensional schematic diagram of an electronic component according to a third embodiment of the present invention.

The manufacturing method of the electronic component 300 of this embodiment is similar to the manufacturing method of the electronic component 100 of the aforementioned embodiment. Similar components are represented by the same reference numerals and have similar functions, materials or formation methods, and the description is omitted. For example, the electronic component 300 includes a substrate 110 and an electronic component layer 120. The second surface 110c of the substrate 110 has a stress relief structure 350. The formation method of the stress relief structure 350 can be the same or similar to the stress relief structure 150 of the aforementioned embodiment.

Please refer to FIG. 3 and FIG. 1D/FIG. 1E simultaneously. The electronic component 300 of this embodiment is similar to the electronic component 100 of the aforementioned embodiment. The difference between the two is that when viewed from above (eg, in the direction facing the second surface 110c), the stress release structure 350 can have different patterns.

3 , from the above view (eg, in the direction facing the second surface 110 c ), the stress release structure 350 may be a plurality of point structures. From the above view, the stress release structure 350 is distributed on both sides of the electronic component 300 , but the present invention is not limited thereto.

In one embodiment, the electronic component 300 shown in FIG. 3 may be a part of a wafer; or, a chip.

FIG. 4 is a three-dimensional schematic diagram of an electronic component according to a fourth embodiment of the present invention.

The manufacturing method of the electronic component 400 of this embodiment is similar to the manufacturing method of the electronic component 100 of the aforementioned embodiment. Similar components are represented by the same reference numerals and have similar functions, materials or formation methods, and the description is omitted. For example, the electronic component 400 includes a substrate 110 and an electronic component layer 120. The second surface 110c of the substrate 110 has a stress relief structure 450. The formation method of the stress relief structure 450 can be the same or similar to the stress relief structure 150 of the aforementioned embodiment.

Please refer to FIG. 4 and FIG. 1D/FIG. 1E simultaneously. The electronic component 400 of this embodiment is similar to the electronic component 100 of the aforementioned embodiment. The difference between the two is that when viewed from above (eg, facing the direction of the second surface 110c), the stress release structure 450 can have different patterns.

4 , when viewed from above (eg, facing the second surface 110 c ), the stress release structure 450 may be a plurality of strip structures. When viewed from above, the pattern of the stress release structure 450 may be similar to a Chinese character “回”, but the present invention is not limited thereto.

In one embodiment, the electronic component 400 shown in FIG. 4 may be a part of a wafer; or, a chip.

In summary, based on the above, by means of the stress relief structure on the second surface of the substrate, the possible direction of warping and/or the overall warping can be adjusted in the electronic component and/or its manufacturing process. Moreover, the stress relief structure can be formed directly on the surface of the substrate without the need for additional components and/or film layers. In this way, the product yield and/or quality can be improved, and the possibility of corresponding thickness increase and/or complexity increase can also be reduced.

100, 200, 300, 400: electronic components 101: wafer 102: chip area 103: chip 110: substrate 110a: first surface 110b, 110c: second surface 120: electronic component layer 128: conductive terminal 150, 250, 350, 450: stress release structure R1: first area R2: second area P1: turning point

Figures 1A to 1D are partial schematic diagrams of a partial manufacturing method of an electronic component according to the first embodiment of the present invention. Figure 1E is a three-dimensional schematic diagram of an electronic component according to the first embodiment of the present invention. Figure 2 is a three-dimensional schematic diagram of an electronic component according to the second embodiment of the present invention. Figure 3 is a three-dimensional schematic diagram of an electronic component according to the third embodiment of the present invention. Figure 4 is a three-dimensional schematic diagram of an electronic component according to the fourth embodiment of the present invention.

100: Electronic components

101: Wafer

102: Chip area

103: Chip

110: Substrate

110c: Second surface

120: Electronic component layer

128: Conductive terminal

150: Stress relief structure

Claims (8)

A method for manufacturing an electronic component, comprising: providing a substrate having a first surface and a second surface opposite to the first surface, and having an electronic component layer on the first surface of the substrate; and forming a stress relief structure on the second surface of the substrate, wherein the electronic component has a first region and a second region separated from each other, wherein: the conductor density in the first region is greater than the conductor density in the second region; and the stress relief structure density in the first region is greater than the stress relief structure density in the second region. A method for manufacturing an electronic component as described in claim 1, wherein the stress relief structure is formed by removing a portion of the substrate from the second surface. A method for manufacturing an electronic component as described in claim 2, wherein the method for removing part of the substrate includes laser scribing. A method for manufacturing an electronic component as described in claim 1, wherein at least a heating step is performed after forming the stress release structure. An electronic component comprises: a substrate having a first surface and a second surface opposite to the first surface, wherein the second surface of the substrate has a stress relief structure; and an electronic component layer located on the first surface of the substrate, wherein the electronic component has a first region and a second region separated from each other, wherein: The conductor density in the first region is greater than the conductor density in the second region; and the stress relief structure density in the first region is greater than the stress relief structure density in the second region. The electronic component as described in claim 5 is a chip. The electronic component as described in claim 5 is a wafer having multiple chip regions. An electronic component as described in claim 7, wherein the stress release structural patterns of each chip region are substantially the same.

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