TWI864481B - Memory structure and manufacturing method thereof - Google Patents

Abstract

A memory structure includes a semiconductor substrate, a word line structure, and an isolation structure. The semiconductor substrate has a trench. The word line structure is located in the trench of the semiconductor, and has a lower gate electrode, a barrier layer surrounding the lower gate electrode, and an upper layer located on the barrier layer. The top surface of the lower gate electrode is arc-shaped. The edge of the top surface is lower than the center of the top surface. The isolation structure is located in the trench of the semiconductor substrate and on the word line structure.

Description

Memory structure and manufacturing method thereof

The present disclosure relates to a memory structure and a method for manufacturing the memory structure.

As technology advances, the size of integrated circuit chips is getting smaller and smaller. The internal parts of integrated circuit chips contain many semiconductor components such as diodes, transistors, and capacitors. Generally speaking, as the size of transistors decreases, the channel length of the component will also become smaller, thus causing the short channel effect, which will lead to more leakage current. In addition, in metal oxide semiconductor field effect transistors (MOSFETs), semiconductors with high reference doping concentrations will generate strong electric fields in the gate-drain overlap region and induce leakage current. This phenomenon is called gate-induced drain leakage (GIDL). In memory cell transistors, dual metal (DM) gates can be used to improve the GIDL problem, but the gate materials usually include polysilicon with a lower work function and tungsten with a higher work function. Polysilicon will increase the resistance of the word line containing the dual gate and reduce the conductivity, which will reduce the signal transmission speed.

One technical aspect of the present disclosure is a memory structure.

According to some embodiments of the present disclosure, a memory structure includes a semiconductor substrate, a word line structure, and an isolation structure. The semiconductor substrate has a trench. The word line structure is located in the trench of the semiconductor substrate and has a lower gate, a blocking layer covering the lower gate, and an upper gate located on the blocking layer. The top surface of the lower gate is arc-shaped, and the edge of the top surface is lower than the center of the top surface. The isolation structure is located in the trench of the semiconductor substrate and on the word line structure.

In some embodiments, the blocking layer has a first portion and a second portion. The second portion is located between the upper gate and the lower gate, and the first portion is located between the bottom of the trench and the lower gate. The second portion is disposed along the top surface of the lower gate and is arc-shaped.

In some implementations, the bottom surface of the upper gate contacts the second portion of the blocking layer and is arc-shaped.

In some implementations, a distance between a top surface and a bottom surface of the upper gate is in a range of 10 nm to 100 nm.

In some implementations, the thickness of the upper gate gradually increases from the center of the upper gate toward the edge of the upper gate.

In some embodiments, the memory structure further includes an insulating layer and an oxide layer. The insulating layer is located on the top surface of the semiconductor substrate. The oxide layer is located between the word line structure and the sidewall of the trench of the semiconductor substrate and extends between the isolation structure and the insulating layer, and contacts the blocking layer and the upper gate.

In some implementations, the lower gate and the upper gate are made of different materials.

Another technical aspect of the present disclosure is a method for manufacturing a memory structure.

According to some embodiments of the present disclosure, a method for manufacturing a memory structure includes forming a trench in a semiconductor substrate; forming a first portion of a blocking layer in the trench of the semiconductor substrate; forming a lower gate in the trench of the semiconductor substrate and on the first portion of the blocking layer; etching the lower gate so that the top surface of the lower gate is arc-shaped and the edge of the top surface is The semiconductor substrate is provided with a first semiconductor layer and a second semiconductor layer formed therein, wherein the first semiconductor layer is provided with a second semiconductor layer and a second semiconductor layer is provided at a lower portion of the semiconductor substrate. The second semiconductor layer is provided with a second semiconductor layer and a second semiconductor layer is provided at a lower portion of the semiconductor substrate. The second semiconductor layer is provided with a second semiconductor layer and a second semiconductor layer is provided at a lower portion of the semiconductor substrate.

In some embodiments, the method for manufacturing the memory structure includes etching the upper gate so that the distance between the top surface and the bottom surface of the upper gate is in the range of 10 nanometers to 100 nanometers.

In some embodiments, the etching of the lower gate to make the top surface of the lower gate arc-shaped is performed using an etchant having a high selectivity to metal.

In the above-mentioned embodiment of the present disclosure, since the top surface of the lower gate of the word line structure is arc-shaped and the edge of the top surface is lower than the center of the top surface, the blocking layer is located on the lower gate, and the upper gate is located on the blocking layer, therefore, compared with the traditional double metal gate design, the cross-sectional area of the lower gate of this word line structure is further increased and the cross-sectional area of the upper gate is further reduced, so that the influence of the lower gate on the resistance of the word line structure is increased, and the influence of the upper gate on the resistance of the word line structure is reduced. After selecting appropriate materials as the lower gate (such as tungsten) and the upper gate (such as polysilicon), the resistance of the word line structure can be made lower than that of the traditional double metal gate word line, thereby increasing the signal transmission speed. In addition, the upper gate can still maintain a sufficiently thick edge thickness, which not only reduces the resistance of the word line structure, but also reduces the gate induced drain leakage (GIDL). Therefore, the word line structure can replace the traditional gate design and can be used in the transistor of the memory cell. In addition to reducing the GIDL caused by the shrinking of transistor elements, it also reduces the resistance of the word line and improves the conductivity to increase the speed of signal transmission.

The embodiments disclosed below provide many different embodiments, or examples, for implementing different features of the subject matter provided. Specific examples of components and arrangements are described below to simplify the present invention. Of course, these examples are only examples and are not intended to be limiting. In addition, the present invention may repeat component symbols and/or letters in each example. This repetition is for the purpose of simplicity and clarity, and does not itself specify the relationship between the various embodiments and/or configurations discussed.

Spatially relative terms such as "below," "beneath," "lower," "above," "upper," and the like may be used herein for descriptive purposes to describe the relationship of one element or feature to another element or feature as illustrated in the accompanying figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the accompanying figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

FIG. 1 shows a cross-sectional view of a memory structure 100 according to an embodiment of the present disclosure. As shown in the figure, the memory structure 100 includes a semiconductor substrate 120, a word line structure 140 and an isolation structure 160. The semiconductor substrate 120 has a trench 122, and the bottom of the trench 122 is arc-shaped. The word line structure 140 is located in the trench 122 of the semiconductor substrate 120 and has a lower gate 141, a blocking layer 142 and an upper gate 143. The blocking layer 142 covers the lower gate 141. The upper gate 143 is located on the blocking layer 142. With such a configuration, the blocking layer 142 can prevent the lower gate 141 from contacting the upper gate 143, thereby preventing the lower gate 141 from reacting with the upper gate 143 to form a compound. In addition, the top surface 144 of the lower gate 141 is arc-shaped, and the edge of the top surface 144 is lower than the center of the top surface 144, so that the cross-sectional area of the lower gate 141 is larger than the cross-sectional area of the upper gate 143, thereby further enhancing the influence of the lower gate 141 on the resistance and conductivity of the word line structure 140. Herein, the cross-sectional area of the lower gate 141 and the cross-sectional area of the upper gate 143 can be represented by the area of the pattern region where each is located in FIG. 1 . The isolation structure 160 is located in the trench 122 of the semiconductor substrate 120 and on the word line structure 140 .

In some embodiments, the material of the lower gate 141 may be metal, such as tungsten, and the material of the upper gate 143 may be polysilicon with a low work function. This design can be used to reduce gate induced drain leakage (GIDL). The material of the blocking layer 142 and the isolation structure 160 may be nitride. For example, the material of the blocking layer 142 may be titanium nitride, and the material of the isolation structure 160 may be silicon nitride, but this is not intended to limit the present disclosure.

Since the top surface 144 of the lower gate 141 of the word line structure 140 is arc-shaped, compared with the traditional double metal gate design, the cross-sectional area of the lower gate 141 is further increased, and the cross-sectional area of the upper gate 143 is further reduced, so that the influence of the lower gate 141 on the resistance of the word line structure 140 is increased, and the influence of the upper gate 143 on the resistance of the word line structure 140 is reduced. After selecting appropriate materials as the lower gate 141 (such as tungsten metal) and the upper gate 143 (such as polysilicon), the resistance of the word line structure 140 can be made lower than the resistance of the word line using the traditional double metal gate design, and the conductivity can be increased to improve the speed of signal transmission. In addition, since the edge thickness of the upper gate 143 is thick enough, in addition to reducing the resistance of the word line structure 140, the characteristic of reducing GIDL can also be maintained at the same time. The word line structure 140 can replace the traditional gate design and can be used in the transistor of the memory cell. In addition to reducing the GIDL caused by the shrinking of the transistor element, it can also reduce the resistance of the word line, so that the conductivity and signal transmission speed are improved.

In the present embodiment, the blocking layer 142 has a first portion 147 and a second portion 148. The first portion 147 of the blocking layer 142 is located between the surface of the bottom of the trench 122 of the semiconductor substrate 120 and the lower gate 141. The second portion 148 of the blocking layer 142 is located between the upper gate 143 and the lower gate 141, and the second portion 148 is disposed along the top surface 144 of the lower gate 141 and is arc-shaped. The blocking layer 142 can prevent the lower gate 141 from contacting the upper gate 143, thereby preventing the lower gate 141 and the upper gate 143 from reacting and forming a compound. In some embodiments, the material of the blocking layer 142 is different from the material of the lower gate 141 and the upper gate 143. The material of the blocking layer 142 includes metal nitride, for example, titanium nitride, but this is not intended to limit the present disclosure.

In addition, the bottom surface of the upper gate 143 contacts the second portion 148 of the blocking layer 142 and is arc-shaped. In some embodiments, the distance D between the top surface and the bottom surface of the upper gate 143 is in the range of 10 nm to 100 nm, and the thickness of the upper gate 143 in the vertical direction gradually increases from the center of the upper gate 143 to the edge of the upper gate 143. In other words, the top surface of the upper gate 143 is flatter than the arc-shaped bottom surface, so that the thickness of the upper gate 143 changes with the position. Since the upper gate 143 is thickest at the edge and thinnest at the center, the upper gate 143 has a smaller cross-sectional area than a conventional layered structure, thereby reducing the effect of the upper gate 143 on the resistance of the word line structure 140. Therefore, after selecting appropriate materials (for example, the upper gate 143 is polysilicon and the lower gate 141 is tungsten), the resistance of the word line structure 140 can be reduced. In addition, the upper gate 143 still has a sufficiently thick edge to reduce GIDL.

In this embodiment, the memory structure 100 may further include an insulating layer 180 and an oxide layer 190. The insulating layer 180 is located on the top surface of the semiconductor substrate 120 and adjacent to the trench 122 of the semiconductor substrate 120. The oxide layer 190 is located between the word line structure 140 and the sidewall of the trench 122 of the semiconductor substrate 120 and extends to a position between the isolation structure 160 and the insulating layer 180. The oxide layer 190 contacts the first portion 147 of the blocking layer 142 and the upper gate 143. The oxide layer 190 serves as a gate dielectric, the semiconductor substrate 120 serves as a base, and the word line structure 140 serves as a gate, so that a metal oxide semiconductor (MOS) capacitor can be formed, which is a necessary structure in a metal oxide semiconductor field effect transistor (MOSFET). In some embodiments, the material of the oxide layer 190 includes silicon dioxide, and the material of the semiconductor substrate 120 includes silicon, but this is not intended to limit the present disclosure.

In the present embodiment, the material of the lower gate 141 of the word line structure 140 is different from the material of the upper gate 143. In some embodiments, the material of the lower gate 141 may be a metal, including tungsten; the material of the upper gate 143 may be a material with a low work function, including polysilicon with a low work function, for example, N-type impurity-doped polysilicon. In this way, the problem of GIDL in the traditional single metal gate word line can be improved. This word line structure 140 can be applied to MOSFET, and can also be further applied to the transistor of the memory cell to reduce the GIDL caused by size reduction and improve the analog performance. In addition, since the second portion 148 of the blocking layer 142 is located between the upper gate 143 and the lower gate 141 , the interaction between the material of the lower gate 141 and the material of the upper gate 143 can be blocked, thereby preventing the formation of a compound (such as tungsten silicide).

It should be understood that the connection relationship, materials and functions of the components described above will not be repeated, and are described first. In the following description, a method for manufacturing the memory structure 100 is described.

FIG. 2 to FIG. 7 illustrate cross-sectional views of the manufacturing method of the memory structure 100 in FIG. 1 at an intermediate stage. Referring to FIG. 2, the manufacturing method of the memory structure 100 includes forming an insulating layer 180 on the upper surface of the semiconductor substrate 120, forming a trench 122 in the semiconductor substrate 120, and forming an oxide layer 190 on the surface of the trench 122, the sidewall of the insulating layer 180, and the top surface of the insulating layer 180. In some embodiments, the oxide layer 190 can be formed by atomic layer deposition (ALD) or by atomic layer deposition and in-situ steam generation (ISSG) rapid thermal processing oxidation.

Referring to FIG. 3 and FIG. 4 simultaneously, the first portion 147 of the blocking layer 142 may then be formed in the trench 122 of the semiconductor substrate 120 and on the insulating layer 180. Then, the lower gate 141 is formed in the trench 122 of the semiconductor substrate 120 and on the first portion 147 of the blocking layer 142. Next, the lower gate 141 is etched so that the top surface 144 of the lower gate 141 is arc-shaped, and the edge of the top surface 144 is lower than the center of the top surface 144. In addition, the first portion 147 of the blocking layer 142 is etched so that the first portion 147 of the blocking layer 142 is not higher than the edge of the lower gate 141. In some embodiments, the material of the lower gate 141 and the material of the first portion 147 of the blocking layer 142 are different metals. The lower gate 141 and the first portion 147 of the blocking layer 142 can be etched using an etchant with a high selectivity to metal, so that the top surface 144 of the lower gate 141 is curved and the first portion 147 of the blocking layer 142 is not higher than the edge of the lower gate 141.

Referring to FIG. 5 and FIG. 6 simultaneously, the second portion 148 of the blocking layer 142 may then be formed in the trench 122 of the semiconductor substrate 120 and on the lower gate 141, so that the lower gate 141 is covered by the first portion 147 and the second portion 148 of the blocking layer 142. The first portion 147 and the second portion 148 of the blocking layer 142 may be the same material, so the interface is not shown. The first portion 147 and the second portion 148 of the blocking layer 142 may have the same thickness, and the second portion 148 is arc-shaped. Then, the upper gate 143 may be formed in the trench 122 of the semiconductor substrate 120, the second portion 148 of the blocking layer 142, and on the oxide layer 190. Since the second portion 148 of the blocking layer 142 separates the lower gate 141 from the upper gate 143, the material of the lower gate 141 and the material of the upper gate 143 are prevented from interacting to produce a compound. Then, dry etching can be used to make the distance D between the top surface and the bottom surface of the upper gate 143 in the range of 10 nm to 100 nm, and then the lower gate 141, the blocking layer 142 and the upper gate 143 can define the word line structure 140. Since the bottom surface of the upper gate 143 is curved, the top surface is flatter than the bottom surface, and the thickness of the upper gate 143 gradually increases from the center to the edge, the upper gate 143 has a smaller cross-sectional area compared to the traditional layered gate structure, so that the material of the upper gate 143 has a smaller impact on the resistance of the word line structure 140. Since the top surface 144 of the lower gate 141 is curved, the lower gate 141 has a larger cross-sectional area compared to the traditional gate structure, so that the material (such as metal) of the lower gate 141 has a greater impact on the resistance of the word line structure 140.

Referring to FIG. 1 and FIG. 7 at the same time, an isolation structure 160 may then be formed in the trench 122 of the semiconductor substrate 120, on the word line structure 140, and on the oxide layer 190, so that the isolation structure 160 fills the trench 122 and covers the insulating layer 180 and the oxide layer 190, thereby obtaining the memory structure 100 of FIG. 1. In subsequent processes, the isolation structure 160, the oxide layer 190, and the insulating layer 180 above the insulating layer 180 may be removed by a chemical mechanical polishing planarization process, so that the top surface of the isolation structure 160 is coplanar with the top surface of the oxide layer 190.

The foregoing summarizes the features of several embodiments so that those skilled in the art can better understand the aspects of the present disclosure. Those skilled in the art should understand that they can easily use the present disclosure as a basis for designing or modifying other processes and structures to achieve the same purpose and/or achieve the same advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions and modifications here without departing from the spirit and scope of the present disclosure.

100: memory structure 120: semiconductor substrate 122: trench 140: word line structure 141: lower gate 142: blocking layer 143: upper gate 144: top surface 147: first part 148: second part 160: isolation structure 180: insulation layer 190: oxide layer D: distance

The disclosure is best understood from the following embodiments when read in conjunction with the accompanying illustrations. Note that in accordance with standard practice in the industry, the various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or decreased for clarity of discussion. FIG. 1 illustrates a cross-sectional view of a memory structure according to an embodiment of the disclosure. FIGS. 2 to 7 illustrate cross-sectional views of the method of manufacturing the memory structure of FIG. 1 at intermediate stages.

100:Memory structure

120:Semiconductor substrate

122: Groove

140: Character line structure

141: Lower gate pole

142: Barrier layer

143: Upper gate pole

144: Top

147: Part 1

148: Part 2

160: Isolation structure

180: Insulation layer

190: Oxide layer

D: Distance

Claims (8)

A memory structure includes: a semiconductor substrate having a trench; a word line structure located in the trench of the semiconductor substrate, having a lower gate, a blocking layer covering the lower gate, and an upper gate located on the blocking layer, wherein the distance between the top surface and the bottom surface of the upper gate is in the range of 10 nanometers to 100 nanometers, wherein a top surface of the lower gate is arc-shaped and the top surface There is no horizontal portion, and the edge of the top surface is lower than the center of the top surface, and the bottom surface of the upper gate contacts the blocking layer and is arc-shaped; an isolation structure is located in the trench of the semiconductor substrate and on the word line structure; and an oxide layer is located on a side wall of the trench and contacts the word line structure and the isolation structure, wherein an upper surface of the oxide layer is coplanar with an upper surface of the isolation structure. The memory structure as described in claim 1, wherein the blocking layer has a first portion and a second portion, the second portion is between the upper gate and the lower gate, the first portion is between the bottom of the trench and the lower gate, and the second portion is arranged along the top surface of the lower gate and is arc-shaped. A memory structure as described in claim 1, wherein the material of the blocking layer includes nitride. A memory structure as described in claim 1, wherein the thickness of the upper gate gradually increases from the center of the upper gate to the edge of the upper gate. The memory structure as described in claim 1 further includes: an insulating layer located on the top surface of the semiconductor substrate; wherein the oxide layer is located between the word line structure and the sidewall of the trench of the semiconductor substrate and extends between the isolation structure and the insulating layer, and the oxide layer contacts the blocking layer and the upper gate. A memory structure as described in claim 1, wherein the material of the lower gate is different from that of the upper gate. A method for manufacturing a memory structure includes: forming a trench in a semiconductor substrate; forming an oxide layer in the trench; forming a first portion of a blocking layer in the trench of the semiconductor substrate; forming a lower gate in the trench of the semiconductor substrate and on the first portion of the blocking layer; etching the lower gate so that a top surface of the lower gate is arc-shaped, the top surface has no horizontal portion, and the edge of the top surface is lower than the center of the top surface; forming a second portion of the blocking layer in the trench of the semiconductor substrate and on the lower gate so that the lower gate is covered by the blocking layer; forming an upper gate on the blocking layer; The method comprises: forming a semiconductor substrate on the second portion of the semiconductor substrate, and making the bottom surface of the upper gate electrode contact the blocking layer and be arc-shaped; etching the upper gate electrode so that the distance between the top surface and the bottom surface of the upper gate electrode is in the range of 10 nanometers to 100 nanometers, wherein the lower gate electrode, the blocking layer and the upper gate electrode define a word line structure; forming an isolation structure in the trench of the semiconductor substrate and on the word line structure, wherein the oxide layer is located on a side wall of the trench and contacts the word line structure and the isolation structure; and planarizing the isolation structure and the oxide layer so that an upper surface of the oxide layer is coplanar with an upper surface of the isolation structure. A method for manufacturing a memory structure as described in claim 7, wherein etching the lower gate electrode so that the top surface of the lower gate electrode is arc-shaped uses an etchant with a high selectivity to metal.

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