TWI863723B - Integrated circuit structure and method for operating the same - Google Patents

Abstract

An integrated circuit structure structure includes a substrate and a first resistive memory string over the substrate. The first resistive memory string includes memory cells, and each of the memory cells includes a word line transistor and a resistor. The word line transistor includes a channel region, a gate over the channel region, and a plurality of source/drain regions on opposite sides of the channel region. The resistor is over the word line transistor and is connected with the word line transistor in parallel. The word line transistors of two adjacent memory cells share a same one of the source/drain regions, and the memory cells are connected in series using the sharing ones of the source/drain regions.

Description

Integrated circuit structure and operation method thereof

The present disclosure relates to an integrated circuit structure, and more particularly to an operating method of the integrated circuit structure.

The semiconductor industry has experienced rapid growth due to the continuous improvement in the integration density of various electronic components such as transistors, diodes, resistors, capacitors, etc. In most cases, the increase in integration density comes from the repeated reduction of minimum feature size, which allows more components to be integrated into a given area.

The present disclosure provides an integrated circuit structure. The integrated circuit structure includes a substrate and a first resistive memory string. The first resistive memory string is located above the substrate and includes multiple memory cells. Each of the multiple memory cells includes a word line transistor, a gate, and a resistor. The word line transistor includes a channel region, a gate located above the channel region, and multiple source/drain regions located on opposite sides of the channel region. The resistor is located above the word line transistor and is connected in parallel with the word line transistor. Two adjacent word line transistors of the multiple memory cells share the same source/drain region, and the multiple memory cells are connected in series using the multiple shared source/drain regions.

In some embodiments, each of the plurality of memory cells further includes a pair of contact structures. The contact structures are located above the source/drain regions. The resistor is located above a first one of the contact structures and is not covered by a second one of the contact structures.

In some embodiments, each of the plurality of memory cells further includes a metal line extending laterally from above the resistor, across the gate, to above a second one of the contact structures. The resistor is connected in series with the word line transistor using the contact structure and the metal line.

In some implementations, the metal lines are arranged in two rows from a top view. Each of the metal lines is offset relative to the next metal line along the length of the gate.

In some embodiments, the integrated circuit structure further includes a string select transistor and a ground select line transistor. The string select transistor has a source/drain region. The source/drain region of the string select transistor is electrically coupled to a first terminal of the source/drain region of the first resistive memory string. The ground select line transistor has a source/drain region. The source/drain region of the ground select line transistor is electrically coupled to a second terminal of the source/drain region of the first resistive memory string, and a gate of the string select transistor is electrically coupled to a gate of the ground select line transistor.

In some embodiments, the integrated circuit structure further includes: a second resistive memory string and an auxiliary transistor. The second resistive memory string is located above the substrate. The auxiliary transistor is located above the substrate and electrically couples a first terminal of the pole/drain region of the second resistive memory string to a second terminal of the source/drain region of the first resistive memory string.

The present disclosure provides an integrated circuit structure. The integrated circuit structure includes a substrate and a resistive memory string. The substrate has a diffusion region. The resistive memory string includes a first sub-string, a second sub-string, a first metal line, and a third metal contact structure. The first sub-string includes a first gate and a second gate extending above the diffusion region, and a first metal contact structure located between the first gate and the second gate and above the diffusion region. The second sub-string includes a third gate and a fourth gate extending above the diffusion region, and a second metal contact structure located between the third gate and the fourth gate and above the diffusion region. The first metal line extends laterally from above the first metal contact structure of the first substring, across the second gate and the third gate, to above the second metal contact structure of the second substring. The third metal contact structure is located between the second gate and the third gate and above the diffusion region, and the third metal contact structure is configured to apply an operating voltage.

In some embodiments, a region without metal contact structure is defined between the first metal contact structure and the second metal contact structure, and the region without metal contact structure is located below the first metal line.

In some embodiments, the second substring further includes a fourth metal contact structure, a fifth metal contact structure, a first resistor, and a second metal line. The fourth metal contact structure and a fifth metal contact structure are located above the diffusion region and on opposite sides of the fourth gate. The first resistor is located above the fourth metal contact structure. The second metal line extends laterally from above the first resistor, across the fourth gate, to above the fifth metal contact structure.

In some embodiments, the first metal contact structure and the second metal contact structure are arranged in a first row, and the third metal contact structure, the fourth metal contact structure, and the fifth metal contact structure are arranged in a second row.

In some embodiments, the first substring further includes a sixth metal contact structure, a seventh metal contact structure, a second resistor, and a third metal line. The sixth metal contact structure and the seventh metal contact structure are located above the diffusion region and on opposite sides of the first gate. The second resistor is located above the sixth metal contact structure. The third metal line extends laterally from above the second resistor, across the first gate, to above the seventh metal contact structure.

In some embodiments, the first metal contact structure and the second metal contact structure are arranged in a first row, and the third metal contact structure, the fourth metal contact structure, the fifth metal contact structure, the sixth metal contact structure, and the seventh metal contact structure are arranged in a second row.

In some implementations, the integrated circuit structure further includes a resistor. The resistor is vertically disposed between the first metal contact structure and the first metal line.

The present disclosure provides an operation method of an integrated circuit structure. The integrated circuit structure includes a resistive memory string located above a substrate, and the resistive memory string has a plurality of sub-strings connected in series. Each of the plurality of sub-strings includes a plurality of word line transistors connected in series and a pair of terminal transistors, thereby forming a connection terminal between two adjacent plurality of terminal transistors of the plurality of sub-strings. Each of the plurality of sub-strings also includes a plurality of resistors. Each of the plurality of resistors is connected in parallel to a corresponding one of the plurality of word line transistors. The method includes: alternately applying a first operating voltage and a second operating voltage to a plurality of connection terminals of the resistive memory string; performing a programming operation on the resistive memory string; and performing an erase operation on the resistive memory string.

In some embodiments, the first operating voltage is a programming voltage and the second operating voltage is a ground voltage.

In some implementations, the step of performing a programming operation or performing an erase operation includes: turning on the aforementioned pair of terminal transistors of one of the plurality of substrings, the one of the plurality of substrings being a selected cell group, wherein the turning on step causes a voltage difference to be formed between the aforementioned pair of terminal transistors of the plurality of substrings, thereby causing a current to flow through the aforementioned one of the plurality of substrings.

In some implementations, the method further includes: turning off one of the word line transistors of one of the sub-strings, allowing current to flow through a resistor connected in parallel with the turned-off word line transistor.

In some embodiments, the method further includes: turning on one of the word line transistors of one of the substrings, allowing current to flow through the first one of the word line transistors that is turned on, but bypassing a resistor connected in parallel with the first one of the word line transistors that is turned on.

In some implementations, the step of performing a programming operation or performing an erase operation includes: turning on a first one of the aforementioned pair of terminal transistors of one of the plurality of substrings; turning off a second one of the aforementioned pair of terminal transistors of the aforementioned one of the plurality of substrings, the aforementioned one of the plurality of substrings serving as an operation voltage inhibition region, wherein the turning on step and the turning off step maintain a consistent voltage between the aforementioned pair of terminal transistors of the aforementioned one of the plurality of substrings to eliminate operation interference of the aforementioned one of the plurality of substrings.

In some implementations, the method further includes turning on a plurality of word line transistors of a plurality of sub-strings.

The following disclosure provides many different embodiments, or examples, for implementing different features of the subject matter provided. Specific examples of components and configurations are described below to simplify the disclosure. Of course, these are examples only and are not intended to be limiting. For example, in the following description, the formation of a first feature above or on a second feature may include an embodiment in which the first feature and the second feature are directly in contact, and may also include an embodiment in which an additional feature may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, the disclosure may repeatedly refer to numbers and/or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself specify the relationship between the various embodiments and/or configurations discussed.

Additionally, for ease of description, spatially relative terminology such as "below," "beneath," "lower," "above," "upper," and the like may be used herein to describe the relationship of one element or feature to another element or feature illustrated in the figures. Spatially relative terminology is intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should be similarly interpreted accordingly.

As used herein, "approximately," "about," "roughly," or "substantially" shall generally mean within 20%, or within 10%, or within 5% of a given value or range. However, one skilled in the art will recognize that the values or ranges cited throughout the description are examples only and may decrease as the scale of integrated circuits decreases. The quantities given herein are approximate, meaning that the terms "approximately," "about," "roughly," or "substantially" may be inferred where not expressly stated.

Resistive random-access memories (ReRAMs) are available in a variety of array configurations, including NOR-type and NAND-type settings. NAND-type resistive memory strings can be used in a mixed-mode matrix-vector multiplication (MVM) architecture. In this architecture, each weight cell can be designed with a resistive memory cell in parallel with a transistor. These memory cells can vary in type, from resistive memory to phase change memories (PCMs). When combined, they can form a series-connected NAND-type resistive memory string. However, this architecture faces challenges during certain operations, such as reading or programming/erasing. For example, to achieve a selected memory cell requires turning off its associated transistor, while the transistors in the unselected cells remain active. This design choice, combined with the series connection of multiple resistive memory cells, can result in an increase in series impedance, which can affect the efficiency of the selected memory cell.

Therefore, various embodiments of the present disclosure provide a layout to improve long NAND-type resistive memory strings so that the series (or loading) impedance associated with the selected memory cell can be reduced. The present disclosure introduces an additional electrical connection structure (pickup connection) to the long NAND-type resistive memory string. The additional electrical connection structure can divide the long impedance string (R-string) into shorter ones. In addition, a suppression scheme can be applied to the unselected memory cells on the resistive memory string, ensuring that the unselected memory cells remain undisturbed during operation.

Refer to Figures 1A to 1E. Figure 1A is a schematic diagram of a memory cell 101 according to some embodiments of the present disclosure. Figure 1B shows a schematic circuit diagram of a resistive memory string 100 including multiple memory cells 101 according to some embodiments of the present disclosure. In some embodiments, the resistive memory string 100 can be a NAND-type resistive memory string. Figure 1C shows a schematic top view of a semiconductor structure 10 including a resistive memory string 100 according to some embodiments of the present disclosure. Figures 1D and 1E show schematic cross-sectional views obtained from reference section D1-D1’ and reference section E1-E1’ of Figure 1C.

As shown in FIG. 1A , the memory cell 101 may include a current-carrying node 102, a current-carrying node 103, a control terminal 104, a transistor 105, and a programmable resistor 106. In some embodiments, the memory cell 101 may be a variable impedance cell, and the programmable resistor 106 may be interactively referred to as a resistive memory cell. The voltage V _S at the current-carrying node 102 may be described as a source voltage of the memory cell 101, and the voltage V _D at the second current-carrying node 103 may be described as a drain voltage of the memory cell 101. Transistor 105 and programmable resistor 106 are connected in parallel with power node 102 and power node 103. The gate of transistor 105 is connected to control terminal 104. Control terminal 104 may correspond to a wordline in a memory array (e.g., wordlines 120-124 as shown in FIG. 1C). The voltage _VG on control terminal 104 may be described as the gate voltage of transistor 105.

In some embodiments, a cell current may be applied to the power node 103, with a current amplitude that is set or adjustable in the design to establish a voltage drop in the memory cell 101 based on the voltage range of the voltage sense amplifier and the resistance of the programmable resistor 106 in the memory cell. The current amplitude may be adjusted based on the specific implementation of the memory array to generate a usable range of voltages across the resistive memory string 100 (see FIG. 1B ) supplied to the summing node. In addition, the programmable resistance range of the programmable resistor 106 and the programmable critical configuration of the transistor 105 may be designed to operate with a selected current level and a specified sensing range.

In some embodiments, transistor 105 can be implemented using a MOS transistor, having an n-channel or a p-channel, configured as a switch, providing a low impedance path when transistor 105 is turned on, effectively bypassing programmable resistor 106, so that the voltage drop of memory cell 101 can be very small; and providing a high impedance path when transistor 105 is turned off, effectively blocking the current through the switch, so that the voltage drop of memory cell 101 is mainly caused by the resistance of the programmable resistor and the current through memory cell 101.

As shown in FIG. 1B , a resistive memory string 100 may include a plurality of memory cells 101, wherein each memory cell 101 may include a transistor 105 and a programmable resistor 106 connected in parallel therewith. In the resistive memory string 100, the direction of current plays a role in manipulating the resistance value of a particular programmable resistor 106. To achieve this, each memory cell 101 in the resistive memory string 100 is equipped with a parallel transistor 105. When the goal is to program the resistance value of the programmable resistor 106 in a target memory cell 101, the associated parallel transistor 105 in the target cell is turned off. This action isolates the programmable resistor 106, ensuring that the programming current flows directly through it. At the same time, to ensure that the rest of the memory string 100 remains operational and that the current does not erroneously change other programmable resistors 106, the parallel transistors 105 of all other memory cells 101 in the resistive memory string 100 remain turned on. This regulation allows for precise control of a single programmable resistor 106 in the memory string 100, ensuring accurate data storage and retrieval.

By way of example and not limitation of the present disclosure, the resistive memory string 100 may include five memory cells 101 connected in series between a summing node 107 and a reference line (e.g., ground line 108). Other embodiments may include more or fewer memory cells 101. The summing node 107 is connected to a voltage sense amplifier to generate a signal representing a sum of products output of the resistive memory string 100. A current source 109 is connected to the resistive memory string 100 to provide a constant current during a sensing operation. In some embodiments, five word lines may be connected to the control terminal 104 of the memory cell 101 of each resistive memory string 100 in the memory array. In some embodiments, the voltage applied to the control terminal 104 (or word line) corresponds to the variable inputs n1, n2, n3, n4, and n5. In some embodiments, the transistor 105 may be interchangeably referred to as a word line transistor.

In some embodiments, the weight of the memory cell 101 is set as a function of the current in the resistive memory string 100, the critical voltage (Vt) of the transistor 105 in the memory cell 101, and the programmed resistance value of the resistor 106. The variable resistance value of each memory cell 101 in the resistive memory string 100 is a function of the current in the resistive memory string 100, the critical voltage (Vt) of the transistor 105 in the memory cell 101, the voltage on the word line applied to the gate of the memory cell 101, and the programmed resistance value of the resistor 106.

As shown in FIG. 1C , the resistive memory string 100 may include a series of source/drain regions 110-115 that serve as source/drain terminals for five transistors 105 in FIG. 1C . The gates of the five transistors 105 may be provided on word lines 120-124. Parallel resistors 106 are provided in each memory cell 101, bridging the transistors 105 using a current path. Contact structures 198, 199 may be connected to upper wires (not shown), which may be connected to other metal connection structures of the memory string, or to peripheral circuits that support the sum-of-products configuration. In some embodiments, contact structure 198 and contact structure 199 may be interchangeably referred to as electrical connection structures.

Specifically, the memory cell 101 may be constructed after the contact formation process, and then a subsequent metal path process may be performed to connect two memory cells 101 to each other. Each source/drain region (e.g., source/drain regions 111-114) in the resistive memory string 100 may be interconnected with two adjacent source/drain regions, excluding the source/drain regions (e.g., source/drain region 110 and source/drain region 115) at the terminal portion of the resistive memory string 100. Each conductor terminal has dual contact structures (e.g., two contact structures 170-175 and contact structures 160-164 (see FIG. 1D and FIG. 1E)) to facilitate these interconnections with adjacent source/drain regions. Metal paths (e.g., metal connection structures 130-134) can use one of the contact structures (from either contact structures 160-164 or contact structures 170-174) to connect to the memory cell 101 of the other contact structure on the adjacent conductor terminal, thereby constructing a resistive memory string 100.

With the memory cell 101 including a parallel resistor 106 bridging the transistor 105, and the source/drain regions 110-115 as source/drain terminals, the design can have a higher pattern density. This layout can allow for higher memory density, which means more data can be stored in a smaller area. This design provides a versatile method of interconnecting the memory cell 101. Each source/drain region (e.g., source/drain regions 111-114) is connected to two adjacent terminals, except for the terminal terminals (e.g., source/drain region 110 and source/drain region 115). This design flexibility can improve data flow and speed up read/write operations.

Specifically, in the first memory cell 101 formed on the source/drain region 110 and the source/drain region 111, the contact structure 160 (see FIG. 1D ) includes a programmable resistor 106, which can be formed to be electrically contacted with the source/drain region 110, a contact structure 170 can form an electrical contact with the source/drain region 111, and a metal connection structure 130 can be formed to extend laterally from above the programmable resistor 106 through the word line 120 to above the contact structure 170. That is, a pair of contact structures 160 and 170 are formed on the source/drain region 110 and the source/drain region 111 , wherein the programmable resistor 106 is located above the contact structure 160 and is not covered by the contact structure 170 .

In the second memory cell 101 formed on the source/drain region 111 and the source/drain region 112, the contact structure 161 (see Figure 1E) includes a programmable resistor 106, which can be formed to be electrically contacted with the source/drain region 111, a contact structure 171 can form an electrical contact with the source/drain region 112, and a metal connection structure 131 can be formed to extend laterally from above the programmable resistor 106 through the word line 121 to above the contact structure 171. In other words, a pair of contact structures 161 and 171 are formed on the source/drain regions 111 and 112 , wherein the programmable resistor 106 is located above the contact structure 161 and is not covered by the contact structure 171 .

In the third memory cell 101 formed on the source/drain region 112 and the source/drain region 113, the contact structure 162 (see FIG. 1D ) includes a programmable resistor 106, which can be formed to be electrically contacted with the source/drain region 112, a contact structure 172 can be formed to be electrically contacted with the source/drain region 113, and a metal connection structure 132 can be formed to extend laterally from above the programmable resistor 106 through the word line 122 to above the contact structure 172. In other words, a pair of contact structures 162 and 172 are formed on the source/drain region 112 and the source/drain region 113 , wherein the programmable resistor 106 is located above the contact structure 162 and is not covered by the contact structure 172 .

In the fourth memory cell 101 formed on the source/drain region 113 and the source/drain region 114, the contact 163 (see FIG. 1E ) includes a programmable resistor 106, which can be formed to be electrically contacted with the source/drain region 113, a contact 173 can be formed to be electrically contacted with the source/drain region 114, and a metal connection structure 133 can be formed to extend laterally from above the programmable resistor 106 through the word line 123 to above the contact 173. In other words, a pair of contact structures 163 and 173 are formed on the source/drain regions 113 and 114 , wherein the programmable resistor 106 is located above the contact structure 163 and is not covered by the contact structure 173 .

In the fifth memory cell 101 formed on the source/drain region 114 and the source/drain region 115, the contact 164 (see Figure 1D) includes a programmable resistor 106, which can be formed to be electrically contacted with the source/drain region 114, a contact structure 174 can be formed to be electrically contacted with the source/drain region 115, and a metal connection structure 134 can be formed to extend laterally from above the programmable resistor 106 through the word line 124 to above the contact structure 174. In other words, a pair of contact structures 164 and 174 are formed on the source/drain regions 114 and 115 , wherein the programmable resistor 106 is located above the contact structure 164 and is not covered by the contact 174 .

The metal connection structures 130-134 can be arranged in two columns r1 and r2. From the top view, each metal connection structure 130-134 is shifted relative to the next one of the metal connection structures 130-134 along the length direction of the word line 120-124, optimizing space utilization and ensuring a clear path for current. This setting can minimize interference and crosstalk between adjacent paths, ensuring clearer and more accurate data transmission. Specifically, the metal connection structure 131 and the metal connection structure 133 can be arranged in column r1, while the metal connection structures 130, 132 and 134 can be arranged in column r2, which is parallel to r1. Likewise, the programmable resistors 106 may be arranged in two columns r1 and r2, with each programmable resistor 106 being offset relative to the next programmable resistor 106 along the length of the word lines 120-124.

Thus, the resistive memory string 100 can provide a high density patterned, flexible and reliable memory storage layout with an architecture optimized for efficient data flow, manufacturing consistency and easy integration into a wider semiconductor system.

As shown in FIG. 1D and FIG. 1E , a diffusion region 181 may be formed above a substrate 180. The substrate 180 may be a semiconductor substrate, such as a single crystal silicon bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, etc., which may be doped (e.g., with p-type or n-type impurities) or undoped. The semiconductor insulator substrate may be a semiconductor material layer formed on an insulating layer. The insulating layer may be, for example, a buried oxide (BOX) layer, a silicon oxide layer, etc. The insulating layer is disposed on a substrate, typically a silicon or glass substrate. Other substrates, such as multi-layer or gradient substrates may also be used. In some embodiments, the substrate 180 may be a carrier wafer, such as a low-cost wafer or a recycled wafer. In some embodiments, the substrate 180 may include silicon; germanium; a compound semiconductor including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and/or indium antimonide; an alloy semiconductor including silicon germanium, gallium arsenide phosphide, indium arsenic aluminum, aluminum arsenic gallium, gallium arsenic indium, indium arsenic phosphide, and/or gallium arsenic indium phosphide; the like; or a combination thereof.

The word lines 120-124 are formed over the diffusion region 181. In some embodiments, the word lines 120-124 may be made of tungsten (W), cobalt (Co), ruthenium (Ru), molybdenum (Mo), aluminum (Al), copper (Cu), combinations thereof, or other suitable materials. In some embodiments, the word lines 120-124 may be interchangeably referred to as gates, polycrystalline gates, metal gates, gate structures, gate strips, gate lines, gate layers, or gate patterns.

Source/drain regions 110-115 are formed on opposite sides of word lines 120-124, which can be formed by implanting n-type dopants (N ⁺ ) (e.g., phosphorus or arsenic) or p-type dopants (P ⁺ ) in diffusion regions 181 (or open regions) of substrate 180, so that source/drain regions 110-115 can be N+ polysilicon layers or P+ polysilicon layers. In some embodiments, source/drain regions 110-115 can be interchangeably referred to as current conduction terminals, source/drain patterns, or doped semiconductor layers. Channel regions 182 are formed below word lines 120-124. Each transistor 105 may include a channel region 182, a corresponding one of word lines 120-124, and a corresponding pair of source/drain regions 110-115. Transistors 105 in two adjacent memory cells 101 share the same source/drain region 110-115, and the memory cells 101 are connected in series using the shared source/drain region 110-115.

The programmable resistor 106 is formed in the contact structures 160-164 and has a vertical distance from the metal connection structures 130-134. In some embodiments, the programmable resistor 106 may include a transition metal oxide layer, for example, which can be programmed with a variable resistance value using programming pulses and verify operations, such as for the implementation of a resistive RAM. By way of example but not limitation of the present disclosure, the programmable resistor may include a two-terminal element having first and second electrodes, with a metal oxide sandwiched therebetween, the metal oxide being programmable to a plurality of resistance values. In these embodiments, the metal oxide layer may include one or more metal oxides such as tungsten oxide, titanium oxide, nickel oxide, aluminum oxide, copper oxide, zirconium oxide, niobium oxide, tantalum oxide, titanium nickel oxide, chromium-doped SrZrO3, chromium-doped SrTiO3, PCMO and LaCaMnO. In some embodiments, the programmable resistor element between the electrodes may include WO/Cu, WO/Ag, TiO/Cu, TiO/Ag, NiO/Cu, NiO/Ag, AlO/Cu, AlO/Ag, CuO/Cu, CuO/Ag, ZrO/Cu, ZrO/Ag, NbO/Cu, NbO/Ag, TaO/Cu, TaO/Ag, TiNO/Cu, TiNO/Ag, Cr-doped SrZrO ₃ /Cu, Cr-doped SrZrO ₃ /Ag, Cr-doped SrTiO3/Cu, Cr-doped SrTiO3/Ag, PCMO/CU, PCMO/Ag, LaCaMnO/Cu, LaCaMnO/Ag, SiO ₂ /Cu, SiO ₂ /Ag, or any combination thereof.

In some embodiments, the programmable resistor 106 may include a phase change memory element. Embodiments of phase change materials include phase change based memory materials, including chalcogenide based materials and other materials. Chalcogenides include any four elements oxygen (O), sulfur (S), selenium (Se) and tellurium (Te), forming the VIA group of the periodic table. Chalcogenides include compounds of chalcogenides and a more positively charged element or group. Chalcogen alloys include combinations of chalcogenides with other materials such as transition metals. Chalcogen alloys typically include one or more elements from the IVA group of the periodic table, such as germanium (Ge) and tin (Sn). Chalcogen alloys often include a combination of one or more of antimony (Sb), gallium (Ga), indium (In) and silver (Ag). Many phase change based memory materials have been described in the technical literature, including: Ga/Sb, In/Sb, In/Se, Sb/Te, Ge/Te, Ge/Sb/Te, In/Sb/Te, Ga/Se/Te, Sn/Sb/Te, In/Sb/Ge, Ag/In/Sb/Te, Ge/Sn/Sb/Te, Ge/Sb/Se/Te and Te/Ge/Sb/S alloys. Within the Ge/Sb/Te alloy family, a wide range of alloy compositions is possible. These compositions can be referred to as TeaGebSb100-(a+b). In other embodiments, transition metals, such as chromium (Cr), iron (Fe), nickel (Ni), niobium (Nb), palladium (Pd), platinum (Pt), and mixtures or alloys thereof, may be combined with Ge/Sb/Te to form a phase change alloy having programmable resistance properties.

In some embodiments, chalcogenides and other phase change materials are doped with impurities to modify the conductivity, transition temperature, melting temperature, and other properties of storage devices using the doped chalcogenides. Representative impurities used to dope chalcogenides include nitrogen, silicon, oxygen, silicon dioxide, silicon nitride, copper, silver, gold, aluminum, aluminum oxide, tantalum, tantalum oxide, tantalum nitride, titanium, and titanium oxide.

In addition to the above-mentioned programmable resistor structures based on phase change cells and metal oxide cells, other programmable resistor structures also include solid state electrolyte memory cells, magnetoresistive memory cells, spin transfer torque materials and magnetic materials, and can be applied in the present disclosure.

In some embodiments, each of the contact structures 160-164 has two parts (or referred to as segments, such as a lower part and an upper part) sandwiching the programmable resistor 106. Specifically, the contact structure 160 (see FIG. 1D ) may have a lower part 160a and an upper part 160b, the lower part 160a being located between the source/drain region 110 and the programmable resistor 106, and the upper part 160b being located between the programmable resistor 106 and the metal connection structure 130. In some embodiments, the contact structures 160-164, 170-175, 198, and 199 may be made of tungsten (W), cobalt (Co), nimum (Ru), molybdenum (Mo), aluminum (Al), copper (Cu), combinations thereof, or other suitable materials. In some implementations, contact structures 160-164, 170-175, 198, and 199 may be interchangeably referred to as metal contact structure points, metal plugs, conductive contacts, metal vias, or interlayer connectors.

In some embodiments, the metal connection structures 130-134 may be made of tungsten (W), cobalt (Co), nimium (Ru), molybdenum (Mo), aluminum (Al), copper (Cu), combinations thereof, or other suitable materials. In some embodiments, the metal connection structures 130-134 may be interchangeably referred to as metal wires, metal line segments, metal strips, metal patterns, metal bridge elements, or metal paths. In some embodiments, the material of the metal connection structures 130-134 may be different from the material of the contact structures 160-164, 170-175, 198, and 199. In some embodiments, the material of the metal connection structures 130-134 may be the same as the material of the contact structures 160-164, 170-175, 198, and 199.

See FIG. 1F. FIG. 1F illustrates a top view of a semiconductor structure 20 operating in accordance with certain embodiments of the present disclosure, wherein the semiconductor structure 20 includes a resistive memory string 200 and a circuit 285 for the resistive memory string 200. In some embodiments, the resistive memory string 200 may be a NAND type resistive memory string. The description provided in FIG. 1F refers to another embodiment of the resistive memory string 200, specifically, different from the embodiment shown in FIGS. 1A to 1E. In this variation illustrated in FIG. 1F , the memory cell 201 , transistor 205 , source/drain regions 210 - 219 , contact structures 220 - 228 , 270 - 278 , 298 , 299 , metal connection structures 230 - 238 , and programmable resistor 206 are substantially similar in materials and manufacturing methods to those of FIGS. 1A - 1E . This means that memory cell 201 can correspond to memory cell 101, transistor 205 can correspond to transistor 105, source/drain regions 210-219 can correspond to source/drain regions 110-115, word lines 220-228 can correspond to word lines 120-124, contact structures 270-278, 298 and 299 can correspond to contact structures 170-174, metal connection structures 230-238 can correspond to metal connection structures 130-134, and programmable resistor 206 can correspond to programmable resistor 106 in the previous figure.

The difference in this embodiment lies in the arrangement of the memory cells 201 and the addition of a circuit 285 electrically connected to the resistive memory string 200. The resistive memory string 200 may include nine memory cells 201 connected together. The circuit 285 may include a cell select transistor 283 and a ground select line transistor 284. The source/drain region of the cell select transistor 283 is electrically connected to the source/drain regions 212, 214, 216, and 218 of the programmable resistor 206, and the source/drain region of the ground select line transistor 284 is electrically connected to the source/drain regions 211, 213, 215, and 217. The gate of the cell selection transistor 283 is electrically connected to the gate of the ground selection line transistor 284.

At least one memory cell 201 is selected in the resistive memory string 200 for an operation of reading, writing or erasing data in the selected memory cell 201. This selection can be accomplished using an operating voltage applied to a selected transistor (e.g., a cell select transistor 283, a ground select line transistor 284). The gate of the cell select transistor 283 and the gate of the ground select line transistor 284 are electrically connected. This means that when a particular voltage is applied to the gate of one of them, the other can respond accordingly. The operating voltage is applied to these gates to control the open (or 'on') and closed (or 'off') states of these transistors. Turning a transistor on (ie, making it conductive) or off (ie, making it non-conductive) can determine the path of current in the resistive memory string 200.

When reading a memory cell 201, the cell select transistor 283 and ground select line transistor 284 associated with the desired memory cell in the resistive memory string 200 are turned on (or 'on') by applying appropriate operating voltages thereto. The other cell select transistors 283 and ground select line transistors 284 associated with the unwanted memory cells 201 in the memory string 200 are turned off (or 'off'). This isolates the target memory cell 201, ensuring that current flows specifically through the memory cell 201. The impedance of the programmable resistor 206 in the memory cell 201 can then be measured. Based on the impedance, the state of the memory cell ('0' or '1') can be determined. To write data to the memory cell 201, a higher voltage (e.g., a write voltage or programming voltage) is applied. As previously described, only the cell select transistor 283 and the ground select line transistor 284 associated with the target memory cell 201 are turned on (or 'on'). This high voltage causes the impedance of the programmable resistor 206 in the memory cell 201 to change, thereby storing a '0' or '1'. To erase the data of the memory cell 201, a different voltage (e.g., an erase voltage) is applied. Just as in read and write operations, the cell select transistor 283 and ground select line transistor 284 associated with the target memory cell 201 are turned on (or 'on') during an erase operation. This erase voltage resets the impedance of the programmable resistor 106 in the memory cell 101 to its initial state.

Therefore, a specific operating voltage is applied to the gates of the cell select transistor 283 and the ground select line transistor 284 to accurately select and operate a single memory cell 201 in the resistive memory string 200. This technology ensures that data is accurately read, written, and erased in the desired memory cell 201 while preventing unintentional changes to neighboring memory cells 201.

See FIG. 1G. FIG. 1G illustrates a top view of a semiconductor structure 30 according to some embodiments of the present disclosure, wherein the semiconductor structure 30 includes a resistive memory string 300 and a circuit 385 for operating the resistive memory string 300. Although FIG. 1G illustrates an embodiment of a semiconductor structure 30 having a different structural configuration than the semiconductor structure 20 in FIG. 1F. In addition, the present disclosure may repeat reference numbers and/or letters in various examples. This repetition is for simplicity and clarity and does not limit the relationship between the various embodiments and/or configurations discussed.

As shown in FIG. 1G , the difference between the embodiment in FIG. 1G and the embodiment in FIG. 1F is that the resistive memory string 300 may include a plurality of resistive memory strings 200 connected in series with at least one auxiliary transistor 386. In some embodiments, the resistive memory string 200 shown in FIG. 1G may be interchangeably referred to as a sub-resistive memory string. Specifically, taking two series-connected resistive memory strings 200 as an example, the auxiliary transistor 386 can electrically connect the second end of the source/drain region 210-219 in the first resistive memory string 200 (i.e., the source/drain region 219) to the first end of the source/drain region 210-219 in the second resistive memory string 200 (i.e., the source/drain region 210).

In addition, the circuit 385 may include a string select transistor 383 and a ground select line transistor 384. The source/drain region of the string select transistor 383 may be electrically connected to the second end (i.e., source/drain region 219) of the source/drain regions 210-219 of the first and second resistive memory strings 200. The source/drain region of the ground select line transistor 384 may be electrically connected to the first end (i.e., source/drain region 210) of the source/drain regions 210-219 in the first and second resistive memory strings 200. The gate of the string select transistor 383 is electrically connected to the gate of the ground select line transistor 384.

At least one resistive memory string 200 (or sub-string) is selected in order to perform operations such as reading, writing or erasing data in the selected resistive memory string 200. This selection can be accomplished by applying an operating voltage to a selection transistor (e.g., a string selection transistor 383, a ground selection line transistor 384). The gates of the string selection transistor 383 and the ground selection line transistor 384 are electrically connected. This means that when a specific voltage is applied to one gate, the other can respond accordingly. The operating voltages applied to these gates are used to control the open (or 'on') and closed (or 'off') states of these resistive memory strings 200. By turning the RMM string 'on' (ie, making it conductive) or 'off' (ie, making it non-conductive), the path of current in the RMM string 300 can be determined.

When the desired resistive memory string 200 is selected, a read voltage may be further applied to the selected memory cell 201 in the resistive memory string 200. Depending on the impedance state (low impedance or high impedance) of the memory cell 201, the amount of current flowing through it may be determined. This current may then be used to determine whether the memory cell 201 is in a programmed or erased state. A write voltage (or programming voltage) higher than the read voltage may be applied to the memory cell 201 in the resistive memory string 200 to cause it to change its impedance state. Depending on the type of resistive memory, the impedance may increase or decrease, thereby programming the memory cell 201 in the selected resistive memory string 200. An erase voltage different from the write voltage may be applied to restore the memory cell 201 in the selected resistive memory string 200 to its initial state. In some embodiments, the operating voltage may be removed from the gates of the string select transistor 383 and the ground select line transistor 384. Turning off the string select transistor 383 and the ground select line transistor 384 ensures that the selected memory string 200 (or sub-string) is isolated to prevent any unintended operation thereon.

The presence of string select transistors 383 and ground select line transistors 384 can allow for accurate selection of individual resistive memory strings 200 (or substrings). This can ensure that only the required resistive memory strings 200 can be used for operation, minimizing interference and crosstalk with adjacent resistive memory strings 200. In some embodiments, turning off the string select transistors 383 and ground select line transistors 384 after operation can ensure that accidental read/write operations are minimized. This isolation can further ensure data integrity and reduce power leakage of the semiconductor structure 30.

Please refer to Figures 2A to 2F. Figure 2A shows a schematic circuit diagram of a resistive memory string 400 according to some embodiments of the present disclosure. In some embodiments, the resistive memory string 400 can be a NAND-type resistive memory string. Figures 2B and 2C show schematic equivalent circuit diagrams for operating the resistive memory string 400 in Figure 2A. Figure 2D shows a schematic top view of a semiconductor structure 40 including the resistive memory string 400 according to some embodiments of the present disclosure. Figures 2E and 2F show schematic cross-sectional views obtained from the reference cross-section E2-E2' and the reference cross-section F2-F2' in Figure 2D.

The description provided in the present disclosure may refer to another embodiment of a resistive memory string 400, specifically, a different configuration than the embodiment shown in Figures 1A to 1G. The resistive memory string 400 may include multiple sub-resistive memory strings 400a, and the sub-resistive memory strings 400a may include at least one transistor 405a and a pair of transistors 405b located at opposite ends of the sub-resistive memory strings 400a. As shown in Figure 2A, each sub-resistive memory string 400a may include two memory cells 401. Other embodiments may include more or fewer memory cells 401.

In some embodiments, the sub-resistance memory string 400a may be interchangeably referred to as a cell group. In this variation illustrated in FIG. 2A, the memory cell 401, transistors 405a, 405b, and programmable resistor 406 are substantially the same as in FIG. 1B in terms of materials and manufacturing methods. This means that the memory cell 401 may correspond to the memory cell 101, the transistors 405a and 405b may correspond to the transistor 105, and the programmable resistor 406 may correspond to the programmable resistor 106 in the previous figure.

The difference in this embodiment is the addition of a pair of transistors 405b. Multiple sub-resistance memory strings 400a can be connected in series using the shared source/drain region of their transistors 405b. In addition, the non-shared source/drain region of transistor 405b is electrically connected to another non-shared source/drain region of an adjacent terminal transistor 405b. In some embodiments, the voltage applied to the control terminal 404 (or word line) of the memory cell 401 corresponds to the variable inputs _x1 , _x2 , _x3 and _x4 . In some embodiments, transistor 405a can be interchangeably referred to as a word line transistor, and transistor 405b can be interchangeably referred to as a terminal transistor.

As shown in FIG. 2A , power line PLA and power line PLB are connected to the resistive memory string 400 and are connected from a pickup terminal between every two adjacent sub-resistive memory strings 400a, and this pickup terminal can be a shared source/drain region of two adjacent transistors 405b. The connection terminals of power line PLA and power line PLB are arranged alternately. A first operating voltage (e.g., a high voltage or programming voltage Vpgm) can be applied to power line PLA, and a second operating voltage (e.g., a low voltage or ground voltage GND) can be applied to power line PLB, and the second operating voltage is different from (or lower than) the first operating voltage.

In the process of determining which sub-resistance memory string 400a to turn on, transistors 405b located at opposite terminals in the sub-resistance memory string 400a are switched to an on state (or 'on'). This configuration allows one terminal of the selected sub-resistance memory string 400a to receive a first operating voltage provided by the power line PLA, while the opposite terminal receives a second operating voltage provided by the power line PLB. This configuration can establish a voltage difference between these terminals, causing current to flow from one end of the selected sub-resistance memory string 400a to the other end. Therefore, the turn-on configuration of this sub-resistance memory string 400a can be referred to as 'selected'. By switching the corresponding transistor 405a within the selected sub-resistance memory string 400a, an operation can be caused on the programmable resistor 406 within the selected memory cell 401, such as reading, writing or erasing data.

On the other hand, the transistors 405b at the opposite ends of each unselected sub-resistance memory string 400a adopt a hybrid configuration, one is in an open state (or 'on') and the other is in a closed state (or 'off'). This configuration can ensure that a consistent operating voltage is maintained between the two ends of the unselected sub-resistance memory string 400a, and the consistent operating voltage can be a first operating voltage provided by the power line PLA, or the consistent operating voltage can be a second operating voltage provided by the power line PLB. The state of no voltage difference between these ends can avoid current flow in these unselected sub-resistance memory strings 400a, thereby preventing programming interference.

As shown in FIG. 2B , in order to clearly explain the operation of the resistive memory string 400, particularly when selecting the sub-resistive memory string 400a, specific terminals within the resistive memory string 400 are labeled a, ia, SA, b, ib, and SB. Terminals a, ia, and SA are electrically connected to the power line PLA, and terminals b, ib, and SB are electrically connected to the power line PLB. Specifically, the selected sub-resistive memory string 400a is located between the terminals SA and SB. The unselected sub-resistive memory string 400a associated with the terminals a, ia, B, and ib is located outside the boundary marked by the terminals SA and SB. In detail, terminal a can connect the power line PLA to the resistive memory string 400, and its position is close to the terminal SA and away from the terminal SB. Terminal ia can also connect the power line PLA to the resistive memory string 400, and its position is close to the terminal SB and far away from the terminal SA. Terminal b can connect the power line PLB to the resistive memory string 400, and its position is close to the terminal SB and far away from the terminal SA. Terminal ib can connect the power line PLB to the resistive memory string 400, and its position is close to the terminal SA and far away from the terminal SB.

As shown in FIG. 2B , when both transistors 405 b in the sub-resistance memory string 400 a located between terminal SA and terminal SB are turned on (or set to an on state ('on')), terminal SA can receive a first operating voltage (e.g., a high voltage or programming voltage V _pgm ) from power line PLA. At the same time, terminal SB can receive a second operating voltage (e.g., a low voltage or ground voltage GND) from power line PLB. A voltage difference can thus be established between terminal SA and terminal SB, causing a current to flow from terminal SA of the selected sub-resistance memory string 400 a to terminal SB. This causes both the first and second operating voltages to be applied to the memory cell 401 located between terminal SA and terminal SB. In some implementations, the region between the terminal SA and the terminal SB may be referred to as a selected cell group region 441 .

Regulation of the current can allow for precise selection and operation of the memory cell 401 in the selected sub-resistance memory string 400a. This can be achieved by switching the state of the transistor 405a in the sub-resistance memory string 400a, thereby controlling the state of the programmable resistor 406 in the selected memory cell 401.

Specifically, in the selected cell group region 441, if the transistor 405a is turned off (set to an off state) by the corresponding word line, current can pass through the programmable resistor 406 connected in parallel with the turned-off transistor 405a. Such an operation can turn on the corresponding memory cell 401. This configuration can allow various tasks to be performed on the programmable resistor 406, such as reading, writing or erasing data.

On the contrary, in the selected cell group region 441, when the transistor 405a is turned on (set to an on state) by the corresponding word line, the current mainly flows through the transistor 405a and bypasses (or does not pass) the programmable resistor 406 connected in parallel with the turned-on transistor 405a. As a result, the programmable resistor 406 can remain in a non-turned on or non-operating state.

For the sub-resistance memory string 400a located between the terminals SA and ib, and between the terminal a and the terminal ib, when the transistor 405b on one side is turned on (or set to an on state) and the other side is turned off (or set to an off state), all voltages between the terminal a and the terminal SA will remain consistent with the first operation voltage (e.g., the programming voltage _Vpgm provided by the power line PLA). Therefore, no voltage difference (or gradient) is established to ensure that the current does not flow through these unselected sub-resistance memory strings 400a, thereby eliminating any possible operation interference. The region where the first operation voltage is maintained between the terminal a and the terminal SA can be referred to as a first operation voltage inhibition region 442.

Similarly, for the sub-resistance memory string 400a located between terminal SB and terminal ia, and between terminal b and terminal ia, when the transistor 405b on one side is turned on (or set to an on state) and the opposite side is turned off (or set to a closed state), all voltages between terminal SB and terminal b will remain consistent with the second operating voltage (e.g., the ground voltage GND provided by the power line PLB). Again, the state (or gradient) without a voltage difference can ensure that current does not flow through these unselected sub-resistance memory strings 400a, thereby eliminating any possible operational interference. This region where the second operating voltage is maintained between terminal b and terminal SB can be referred to as a second operation voltage inhibition region 443.

That is, the transistor 405b associated with the terminal a and the terminal b is turned on. This allows the suppression voltage (which may be the first or second operating voltage) to be transmitted to the unselected sub-resistance memory string 400a located between the terminal a and the terminal b, thereby preventing any possible operation interference in the first and second operating voltage suppression regions 442 and 443. In contrast, the transistor 405b associated with the terminal ia and the terminal ib is turned off. This ensures that the first and second operating voltages do not interfere with the unselected sub-resistance memory string 400a within the first and second operating voltage suppression regions 442 and 443.

In the first operating voltage suppression region 442, word lines 421 and 422 can be selected to turn on transistor 405a. This action ensures that the first operating voltage can be diverted away from the programmable resistor 406 connected in parallel to transistor 405a. Similarly, in the second operating voltage suppression region 443, word lines 421 and 422 can be selected to turn on transistor 405a. This action ensures that the second operating voltage can be diverted away from the programmable resistor 406 connected in parallel to transistor 405a.

As shown in FIG. 2D, the resistor memory string 400 may include a series of source/drain regions 410-414, which in FIG. 2D serve as source/drain terminals for a series of transistors 405a and 405b. The gates of transistors 405a and 405b may be disposed on word lines 420-423. A current path bridged to transistor 405a is used in each memory cell 401 to connect resistor 406 in parallel. Contact structures 498 and contact structures 499 may be connected to conductive structures (not shown) located on an upper layer, which may be connected to power lines PLA and PLB. In some embodiments, contact structures 498 and 499 may be referred to interchangeably as electrical connection structures.

Specifically, the resistor memory string 400 can be manufactured after the contact formation process, and a subsequent metal wiring process can be performed to connect two adjacent memory cells 401 to each other, and to connect two adjacent sub-resistance memory strings 400a to each other. Each source/drain region (e.g., source/drain regions 411-413) in the sub-resistance memory string 400a can be connected to two adjacent source/drain regions, but does not include the source/drain region at the terminal portion of the sub-resistance memory string 400a (e.g., the corresponding two in the source/drain region 410 and the source/drain region 414). Each conductive terminal has dual contact structures (e.g., contact structures 470-473 and contact structures 460-461 (see Figures 2E and 2F)) to facilitate connection to adjacent source/drain regions.

In some embodiments, metal wiring (e.g., metal connection structure 431 and metal connection structure 432) can use a first contact structure (contact structure 160 or contact structure 161 shown in Figures 2E and 2F) to connect the memory cell 401 to a second contact structure (contact structure 471 or contact structure 472) on an adjacent conductor terminal. In some embodiments, metal wiring (e.g., metal connection structure 430 and metal connection structure 433) may use a first contact structure (contact structure 470 or contact structure 473) to connect the first sub-resistance memory string 400a to a second contact structure (contact structure 473 or contact structure 470) on an adjacent second sub-resistance memory string 400a, thereby forming a resistance memory string 400.

Since the memory cell 401 includes a parallel resistor 406 bridged to the transistor 405a, and the source/drain regions 410-414 serve as source/drain terminals, this design can have a higher pattern density. This layout can allow for higher memory density, which means more data can be stored in a smaller area. This design provides a method for connecting the memory cell 401 and the sub-resistive memory string 400a. Each source/drain region (e.g., source/drain regions 411-413) is connected to two adjacent terminals, except for the terminal terminals (e.g., source/drain region 410 and source/drain region 414). This flexibility can improve data flow and speed up read/write operations.

Specifically, in the first memory cell 401 formed on the source/drain region 411 and the source/drain region 412, the contact structure 460 (see Figure 2F) includes a programmable resistor 406, which can be formed to electrically contact the source/drain region 411, a contact structure 471 can be formed to electrically contact the source/drain region 412, and a metal connection structure 431 can be formed to extend laterally from above the programmable resistor 406 through the word line 421 to above the contact structure 471. That is, a pair of contact structures 460 and contact structures 471 are formed on the source/drain region 411 and the source/drain region 412, wherein the programmable resistor 406 is located above the contact structure 460 and is not covered by the contact structure 471.

In the second memory cell 401 formed on the source/drain region 412 and the source/drain region 413, the contact structure 461 (see Figure 2E) includes a programmable resistor 406, which can be formed to electrically contact the source/drain region 412, a contact structure 472 can be formed to electrically contact the source/drain region 413, and a metal connection structure 432 can be formed to extend laterally from above the programmable resistor 406 through the word line 422 to above the contact structure 472. In other words, a pair of contact structures 461 and contact structures 472 are formed on source/drain regions 412 and source/drain regions 413, wherein the programmable resistor 406 is located above the contact structure 461 and is not covered by the contact structure 472.

A contact structure 470 may be formed on the source/drain region 411 of the first (first) sub-resistance memory string 400a, and a metal connection structure 430 may be formed to extend laterally from above the contact structure 470 through two word lines 420 in two different (first and second) sub-resistance memory strings 400a, to above a contact structure 473 formed on the source/drain region 411 of the second (second) sub-resistance memory string 400a. The contact structure 470 of the first sub-resistance memory string 400a and the contact structure 473 of the second sub-resistance memory string 400a may define a metal contact-free region below the metal connection structure 430.

Similarly, a contact structure 473 may be formed on the source/drain region 414 of the first (first) sub-resistance memory string 400a, and a metal connection structure 433 may be formed to extend laterally from above the contact structure 473 through two word lines 423 in two different (first and third) sub-resistance memory strings 400a, to above the contact structure 473 formed on the source/drain region 414 of the second (third) sub-resistance memory string 400a. The contact structure 473 in the first sub-resistance memory string 400a and the contact structure 470 in the third sub-resistance memory string 400a may define a metal contact structure-free region below the metal connection structure 433.

The metal connection structures 430-433 may be arranged in two columns r3 and r4, each metal connection structure 430-433 being offset relative to the next one of the plurality of metal connection structures 430-433 along the length direction of the word lines 420-423, which can optimize space utilization and ensure the path of the current from the top view. This setting can minimize interference and cross-talk between adjacent paths, ensuring more accurate data transmission. Specifically, the metal connection structures 430 and 432 may be arranged in the r4 row, and the metal connection structures 431 and 433 may be arranged in the r3 column, which is parallel to the r4 column. Similarly, the programmable resistors 406 can be arranged in two columns r3 and r4, with each programmable resistor 406 offset relative to the next programmable resistor 406 along the length of the word lines 420-423. Therefore, the resistive memory string 400 can provide a higher pattern density, flexibility and reliable layout for memory storage.

As shown in FIG. 2D and FIG. 2E, a diffusion region 481 may be formed on a substrate 480. Word lines 420-423 are formed on the diffusion region 481. Source/drain regions 410-414 are formed on both sides of the word lines 420-423. A channel region 482 is formed under the word lines 420-423. Each transistor 405a and 405b may include a channel region 482, a corresponding one of the word lines 420-423, and a corresponding one of the source/drain regions 410-414.

In two adjacent memory cells 401, transistors 405a share the same source/drain region 412, and the memory cells 401 are connected in series using the shared source/drain region 412. In two adjacent sub-resistance memory strings 400a, transistors 405b share the same source/drain region 410 or 414, and the sub-resistance memory strings 400a are connected in series using the shared source/drain region 410 or 414. The programmable resistor 406 can be formed to be configured in the contact structure 460 and the contact structure 461, and to have a vertical distance between the metal connection structure 431 and the metal connection structure 432. In some embodiments, the metal connection structures 430-433 may be made of a different material than the contact structures 460, 461, 470-473, 498, and 499. In some embodiments, the metal connection structures 430-433 may be made of the same material as the contact structures 460, 461, 470-473, 498, and 499.

In this variation shown in FIGS. 2A to 2F , the substrate 480, diffusion region 481, source/drain regions 410 - 114, word lines 420 - 423, contact structures 460 , 461 , 470 - 473 , 498 and 499 , and metal connection structures 430 - 433 are substantially similar in materials and manufacturing methods to those in FIGS. 1A to 1E . This means that substrate 480 can correspond to substrate 180, diffusion region 481 can correspond to diffusion region 181, source/drain regions 410-114 can correspond to source/drain regions 110-115, word lines 420-423 can correspond to word lines 120-124, contact structures 460, 461, 470-473, 498 and 499 can correspond to contact structures 160-164, 170-174, 198 and 199, and metal connection structures 430-433 can correspond to metal connection structures 130-134 in the picture.

Refer to FIG. 2C. In-storage computing, commonly referred to as computing-in-memory (CiM), can be integrated into the resistive memory string 400 to increase its functional capacity. The aforementioned computing-in-storage may include a series of steps. First, the power line PLA and the power line PLB are grounded. Next, all transistors 405b in the resistive memory string 400 are turned off to ensure data integrity. Then, the data input is directed to word line 421 and word line 422. Then, the resistance of the system is measured in the form of voltage or current to obtain the in-memory computing result. Therefore, the implementation of computation in storage of the resistive memory string 400 not only amplifies its computational capabilities, but also facilitates a seamless interface between data storage and processing functions.

Please refer to Figures 3A to 3E. Figure 3A shows a schematic circuit diagram of a resistive memory string 500 according to some embodiments of the present disclosure. Figure 3B shows a schematic top view of a semiconductor structure 50 including a resistive memory string 500 according to some embodiments of the present disclosure. Figure 3C shows a partial enlarged view of the area in Figure 3B. Figures 3D and 3E show schematic cross-sectional views obtained from reference section D3-D3' and reference section E3-E3' of Figure 3B.

In this variation illustrated in FIGS. 3A-3E , the resistive memory string 500, the sub-resistive memory string 500a, the substrate 580, the diffusion region 581, the transistors 505a and 505b, the word lines 520-523, the source/drain regions 510-514, the contact structures 560, 561, 570-573, 598, and 599, the metal connection structures 530-533, the programmable resistor 506, and the memory cell 501 are substantially similar in materials and manufacturing methods to those in FIGS. 2A to 2F . This means that the resistor string 500 may correspond to the resistor string 400, the sub-resistance string 500a may correspond to the sub-resistance string 400a, the substrate 580 may correspond to the substrate 480, the diffusion region 581 may correspond to the diffusion region 481, the transistors 505a and 505b may correspond to the transistors 405a and 405b, the word lines 520-523 may correspond to the word lines 420-423, the source/drain regions 510-51 4 may correspond to source/drain regions 410-414, contact structures 560-562, 570-572, 598, and 599 may correspond to contact structures 460, 461, 470-473, 498, and 499, metal connection structures 530-533 may correspond to metal connection structures 430-433, programmable resistor 506 may correspond to programmable resistor 406, and memory cell 501 may correspond to memory cell 401 in the previous figure.

The difference in this embodiment is that an additional programmable resistor 506 is formed in the contact structures 573 and 570 and has a vertical distance from the metal connection structures 530 and 533. That is, the programmable resistor 506 can be located at the junction where it crosses the two transistors 505b in the series-connected sub-resistance memory string 500a. These programmable resistors 506 not only serve as series components, but also as balanced weight memory cells 501. The resistance memory string 500 can ensure the flexibility of operation to provide programming, erasing or reading voltages through the power lines PLA and PLB.

As shown in FIG. 3C , in order to provide a clearer description of the operating method of the resistive memory string 500, new reference numbers are assigned to the structures shown in FIG. 3C . In the selected sub-resistive memory string 500a, the word lines are WL11, WL12, WL13, and WL14. In a group of sub-resistive memory strings 500a adjacent to the selected sub-resistive memory string 500a, the word lines are numbered WL03 and WL04. And in another adjacent sub-resistive memory string 500a, the word lines are numbered WL21 and WL22. The power line PLA can establish an electrical connection at a pickup terminal between the word line WL11 and the word line WL04. The power line PLB can establish an electrical connection between the connecting terminal of the word line WL14 and the word line WL21. The programmable resistor 506 connected in parallel with the word line WL04 and the word line WL11 can be numbered as the memory cell Cell0; the programmable resistor 506 connected in parallel with the word line WL12 can be numbered as the memory cell Cell1; the programmable resistor 506 connected in parallel with the word line WL13 can be numbered as the memory cell Cell2; the programmable resistor 506 connected in parallel with the word line WL14 and the word line WL21 can be numbered as the memory cell Cell3; the programmable resistor 506 connected in parallel with the word line WL22 can be numbered as the memory cell Cell4.

When the transistors associated with word line WL03, word line WL04, word line WL11, word line WL13, word line WL14, word line WL21, and word line WL22 are turned on (i.e., set to an on state) and the transistor associated with word line WL12 is turned off (i.e., set to an off state), current will flow through the programmable resistor 506 connected in parallel with the turned-off transistors, including word line WL12. Conversely, current will bypass the programmable resistor 506 connected in parallel with the turned-on transistors, including word line WL04, word line WL11, word line WL13, word line WL14, and word line WL21. Word line WL03 and word line WL22 will help provide the suppression voltage provided by power line PLA and power line PLB to the unselected memory cells, thereby reducing the operation interference in the resistive memory string 500. The memory cell Cell1 can be interchanged to be called the selected memory cell.

When the transistors associated with word line WL03, word line WL04, word line WL11, word line WL12, word line WL14, word line WL21, and word line WL22 are turned on (i.e., set to an on state) and the transistor associated with word line WL13 is turned off (i.e., set to an off state), current will flow through the programmable resistor 506 connected in parallel with the turned-off transistors, including word line WL13. Conversely, current will flow through the programmable resistor 506 connected in parallel with the turned-on transistors, including word line WL04, word line WL11, word line WL12, word line WL14, and word line WL21. Word line WL03 and word line WL22 will help provide the suppression voltage provided by power line PLA and power line PLB to the unselected memory cells, thereby reducing the operation interference in the resistive memory string 500. The memory cell Cell2 can be interchangeably referred to as the selected memory cell.

When the transistors associated with word line WL03, word line WL04, word line WL11, word line WL12, word line WL13, word line WL21, and word line WL22 are turned on (i.e., set to an on state) and the transistor associated with word line WL14 is turned off (i.e., set to an off state), current will flow through the programmable resistor 506 connected in parallel with the turned-off transistors, including word line WL14. Conversely, current will flow through the programmable resistor 506 connected in parallel with the turned-on transistors, including word line WL04, word line WL11, word line WL12, word line WL13, and word line WL21. Word lines WL03 and WL22 will help provide the suppression voltage provided by power line PLA and power line PLB to the unselected memory cells, thereby reducing the operation interference in the resistive memory string 500. The memory cell Cell3 can be interchanged to be called the selected memory cell.

The resistive memory strings described in this disclosure are versatile and can be used in a variety of applications, including sum-of-product computations, neural network processing, in-memory search or in-memory computing, and in-storage search or in-storage computing.

Although the present invention has been described in detail with reference to some embodiments, other embodiments are possible. Therefore, the spirit and scope of the appended claims should not be limited to the embodiments described herein. The present disclosure provides a layout in various embodiments to improve long NAND-type resistive memory strings, so that the series (or loading) impedance associated with selected memory cells can be reduced. The present disclosure introduces an additional electrical connection structure (pickup connection) to the long NAND-type resistive memory string. The additional electrical connection structure can divide the long impedance string (R-string) into shorter ones. In addition, a suppression scheme can be applied to unselected memory cells on the resistive memory string to ensure that the unselected memory cells remain undisturbed during operation.

The foregoing content summarizes the features of several implementations so that those skilled in the art can better understand the state of the present disclosure. Those skilled in the art should understand that they can easily use the present disclosure as a basis for designing or modifying other processes and structures for implementing the same purpose and/or achieving the same advantages of the implementations introduced herein. Those skilled in the art should also recognize that such equivalent structures do not deviate from the spirit and scope of the present disclosure, and such equivalent structures can be variously changed, replaced, and substituted herein without departing from the spirit and scope of the present disclosure.

20, 30, 40, 50: semiconductor structure

100, 200, 300, 400, 500: Resistive memory string

400a, 500a: sub-resistance memory string

101, 201, 401, 501, Cell1, Cell2, Cell3: memory cells

102: Power on node

103: Powered Node

104: Control terminal

105, 205, 405a, 405b, 505a, 505b: transistors

106, 206, 406, 506: Programmable resistors

107: Sum nodes

108: Ground wire

109: Current source

110-115, 210-219, 410-414, 510-514: Source/drain regions

120-124, 220-228, 420-423, 520-523, WL03, WL04, WL11, WL12, WL13, WL14, WL21, WL22: word line

130-134, 230-238, 430-433, 530-533: Metal connection structure

160-164, 170-175, 198, 199, 270-278, 298, 299, 460-461, 470-473, 498, 499, 560, 561, 570-573, 598, 599: Contact structure

160a: Lower part

160b: Upper part

180, 480, 580: base material

181, 481, 581: diffusion area

283, 383: Select transistors

284, 384: Ground selection line transistor

285, 385: Circuit

386: Auxiliary transistor

441: Selected unit group area

442: First operating voltage suppression region

443: Second operating voltage suppression region

a, b, ia, ib, SA, SB: terminals

D1-D1’, E1-E1’, E2-E2’, F2-F2’, D3-D3’, E3-E3’: Section

GND: Ground voltage

n1, n2, n3, n4, n5, _x1 , _x2 , _x3 and _x4 : input

PLA, PLB: Power cord

r1, r2, r3, r4: columns

V _D , V _G , _VS : voltage

V _pgm : Programming voltage

The aspects of the present disclosure are best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that various features are not drawn to scale in accordance with standard practices in the industry. In fact, the sizes of various features may be arbitrarily increased or decreased for clarity of discussion. FIG. 1A is a schematic diagram of a memory cell according to some embodiments of the present disclosure. FIG. 1B illustrates a schematic circuit diagram of a resistive memory string including a plurality of memory cells according to some embodiments of the present disclosure. FIG. 1C illustrates a schematic top view of a semiconductor structure including a resistive memory string according to some embodiments of the present disclosure. FIG. 1D and FIG. 1E illustrate schematic cross-sectional views obtained from reference cross-section D1-D1' and reference cross-section E1-E1' of FIG. 1C. FIG. 1F and FIG. 1G illustrate schematic top views of a semiconductor structure including a circuit for operating a resistive memory string according to some embodiments of the present disclosure. FIG. 2A illustrates a schematic circuit diagram of a resistive memory string according to some embodiments of the present disclosure. FIG. 2B and FIG. 2C illustrate schematic equivalent circuit diagrams of a method for operating the resistive memory string in FIG. 2A. FIG. 2D illustrates a schematic top view of a semiconductor structure including a resistive memory string according to some embodiments of the present disclosure. Figures 2E and 2F show schematic cross-sectional views obtained from reference cross-section E2-E2' and reference cross-section F2-F2' of Figure 2D. Figure 3A shows a schematic circuit diagram of a resistive memory string according to some embodiments of the present disclosure. Figure 3B shows a schematic top view of a semiconductor structure including a resistive memory string according to some embodiments of the present disclosure. Figure 3C shows a partial enlarged view of Figure 3B. Figures 3D and 3E show schematic cross-sectional views obtained from reference cross-section D3-D3' and reference cross-section E3-E3' of Figure 3B.

40:Semiconductor structure

400: Resistive memory string

400a: Sub-resistance memory string

401: Memory unit

405a, 405b: transistors

406: Programmable resistor

410-414: Source/drain region

420-423: Word line

430-433: Metal connection structure

470-473, 498, 499: Contact structure

PLA, PLB: Power cord

r3, r4: columns

Claims (19)

An integrated circuit structure includes: a substrate; and a first resistive memory string located above the substrate and including a plurality of memory cells, each of the memory cells including: a word line transistor including a channel region, a gate located above the channel region, and a plurality of source/drain regions located at opposite sides of the channel region; a resistor located above the word line transistor and connected in parallel with the word line transistor, wherein the memory cells Two adjacent word line transistors of the cell share the same source/drain region, and the memory cells are connected in series using the shared source/drain regions; and a metal line extending laterally and crossing the gate, wherein the metal lines of the memory cells are arranged in two rows as viewed from a direction perpendicular to a top surface of the substrate, and each of the metal lines is offset relative to the next metal line of the metal lines along a plurality of length directions of the gates. An integrated circuit structure as described in claim 1, wherein each of the memory cells further comprises: a pair of contact structures located above the source/drain regions, wherein the resistor is located above a first one of the pair of contact structures and is not covered by a second one of the pair of contact structures. An integrated circuit structure as described in claim 2, wherein the metal line of each of the memory cells extends laterally from above the resistor to above the second of the pair of contact structures, wherein the resistor is connected in series with the word line transistor using the pair of contact structures and the metal line. The integrated circuit structure as described in claim 1 further includes: a string selection transistor having a source/drain region, wherein the source/drain region of the string selection transistor is electrically coupled to a first terminal of the source/drain regions of the first resistive memory string; and a ground selection line transistor having a source/drain region, wherein the source/drain region of the ground selection line transistor is electrically coupled to a second terminal of the source/drain regions of the first resistive memory string, and a gate of the string selection transistor is electrically coupled to a gate of the ground selection line transistor. The integrated circuit structure as described in claim 4 further includes: a second resistive memory string located above the substrate; and an auxiliary transistor located above the substrate and electrically coupling a first terminal of the plurality of source/drain regions of the second resistive memory string to the second terminal of the source/drain regions of the first resistive memory string. An integrated circuit structure includes: a substrate having a diffusion region; and a resistive memory string including: a first substring including a first gate and a second gate extending above the diffusion region and a first metal contact structure located between the first gate and the second gate and located above the diffusion region; a second substring including a third gate and a fourth gate extending above the diffusion region and a first metal contact structure located between the third gate and the fourth gate. A second metal contact structure between the gates and located above the diffusion region; a first metal line extending laterally from above the first metal contact structure of the first substring, across the second gate and the third gate, to above the second metal contact structure of the second substring; and a third metal contact structure located between the second gate and the third gate and located above the diffusion region, the third metal contact structure being configured to apply an operating voltage. An integrated circuit structure as described in claim 6, wherein a metal contact structure-free region is defined between the first metal contact structure and the second metal contact structure, and the metal contact structure-free region is located below the first metal line. The integrated circuit structure as described in claim 6, wherein the second substring further includes: A fourth metal contact structure and a fifth metal contact structure, located above the diffusion region and on opposite sides of the fourth gate; a first resistor, located above the fourth metal contact structure; and a second metal line, extending laterally from above the first resistor, across the fourth gate, to above the fifth metal contact structure. An integrated circuit structure as described in claim 8, wherein the first metal contact structure and the second metal contact structure are arranged in a first row, and the third metal contact structure, the fourth metal contact structure and the fifth metal contact structure are arranged in a second row. An integrated circuit structure as described in claim 8, wherein the first substring further includes: a sixth metal contact structure and a seventh metal contact structure, located above the diffusion region and on opposite sides of the first gate; a second resistor, located above the sixth metal contact structure; and a third metal line, extending laterally from above the second resistor, across the first gate, to above the seventh metal contact structure. An integrated circuit structure as described in claim 10, wherein the first metal contact structure and the second metal contact structure are arranged in a first row, and the third metal contact structure, the fourth metal contact structure, the fifth metal contact structure, the sixth metal contact structure and the seventh metal contact structure are arranged in a second row. The integrated circuit structure as described in claim 6 further includes: a resistor vertically disposed between the first metal contact structure and the first metal line. An operating method of an integrated circuit structure, the integrated circuit structure includes a resistive memory string located above a substrate, the resistive memory string having a plurality of sub-strings connected in series, each of the sub-strings including a plurality of word line transistors connected in series and a pair of terminal transistors, thereby forming a connection terminal between two adjacent terminal transistors of the sub-strings , each of the sub-strings further includes a plurality of resistors, each of the resistors is connected in parallel to a corresponding one of the word line transistors, and the method includes: alternately applying a first operating voltage and a second operating voltage to the connection terminals of the resistive memory string; performing a programming operation on the resistive memory string; and performing an erasing operation on the resistive memory string. The method as described in claim 13, wherein the first operating voltage is a programming voltage and the second operating voltage is a ground voltage. The method as described in claim 13, wherein the step of performing the programming operation or performing the erasing operation includes: turning on the pair of terminal transistors of one of the substrings, the one of the substrings being a selected cell group, wherein the turning on step causes a voltage difference to be formed between the pair of terminal transistors of the substrings, thereby causing a current to flow through the one of the substrings. The method as described in claim 15 further includes: turning off one of the word line transistors of one of the sub-strings, allowing the current to flow through the resistor in parallel with the turned-off word line transistor. The method as described in claim 15 further includes: turning on one of the word line transistors of one of the sub-strings, allowing the current to flow through the turned-on one of the word line transistors but bypassing the resistor connected in parallel with the turned-on one of the word line transistors. The method as described in claim 13, wherein the step of performing the programming operation or performing the erasing operation includes: turning on a first of the pair of terminal transistors of one of the substrings; and turning off a second of the pair of terminal transistors of the one of the substrings, the one of the substrings serving as an operation voltage inhibition region, wherein the turning on step and the turning off step maintain a consistent voltage between the pair of terminal transistors of the one of the substrings to eliminate an operation interference of the one of the substrings. The method as described in claim 18 further includes: turning on the word line transistors of the sub-strings.

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