TWI862182B - An integrated circuit having fewer power pins - Google Patents

Abstract

Disclosed is an integrated circuit having fewer power pins, which comprises a package casing, a power pin terminal, a die, a conductive path and two or more first small bonding pads. The power pin terminal penetrates through the package casing, the die is disposed in the package casing, and the conductive path and the first small bonding pads are respectively disposed on the die. A connection area is configured between the conductive path and the die. The first small bonding pads are respectively disposed in the connection area and are adjacently connected. One of the first small bonding pads is connected to the conductive path, and one of the first small bonding pads is connected to the power pin terminal through a wire. In this way, the number of power pins can be reduced, so that the expandable functionality of the I/O pins in the integrated circuit can be increased.

Description

Integrated circuits that reduce power pins

The present invention relates to an integrated circuit, and more particularly to an integrated circuit capable of reducing power pins.

In the prior art, a known integrated circuit (IC) packaging method is composed of a packaging shell, a die and a plurality of pin terminals. The die is packaged in the packaging shell, and the pin terminals are penetrated on the packaging shell. In addition to preventing moisture from penetrating into the die and reducing damage to the die caused by external force impact, the packaging shell includes a plurality of power pin terminals. An external power circuit can provide the power required by the die through the power pin terminals and the integrated circuit.

However, the package shell of the traditional integrated circuit must be equipped with a considerable number of power pin terminals to provide the chip with stable power, which results in the number of pins originally used for data input/output (I/O) in the traditional integrated circuit being occupied by the majority of power pin terminals. Therefore, how to solve the above-mentioned problems of the prior art is indeed necessary to propose a better solution.

In view of the above-mentioned shortcomings of the prior art, the main purpose of the present invention is to provide an integrated circuit that can reduce power pins, which improves the integrated circuit architecture and solves the problem that most power pin terminals occupy I/O pins in the prior art.

To achieve the above-mentioned purpose, the main technical means adopted by the present invention is to make the above-mentioned integrated circuit capable of reducing power pins include a packaging shell, a power pin terminal, a die, a conductive path and more than two first small solder pads, the power pin terminal is arranged on the packaging shell, the die is arranged inside the packaging shell, the conductive path is arranged on the die, and there is a first connection area between the conductive path and the outer edge of the die, and the first small solder pads are arranged in the first connection area and connected adjacently; wherein, any one of the first small solder pads is connected to the conductive path, and any one of the first small solder pads is connected to the power pin terminal through a wire.

The present invention arranges the first small solder pads in the first connection area adjacently and connected to the conductive path, and the power pin terminal is connected to any one of the first small solder pads through the wire, so that the number of power pins can be reduced, thereby increasing the expandable functionality of the I/O pins in the integrated circuit.

To achieve the above-mentioned purpose, another main technical means adopted by the present invention is to make the above-mentioned integrated circuit capable of reducing power pins include a package shell, a power pin terminal, a die, a ring-shaped conductive path, two or more first elongated solder pads and a large solder pad, the power pin terminal is arranged on the package shell, the die is arranged inside the package shell, the conductive path is arranged on the die, and a conductive path is arranged between the conductive path and the outer edge of the die. A first connection area is formed between the conductive path and a second connection area is formed by the inside of the conductive path, and the first elongated pads are arranged at relative positions of the first connection area; wherein the first elongated pads are connected to the conductive path, and any one of the first elongated pads is connected to the power supply terminal through a wire; the large pad is arranged in the second connection area, and the large pad is connected to the first elongated pads through two or more wires.

The present invention arranges the first elongated pads in the first connection area and the large pad in the second connection area, and the power pin terminal is connected to any one of the first elongated pads through the wire, so that the number of power pins can be reduced, thereby increasing the expandable functionality of the I/O pins in the integrated circuit.

The first embodiment of the present invention provides an integrated circuit capable of reducing power pins. Referring to FIG. 1 , the integrated circuit comprises a package shell 10, a power pin terminal 20, a die 30, a conductive path 40, and two or more first small solder pads 50. The power pin terminal 20 can be inserted into the package shell 10, the die 30 is disposed inside the package shell 10, the conductive path 40 is disposed on the die 30, and There is a first connection area A1 between the conductive path 40 and the outer edge of the die 30, and the first small solder pads 50 are respectively arranged in the first connection area A1, and the first small solder pads 50 are located adjacent to each other and form an electrical connection; wherein, any one of the first small solder pads 50 is electrically connected to the conductive path 40, and any one of the first small solder pads 50 is electrically connected to the power pin terminal 20 through a wire W1.

The present invention reduces the number of power pins and increases the expandable functionality of I/O pins in the integrated circuit by connecting the first small solder pads 50 disposed in the first connection area A1 adjacent to each other and connected to the conductive path 40, and the power pin terminal 20 is connected to any one of the first small solder pads 50 through the wire W1.

In this embodiment, as shown in FIG. 1 , there is further a second connection area A2 between the conductive path 40 and the outer edge of the die 30, and the second connection area A2 does not overlap with the first connection area A1. The conductive path 40 is disposed in a ring shape on the die 30, and the conductive path 40 can be in a square shape. Further, the first connection area A1 is formed from the outer side of the conductive path 40 to the outer edge of the die 30, and the second connection area A2 can be formed by the inner part of the conductive path 40 in a ring shape. In this embodiment, the first small pads 50 are electrically connected through a conductive layer 60, and any of the first small pads 50 is electrically connected to the conductive path 40 through another conductive layer 60. In addition, one end of the wire W1 is welded to the surface of any of the first small pads 50, and the other end of the first wire W1 is welded to the power pin terminal 20, so that any of the first small pads 50 is electrically connected to the power pin terminal 20.

Please refer to Figure 2. In this embodiment, more than two second small solder pads 51 are further included. The second small solder pads 51 are respectively arranged in the first connection area A1 or the second connection area A2, and are located adjacent to each other and form an electrical connection. The first small solder pads 50 are located on a top side of the conductive path 40, and the second small solder pads 51 are located on an adjacent side of the top side of the conductive path 40; wherein any one of the second small solder pads 51 is electrically connected to the conductive path 40, and any one of the second small solder pads 51 is electrically connected to any one of the first small solder pads 50 through another wire W2.

To provide other application methods, please refer to FIG. 3. In this embodiment, more than two third small solder pads 52 and more than two fourth small solder pads 53 are further included. The third small solder pads 52 are respectively arranged in the first connection area A1 or the second connection area A2, and the third small solder pads 52 are located adjacent to each other and form an electrical connection. The fourth small solder pads 53 are respectively arranged in the first connection area A1 or the second connection area A2. The second connection area A2, and the fourth small solder pads 53 are located adjacent to each other and form an electrical connection; the third small solder pads 52 are located on another adjacent side of the top side of the conductive path 40, and the fourth small solder pads 53 are located opposite to the first small solder pads 50. In the present embodiment, the fourth small solder pads 53 are located on a bottom side of the conductive path 40, and the bottom side is opposite to the top side.

Among them, any one of the third small welding pads 52 is electrically connected to the conductive path 40, any one of the fourth small welding pads 53 is electrically connected to the conductive path 40, any one of the third small welding pads 52 is electrically connected to any one of the first small welding pads 50 through another wire W3, any one of the fourth small welding pads 53 is electrically connected to any one of the second small welding pads 51 through another wire W4, and any one of the fourth small welding pads 53 is electrically connected to any one of the third small welding pads 52 through another wire W5. It must be specially pointed out that all the small solder pads 50, 51, 52, 53 in the present invention can be respectively arranged not only in the first connection area A1, but also in the second connection area A2. In this embodiment, it is only an example and does not limit the spatial arrangement of all the small solder pads 50, 51, 52, 53.

Furthermore, in this embodiment, the areas of the first small solder pads 50 , the second small solder pads 51 , the third small solder pads 52 and the fourth small solder pads 53 are between 900 and 7225 square micrometers (μm ² ) to provide a more suitable soldering space and space utilization.

Regarding the second embodiment of the present invention, please refer to Figures 2 and 4. The main technical content is roughly the same as the first embodiment, as shown in Figure 4, but the main difference is that this embodiment further includes a first long solder pad 70, and the first long solder pad 70 is arranged in the second connection area A2; wherein, the first long solder pad 70 is electrically connected to any one of the second small solder pads 51 through another wire W6, and the first long solder pad 70 is electrically connected to any one of the first small solder pads 50 through another wire W7.

Please refer to Figure 5. Another difference between the present embodiment and the first embodiment is that the present embodiment further includes a second elongated solder pad 71, a third elongated solder pad 72 and a fourth elongated solder pad 73. The second elongated solder pad 71, the third elongated solder pad 72 and the fourth elongated solder pad 73 are respectively arranged in the second connection area A2. In the present embodiment, the first to fourth elongated solder pads 70, 71, 72, 73 may be unconnected, connected, non-overlapping or overlapping with each other. The second long pad 71 is electrically connected to any one of the second small pads 51 through another wire W8, and the second long pad 71 is electrically connected to any one of the fourth small pads 53 through another wire W9; the third long pad 72 is electrically connected to any one of the fourth small pads 53 through another wire W10, and the third long pad 72 is electrically connected to any one of the third small pads 52 through another wire W11; the fourth long pad 73 is electrically connected to any one of the third small pads 52 through another wire W12, and the fourth long pad 73 is electrically connected to any one of the first small pads 50 through another wire W13.

In addition, in the present embodiment, the areas of the first elongated bonding pad 70, the second elongated bonding pad 71, the third elongated bonding pad 72 and the fourth elongated bonding pad 73 are between 2800 and 14800 μm ² to provide a more extensible bonding space and space utilization.

Regarding the third embodiment of the present invention, please refer to Figure 6. Its main technical content is roughly the same as the above-mentioned embodiments, such as Figures 4 and 6, but the main difference is that this embodiment provides more than two fifth small welding pads 54 to replace the long welding pads in the second embodiment; in this embodiment, the fifth small welding pads 54 are respectively arranged in the second connection area A2, and the fifth small welding pads 54 are located adjacent to each other and form an electrical connection; wherein any one of the fifth small welding pads 54 is electrically connected to any one of the second small welding pads 51 through another wire W14, and any one of the fifth small welding pads 54 is electrically connected to any one of the first small welding pads 50 through another wire W15.

In addition, in this embodiment, the area of the fifth small bonding pads 54 is between 900 and 7225 μm ² to provide more flexible bonding space configuration and space utilization.

Regarding the fourth embodiment of the present invention, another integrated circuit that can reduce power pins is provided, please refer to Figure 7, which includes a packaging shell 100, a power pin terminal 200, a chip 300, an annular conductive path 400, two or more first long solder pads 500 and a large solder pad 600. However, the difference between this embodiment and the aforementioned embodiments is that this embodiment further provides the first long solder pads 500 and the large solder pad 600. The first long solder pads 500 can replace the solder pads in the first connection area A1 or the second connection area A2 in the aforementioned embodiments, and the large solder pad 600 can also replace the solder pads in the first connection area A1 or the second connection area A2 in the aforementioned embodiments.

In this embodiment, as shown in FIG. 7 , the power pin terminal 200 can also be passed through the package shell 100, the die 300 is disposed inside the package shell 100, the conductive path 400 is disposed in a ring shape on the die 300, and is also in a U-shape, and a first connection area A10 is formed between the conductive path 400 and the outer edge of the die 300, and a second connection area A20 is formed by the inner part of the U-shape of the conductive path 400 in a ring shape, and the first elongated solder pads 500 are respectively disposed at relative positions of the first connection area A10.

In this embodiment, as shown in FIG. 7 , the relative position of the first connection area A10 refers to non-adjacent sides, and the first elongated pads 500 can be disposed at the top and bottom of the first connection area A10; or in this embodiment, the first elongated pads 500 can also be disposed at two adjacent sides of the first connection area A10, which is only an example and not a limitation. Among them, the first elongated pads 500 are electrically connected to the conductive path 400, and any of the first elongated pads 500 is electrically connected to the power pin terminal 200 through a wire WR1; through the first elongated pads 500, a more extensible welding space and space utilization can be provided for the first connection area A10.

In this embodiment, the large welding pad 600 can be set at any position in the second connection area A20. In this embodiment, it can be located in the center. The large welding pad 600 is electrically connected to the first long welding pads 500 through two or more other wires WR2. The large welding pad 600 can reduce the welding space in the second connection area A20 and improve space utilization.

The present invention reduces the number of power pins by setting the first elongated pads 500 in the first connection area A10 and the large pad 600 in the second connection area A20, and the power pin terminal 200 is connected to any one of the first elongated pads 500 through the wire WR1, thereby increasing the expandable functionality of the I/O pins in the integrated circuit.

In this embodiment, in order to improve its application, please refer to FIG. 8, which further includes more than two second elongated solder pads 510, and the second elongated solder pads 510 can also replace the solder pads in the first connection area A1 or the second connection area A2 in the above-mentioned embodiments; in this embodiment, the second elongated solder pads 510 are respectively arranged at another relative position of the first connection area A10, and are connected to the second elongated solder pads 510. The first elongated pads 500 are disposed at different positions, and the second elongated pads 510 can be disposed at two adjacent sides of the conductive path 400, or at the top and bottom sides of the first connection area A10; wherein the second elongated pads 510 are electrically connected to the conductive path 400, and the large pad 600 is electrically connected to the second elongated pads 510 through two or more wires WR3.

In addition, in this embodiment, the areas of the first elongated pads 500 and the second elongated pads 510 are between 2800 and 14800 μm ² , and the area of the large pad 600 is between 2800 and 34225 μm ² , so as to provide a more extensible and flexible welding space and improve space utilization.

10: Encapsulation shell

20: Power pin terminal

30: Grain

40: Conductive path

50: First small pad

51: Second small welding pad

52: Third small welding pad

53: Fourth small welding pad

54: Fifth small welding pad

60: Conductive layer

70: First long pad

71: Second long welding pad

72: The third long pad

73: Fourth long welding pad

100: Encapsulation shell

200: Power pin terminal

300: Grain

400: Conductive path

500: First long pad

510: Second long pad

600:Large welding pad

A1: First connection area

A2: Second connection area

A10: First connection area

A20: Second connection area

W1: Conductor

W2: Conductor

W3: Conductor

W4: Conductor

W5: Conductor

W6: Conductor

W7: Conductor

W8: Conductor

W9: Conductor

W10: Conductor

W11: Conductor

W12: Conductor

W13: Conductor

W14: Conductor

W15: Conductor

WR1: Conductor

WR2: Conductor

WR3: Conductor

FIG. 1 is a schematic diagram of an integrated circuit with reduced power pins of the first embodiment of the present invention. FIG. 2 is another schematic diagram of an integrated circuit with reduced power pins of the first embodiment of the present invention. FIG. 3 is another schematic diagram of an integrated circuit with reduced power pins of the first embodiment of the present invention. FIG. 4 is a schematic diagram of an integrated circuit with reduced power pins of the second embodiment of the present invention. FIG. 5 is another schematic diagram of an integrated circuit with reduced power pins of the second embodiment of the present invention. FIG. 6 is a schematic diagram of an integrated circuit with reduced power pins of the third embodiment of the present invention. FIG. 7 is a schematic diagram of an integrated circuit capable of reducing power pins according to the fourth embodiment of the present invention. FIG. 8 is a schematic diagram of another integrated circuit capable of reducing power pins according to the fourth embodiment of the present invention.

10: Encapsulation shell

20: Power pin terminal

30: Grain

40: Conductive path

50: First small welding pad

60: Conductive layer

A1: First connection area

A2: Second connection area

W1: Conductor

Claims (10)

An integrated circuit capable of reducing power pins includes: a package shell; a power pin terminal disposed on the package shell; a die disposed inside the package shell; a conductive path disposed on the die and having a first connection area between the conductive path and the outer edge of the die; and two or more first small solder pads disposed in the first connection area and connected adjacently; wherein any one of the first small solder pads is connected to the conductive path, and any one of the first small solder pads is connected to the power pin terminal through a wire. An integrated circuit capable of reducing power pins as described in claim 1, wherein there is a second connection area between the conductive path and the outer edge of the die, and the first small solder pads can be arranged in the second connection area. An integrated circuit capable of reducing power pins as described in claim 2, wherein the conductive path is arranged in a ring shape on the die, and the second connection area is formed by the inner part of the conductive path in a ring shape. An integrated circuit capable of reducing power pins as described in claim 2 or 3, further comprising two or more second small solder pads, the second small solder pads being disposed in the first connection area or the second connection area and connected adjacently; wherein any one of the second small solder pads is connected to the conductive path, and any one of the second small solder pads is connected to any one of the first small solder pads via another wire. The integrated circuit capable of reducing power pins as described in claim 4, further comprising two or more third small solder pads and two or more fourth small solder pads, wherein the third small solder pads are disposed in the first connection area or the second connection area and are adjacently connected; the fourth small solder pads are disposed in the first connection area or the second connection area and are adjacently connected; wherein any one of the third small solder pads is adjacent to the The conductive path is connected to any one of the fourth small pads, any one of the third small pads is connected to any one of the first small pads through another conductive path, any one of the fourth small pads is connected to any one of the second small pads through another conductive path, and any one of the fourth small pads is connected to any one of the third small pads through another conductive path. An integrated circuit capable of reducing power pins as described in claim 2 or 3, further comprising two or more second small solder pads and a first long solder pad, wherein the second small solder pads are disposed in the first connection area or the second connection area and are adjacently connected, and the first long solder pad is disposed in the second connection area; wherein any one of the second small solder pads is connected to the conductive path, the first long solder pad is connected to any one of the second small solder pads through another wire, and the first long solder pad is connected to any one of the first small solder pads through another wire. An integrated circuit capable of reducing power pins as described in claim 6, further comprising two or more third small solder pads, two or more fourth small solder pads, a second long solder pad, a third long solder pad and a fourth long solder pad, wherein the third small solder pads are disposed in the first connection area or the second connection area and are adjacently connected; the fourth small solder pads are disposed in the first connection area or the second connection area and are adjacently connected, and the second long solder pad, the third long solder pad and the fourth long solder pad are disposed in the second connection area; wherein any one of the third small solder pads is connected to the conductive path, and the fourth small solder pads are connected to the conductive path. Any of the pads is connected to the conductive path, the second long pad is connected to any of the second small pads through another wire, and the second long pad is connected to any of the fourth small pads through another wire; the third long pad is connected to any of the fourth small pads through another wire, and the third long pad is connected to any of the third small pads through another wire; the fourth long pad is connected to any of the third small pads through another wire, and the fourth long pad is connected to any of the first small pads through another wire. An integrated circuit capable of reducing power pins as described in claim 2 or 3, further comprising two or more second small solder pads and two or more fifth small solder pads, wherein the second small solder pads are disposed in the first connection area or the second connection area and are adjacently connected, and the fifth small solder pads are disposed in the second connection area and are adjacently connected; wherein any one of the second small solder pads is connected to the conductive path, any one of the fifth small solder pads is connected to any one of the second small solder pads through another wire, and any one of the fifth small solder pads is connected to any one of the first small solder pads through another wire. An integrated circuit capable of reducing power pins includes: a package shell; a power pin terminal disposed on the package shell; a die disposed inside the package shell; an annular conductive path disposed around the die, forming a first connection area between the conductive path and the outer edge of the die, and forming a second connection area by the inside of the conductive path; More than one first elongated pads are arranged at relative positions of the first connection area; wherein the first elongated pads are connected to the conductive path, and any one of the first elongated pads is connected to the power pin terminal through a wire; and a large pad is arranged in the second connection area, and the large pad is connected to the first elongated pads through another two or more wires. The integrated circuit capable of reducing power pins as described in claim 9 further comprises two or more second elongated pads, the second elongated pads are arranged in the first connection area and are arranged at different positions from the first elongated pads; wherein the second elongated pads are connected to the conductive path, and the large pad is connected to the second elongated pads through two or more other wires.

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