TWI860491B - Chip testing device - Google Patents
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- TWI860491B TWI860491B TW110137816A TW110137816A TWI860491B TW I860491 B TWI860491 B TW I860491B TW 110137816 A TW110137816 A TW 110137816A TW 110137816 A TW110137816 A TW 110137816A TW I860491 B TWI860491 B TW I860491B
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Abstract
Description
本發明係關於一種檢測裝置,特別係關於一種用以批次檢測晶片的晶片檢測裝置。The present invention relates to a testing device, and more particularly to a wafer testing device for batch testing of wafers.
近年來由於製程技術的提升,有效地增加了晶片生產的速度,這些晶片於上市流通前均需要通過多道檢測流程以篩選不良的部分,而伴隨著生產加速俾有必要同步使檢測速度加快,以配合生產效率。因此,如何有效提升晶片檢測速率,成為目前晶片相關製造廠最渴望精進的課題。In recent years, due to the improvement of process technology, the speed of chip production has been effectively increased. These chips need to go through multiple inspection processes to screen out defective parts before they are put on the market. With the acceleration of production, it is necessary to increase the inspection speed to match the production efficiency. Therefore, how to effectively improve the chip inspection rate has become the most desired subject for chip-related manufacturers.
以封裝後的晶片2為例,請參考第1圖所示,由於晶片2的接點21設置緊密,檢測器1的接點11設置疏遠,兩者之間無法直接對應接觸,晶片檢測裝置需透過導線3使檢測器1的接點11與晶片2的接點21相互連接(若以探針組件接觸晶片2的接點21,探針組件與檢測器1的接點11之間仍需藉由導線連接)。當要批次進行晶片檢測時,便會設置有大量的導線3,具有導線3的裝置的配置會佔據許多檢測裝置的空間(例如接點21的上方空間),使檢測器1與晶片2之間的距離無法減少(例如檢測器得要配合導線的佈置及/或為更方便連接等因素,是設置在晶片固定處之左右外側),也因導線之特性阻抗、信號衰減等因素干擾,導致檢測裝置的檢測速度遭遇瓶頸,無法有效的進一步提升。也就是說,此種檢測裝置的檢測速度會低於晶片運行時的實際速度(也就是降速測試),無法符合晶片實際使用狀況之檢測。Taking the packaged
綜上,晶片檢測裝置實有改善之必要。In summary, there is a real need to improve chip inspection equipment.
需說明的是,上述之技術內容係用於幫助對本發明所欲解決問題的理解,其不必然是本領域已公開或公知者。It should be noted that the above technical contents are used to help understand the problems to be solved by the present invention, and they are not necessarily those that have been disclosed or known in the art.
本發明之一目的在於提供一種可直接地與複數晶片電性連接以提升檢測速度的晶片檢測裝置。One object of the present invention is to provide a chip testing device that can be directly electrically connected to a plurality of chips to increase the testing speed.
為達上述目的,本發明所提供的晶片檢測裝置包含一測試器及一連接組件。測試器設置於複數晶片的上方;連接組件設置在測試器及複數晶片之間,用以使複數晶片與測試器直接地相互電性連接。連接組件包含一上側面及相對上側面之一下側面,上側面包含複數第一接點,下側面包含複數第二接點,複數第一接點彼此之間之一第一直線距離,大於複數第二接點彼此之間之一第二直線距離,且複數第一接點與測試器直接地連接,複數第二接點與複數晶片直接地連接。To achieve the above-mentioned purpose, the chip detection device provided by the present invention includes a tester and a connection assembly. The tester is arranged above a plurality of chips; the connection assembly is arranged between the tester and the plurality of chips, and is used to directly electrically connect the plurality of chips and the tester to each other. The connection assembly includes an upper side surface and a lower side surface opposite to the upper side surface, the upper side surface includes a plurality of first contacts, the lower side surface includes a plurality of second contacts, a first straight line distance between the plurality of first contacts is greater than a second straight line distance between the plurality of second contacts, and the plurality of first contacts are directly connected to the tester, and the plurality of second contacts are directly connected to the plurality of chips.
於一實施例中,本發明之晶片檢測裝置之連接組件包含一連接器及一探針卡,連接器設置於探針卡的上方,複數第一接點設置在連接器之一側面上,複數第二接點設置在探針卡之一側面上。In one embodiment, the connection assembly of the chip detection device of the present invention includes a connector and a probe card, the connector is arranged above the probe card, a plurality of first contacts are arranged on a side of the connector, and a plurality of second contacts are arranged on a side of the probe card.
於一實施例中,本發明之晶片檢測裝置之探針卡包含複數第三接點,複數第三接點設置在探針卡的另一側面上,複數第三接點彼此之間之一第三直線距離大於複數第二接點之間之第二直線距離。In one embodiment, the probe card of the chip detection device of the present invention includes a plurality of third contacts, which are arranged on the other side of the probe card, and a third straight line distance between the plurality of third contacts is greater than a second straight line distance between the plurality of second contacts.
於一實施例中,本發明之晶片檢測裝置之探針卡之複數第三接點是平均分布地設置在探針卡之另一側面上。In one embodiment, the plurality of third contacts of the probe card of the chip detection device of the present invention are evenly distributed on the other side of the probe card.
於一實施例中,本發明之晶片檢測裝置之連接組件更包含一測試載板,設置在連接器及探針卡之間。In one embodiment, the connection assembly of the chip testing device of the present invention further includes a test carrier disposed between the connector and the probe card.
於一實施例中,本發明之晶片檢測裝置之測試載板包含複數第四接點,複數第四接點彼此之間之第四直線距離大於複數第三接點彼此之間之第三直線距離。In one embodiment, the test carrier of the chip testing device of the present invention comprises a plurality of fourth contacts, and a fourth straight line distance between the plurality of fourth contacts is greater than a third straight line distance between the plurality of third contacts.
於一實施例中,本發明之晶片檢測裝置之測試載板之複數第四接點是分別對應複數第一接點設置。In one embodiment, the plurality of fourth contacts of the test carrier of the chip testing device of the present invention are respectively arranged corresponding to the plurality of first contacts.
於一實施例中,本發明之晶片檢測裝置之探針卡為微機電探針卡。In one embodiment, the probe card of the chip testing device of the present invention is a micro-electromechanical probe card.
於一實施例中,本發明之晶片檢測裝置之連接器是鎖固於測試載板上。In one embodiment, the connector of the chip testing device of the present invention is locked on the test carrier.
於一實施例中,本發明之晶片檢測裝置之測試載板與探針卡之間是透過焊接彼此固定。In one embodiment, the test carrier and the probe card of the chip testing device of the present invention are fixed to each other by welding.
於一實施例中,本發明之晶片檢測裝置之連接器是彈簧連接器或表面貼焊連接器。In one embodiment, the connector of the chip detection device of the present invention is a spring connector or a surface mount connector.
為讓上述目的、技術特徵及優點能更明顯易懂,下文係以較佳之實施例配合所附圖式進行詳細說明。In order to make the above-mentioned objectives, technical features and advantages more clearly understood, the following is a detailed description with reference to preferred embodiments and the accompanying drawings.
以下將具體地描述根據本發明的具體實施例;惟,在不背離本發明之精神下,本發明尚可以多種不同形式之實施例來實踐,不應將本發明保護範圍解釋為限於說明書所陳述者。The following will specifically describe specific embodiments of the present invention; however, without departing from the spirit of the present invention, the present invention can also be implemented in a variety of different forms of embodiments, and the protection scope of the present invention should not be interpreted as limited to what is described in the specification.
除非上下文中清楚地另外指明,否則本文所用之單數形式「一」、「該」及類似用語亦包含複數形式,而用語「第一」、「第二」等在本文中係用以闡述各元件或組件,而非該等元件或組件具備必要順序或優先性。此外,所述之方位(如上、下、左、右等)係為相對方位,可依據晶片檢測裝置的使用狀態而定義,並非指示或暗示晶片檢測裝置需有特定方向之放置方式或構造,亦不能理解為對本發明的限制。在附圖中,為清晰說明起見,可誇大晶片、測試器、接點、測試載板等之尺寸及相對尺寸。Unless the context clearly indicates otherwise, the singular forms "a", "the" and similar terms used herein also include the plural forms, and the terms "first", "second", etc. are used herein to describe various elements or components, not to indicate that these elements or components have a necessary order or priority. In addition, the directions (such as up, down, left, right, etc.) described are relative directions and can be defined according to the use status of the chip detection device. They do not indicate or imply that the chip detection device needs to be placed or constructed in a specific direction, nor can they be understood as limitations on the present invention. In the attached drawings, the size and relative size of the chip, tester, contact, test carrier, etc. may be exaggerated for the sake of clarity.
請參考第2圖所示,為本發明一實施例之晶片檢測裝置10之示意圖。晶片檢測裝置10可連接至一電子裝置以發送及接收訊號,進行移動或分析等作業,但不以此作為限制。晶片檢測裝置10可用以批次檢測多個晶片20,晶片20可為已封裝完成的晶粒,例如快閃記憶體的晶粒。進行檢測時,一或多個晶片20放置在一承載座30上並固定,晶片檢測裝置10從上而下接觸晶片20。晶片檢測裝置10包含一測試器100以及一連接組件200,各元件之技術內容說明如下。Please refer to FIG. 2, which is a schematic diagram of a
於此一實施例中,測試器100設置於複數待測的晶片20的上方,例如為正上方。連接組件200設置在測試器100及複數待測的晶片20之間,使複數待測的晶片20藉由連接組件200直接地與測試器100相互電性連接。連接組件200包含一上側面210及相對上側面210之一下側面220,上側面210包含複數第一接點211,下側面220包含複數第二接點221,第一接點211直接與測試器100的接點101接觸並電性連接,第二接點221直接與晶片20的接點21接觸並電性連接。In this embodiment, the
詳細而言,連接組件200可包含一連接器300及一探針卡400,連接器300設置在探針卡400的上方,例如為正上方,連接器300之一側面310便作為連接組件200之上側面210,探針卡400之一側面410便作為連接組件200之下側面220。In detail, the
請同時參考第3A圖所示,連接器300例如可為彈簧連接器陣列(Pogo Pin Array),具有側面310及相對側面310之另一側面320,以及設置有複數貫穿孔,複數彈簧探針311分別設置於貫穿孔中,每一彈簧探針311包含一針(Plunger)、一管(Tube)、一彈簧(Spring)等構件,彈簧探針311可為雙頭彈簧探針,其兩端311a、311b分別自側面310及另一側面320露出,兩端311a、311b皆可分別地受壓後朝彈簧連接器300的方向收縮(端311a向下收縮、端311b向上收縮)。圖中側面310所示之彈簧探針311分為兩區矩形陣列,另一側面320之彈簧探針排列方式可與之對應,但不以此作為限制。端311a與端311b的位置不一定相互對應。Please also refer to FIG. 3A , the
請參考第3B圖所示,連接器300又例如可為表面貼焊連接器(SMD connector)300’。圖中所示為表面貼焊連接器300’之俯視示意圖。表面貼焊連接器300’具有位於一上表面之複數第一連接點312及位於相對上表面之一下表面之複數第二連接點313。第一連接點312是直接與測試器100的接點101接觸並電性連接,第二連接點313是直接與晶片20的接點21接觸並電性連接。其中,表面貼焊連接器300’更包含一蓋體314,以便於作業中藉由機械移動連接器300’同時避免在此過程中讓第一連接點312受擠壓、變形,蓋體314也例如可以用麥拉貼片(Mylar)取代,但不以此作為限制。使用表面貼焊連接器300’時,蓋體314或麥拉貼片將被摘除。如第3C圖所示,為另一種表面貼焊連接器300’’,其具有與表面貼焊連接器300’相似的外型,於一表面上具有複數第一連接點312’,另一表面上具有複數第二連接點313’,第一連接點312’可直接地與接點101電性連接,第二連接點313’ 可直接地與接點21電性連接。Please refer to FIG. 3B , the
請參考第4圖所示,為本發明之一實施例之探針卡400之側面410之示意圖,虛線是示意性的示出對應的單一晶片(晶粒)20的外輪廓,於本實施例中,探針卡400可為微機電探針卡(MEMS Probe card)。檢測時,複數晶片20彼此對齊排列,由於晶片20之接點21位於晶片20之一側邊,探針卡400包含之複數第二接點221便是分別對應接點21地設置於側面410上。Please refer to FIG. 4, which is a schematic diagram of the
請參考第5圖所示,為探針卡400之另一側面420之示意圖,另一側面420包含複數第三接點421,複數第三接點421在示意單一晶片20的外輪廓中平均分布,第三接點421是直接接觸並電性連接連接器300的探針311之一端311b,探針311透過第三接點421與晶片20之一個接點21電性導通、連接。Please refer to FIG. 5 , which is a schematic diagram of the
請重新參考第2圖至第5圖所示,以連接器300為彈簧連接器作為示例,複數第一接點211(彈簧探針311之端311a)彼此之間具有一第一直線距離D1(相鄰之第一連接點312之間可具有一直線距離D1’;相鄰之第一連接點312’之間可具有一直線距離D1’’),複數第二接點221彼此之間具有一第二直線距離D2,複數第三接點421彼此之間具有一第三直線距離D3,其中第三直線距離D3大於第二直線距離D2。也就是,複數第二接點221是緊密且聚集的布置,複數第三接點421是相較分散且平均的布置。如此一來,藉由第二接點221與第三接點421的設置,探針卡400可初步地將原本設置密集的接點21,導引成彼此分散並相隔一距離,俾便對應至連接器300之彈簧探針311的布置,或者第二連接點313、313’的布置。視情況,第一直線距離D1(或直線距離D1’、D1’’)大於第二直線距離D2,更可大於第三直線距離D3,使接點彼此之間的距離進一步加大,俾便連接測試器100的接點101。Please refer to FIG. 2 to FIG. 5 again, taking the
請參考第6圖所示,於本發明之一實施例中,連接組件200更可包含一測試載板500(Load Board P.C.B.),測試載板500設置在連接器300與探針卡400之間,可與探針卡400焊接在一起而相互固定,增強探針卡400遭受壓力的可靠度,而可直接承接測試器100。連接器300則可被鎖固於測試載板500上(圖未示出鎖點),但不以此作為限制。測試載板500包含一上側面510,上側面510具有複數第四接點511,第四接點511是直接接觸並電性連接連接器300的探針311之一端311b。複數第四接點511彼此之間具有一第四直線距離D4,第四直線距離D4可等於第三直線距離D3,也可以大於第三直線距離D3,以進一步拉開接點之間的距離,且更有彈性地配合連接器300的尺寸,即是,配合連接器300的彈簧探針311或第二連接點313、313’之間的設置距離。Please refer to FIG. 6 , in one embodiment of the present invention, the
綜合上述,本發明之晶片檢測裝置具有的連接組件可以藉由探針卡、測試載板及/或連接器,使待測的晶片的接點可直接地,例如沿垂直方向直接地、垂直地,連接測試器的接點,如此在批次檢測多個晶片的時候免除設置導線的缺失,使測量晶片的檢測速度加快,例如自800兆字節每秒(MB/s)提升至1.2吉字節每秒(GB/s),更接近或符合市面上晶片實際運作時的速度,也能協助提升晶片的整體生產速度。In summary, the connection assembly of the chip inspection device of the present invention can directly connect the contacts of the chip to be tested to the contacts of the tester, for example, directly and vertically in the vertical direction, through a probe card, a test carrier and/or a connector. This eliminates the need to set up missing wires when testing multiple chips in batches, thereby increasing the inspection speed of the measured chips, for example, from 800 megabytes per second (MB/s) to 1.2 gigabytes per second (GB/s), which is closer to or in line with the actual operating speed of chips on the market, and can also help improve the overall production speed of chips.
上述之實施例僅用來例舉本發明之實施態樣,以及闡釋本發明之技術特徵,並非用來限制本發明之保護範疇。任何熟悉此技術者可輕易完成之改變或均等性之安排均屬於本發明所主張之範圍,本發明之權利保護範圍應以申請專利範圍為準。The above embodiments are only used to illustrate the implementation of the present invention and to explain the technical features of the present invention, and are not used to limit the scope of protection of the present invention. Any changes or equivalent arrangements that can be easily completed by those familiar with this technology are within the scope of the present invention, and the scope of protection of the present invention shall be based on the scope of the patent application.
1:檢測器
2:晶片
3:導線
10:晶片檢測裝置
11:接點
20:晶片
21:接點
30:乘載座
100:測試器
101:接點
200:連接組件
210:上側面
211:第一接點
220:下側面
221:第二接點
300:連接器
300’、300’’:表面貼焊連接器
310:側面
311:彈簧探針
311a、311b:端
312、312’:第一連接點
313、313’:第二連接點
314:蓋體
320:另一側面
400:探針卡
410:側面
420:另一側面
421:第三接點
500:測試載板
510:上側面
511:第四接點
D1:第一直線距離
D1’、D1’’:直線距離
D2:第二直線距離
D3:第三直線距離
D4:第四直線距離
1: Detector
2: Chip
3: Wire
10: Chip detection device
11: Contact
20: Chip
21: Contact
30: Carrier
100: Tester
101: Contact
200: Connection assembly
210: Upper side
211: First contact
220: Lower side
221: Second contact
300: Connector
300', 300'': Surface mount connector
310: Side
311:
第1圖為習知的檢測器與晶片連接方式的示意圖;FIG. 1 is a schematic diagram of a conventional method of connecting a detector to a chip;
第2圖為根據本發明之一實施例之晶片檢測裝置之側視示意圖;FIG. 2 is a schematic side view of a chip inspection device according to an embodiment of the present invention;
第3A圖至第3C圖為根據本發明之一實施例之晶片檢測裝置之不同類型連接器之示意圖;FIGS. 3A to 3C are schematic diagrams of different types of connectors of a chip testing device according to an embodiment of the present invention;
第4圖為根據本發明之一實施例之晶片檢測裝置之探針卡之一側面之示意圖;FIG. 4 is a schematic diagram of a side surface of a probe card of a chip detection device according to an embodiment of the present invention;
第5圖為根據本發明之一實施例之晶片檢測裝置之探針卡之另一側面之示意圖;以及FIG. 5 is a schematic diagram of another side of the probe card of the chip detection device according to an embodiment of the present invention; and
第6圖為根據本發明之另一實施例之晶片檢測裝置之側視示意圖。FIG6 is a side view schematic diagram of a chip inspection device according to another embodiment of the present invention.
10:晶片檢測裝置 10: Chip detection device
20:晶片 20: Chip
21:接點 21: Contact
30:乘載座 30: Passenger seat
100:測試器 100: Tester
101:接點 101: Contact
200:連接組件 200:Connection components
210:上側面 210: Upper side
211:第一接點 211: First contact
220:下側面 220: Lower side
221:第二接點 221: Second contact
300:連接器 300: Connector
310:側面 310: Side
311:彈簧探針 311: Spring probe
311a、311b:端 311a, 311b: end
320:另一側面 320: The other side
400:探針卡 400:Probe card
410:側面 410: Side
420:另一側面 420: The other side
421:第三接點 421: Third contact
D1:第一直線距離 D1: First straight line distance
D2:第二直線距離 D2: Second straight line distance
D3:第三直線距離 D3: Third straight line distance
Claims (8)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW110137816A TWI860491B (en) | 2021-10-12 | 2021-10-12 | Chip testing device |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW110137816A TWI860491B (en) | 2021-10-12 | 2021-10-12 | Chip testing device |
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| Publication Number | Publication Date |
|---|---|
| TW202316129A TW202316129A (en) | 2023-04-16 |
| TWI860491B true TWI860491B (en) | 2024-11-01 |
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| Application Number | Title | Priority Date | Filing Date |
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| TW110137816A TWI860491B (en) | 2021-10-12 | 2021-10-12 | Chip testing device |
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| CN115963378A (en) * | 2021-10-12 | 2023-04-14 | 复格企业股份有限公司 | Chip detection device |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20040223309A1 (en) * | 2000-05-23 | 2004-11-11 | Haemer Joseph Michael | Enhanced compliant probe card systems having improved planarity |
| TW201135253A (en) * | 2009-12-31 | 2011-10-16 | Formfactor Inc | Wafer test cassette system |
| TW201140073A (en) * | 2009-12-11 | 2011-11-16 | Gigalane Co Ltd | Probe card |
| TW201405132A (en) * | 2012-07-25 | 2014-02-01 | 日本麥克隆尼股份有限公司 | Probe card and test equipment |
| TW202035996A (en) * | 2019-03-18 | 2020-10-01 | 中華精測科技股份有限公司 | Probe card testing device and signal switching module thereof |
-
2021
- 2021-10-12 TW TW110137816A patent/TWI860491B/en active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20040223309A1 (en) * | 2000-05-23 | 2004-11-11 | Haemer Joseph Michael | Enhanced compliant probe card systems having improved planarity |
| TW201140073A (en) * | 2009-12-11 | 2011-11-16 | Gigalane Co Ltd | Probe card |
| TW201135253A (en) * | 2009-12-31 | 2011-10-16 | Formfactor Inc | Wafer test cassette system |
| TW201405132A (en) * | 2012-07-25 | 2014-02-01 | 日本麥克隆尼股份有限公司 | Probe card and test equipment |
| TW202035996A (en) * | 2019-03-18 | 2020-10-01 | 中華精測科技股份有限公司 | Probe card testing device and signal switching module thereof |
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| TW202316129A (en) | 2023-04-16 |
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