CN111830400A - Chip testing device - Google Patents

Abstract

The embodiment of the present invention discloses a chip testing device. By setting the surface of the lead frame away from the PCB board, the surface includes a recessed structure, and the recessed structure is used to place the chip to be tested; the bottom surface of the recessed structure includes a plurality of first via holes, and the test pin head is detachable The test pin is fixed and penetrated in the first via hole, so that when the test pin is damaged or different types of test pins need to be used to test the chip to be tested, the test pin can be easily removed from the lead frame, thereby facilitating the replacement of the test pin. In addition, the plurality of test needles include a first test needle and a second test needle, the first test needle is electrically connected to the first radio frequency signal line on the PCB, and the second test needle is electrically connected to the second radio frequency signal line on the PCB. connection, and then the performance test of the chip to be tested can be realized. In addition, in the chip testing device provided by the embodiment of the present invention, the structure of the lead frame is simple, so the difficulty of manufacturing the lead frame is relatively small.

Description

A chip testing device

technical field

Embodiments of the present invention relate to the technical field of chip testing, and in particular, to a chip testing device.

Background technique

With the rapid development of 5G technology and big data, the frequency and speed of chip operation are getting higher and higher.

During or after the production of the chip, the chip needs to be tested to obtain the working performance of the chip, for example, the high-speed and high-frequency indicators of the chip need to be tested. Due to different chip sizes and packaging forms, different chips may need to be tested with different test needles, and as the test needles are used for an extended period of time, the test needles may be damaged. Therefore, it is an urgent problem to design a chip testing device with easy replacement of test needles.

SUMMARY OF THE INVENTION

The invention provides a chip testing device, so that the test needle can be easily replaced, and the chip testing device has a relatively simple structure.

An embodiment of the present invention provides a chip testing device, comprising: a guide frame, a plurality of test needles, and a PCB board, and the guide frame is arranged on one side of the PCB board;

The surface of the lead frame away from the PCB board includes a concave structure, and the concave structure is used for placing the chip to be tested; the bottom surface of the concave structure includes a plurality of first via holes, and the test needles are detachably fixed and penetrated in the first via holes;

The plurality of test needles include a first test needle and a second test needle. The first test needle is electrically connected to the first radio frequency signal line on the PCB, and the second test needle is electrically connected to the second radio frequency signal line on the PCB.

Optionally, the plurality of test pins further include a third test pin and a fourth test pin, the third test pin is electrically connected to the first digital signal line on the PCB, and the fourth test pin is connected to the second digital signal on the PCB. The signal lines are electrically connected, and the first radio frequency signal line, the second radio frequency signal line, the first digital signal line and the second digital signal line are arranged on the same PCB board.

Optionally, the test needle includes a needle tip portion, a needle body portion and a fixing portion, wherein the needle body portion is located between the needle tip portion and the fixing portion, the shape of the needle tip portion is conical, and the needle tip portion is used for contacting the chip to be tested;

The needle body part and the fixed part are cylindrical, and the needle body part is located in the first via hole, the fixed part is located on the side of the guide frame close to the PCB board, and the diameter of the fixed part is larger than the diameter of the first via hole;

Optionally, the diameter of the needle body portion is greater than or equal to 0.01 mm and less than or equal to 1 mm; the diameter of the fixing portion is greater than or equal to 0.01 mm and less than or equal to 1.5 mm.

Optionally, the chip testing device further includes a grounding copper block, the grounding copper block is arranged on the bottom surface of the recessed structure, and the area of the grounding copper block is smaller than the bottom surface area of the recessed structure; the grounding copper block includes a plurality of second vias, a plurality of test The needle further includes a fifth test needle, and the fifth test needle penetrates the second via hole;

The bottom surface of the recessed structure includes a center area and an edge area surrounding the center area, wherein the ground copper block is located in the center area, and the first test needle, the second test needle, the third test needle and the fourth test needle are located at the edge area.

Optionally, the chip testing device further includes a test seat shell, the test seat shell and the pedestal frame are arranged on the same side of the PCB board, and the test seat shell is located around the pedestal frame, and the test seat shell and the pedestal frame constitute the test seat. , the test seat shell is fixedly connected with the pedestal frame, or the test seat shell and the pedestal frame are integrated.

Optionally, the PCB board is a radio frequency PCB board, and the chip testing device further includes a digital PCB board and a test seat shell; the test seat shell and the lead frame form a test seat, and the test seat shell and the lead frame are fixedly connected, or the test seat shell Body and lead frame as one structure;

The housing of the test seat is arranged on one side of the digital PCB board, the pedestal frame is arranged on the side of the test seat away from the digital PCB board, and the surface of the pedestal frame on the side away from the digital PCB board includes a concave structure; the RF PCB board is partially arranged on the pedestal frame and the test seat; at the recessed structure, the first via penetrates the lead frame;

The plurality of test needles also include a third test needle and a fourth test needle, the third test needle is electrically connected to the first digital signal line, and the fourth test needle is electrically connected to the second digital signal line; the first digital signal line and the first digital signal line are electrically connected. Two digital signal lines are disposed on the digital PCB board, and the first radio frequency signal line and the second radio frequency signal line are disposed on the radio frequency PCB board.

Optionally, the chip testing device further includes an elastic support structure;

The housing of the test seat includes a third via hole. In the thickness direction of the chip testing device, the third via hole corresponds to the first via hole one-to-one. The hole corresponds to the third via hole.

Optionally, the radio frequency PCB board includes a first radio frequency PCB board and a second radio frequency PCB board, and a distance exists between the first radio frequency PCB board and the second radio frequency PCB board between the lead frame and the test seat housing;

The third test pin and the fourth test pin are conductive pogo pins, and the test seat housing includes a third via hole. In the thickness direction of the chip testing device, the third via hole corresponds to the first via hole one-to-one, and the conductive pogo pin penetrates the first via hole. There are three via holes and a first via hole corresponding to the third via hole, and the conductive pogo pins are located between the first radio frequency PCB board and the second radio frequency PCB board.

Optionally, both the first test needle and the second test needle include a needle tip portion, a needle body portion and a fixing portion, wherein the needle body portion is located between the needle tip portion and the fixing portion, and the side of the needle tip portion away from the needle body portion includes a concave portion. Slot, the tip of the needle is used to contact the chip to be tested;

The needle body part and the fixing part are cylindrical, and the needle body part is located in the first via hole, the fixing part is located on the side of the lead frame close to the RF PCB board, and the diameter of the fixing part is larger than the diameter of the first via hole;

Optionally, the diameter of the needle body portion is greater than or equal to 0.01 mm and less than or equal to 1 mm; the diameter of the fixing portion is greater than or equal to 0.01 mm and less than or equal to 1.5 mm.

Optionally, the height of the test needle is greater than or equal to 0.01 mm and less than or equal to 3 mm.

Optionally, the lead frame and/or the test seat housing further includes a fourth via hole, and a fifth via hole is provided on the PCB board. In the thickness direction of the chip testing device, the fifth via hole and the fourth via hole are one by one. Correspondingly; the chip testing device further includes a fixing structure, and the fixing structure is penetrated in the fourth via hole and the fifth via hole, and is used for fixing the test seat and the PCB board;

The pedestal and/or the test seat housing further includes a sixth via hole, and a seventh via hole is provided on the PCB board. In the thickness direction of the chip testing device, the seventh via hole corresponds to the sixth via hole one-to-one; chip testing The device further includes a positioning structure, which is penetrated in the sixth via hole and the seventh via hole, and is used for positioning the test seat and the PCB board.

Optionally, the lead frame and/or the test seat housing further includes a fourth via hole, and a fifth via hole is provided on the digital PCB board. In the thickness direction of the chip testing device, the fifth via hole is the same as the fourth via hole. One correspondence; the chip testing device further includes a fixing structure, and the fixing structure is penetrated in the fourth via hole and the fifth via hole, and is used for fixing the test seat and the digital PCB board;

The pedestal and/or the test seat housing further includes a sixth via hole, and the RF PCB board and the digital PCB board are provided with a seventh via hole. In the thickness direction of the chip testing device, the seventh via hole and the sixth via hole are One-to-one correspondence; the chip testing device further includes a positioning structure, which is penetrated in the sixth via hole and the seventh via hole, and is used for positioning the test seat and the PCB board.

Optionally, the chip testing device further includes a first radio frequency connector and a second radio frequency connector, the first radio frequency connector is electrically connected to the first radio frequency signal line, and the second radio frequency connector is electrically connected to the second radio frequency signal line.

The chip testing device provided by the embodiment of the present invention includes a recessed structure on the surface of the guide frame away from the PCB board, and the recessed structure is used to place the chip to be tested; the bottom surface of the recessed structure includes a plurality of first via holes, and the test needle is detachably fixed Through the first via hole; when the test needle is damaged or different types of test needles need to be used to test the chip to be tested, the test needle can be easily removed from the lead frame, thereby facilitating the replacement of the test needle. In addition, the plurality of test needles include a first test needle and a second test needle, the first test needle is electrically connected to the first radio frequency signal line on the PCB board, and the second test needle head is electrically connected to the second radio frequency signal line on the PCB board. connection, and then the performance test of the chip to be tested can be realized. In addition, in the chip testing device provided by this embodiment, the structure of the lead frame is simple, so the difficulty of manufacturing the lead frame is relatively small.

Description of drawings

1 is a schematic structural diagram of a chip testing device provided by an embodiment of the present invention;

2 is a schematic structural diagram of a test needle provided by an embodiment of the present invention;

Fig. 3 is a partial enlarged view of Fig. 1;

Fig. 4 is the top view of the bottom surface of the recessed structure in Fig. 1;

5 is a schematic structural diagram of another chip testing device provided by an embodiment of the present invention;

Fig. 6 is a partial enlarged view of Fig. 5;

7 is a cross-sectional view of a chip testing device provided by an embodiment of the present invention;

Fig. 8 is a partial enlarged view of Fig. 6;

9 is a schematic structural diagram of a test needle provided by an embodiment of the present invention;

Detailed ways

The present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention, but not to limit the present invention. In addition, it should be noted that, for the convenience of description, the drawings only show some but not all structures related to the present invention.

FIG. 1 is a schematic structural diagram of a chip testing device provided by an embodiment of the present invention. Referring to FIG. 1 , the chip testing device includes a lead frame 110 , a plurality of test pins 120 , and a PCB board 130 . The lead frame 110 is disposed on the PCB board 130 . one side;

The surface of the lead frame 110 away from the PCB board 130 includes a concave structure 111, and the concave structure 111 is used for placing the chip to be tested; the bottom surface of the concave structure 111 includes a plurality of first vias 101, and the test needles 120 are detachably fixed through the first through holes 101. In the via hole 101;

The plurality of test needles 120 include a first test needle 121 and a second test needle 122 . The first test needle 121 is electrically connected to the first radio frequency signal line 141 on the PCB board 130 , and the second test needle 122 is connected to the PCB board 130 . The second radio frequency signal line 142 is electrically connected.

Specifically, the lead frame 110 may be formed by using insulating materials such as plastic. The PCB board 130 may have circuit structures thereon. A side of the lead frame 110 away from the PCB board 130 has a concave structure 111 , and the concave structure 111 is used for placing the chip to be tested. That is, when the chip to be tested is tested, the chip to be tested can be placed in the recessed structure 111 . The bottom surface of the recessed structure 111 includes a plurality of first via holes 101 , wherein the bottom surface of the recessed structure 111 is the surface parallel to the surface of the recessed structure 111 and the surface of the lead frame 110 of the PCB board 130 , and the test needle 120 is detachably fixed and penetrated through the first vias. In the hole 101 , when the test needle 120 is damaged or different types of test needles 120 need to be used to test the chip under test, the test needle 120 can be easily removed from the lead frame 110 , thereby facilitating the replacement of the test needle 120 .

Referring to FIG. 1 , a first RF signal line 141 and a second RF signal line 142 are provided on the PCB board 130 , the first test pin 121 is electrically connected to the first RF signal line 141 , and the second test pin 122 is electrically connected to the second RF signal line 142 electrical connections. Wherein, the first radio frequency signal line 141 and the second radio frequency signal line 142 may be used for transmitting high frequency signals. When testing the chip, the chip to be tested can be placed in the concave structure 111, wherein the surface of the chip to be tested and the test needle 120 in contact can include metal pads. After the chip to be tested is placed in the concave structure 111, by pressing the chip, the pads of the chip to be tested can be brought into contact with the test needles 120 . For different chips to be tested, different lead frames 110 or PCB boards 130 may be used for testing, so that the chips to be tested and the PCB board 130 can be matched with the chips to be tested. The present invention does not limit the size of the concave structure 111 of the lead frame 110 , and the size of the concave structure 111 of different lead frames 110 may be different, and further, for the chips to be tested of different sizes, different lead frames 110 can be selected to match them. . The chip to be tested usually includes two RF signal terminals. For the chip to be tested whose RF signal terminals are in different positions, the RF signal line can also be selected to be tested on the PCB board 130 corresponding to the position of the RF signal terminal.

1, optionally, the chip testing device further includes a first radio frequency connector 210 and a second radio frequency connector 220, the first radio frequency connector 210 is electrically connected to the first radio frequency signal line 141, and the second radio frequency connector 220 is electrically connected to the second radio frequency signal line 142 . When testing the chip under test, one of the first radio frequency connector 210 and the second radio frequency connector 220 can be connected to an oscilloscope or a network analyzer, and the other can be connected to a radio frequency signal. Exemplarily, the first RF connector 210 is connected to a RF signal, and the second RF connector 220 is connected to an oscilloscope or a network analyzer, then by observing the waveforms of the oscilloscope and the network analyzer, combined with the first RF connector 210 to capture the size of the RF signal , the high-speed and high-frequency performance of the chip can be analyzed.

In the chip testing device provided in this embodiment, the surface of the guide frame away from the PCB board includes a concave structure, and the concave structure is used to place the chip to be tested; the bottom surface of the concave structure includes a plurality of first via holes, and the test needles are detachably fixed and passed through. It is arranged in the first via hole; when the test needle is damaged or different types of test needles need to be used to test the chip to be tested, the test needle can be easily removed from the lead frame, thereby facilitating the replacement of the test needle. In addition, the plurality of test needles include a first test needle and a second test needle, the first test needle is electrically connected to the first radio frequency signal line on the PCB board, and the second test needle head is electrically connected to the second radio frequency signal line on the PCB board. connection, and then the performance test of the chip to be tested can be realized. In addition, in the chip testing device provided by this embodiment, the structure of the lead frame is simple, so the difficulty of manufacturing the lead frame is relatively small.

1 , optionally, the plurality of test pins 120 further include a third test pin 123 and a fourth test pin 124 , the third test pin 123 is electrically connected to the first digital signal line 151 on the PCB 130 , and the third test pin 123 is electrically connected to the first digital signal line 151 on the PCB 130 . The four test pins 124 are electrically connected to the second digital signal line 152 on the PCB board 130. The first radio frequency signal line 141, the second radio frequency signal line 142, the first digital signal line 151, and the second digital signal line 152 are arranged on the same PCB on board 130.

Specifically, the existing PCB board 130 may include a digital PCB board and a radio frequency PCB board. In the chip testing device shown in FIG. 1 , the digital PCB board and the radio frequency PCB board are the same PCB board 130 , and the PCB board 130 includes both digital signal lines and radio frequency signal lines. The first digital signal line 151 and the second digital signal line 152 may be used to transmit digital signals. Optionally, the chip to be tested may include two digital signal ports. When testing the chip to be tested, the chip to be tested can be placed in the recessed structure 111, and the two test ports of the chip to be tested can be respectively connected with the third test port. The needles 123 and the fourth test needles 124 are in contact, and then the third test needles 123 , the first digital signal lines 151 , the fourth test needles 124 and the second digital signal lines 152 are electrically connected to realize the performance test of the digital signal port of the chip under test.

2 is a schematic structural diagram of a test needle provided by an embodiment of the present invention. Referring to FIG. 2 , optionally, the test needle 120 includes a needle tip portion 1201 , a needle body portion 1202 and a fixing portion 1203 , wherein the needle body portion 1202 is located at the needle tip portion Between 1201 and the fixing portion 1203, the shape of the tip portion 1201 is conical, and the tip portion 1201 is used to contact the chip to be tested;

The needle body part 1202 and the fixing part 1203 are cylindrical, and the needle body part 1202 is located in the first via hole 101 , the fixing part 1203 is located on the side of the guide frame 110 close to the PCB board 130 , and the diameter of the fixing part 1203 is larger than that of the first through hole 101 . the diameter of the hole 101;

Optionally, the diameter of the needle body portion is greater than or equal to 0.01 mm and less than or equal to 1 mm; the diameter of the fixing portion is greater than or equal to 0.01 mm and less than or equal to 1.5 mm.

Optionally, the test pins 120 shown in FIG. 2 may be suitable for the chips to be tested of QFN (Quad Flat No-lead Package) and QFP (Quad Flat Package, square flat package). Specifically, for QFN and LGA chips to be tested, the pad surface of the bottom surface of the chip to be tested is usually flat, and the tip 1201 of the test needle 120 shown in FIG. 2 is conical. the underside pad contacts. Optionally, the tip of the needle tip portion is in the shape of a hemisphere as shown in FIG. 2 . When installing the test needle 120 , the guide frame 110 can be inverted, and then the test needle 120 can be pushed through the first through hole 101 of the recessed structure 111 by pressing the test needle 120 . The diameter is equal to the diameter of the first via hole 101 , so that the test needle 120 and the sidewall of the first via hole 101 can contact each other and have a force, so that the test needle 120 will not fall out of the first via hole 101 . After installation, the fixing portion 1203 is located on the side of the lead frame 110 close to the PCB board 130 , so that the test needles 120 will not drop from the surface of the lead frame 110 with the concave structure 111 .

FIG. 3 is a partial enlarged view of FIG. 1 , and FIG. 4 is a top view of the bottom surface of the recessed structure in FIG. 1 . With reference to FIGS. 1 , 3 and 4 , optionally, the chip testing device further includes a ground copper block 160 . 160 is disposed on the bottom surface of the recessed structure 111, and the area of the ground copper block 160 is smaller than that of the bottom surface of the recessed structure 111; The fifth test needle 125 penetrates the second via hole 102;

The bottom surface of the recessed structure 111 includes a central area 1111 and an edge area 1112 surrounding the central area 1111, wherein the ground copper block 160 is located in the central area 1111, the first test needle 121, the second test needle 122, the third test needle 123 and the third test needle Four test needles 124 are located in edge region 1112 .

Specifically, the middle part of the chip under test of QFN and LGA usually includes a ground pad. The chip testing apparatus shown in FIG. 1 and FIG. 3 can be used for the chip under test of QFN and LGA, and includes a ground chip corresponding to the ground pad. Therefore, when the chip testing device of this embodiment is used to test the chip to be tested, the chip to be tested can be reliably grounded.

Continuing to refer to FIG. 1 , optionally, the chip testing device further includes a test seat housing 170 , the test seat housing 170 and the lead frame 110 are disposed on the same side of the PCB board 130 , and the test seat housing 170 is located on the side of the lead frame 110 . Around the periphery, the test seat housing 170 and the pedestal frame 110 form a test seat, the test seat housing 170 and the pedestal frame 110 are fixedly connected, or the test seat housing 170 and the pedestal frame 110 are integrally formed.

Continuing to refer to FIG. 1 , optionally, the lead frame 110 and/or the test seat housing 170 further includes a fourth via hole 104 , and the PCB board 130 is provided with a fifth via hole 105 . In the thickness direction y of the chip testing device, The fifth via hole 105 corresponds to the fourth via hole 104 one-to-one; the chip testing device further includes a fixing structure 201 , the fixing structure 201 is penetrated in the fourth via hole 104 and the fifth via hole 105 for connecting the test seat to the PCB plate 130 is fixed;

Optionally, the lead frame 110 and/or the test seat housing 170 further includes a sixth via hole 106 , a seventh via hole 107 is provided on the PCB board 130 , and in the thickness direction y of the chip testing device, the seventh via hole 107 One-to-one correspondence with the sixth via holes 106 ; the chip testing device further includes a positioning structure 202 , which is penetrated in the sixth via hole 106 and the seventh via hole 107 for positioning the test seat and the PCB board 130 .

Specifically, when assembling the chip testing device, the test seat on which the test pins 120 and the ground copper block 160 are installed can be aligned with the seventh via hole 107 through the sixth via hole 106 first, and the sixth via hole 106 and the seventh via hole 107 can be aligned between the sixth via hole 106 and the first A positioning structure 202 such as a positioning pin is inserted into the seven via holes 107 . Then, the fixing structure 201 is inserted into the fourth via hole 104 and the fifth via hole 105 , wherein the fixing structure 201 can be a screw, which is installed and locked on the test seat PCB board 130 by the screw. During chip testing, the concave structure 111 of the lead frame 110 can limit the position of the chip. When the chip to be tested is placed in the concave structure 111 , the chip to be tested can be placed in the concave structure 111 according to the pin1 position. The pin1 corner may be a setting pin of the chip to be tested, and placing the chip to be tested into the concave structure 111 according to the position of the set pin can ensure that the relative position of the chip to be tested and each test needle 120 is accurate.

In the above embodiments, the test seat housing 170 and the lead frame 110 are of the same layer structure. In other embodiments of the present invention, the test seat housing 170 and the lead frame 110 may be of different layer structures. For details, refer to the following embodiments.

FIG. 5 is a schematic structural diagram of another chip testing device provided by an embodiment of the present invention, and FIG. 6 is a partial enlarged view of FIG. 5. Referring to FIG. 5 and FIG. 6, optionally, the PCB board 130 is a radio frequency PCB board 131, and the chip The test device further includes a digital PCB board 132 and a test seat housing 170; the test seat housing 170 and the pedestal 110 form a test seat, the test seat housing 170 is fixedly connected to the pedestal 110, or the test seat housing 170 and the pedestal 110 integrated structure;

The test seat housing 170 is arranged on one side of the digital PCB board 132, the pedestal frame 110 is arranged on the side of the test seat away from the digital PCB board 132, and the surface of the pedestal frame 110 on the side away from the digital PCB board 132 includes a recessed structure 111; The PCB board 131 is partially disposed between the lead frame 110 and the test seat; at the recessed structure 111 , the first via hole 101 penetrates the lead frame 110 ;

The plurality of test pins 120 further include a third test pin 123 and a fourth test pin 124, the third test pin 123 is electrically connected to the first digital signal line 151, and the fourth test pin 124 is electrically connected to the second digital signal line 152; The first digital signal line 151 and the second digital signal line 152 are disposed on the digital PCB board 132 , and the first radio frequency signal line 141 and the second radio frequency signal line 142 are disposed on the radio frequency PCB board 131 .

Specifically, the test seat housing 170 and the pedestal 110 may be separate structures, and the test seat housing 170 and the pedestal 110 may be connected and fixed through a connection structure; the test seat housing 170 and the pedestal 110 may be an integral structure, that is, no need Other connecting structures are connected and fixed.

Referring to FIG. 5 , in this embodiment, the digital PCB board 132 and the RF PCB board 131 are different boards, wherein the digital signal lines (including the first digital signal line 151 and the second digital signal line 152 ) are arranged on the digital PCB board 132 , so the digital signal can be transmitted through the digital signal line on the digital PCB board 132 . The radio frequency signal lines (including the first radio frequency signal line 141 and the second radio frequency signal line 142 ) are disposed on the radio frequency PCB board 131 , and high frequency signals can be transmitted through the radio frequency signal lines on the radio frequency PCB board 131 .

It should be noted that, in this embodiment, the electrical connection between the third test pin 123 and the first digital signal line 151 may be a direct electrical connection or an indirect electrical connection; the fourth test pin 124 and the second digital signal line 152 The electrical connection may be a direct electrical connection or an indirect electrical connection.

Referring to FIG. 5 , optionally, the radio frequency PCB board 131 may include two parts, specifically a first radio frequency PCB board provided with a first radio frequency signal line 141 and a second radio frequency PCB board provided with a second radio frequency signal line 142 , wherein , the first RF PCB board extends from under the first test pin 121 to the first RF connector 210 , and the second RF PCB board extends from under the second test pin 122 to the second RF connector 220 .

FIG. 7 is a cross-sectional view of a chip testing device provided by an embodiment of the present invention. FIG. 7 can be a cross-sectional view obtained by cutting along BB' corresponding to FIG. 6 , and FIG. 8 is a partial enlarged view of FIG. , optionally, the chip testing device further includes an elastic support structure 180;

The test seat housing 170 includes a third via hole 103. In the thickness direction y of the chip testing device, the third via hole 103 corresponds to the first via hole 101 one-to-one. The two test needles 122 are located in the third via hole 103 corresponding to the first via hole 101 .

Optionally, the elastic support structure 180 may be an elastic structure such as a spring, a gel, etc., and the RF PCB board 131 itself may have elasticity. During chip testing, after placing the chip to be tested into the recessed structure 111 of the lead frame 110, the chip to be tested can be pressed. An elastic support structure 180 is provided in the via hole 103 , so that after pressing the chip to be tested, the chip to be tested can be in reliable contact with the first test needle 121 and the second test needle 122 , and then the first test needle 121 and the second test needle 122 Reliability of transmitting high frequency signals.

6-8, the RF PCB board 130 includes a first RF PCB board 1311 and a second RF PCB board 1312, between the lead frame 110 and the test seat housing 170, the first RF PCB board 1311 and the second RF PCB board 1311 There is a distance between the PCB board 1312; the third and fourth test pins are conductive pogo pins 190, and the test seat housing 170 includes a third via hole 103. In the thickness direction y of the chip testing device, the third via hole 103 is connected to the first via hole 103. The vias 101 are in one-to-one correspondence, the conductive pogo pins 190 pass through the third vias 103 and the first vias 101 corresponding to the third vias 103 , and the conductive pogo pins 190 are located on the first RF PCB board 1311 and the second RF PCB board Between 1312 between.

Specifically, the RF PCB 131 is not provided between the third test needle 123 and the test seat housing 170 and between the fourth test needle 124 and the test seat housing 170, and the conductive pogo pins 190 can directly pass through the test seat housing The third via hole 103 of 160 and the first via hole 101 corresponding to the third via hole 103, the third test needle and the third test needle protrude from the recessed structure 111 of the lead frame 110, and can be used to measure digital signals. During chip testing, after placing the chip to be tested into the recessed structure 111 of the lead frame 110, press the chip to be tested, because the conductive spring pin 190 itself has elasticity, so that after pressing the chip to be tested, the chip to be tested can be connected with the third test needle. 123 and the fourth test needle head 124 are in reliable contact, thereby ensuring the reliability of the digital signal transmission by the third test needle head 123 and the fourth test needle head 124 .

It should be noted that, in order to clearly show the structure of the conductive pogo pins 190 , only a part of the structure of the chip testing device is shown in FIG. 8 .

Wherein, for the chip testing device shown in FIGS. 6-8 , the heights of the third test needle and the fourth test needle are higher than the heights of the first test needle and the second test needle.

FIG. 9 is a schematic structural diagram of a test needle provided by an embodiment of the present invention. FIG. 9 may represent the structures of a first test needle and a second test needle. Referring to FIG. 9 , optionally, the first test needle and the second test needle It includes a needle tip portion 1201, a needle body portion 1202 and a fixing portion 1203, wherein the needle body portion 1202 is located between the needle tip portion 1201 and the fixing portion 1203, and the side of the needle tip portion 1201 away from the needle body portion 1202 includes a groove, and the needle tip portion 1201 uses in contact with the chip to be tested;

The needle body part 1202 and the fixing part 1203 are cylindrical, and the needle body part 1202 is located in the first via hole 101 , the fixing part 1203 is located on the side of the lead frame close to the RF PCB board, and the diameter of the fixing part 1203 is larger than that of the first via hole 101 diameter;

Optionally, the diameter of the needle body portion is greater than or equal to 0.01 mm and less than or equal to 1 mm; the diameter of the fixing portion is greater than or equal to 0.01 mm and less than or equal to 1.5 mm.

Optionally, the test needle 120 shown in FIG. 9 may be applicable to the chip under test of LGA (Land Grid Array, grid array package), BGA (Ball Grid Array Package, ball grid array package). Specifically, for the LGA and BGA chips to be tested, the pad surface of the bottom surface of the chip to be tested is usually a convex spherical shape. The tip 1201 of the test needle 120 shown in FIG. 9 has a groove, and the chip to be tested is convex during testing. The outgoing spherical pad can be fitted into the groove of the needle tip portion 1201 . Optionally, the groove of the needle tip portion 1201 may be crown-shaped as shown in FIG. 9 . When installing the test needle 120 , the guide frame 110 can be inverted, and then the test needle 120 can be pushed through the first through hole 101 of the recessed structure 111 by pressing the test needle 120 . The diameter is equal to the diameter of the first via hole 101 , so that the test needle 120 and the sidewall of the first via hole 101 can contact each other and have a force, so that the test needle 120 will not fall out of the first via hole 101 . After installation, the fixing portion 1203 is located on the side of the lead frame 110 close to the PCB board 130 , so that the test needles 120 will not drop from the surface of the lead frame 110 with the concave structure 111 .

On the basis of the above embodiments, in conjunction with FIG. 2 and FIG. 9 , optionally, the height h of the test needle 120 is greater than or equal to 0.01 mm and less than or equal to 3 mm, so that the height of the test needle 120 is smaller, correspondingly , so that the parasitic parameters such as resistance, capacitance and inductance of the test needle 120 are smaller, so that the loss of the test needle 120 when transmitting signals is smaller, which is more conducive to improving the transmission accuracy of high-frequency signals and reducing the transmission of high-frequency signals. Transmission distortion. Preferably, the height h of the test needle 120 is greater than or equal to 0.2 mm and less than or equal to 3 mm.

Continuing to refer to FIG. 5 , optionally, the lead frame 110 and/or the test seat housing 170 further includes a fourth via hole 104 , and the digital PCB board 132 is provided with a fifth via hole 105 . In the thickness direction of the chip testing device, The fifth via hole 105 corresponds to the fourth via hole 104 one-to-one; the chip testing device further includes a fixing structure 201 , the fixing structure 201 is penetrated in the fourth via hole 104 and the fifth via hole 105 for connecting the test socket with the digital The PCB board 132 is fixed;

The pedestal 110 and/or the test seat housing 170 further includes a sixth via hole 106, and the RF PCB board 131 and the digital PCB board 132 are provided with a seventh via hole 107. In the thickness direction of the chip testing device, the seventh via hole 107 is formed. The vias 107 are in one-to-one correspondence with the sixth vias 106 ; the chip testing device further includes a positioning structure 202 , and the positioning structure 202 penetrates the sixth vias 106 and the seventh vias 107 for aligning the test seat and the RF PCB board. 131 for positioning, or for positioning the test socket and the digital PCB board 132 .

Specifically, when assembling the chip testing device, the test socket pair on which the test pins 120 and the grounding copper block 160 are installed can be first aligned with the seventh via hole 107 through the sixth via hole 106 , and the sixth via hole 106 and the seventh via hole 107 are aligned. A positioning structure 202 such as a positioning pin is inserted into the seventh via hole 107 . Then, the fixing structure 201 is inserted into the fourth via hole 104 and the fifth via hole 105 , wherein the fixing structure 201 can be a screw, which is installed and locked on the test seat PCB board 130 by the screw. During chip testing, the concave structure 111 of the lead frame 110 can limit the position of the chip. When the chip to be tested is placed in the concave structure 111 , the chip to be tested can be placed in the concave structure 111 according to the pin 1 position. The pin1 corner may be a setting pin of the chip to be tested, and placing the chip to be tested into the concave structure 111 according to the position of the set pin can ensure that the relative position of the chip to be tested and each test needle 120 is accurate.

Note that the above are only preferred embodiments of the present invention and applied technical principles. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and various obvious changes, readjustments and substitutions can be made by those skilled in the art without departing from the protection scope of the present invention. Therefore, although the present invention has been described in detail through the above embodiments, the present invention is not limited to the above embodiments, and can also include more other equivalent embodiments without departing from the concept of the present invention. The scope is determined by the scope of the appended claims.

Claims (13)

1. A chip testing device, characterized in that, comprising: a guide frame, a plurality of test needles, a PCB board, and the guide frame is arranged on one side of the PCB board; The surface of the lead frame away from the PCB board includes a concave structure, and the concave structure is used to place the chip to be tested; the bottom surface of the concave structure includes a plurality of first via holes, and the test needle is detachably fixed and penetrated in the first via; The plurality of test needles include a first test needle and a second test needle, the first test needle is electrically connected to the first radio frequency signal line on the PCB board, and the second test needle is connected to the PCB board. is electrically connected to the second radio frequency signal line. 2 . The chip testing device according to claim 1 , wherein the plurality of test needles further comprises a third test needle and a fourth test needle, and the third test needle is connected to the first number on the PCB board. 3 . The signal line is electrically connected, the fourth test pin is electrically connected with the second digital signal line on the PCB board, the first radio frequency signal line, the second radio frequency signal line, the first digital signal line, The second digital signal lines are arranged on the same PCB board. 3 . The chip testing device according to claim 2 , wherein the test needle head comprises a needle tip portion, a needle body portion and a fixing portion, wherein the needle body portion is located between the needle tip portion and the fixing portion. 4 . , the shape of the tip portion is conical, and the tip portion is used to contact the chip to be tested; The needle body part and the fixing part are cylindrical, the needle body part is located in the first via hole, the fixing part is located on the side of the lead frame close to the PCB board, and the The diameter of the fixing portion is larger than the diameter of the first via hole; Preferably, the diameter of the needle body portion is greater than or equal to 0.01 mm and less than or equal to 1 mm; the diameter of the fixing portion is greater than or equal to 0.01 mm and less than or equal to 1.5 mm. 4 . The chip testing device according to claim 3 , further comprising a ground copper block, the ground copper block is disposed on the bottom surface of the recessed structure, and the area of the grounded copper block is smaller than that of the recessed structure. 5 . The ground copper block includes a plurality of second via holes, and the plurality of test needles further includes a fifth test needle, and the fifth test needle penetrates through the second through holes; Wherein, the bottom surface of the recessed structure includes a center area and an edge area surrounding the center area, wherein the ground copper block is located in the center area, the first test needle, the second test needle, the third test needle A needle and the fourth test needle are located in the edge region. 5 . The chip testing device according to claim 2 , further comprising a test seat housing, the test seat housing and the lead frame are arranged on the same side of the PCB board, and the test seat The shell is located around the pedestal frame, the test seat shell and the pedestal frame constitute a test seat, the test seat shell is fixedly connected with the pedestal frame, or the test seat shell and the pedestal frame are fixedly connected. Box as one structure. 6 . The chip testing device according to claim 1 , wherein the PCB board is a radio frequency PCB board, and the chip testing device further comprises a digital PCB board and a test seat housing; the test seat housing and the The pedestal frame constitutes a test seat, and the test seat shell is fixedly connected to the pedestal frame, or the test seat shell and the pedestal frame are integrally structured; The test seat housing is arranged on one side of the digital PCB board, the guide frame is arranged on the side of the test seat away from the digital PCB board, and the guide frame is arranged on the side away from the digital PCB board The surface of the device includes the recessed structure; the RF PCB board is partially disposed between the lead frame and the test seat; at the recessed structure, the first via hole penetrates the lead frame; The plurality of test needles further include a third test needle and a fourth test needle, the third test needle is electrically connected to the first digital signal line, and the fourth test needle is electrically connected to the second digital signal line; the third test needle is electrically connected to the second digital signal line; A digital signal line and the second digital signal line are disposed on the digital PCB board, and the first radio frequency signal line and the second radio frequency signal line are disposed on the radio frequency PCB board. 7. The chip testing device according to claim 6, further comprising an elastic support structure; The test seat housing includes a third via hole, and in the thickness direction of the chip testing device, the third via hole corresponds to the first via hole one-to-one, and the elastic support structure is arranged at the same position as the first via hole. A test needle and the second test needle are located in the third via hole corresponding to the first via hole. 8. The chip testing device according to claim 6, wherein the radio frequency PCB board comprises a first radio frequency PCB board and a second radio frequency PCB board, and between the lead frame and the test seat housing, There is a distance between the first RF PCB board and the second RF PCB board; The third test needle and the fourth test needle are conductive pogo pins, the test seat housing includes a third via hole, and in the thickness direction of the chip testing device, the third via hole is connected to the first via hole. One via hole corresponds to each other, the conductive pogo pin penetrates the third via hole and the first via hole corresponding to the third via hole, and the conductive pogo pin is located between the first RF PCB board and the first via hole. between the second RF PCB board. 9 . The chip testing device according to claim 6 , wherein the first test needle head and the second test needle head each comprise a needle tip portion, a needle body portion and a fixing portion, wherein the needle body portion is located at the Between the needle tip portion and the fixing portion, a side of the needle tip portion away from the needle body portion includes a groove, and the needle tip portion is used for contacting the chip to be tested; The needle body part and the fixing part are cylindrical, and the needle body part is located in the first via hole, the fixing part is located on the side of the lead frame close to the RF PCB board, and the The diameter of the fixing portion is larger than the diameter of the first via hole; Preferably, the diameter of the needle body portion is greater than or equal to 0.01 mm and less than or equal to 1 mm; the diameter of the fixing portion is greater than or equal to 0.01 mm and less than or equal to 1.5 mm. 10 . The chip testing device according to claim 1 , wherein the height of the test needle is greater than or equal to 0.01 mm and less than or equal to 3 mm. 11 . 11 . The chip testing device according to claim 5 , wherein the lead frame and/or the test seat housing further comprises a fourth via hole, the PCB board is provided with a fifth via hole, and the In the thickness direction of the chip testing device, the fifth via hole corresponds to the fourth via hole one-to-one; the chip testing device further includes a fixing structure, and the fixing structure penetrates the fourth via hole and the fourth via hole. The fifth via hole is used to fix the test seat and the PCB board; The lead frame and/or the test seat housing further includes a sixth via hole, and a seventh via hole is provided on the PCB board. In the thickness direction of the chip testing device, the seventh via hole is the same as the The sixth via holes are in one-to-one correspondence; the chip testing device further includes a positioning structure, the positioning structure is penetrated in the sixth via hole and the seventh via hole, and is used for aligning the test seat and the PCB board for positioning. 12 . The chip testing device according to claim 6 , wherein the lead frame and/or the test seat housing further comprises a fourth via hole, and the digital PCB board is provided with a fifth via hole. In the thickness direction of the chip testing device, the fifth via hole corresponds to the fourth via hole one-to-one; the chip testing device further includes a fixing structure, and the fixing structure penetrates the fourth via hole and the fourth via hole. The fifth via hole is used to fix the test seat and the digital PCB board; The pedestal and/or the test seat housing further includes a sixth via hole, and both the RF PCB board and the digital PCB board are provided with a seventh via hole. In the thickness direction of the chip testing device, the The seventh via hole is in one-to-one correspondence with the sixth via hole; the chip testing device further includes a positioning structure, and the positioning structure is penetrated in the sixth via hole and the seventh via hole, and is used for Position the test socket and the PCB board. 13. The chip testing device according to any one of claims 1-12, further comprising a first radio frequency connector and a second radio frequency connector, the first radio frequency connector being connected to the first radio frequency signal The wire is electrically connected, and the second radio frequency connector is electrically connected to the second radio frequency signal wire.

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