TWI856602B - Universal memory for in-memory computing and operation method thereof - Google Patents

Abstract

A universal memory for in-memory computing and an operation method thereof are provided. The universal memory includes at least one write word line, at least one unit cell and at least one read word line. The unit cell includes a write transistor and a read transistor. The gate of the write transistor is connected to the write word line. The write transistor is a transistor with adjustable threshold voltage. The gate of the read transistor is connected to the drain or the source of the write transistor. The read word line is connected to the drain or the source of the read transistor. The universal memory is used for a training mode and an inference mode. In the training mode and the inference mode, a weight is stored at different locations of the unit cell.

Description

General purpose memory suitable for in-memory operations and its operation method

This disclosure relates to a memory and an operating method thereof, and in particular to a general purpose memory suitable for in-memory operations and an operating method thereof.

In the operation of artificial intelligence models, a large amount of data needs to be moved between the memory and the processor, forming a Von-Neumann bottleneck. In order to improve the efficiency of the operation, an in-memory operation architecture is proposed.

The operation of artificial intelligence models includes training mode and inference mode. In the training mode, the memory needs to be repeatedly programmed and erased to change the weight value, and a memory with higher endurance is required. In the inference mode, the weight value needs to be maintained for inference calculation, and a memory with higher retention is required.

However, high-reliability memory and high-retention memory are usually different types of memory. In traditional memory technology, it is difficult to find a memory that can have both high reliability and high retention, and no memory can be used for both the training mode and the inference mode of artificial intelligence computing.

This disclosure is about a universal memory suitable for in-memory computing and its operation method, which uses a 2T structure to make the universal memory suitable for training mode and inference mode of artificial intelligence. In the training mode and inference mode, the weight value is stored in different places of the unit memory cell. When the universal memory is executed in the training mode, it can provide high reliability like dynamic random access memory (DRAM) to meet a large number of weight value update actions; when the universal memory is executed in the inference mode, it can provide non-volatility and high retention like non-volatile memory, so that the weight value can be maintained well under low power consumption.

According to one aspect of the present disclosure, a universal memory suitable for in-memory computing (IMC) is proposed. The universal memory includes at least one write word line, at least one unit memory cell and at least one read word line. The unit memory cell includes a write transistor and a read transistor. The gate of the write transistor is connected to the write word line. The write transistor is a critical voltage adjustable transistor. The gate of the read transistor is connected to the drain or source of the write transistor. The read word line is connected to the drain or source of the read transistor. In a training mode, a storage potential at a storage node between a write transistor and a read transistor represents a weight value of a unit memory cell. In an inference mode, a critical voltage of the write transistor represents the weight value of a unit memory cell.

According to another aspect of the present disclosure, a method for operating a universal memory suitable for in-memory calculations is proposed. The universal memory includes at least one unit memory cell, and the unit memory cell includes a write transistor and a read transistor. The gate of the read transistor is connected to the drain or source of the write transistor. The method for operating the universal memory includes the following steps. A weight change procedure of a training mode is performed. In the weight change procedure of the training mode, a storage node between the write transistor and the read transistor is charged or discharged to a storage potential. The storage potential of the storage node represents a weight value (weight) of the unit memory cell. A weight setting procedure of an inference mode is performed. In the weight setting process of the inference mode, the write transistor is programmed or erased to change a critical voltage of the write transistor. The critical voltage of the write transistor represents the weight value of the unit memory cell.

According to another aspect of the present disclosure, a universal memory suitable for in-memory operations is provided. The universal memory includes at least one write word line, at least one unit memory cell and at least one read word line. The unit memory cell includes a write transistor and a read transistor. The gate of the write transistor is connected to the write word line. The write transistor is a critical voltage adjustable transistor. The gate of the read transistor is connected to the drain or source of the write transistor. The read word line is connected to the drain or source of the read transistor. The universal memory is common to a training mode and an inference mode. In training mode and inference mode, a weight value is stored in different locations of the unit memory cell.

In order to better understand the above and other aspects of this disclosure, the following is a specific example, and the attached drawings are used to explain in detail as follows:

200,300,400: memory

210,220,230,240,310ij,410ij,510: unit memory cell

211,221,231,241:Resistance

311ij: variable resistor

411ij: Fixed resistor

500: General memory

511: Write to transistor

512: Read transistors

a: output value

b: offset

BL2: Bit line

CV110,CV111:Characteristic curve

CVi: Curve

f: activation function

FG: Charge storage layer

G1,G2,G3,G4,Gij: Conductivity

I1,I2,I3,I4,Ii: read current

I: Total current

M1: Training mode

M2: Inference mode

ND: Node

P11: Weight change procedure

P12, P22: Weight retention procedure

P13, P23: Reading operation program

P20: Pre-discharge procedure

P21: Weight setting procedure

RBL: Read Bit Line

RWL: Read character line

SN: Storage Node

V1,V2,V3,V4: voltage

VSN0, VSN1, VSN1i: storage potential

VtR, VtW, VtW0, VtW1, VtW1i: critical voltage

Vpass: conduction bias

VWWL, VWWL0, VWWL1, VWBL0, VWBL1: Bias voltage

WBL: Write Bit Line

W1,Wi,Wij,WN: weight value

WL2: character line

WWL: Write Character Line

X1,Xi,XN: input signal

z: operation value

Figure 1 shows a schematic diagram of a node of an artificial intelligence model according to an embodiment.

Figure 2 shows the memory for performing product and sum operations.

FIG. 3 illustrates a memory used to perform training according to one embodiment.

FIG. 4 illustrates a memory used to perform inference according to one embodiment.

FIG. 5 shows a unit memory cell suitable for in-memory computing (IMC) according to an embodiment.

FIG. 6 illustrates a general purpose memory according to one embodiment.

Figure 7 shows a flow chart of the operation method of the general memory.

Figure 8 shows a characteristic curve of a write transistor in a training mode according to an embodiment.

FIG. 9 shows a characteristic curve of a read transistor in a training mode according to an embodiment.

Figure 10A shows an example of writing a weight value of "0" into a unit memory cell during the weight change process in the training mode.

Figure 10B illustrates the weight maintenance process of a unit memory cell in training mode.

Figure 10C illustrates the reading operation process of a unit memory cell in training mode.

Figure 11A shows an example of writing a weight value of "1" into a unit memory cell during the weight change process in the training mode.

Figure 11B illustrates the weight maintenance process of a unit memory cell in training mode.

Figure 11C illustrates the reading operation process of a unit memory cell in training mode.

Figure 12 shows a characteristic curve of a write transistor in an inference mode according to an embodiment.

FIG. 13 shows a characteristic curve diagram of a read transistor in an inference mode according to an embodiment.

Figure 14A shows an example of writing a weight value of "0" to a unit memory cell during the weight setting process in the inference mode.

Figure 14B illustrates the weight maintenance process of a unit memory cell in the inference mode.

Figure 14C illustrates the reading operation process of a unit memory cell in the inference mode.

Figure 15A shows an example of writing a weight value of "1" into a unit memory cell during the weight setting process in the inference mode.

Figure 15B illustrates the weight maintenance process of a unit memory cell in the inference mode.

Figure 15C illustrates the reading operation process of a unit memory cell in the inference mode.

Figure 16 shows the relationship between the current and voltage of the read bit line.

Figure 17 shows an example of stored potential.

Figure 18 illustrates an example of the critical voltage written into a transistor.

Figure 19 shows the voltage curves of the pre-discharge process and the read operation process in the inference mode.

Figure 20 shows a characteristic curve of a write transistor in an inference mode according to an embodiment.

Figure 21 shows an example of the pre-discharge procedure.

Please refer to Figure 1, which shows a schematic diagram of a node ND of an artificial intelligence model according to an embodiment. After the node ND receives several input signals Xi, these input signals Xi and weight values (weight) Wi are multiplied and calculated (multiply-accumulate, MAC) and offset b is added to obtain an operation value z. The operation value z is calculated by the activation function (activation function) f to obtain the output value a. The output value a will be input to the node of the next layer.

From FIG. 1, it can be seen that the product-sum operation is a very important operation in artificial intelligence operations. Please refer to FIG. 2, which shows a memory 200 that performs a product-sum operation. The memory 200 includes, for example, a plurality of unit memory cells 210, 220, 230, 240. Each unit memory cell 210, 220, 230, 240 includes, for example, a resistor 211, 221, 231, 241. The resistors 211, 221, 231, 241 have conductivities G1, G2, G3, G4, respectively. When the voltages V1, V2, V3, V4 are respectively input to the bit line BL2, read currents I1, I2, I3, I4 are respectively formed on the word line WL2. The read current I1 is equal to the product of the voltage V1 and the conductance G1; the read current I2 is equal to the product of the voltage V2 and the conductance G2; the read current I3 is equal to the product of the voltage V3 and the conductance G3; the read current I4 is equal to the product of the voltage V4 and the conductance G4. The total current I is equal to the product of the voltage V1, V2, V3, V4 and the conductance G1, G2, G3, G4. If the voltage V1, V2, V3, V4 represents the input signal Xi, and the conductance G1, G2, G3, G4 represents the weight value Wi, then as described in the following formula (1), the total current I represents the product of the input signal Xi and the weight value Wi. The memory 200 in Figure 2 can be used to implement the product and sum operations in artificial intelligence operations.

I=Σ _i ( W _i * X _i )=Σ _i ( G _i * V _i )........................ .............(1)

Please refer to Figure 3, which shows a memory 300 for executing a training mode (training) according to an embodiment. The memory 300 includes, for example, unit memory cells 310ij arranged in a matrix. Each unit memory cell 310ij has, for example, a variable resistor 311ij. The variable resistor 311ij has a conductance Gij. These conductances Gij represent weight values Wij. In the process of executing the training mode, the weight values Wij need to be continuously updated, so the memory 300 using the variable resistor 311ij can smoothly execute the training mode.

Please refer to Figure 4, which shows a memory 400 for executing an inference mode according to an embodiment. The memory 400 includes, for example, unit memory cells 410ij arranged in a matrix. Each unit memory cell 410ij has, for example, a fixed resistor 411ij. The fixed resistor 411ij has a conductance Gij. These conductances Gij represent weight values Wij. In the process of executing the inference mode, the weight values Wij have already been set and should not be changed at will, so the memory 400 using the fixed resistor 411ij can smoothly execute the inference mode.

The requirements of training mode and inference mode are different. For example, the memory running in training mode needs to have higher reliability (endurance) to meet a large number of weight value Wi update actions; the memory running in inference mode needs to have non-volatility (non-volatility) and higher retention (retention) so that the weight value Wi can be maintained well under low power consumption. Generally speaking, these two types of memory are completely different. For example, the memory 300 in Figure 3 and the memory 400 in Figure 4 use completely different variable resistors 311ij and fixed resistors 411ij.

Please refer to Figure 5, which shows a unit memory cell 510 suitable for in-memory computing (IMC) according to an embodiment. In-Memory Computing is also called Computing In-Memory, Processing In-Memory (PIM), or In-Memory Processing. The unit memory cell 510 includes a write transistor 511 and a read transistor 512. Since the unit memory cell 510 is composed of two transistors, it is also called a 2T structure. The write transistor 511 is a critical voltage adjustable transistor. The gate of the write transistor 511 has a charge storage layer FG. The gate of the read transistor 512 is connected to the drain or source of the write transistor 511.

The write transistor 511 needs to have a lower off-current to ensure good data retention, and the material of its channel layer is, for example, indium gallium zinc oxide (IGZO), indium oxide (In2O3), silicon (Si), germanium (Ge), or trivalent-pentavalent materials. The read transistor 512 needs to have a higher on-current to ensure reading accuracy, and the material of its channel layer is, for example, indium gallium zinc oxide (IGZO), indium oxide (In2O3), silicon (Si), germanium (Ge), or trivalent-pentavalent materials.

Please refer to FIG. 6, which shows a universal memory 500 according to an embodiment. The universal memory 500 includes unit memory cells 510 arranged in a matrix. The universal memory 500 includes one or more write word lines WWL, one or more read word lines RWL, one or more write bit lines WBL, one or more read bit lines RBL and a plurality of unit memory cells 510. The gate of the write transistor 511 is connected to the write word line WWL, one of the drain and the source of the write transistor 511 is connected to the write bit line WBL, and the other of the drain and the source of the write transistor 511 is connected to the gate of the read transistor 512. The gate of the read transistor 512 is connected to the drain or source of the write transistor 511, one of the drain and source of the read transistor 512 is connected to the read bit line RBL, and the other of the drain and source of the read transistor 512 is connected to the read word line RWL.

In this embodiment, the general purpose memory 500 is applicable to the training mode and the inference mode of artificial intelligence. That is to say, when the general purpose memory 500 is executed in the training mode, it can provide the high reliability of dynamic random access memory (DRAM) to meet the large number of weight value Wi update actions; when the general purpose memory 500 is executed in the inference mode, it can provide the non-volatility and high retention of non-volatile memory, so that the weight value Wi can be maintained well under low power consumption. The following describes the operation of the training mode and the inference mode of the general purpose memory 500 respectively.

Please refer to Figure 7, which shows a flow chart of the operation method of the general memory 500. The general memory 500 is applicable to both the training mode M1 and the inference mode M2 of artificial intelligence. The training mode M1 includes a weight change program P11, a weight retention program P12, and a read operation program P13. The weight change program P11 is used to change the weight value Wi; the weight retention program P12 is used to temporarily retain the weight value Wi; the read operation program P13 is used to read the weight value Wi and perform a multiplication operation at the same time. In the training mode M1, the weight change program P11, the weight retention program P12, and the read operation program P13 are repeatedly executed to optimize the artificial intelligence model by continuously adjusting the weight value Wi.

The inference mode M2 includes a weight setting program P21, a weight holding program P22 and a reading operation program P23. The weight setting program P21 is used to set the weight value Wi; the weight holding program P22 is used to hold the weight value Wi; the reading operation program P23 is used to read the weight value Wi and perform a multiplication operation at the same time. In the inference mode M2, the weight value Wi will not change frequently.

The operation of the training mode M1 is first described below. Please refer to Figure 8, which shows a characteristic curve of the write transistor 511 in the training mode M1 according to an embodiment. In the training mode M1, the charge storage layer FG of the write transistor 511 will not be changed, so the characteristic curve will not change. When a higher bias voltage VWWL1 is applied to the gate of the write transistor 511, the write transistor 511 can be turned on; when a lower bias voltage VWWL0 is applied to the gate of the write transistor 511, the write transistor 511 can be turned off.

Please refer to Figure 9, which shows a characteristic curve of the read transistor 512 in the training mode M1 according to an embodiment. In the training mode M1, when the gate of the read transistor 512 has a higher storage potential VSN1, the read transistor 512 can be turned on; when the gate of the read transistor 512 has a lower storage potential VSN0, the read transistor 512 can be turned off.

Please refer to Figure 10A, which illustrates an example of writing a weight value Wi of "0" to the unit memory cell 510 in the weight change procedure P11 of the training mode M1. In the training mode M1, the weight value Wi is stored in the storage node SN between the write transistor 511 and the read transistor 512.

When the unit memory cell 510 wants to write a weight value Wi of "0" in the weight change procedure P11 of the training mode M1, a higher bias voltage VWWL1 (e.g., 3V) is applied to the write word line WWL to turn on the write transistor 511; a lower bias voltage VWBL0 (e.g., 0V) is applied to the write bit line WBL.

Since the write transistor 511 is turned on, the bias voltage VWBL0 inputted from the write bit line WBL can be inputted to the storage node SN, so that the storage node SN has a storage potential VSN0 (e.g., 0V) lower than the critical voltage VtR of the read transistor 512. The storage potential VSN0 of the storage node SN can represent the weight value Wi of "0" of the unit memory cell 510.

Please refer to Figure 10B, which illustrates the weight maintenance procedure P12 of the unit memory cell 510 in the training mode M1. When the unit memory cell 510 wants to temporarily maintain the weight value Wi in the training mode M1, a lower bias voltage VWWL0 (for example, 0V) is applied to the write word line WWL to turn off the write transistor 511.

Since the write transistor 511 is turned off, the storage potential VSN0 of the storage node SN will not change.

Please refer to Figure 10C, which illustrates the example of the read operation procedure P13 of the unit memory cell 510 in the training mode M1. When the weight value Wi of the unit memory cell 510 is to be read and the multiplication operation is performed at the same time, a lower bias voltage VWWL0 (for example, 0V) is applied to the write word line WWL to turn off the write transistor 511; the input signal Xi (for example, 0.8V) is applied to the read bit line RBL.

Since the storage potential VSN0 is lower than the critical voltage VtR of the read transistor 512, the read transistor 512 is turned off and no read current Ii is generated in the read bit line RBL. The read current Ii is 0, which is equivalent to the product of the input signal Xi and the weight value Wi of "0".

Please refer to Figure 11A, which illustrates an example of writing a weight value Wi of "1" to the unit memory cell 510 in the weight change procedure P11 of the training mode M1. In the training mode M1, the weight value Wi is stored in the storage node SN between the write transistor 511 and the read transistor 512.

When the unit memory cell 510 wants to write a weight value Wi of "1" in the weight change procedure P11 of the training mode M1, a higher bias voltage VWWL1 (for example, 3V) is applied to the write word line WWL to turn on the write transistor 511; a higher bias voltage VWBL1 (for example, 1V) is applied to the write bit line WBL.

Since the write transistor 511 is already turned on, the bias voltage VWBL1 inputted from the write bit line WBL can be inputted to the storage node SN, so that the storage node SN has a storage potential VSN1 (e.g., 1V) higher than the critical voltage VtR of the read transistor 512. The storage potential VSN1 of the storage node SN can represent the weight value Wi of "1" of the unit memory cell 510. As described above, in the weight change procedure P11 of the training mode M1, when the weight value Wi changes, the critical voltage VtW of the write transistor 511 remains fixed.

Please refer to Figure 11B, which illustrates the weight maintenance procedure P12 of the unit memory cell 510 in the training mode M1. When the unit memory cell 510 wants to temporarily maintain the weight value Wi in the training mode M1, a lower bias voltage VWWL0 (for example, 0V) is applied to the write word line WWL to turn off the write transistor 511.

Since the write transistor 511 is turned off, the storage potential VSN1 of the storage node SN will not be lost.

Please refer to Figure 11C, which illustrates the example of the read operation procedure P13 of the unit memory cell 510 in the training mode M1. In the read operation procedure P13 of the training mode M1, the weight value Wi is fixed. When the weight value Wi of the unit memory cell 510 is to be read and the multiplication operation is performed at the same time, the write word line WWL is applied with a lower bias voltage VWWL0 (for example, 0V) to turn off the write transistor 511; the read bit line RBL is applied with an input signal Xi (for example, 0.8V).

Since the storage potential VSN1 is higher than the critical voltage VtR of the read transistor 512, the read transistor 512 will be turned on and a read current Ii will be generated on the read bit line RBL. The read current Ii is equal to the product of the input signal Xi and the weight value Wi of "1".

The operation examples of Figures 10A to 11C above can be summarized in Table 1 below, but Table 1 is only an example value and is not intended to limit the present invention.

The following continues to explain the inference mode M2. Please refer to FIG. 12, which shows a characteristic curve diagram of the write transistor 511 in the inference mode M2 according to an embodiment. In the inference mode M2, the charge storage layer FG of the write transistor 511 can be set to two charge amounts, so the write transistor 511 has two characteristic curves CV110 and CV111. When a predetermined bias voltage VWWL is applied to the gate of the write transistor 511, if the write transistor 511 has a higher critical voltage VtW0 (as shown by the characteristic curve CV110), the write transistor 511 will be turned off; if the write transistor 511 has a lower critical voltage VtW1 (as shown by the characteristic curve CV111), the write transistor 511 will be turned on.

Please refer to FIG. 13, which shows a characteristic curve diagram of the read transistor 512 in the inference mode M2 according to an embodiment. In the inference mode M2, when the gate of the read transistor 512 has a higher storage potential VSN1, the read transistor 512 can be turned on; when the gate of the read transistor 512 has a lower storage potential VSN0, the read transistor 512 can be turned off.

Please refer to FIG. 14A, which illustrates an example of writing a weight value Wi of "0" into a unit memory cell 510 in the weight setting procedure P21 of the inference mode M2. The write transistor 511 is a critical voltage adjustable transistor. The gate of the write transistor 511 has a charge storage layer FG. In the inference mode M2, the critical voltage VtW0 of the write transistor 511 represents the weight value Wi of "0". The amount of charge stored in the charge storage layer can usually be modified using Fowler-Nordheim tunneling and hot carrier injection mechanisms (+FN/-FN) so that the write transistor 511 has a higher critical voltage VtW0 or a lower critical voltage VtW1 (shown in Figures 15A to 15C).

When the unit memory cell 510 wants to write a weight value Wi of "0" in the weight setting procedure P21 of the inference mode M2, the -FN mechanism is executed through the write word line WWL to make the write transistor 511 have a higher critical voltage VtW0.

Please refer to Figure 14B, which illustrates the weight maintenance process P22 of the unit memory cell 510 in the inference mode M2. When the unit memory cell 510 wants to maintain the weight value Wi in the inference mode M2, a lower bias voltage VWWL0 (for example, 0V) is applied to the write word line WWL to turn off the write transistor 511.

Please refer to FIG. 14C , which illustrates the read operation procedure P23 of the unit memory cell 510 in the inference mode M2. When the weight value Wi of the unit memory cell 510 is to be read and the multiplication operation is performed at the same time, the write word line WWL is applied with a predetermined bias voltage VWWL (between the critical voltage VtW1 and the critical voltage VtW0); the write bit line WBL is applied with a higher bias voltage VWBL1 (higher than the critical voltage VtR of the read transistor 512). The bias voltage VWWL is lower than the critical voltage VtW0, and the write transistor 511 cannot be turned on. Therefore, the bias voltage VWBL1 cannot reach the read transistor 512, so the read transistor 512 will be turned off and no read current Ii will be generated on the read bit line RBL. The read current Ii is 0, which is equivalent to the product of the input signal Xi and the weight value Wi of "0".

Please refer to Figure 15A, which illustrates an example of writing a weight value Wi of "1" to the unit memory cell 510 in the weight setting procedure P21 of the inference mode M2. When the unit memory cell 510 is to write a weight value Wi of "1" in the weight setting procedure P21 of the inference mode M2, the +FN mechanism is executed through the write word line WWL so that the write transistor 511 has a lower critical voltage VtW1.

Please refer to Figure 15B, which illustrates the weight maintenance process P22 of the unit memory cell 510 in the inference mode M2. When the unit memory cell 510 wants to maintain the weight value Wi in the inference mode M2, a lower bias voltage VWWL0 (for example, 0V) is applied to the write word line WWL to turn off the write transistor 511.

Please refer to FIG. 15C , which illustrates an example of the read operation procedure P23 of the unit memory cell 510 in the inference mode M2. In the read operation procedure P23 of the inference mode M2, the weight value Wi is fixed. When the weight value Wi of the unit memory cell 510 is to be read and the multiplication operation is performed at the same time, the write word line WWL is applied with a predetermined bias voltage VWWL (between the critical voltage VtW1 and the critical voltage VtW0); the write bit line WBL is applied with a higher bias voltage VWBL1 (higher than the critical voltage VtR of the read transistor 512). The bias voltage VWWL is higher than the critical voltage VtW1, which turns on the write transistor 511. Therefore, the bias voltage VWBL1 can reach the read transistor 512, so the read transistor 512 will be turned on, and the read current Ii will be generated in the read bit line RBL. The read current Ii is equal to the product of the input signal Xi and the weight value Wi of "1".

The operations of Figures 14A to 15C above can be summarized as shown in Table 2 below, but Table 2 is only an example value and is not intended to limit the present invention.

The above-mentioned weight value Wi is explained using the two-bit value of "0" and "1" as an example. In another embodiment, the weight value Wi can also be an analog value with a decimal. Please refer to Figures 16 and 17. Figure 16 shows the current and voltage relationship diagram of the read bit line RBL, and Figure 17 illustrates the storage potential VSN1i. As shown in Figure 16, the curve CVi corresponds to different over-drive voltages. As shown in Figure 17, the over-drive voltage is the difference between the storage potential VSN1i and the critical voltage VtR of the read transistor 512. Corresponding to different storage potentials VSN1i, different degrees of over-drive voltage will be formed. The upper curve CVi in Figure 16 corresponds to a higher over-drive voltage. The current formed by the read bit line RBL is positively correlated with the overdrive voltage. That is, the current formed by the read bit line RBL is positively correlated with the storage potential VSN1i. Therefore, various levels of storage potentials VSN1i can be stored in the storage node SN, so that the weight value Wi has different levels of analog values.

That is, as shown in FIG. 17 , in the read operation procedure P13 of the training mode M1, different storage potentials VSN1i of the storage node SN can make the read transistor 512 have different conduction levels, so as to form different read currents Ii corresponding to different weight values Wi in the read transistor 512 .

In addition, please refer to Figure 18, which illustrates the critical voltage VtW1i of the write transistor 511. In the read operation procedure P23 of the inference mode M2, different critical voltages VtW1i of the write transistor 511 can make the write transistor 511 have different conduction levels, so as to form different storage potentials VSN1i at the storage node SN. Different storage potentials VSN1i of the storage node SN can make the read transistor 512 have different conduction levels, so as to form different read currents Ii corresponding to different weight values Wi at the read transistor 512.

In addition, please refer to Figures 19 to 21. Figure 19 shows a voltage curve diagram of a pre-discharge process P20 and a read operation process P23 in the inference mode M2, Figure 20 shows a characteristic curve diagram of the write transistor 511 in the inference mode M2 according to an embodiment, and Figure 21 illustrates the pre-discharge process P20. As shown in Figure 19, the pre-discharge process P20 is executed before executing the read operation process P23. In the pre-discharge process P20, a conduction bias Vpass is applied to the write word line WWL to turn on the write transistor 511. As shown in Figure 20, the conduction bias Vpass is higher than the higher critical voltage VtW0 of the write transistor 511 so that the write transistor 511 is actually turned on. As shown in FIG. 21, after the write transistor 511 is turned on, the storage node SN is discharged, so that the parasitic charge remaining in the storage node SN can be cleared to avoid affecting the result of the read operation program P23.

According to the above embodiment, the universal memory 500 using the 2T structure can be applied to the training mode M1 and the inference mode M2 of artificial intelligence. In the training mode M1 and the inference mode M2, the weight value Wi is stored in different places of the unit memory cell 510. When the universal memory 500 is executed in the training mode M1, it can provide high reliability like dynamic random access memory (DRAM) to meet a large number of weight value Wi update actions; when the universal memory 500 is executed in the inference mode M2, it can provide non-volatility and high retention like non-volatile memory, so that the weight value Wi can be maintained well under low power consumption.

In summary, although the present disclosure has been disclosed as above by the embodiments, it is not intended to limit the present disclosure. Those with ordinary knowledge in the technical field to which the present disclosure belongs can make various changes and modifications without departing from the spirit and scope of the present disclosure. Therefore, the protection scope of the present disclosure shall be subject to the scope defined by the attached patent application.

510: Unit memory cell

511: Write transistor

512: Read transistors

FG: Charge storage layer

RBL: Read Bit Line

RWL: Read character line

WBL: Write Bit Line

WWL: Write Character Line

Claims (10)

A universal memory suitable for in-memory computing (IMC) includes: at least one write word line; at least one unit memory cell, including: a write transistor, the gate of the write transistor is connected to the write word line, the write transistor is a critical voltage adjustable transistor; and a read transistor, the gate of the read transistor is connected to the drain or source of the write transistor; and at least A read word line is connected to the drain or source of the read transistor; wherein in a training mode, a storage potential of a storage node between the write transistor and the read transistor represents a weight value of the unit memory cell; in a weight setting procedure in an inference mode, a critical voltage of the write transistor represents the weight value of the unit memory cell. A general purpose memory suitable for in-memory computing as described in claim 1, wherein the gate of the write transistor has a charge storage layer. An operation method of a universal memory suitable for in-memory computing (IMC), wherein the universal memory includes at least one unit memory cell, the unit memory cell includes a write transistor and a read transistor, the gate of the read transistor is connected to the drain or source of the write transistor, the operation method includes: performing a weight change procedure of a training mode, in which the weight change procedure of the training mode is performed on the write transistor and the read transistor. A storage node between the crystals is charged or discharged to a storage potential, and the storage potential of the storage node represents a weight value (weight) of the unit memory cell; and a weight setting procedure of an inference mode is performed, in which a carrier injection mechanism is performed on the write transistor to change a critical voltage of the write transistor, and the critical voltage of the write transistor represents the weight value of the unit memory cell. The method for operating a general purpose memory suitable for in-memory computing as described in claim 3, wherein in the weight change procedure of the training mode, when the weight value changes, the critical voltage of the write transistor remains fixed. The method for operating a general-purpose memory applicable to in-memory operations as described in claim 3 further includes: performing a read operation procedure of the training mode, in which the storage potential of the storage node changes the conduction degree of the read transistor to form a read current corresponding to the weight value in the read transistor. The method for operating a general purpose memory applicable to in-memory operations as described in claim 3 further includes: Performing a read operation procedure of the inference mode, in which the weight value is fixed and unchanged. The operation method of the general memory applicable to in-memory operation as described in claim 3 further includes: performing a read operation procedure of the inference mode, in which the critical voltage of the write transistor controls the conduction degree of the write transistor to change the storage potential of the storage node, and forms a read current corresponding to the weight value in the read transistor. The method for operating a universal memory suitable for in-memory operation as described in claim 3, wherein the write transistor is connected to a write bit line, and in a read operation procedure in the inference mode, the bias of the write bit line is greater than a critical voltage of the read transistor. The method for operating a general purpose memory applicable to in-memory computing as described in claim 3 further includes: performing a pre-discharge procedure of the inference mode, the pre-discharge procedure of the inference mode being executed before the read computing procedure of the inference mode, and the storage node being discharged during the read computing procedure in the pre-discharge procedure of the inference mode. A universal memory suitable for in-memory computing (IMC), comprising: at least one write word line; at least one unit memory cell, comprising: a write transistor, the gate of the write transistor is connected to the write word line, the write transistor is a critical voltage adjustable transistor; and a read transistor, the gate of the read transistor is connected to the drain or source of the write transistor; and at least one read word line is connected to the drain or source of the read transistor; wherein the universal memory is common to a training mode and an inference mode, in which a weight value is stored in different places of the unit memory cell.

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