TWI889367B - Memory array circuit, ternary content addressable memory and operation method thereof - Google Patents

Abstract

The present disclosure provides a ternary content addressable memory, which includes a first memory unit and a second memory unit, and the second memory unit is electrically connected to the first memory unit. The first memory unit includes a control transistor and a first variable impedance passive component. One end of the first variable impedance passive component is electrically connected to the gate of the control transistor. The second memory unit includes a data transistor and a second variable impedance passive component. The data transistor is connected in series with the control transistor, and one end of the second variable impedance passive component is electrically connected to the gate of the data transistor.

Description

Memory array circuit, ternary content addressable memory and operation method thereof

The present invention relates to a storage circuit and an operating method thereof, and in particular to a memory array circuit, a ternary content addressable memory and an operating method thereof.

With the rapid development of the semiconductor industry, semiconductor components are constantly being innovated. Among many application areas, ternary content addressable memory (TCAM) is widely used in various electronic products.

Traditionally, ternary content addressable memory is usually implemented by two static random access memory (SRAM) cells with additional matching logic elements. However, SRAM-TCAM not only occupies more than ten transistors to represent the search, but it is also energy-consuming due to the volatility of SRAM. Therefore, based on the above reasons, a new ternary content addressable memory is needed to improve the problems of the previous technology.

The present invention provides a memory array circuit, a ternary content addressable memory and an operation method thereof to improve the problems of the prior art.

In one embodiment of the present invention, the ternary content addressable memory proposed by the present invention includes a first memory unit and a second memory unit, wherein the second memory unit is electrically connected to the first memory unit. The first memory unit includes a control transistor and a first variable impedance passive element, wherein one end of the first variable impedance passive element is electrically connected to the gate of the control transistor; the second memory unit includes a data transistor and a second variable impedance passive element, wherein the data transistor is connected in series to the control transistor, and one end of the second variable impedance passive element is electrically connected to the gate of the data transistor.

In one embodiment of the present invention, a source/drain of the control transistor is electrically connected to the bit line, another source/drain of the control transistor is electrically connected to a source/drain of the data transistor, another source/drain of the control transistor and the source/drain of the data transistor are electrically connected to the matching line, and another source/drain of the data transistor is electrically connected to the data line.

In one embodiment of the present invention, the other end of the first variable impedance passive element is electrically connected to the control line, and the other end of the second variable impedance passive element is electrically connected to the word line.

In one embodiment of the present invention, the other end of the first variable impedance passive element and the other end of the second variable impedance passive element are electrically connected to the word line.

In an embodiment of the present invention, each of the first variable impedance passive element and the second variable impedance passive element can be a variable resistor, a variable capacitor, or a capacitive element with electron trapping capability and a fixed dielectric constant.

In one embodiment of the present invention, the memory array circuit proposed by the present invention includes a plurality of ternary content addressable memories, the plurality of ternary content addressable memories are arranged in an array, each of the plurality of ternary content addressable memories includes a first memory cell and a second memory cell, and the second memory cell is electrically connected to the first memory cell. The first memory cell includes a control transistor and a first impedance variable passive element, and one end of the first impedance variable passive element is electrically connected to the gate of the control transistor; the second memory cell includes a data transistor and a second impedance variable passive element, the data transistor is connected in series with the control transistor, and one end of the second impedance variable passive element is electrically connected to the gate of the data transistor.

In one embodiment of the present invention, a source/drain of a control transistor is electrically connected to one of a plurality of bit lines, another source/drain of the control transistor is electrically connected to a source/drain of a data transistor, another source/drain of the control transistor and the source/drain of the data transistor are electrically connected to one of a plurality of match lines, another source/drain of the data transistor is electrically connected to one of a plurality of data lines, a plurality of bit lines and a plurality of data lines are electrically connected to a first circuit, and a plurality of match lines are electrically connected to a second circuit.

In one embodiment of the present invention, the other end of the first variable impedance passive element is electrically connected to one of a plurality of control lines, the other end of the second variable impedance passive element is electrically connected to one of a plurality of word lines, the plurality of control lines are electrically connected to the fourth circuit, and the plurality of word lines are electrically connected to the third circuit.

In an embodiment of the present invention, the other end of the first variable impedance passive element and the other end of the second variable impedance passive element are both electrically connected to one of a plurality of word lines, and the plurality of word lines are electrically connected to a third circuit.

In one embodiment of the present invention, the present invention provides an operation method for a ternary content addressable memory, wherein the ternary content addressable memory comprises a first memory unit and a second memory unit, wherein the first memory unit comprises a control transistor and a first variable impedance passive element, wherein one end of the first variable impedance passive element is electrically connected to a gate of the control transistor, and the second memory unit comprises a data transistor and a second variable impedance passive element, wherein the data transistor is connected in series with the control transistor, and one end of the second variable impedance passive element is electrically connected to a gate of the data transistor. The operation method comprises the following steps: when searching the ternary content addressable memory, searching the first memory unit for a control transistor; The other end of the impedance variable passive element and the other end of the second impedance variable passive element are both applied with a working voltage, and the current value of the bit line is read to determine whether the first memory unit is in a related mode or an irrelevant mode, wherein a source/drain of the control transistor is electrically connected to the bit line, in the irrelevant mode, the channel resistance of the control transistor is in a first resistance state, and in the related mode, the channel resistance of the control transistor is in a third resistance state, and the channel resistance of the data transistor is in a second resistance state or a fourth resistance state, the first resistance state is greater than the second resistance state, the second resistance state is greater than the third resistance state, and the third resistance state is greater than the fourth resistance state.

In one embodiment of the present invention, another source/drain of the control transistor is electrically connected to a source/drain of the data transistor, another source/drain of the control transistor and the source/drain of the data transistor are electrically connected to a matching line, and another source/drain of the data transistor is electrically connected to a data line. The operating method further includes: when the first memory unit is in a related mode, a first voltage is applied to the data line, and a second voltage complementary to the first voltage is applied to the bit line, and the information stored in the second memory unit is judged according to the voltage value of the matching line to correspond to the first search result or the second search result, and the second search result is opposite to the first search result.

In one embodiment of the present invention, the channel resistance of the data transistor is in a fourth resistance state. If the first voltage of the data line is zero voltage and the second voltage of the bit line is an operating voltage, the voltage value of the match line is approximately zero voltage, and the information stored in the second memory unit corresponds to the first search result. If the first voltage of the data line is an operating voltage and the second voltage of the bit line is zero voltage, the voltage value of the match line is a voltage higher than one-third of the operating voltage, and the information stored in the second memory unit corresponds to the second search result.

In one embodiment of the present invention, the channel resistance of the data transistor is in a second resistance state. If the first voltage of the data line is zero voltage and the second voltage of the bit line is an operating voltage, the voltage value of the match line is a voltage higher than one-third of the operating voltage, and the information stored in the second memory unit corresponds to the second search result. If the first voltage of the data line is the operating voltage and the second voltage of the bit line is zero voltage, the voltage value of the match line is approximately a voltage lower than one-third of the operating voltage, and the information stored in the second memory unit corresponds to the first search result.

In one embodiment of the present invention, the other end of the first variable impedance passive element is electrically connected to a control line, and the other end of the second variable impedance passive element is electrically connected to a word line. The step of applying a working voltage to the other end of the first variable impedance passive element and the other end of the second variable impedance passive element includes: applying a working voltage to both the control line and the word line.

In one embodiment of the present invention, the operating method further includes: when programming the first memory cell, applying a programming voltage to the control line, floating the word line, floating the match line, applying a zero voltage to the bit line, and floating the data line; when programming the second memory cell, floating the control line, applying a programming voltage to the word line, floating the match line, floating the bit line, and applying zero voltage to the data line.

In one embodiment of the present invention, the operating method further includes: when erasing the first memory cell, applying zero voltage to the control line, floating the word line, floating the match line, applying an erase voltage to the bit line, and floating the data line; when erasing the second memory cell, floating the control line, applying zero voltage to the word line, floating the match line, floating the bit line, and applying an erase voltage to the data line.

In one embodiment of the present invention, the operating method further includes: when reading the first memory cell, applying a read voltage to the control line, applying a zero voltage to the word line, applying a zero voltage to the match line, applying a test voltage to the bit line, and applying a zero voltage to the data line; when reading the second memory cell, applying a zero voltage to the control line, applying a read voltage to the word line, applying a zero voltage to the match line, applying a zero voltage to the bit line, and applying a test voltage to the data line.

In one embodiment of the present invention, the other end of the first variable impedance passive element and the other end of the second variable impedance passive element are electrically connected to a word line, and the step of applying a working voltage to the other end of the first variable impedance passive element and the other end of the second variable impedance passive element includes: applying the working voltage to the word line.

In one embodiment of the present invention, the operating method further includes: when programming the first memory cell and the second memory cell, applying a programming voltage to the word line, floating the match line, applying a zero voltage to the bit line, and applying a zero voltage to the data line; when erasing the first memory cell, applying a zero voltage to the word line, floating the match line, applying an erase voltage to the bit line, and floating the data line; when erasing the second memory cell, applying a zero voltage to the word line, floating the match line, floating the bit line, and applying an erase voltage to the data line.

In one embodiment of the present invention, the operating method further includes: when reading the first memory cell, applying a read voltage to the word line, floating the match line, applying a test voltage to the bit line, and applying a zero voltage to the data line; when reading the second memory cell, applying a read voltage to the word line, floating the match line, applying a zero voltage to the bit line, and applying a test voltage to the data line.

In summary, the technical solution of the present invention has obvious advantages and beneficial effects compared with the prior art. By means of the technical solution of the present invention, the ternary content addressable memory is a non-volatile ternary content addressable memory, which has high stability, a wider memory window, and saves energy.

The following will describe the above description in detail with an implementation method and provide a further explanation of the technical solution of the present invention.

In order to make the description of the present invention more detailed and complete, reference may be made to the attached drawings and various embodiments described below, in which the same numbers represent the same or similar elements. On the other hand, well-known elements and steps are not described in the embodiments to avoid unnecessary limitations on the present invention.

Please refer to Figures 1 and 2. The technical aspects of the present invention are ternary content addressable memories 100 and 200, which can play an important role in data search and matching in modern digital computing architectures, or can be widely used in related technical links. The ternary content addressable memories 100 and 200 of the present technical aspects can achieve considerable technical progress and have a wide range of industrial utilization value. The specific implementation of the ternary content addressable memories 100 and 200 will be described below in conjunction with Figures 1 and 2.

It should be understood that various implementations of the ternary content addressable memory 100, 200 are described in conjunction with Figures 1 and 2. In the following description, for ease of explanation, many specific details are further set to provide a comprehensive description of one or more implementations. However, the present technology can be implemented without these specific details. In other examples, in order to effectively describe these implementations, known structures and devices are shown in block diagram form. The term "for example" used here means "as an example, instance or illustration." Any embodiment described herein as "for example" is not necessarily interpreted as better or superior to other embodiments.

FIG. 1 is a circuit diagram of a ternary content addressable memory 100 according to an embodiment of the present invention. As shown in FIG. 1 , the ternary content addressable memory 100 includes a first memory unit 110 and a second memory unit 120. Architecturally, the second memory unit 120 is electrically connected to the first memory unit 110. When in use, the first memory unit 110 is used for control, and the second memory unit 120 is used for data storage and search. Specifically, the first memory unit 110 controls the "Care" and "Don't Care" modes; the second memory unit 120 stores some content that needs to be matched.

It should be understood that in the embodiments and the scope of the patent application, the description involving "electrical connection" may generally refer to one component being indirectly electrically coupled to another component through other components, or one component being directly electrically connected to another component without going through other components.

In FIG. 1 , the first memory cell 110 includes a control transistor 111 and a first variable impedance passive element 112. In terms of structure, one end of the first variable impedance passive element 112 is electrically connected to the gate of the control transistor 111. Similarly, the second memory cell 120 includes a data transistor 121 and a second variable impedance passive element 122. In terms of structure, the data transistor 121 is connected in series with the control transistor 111, and one end of the second variable impedance passive element 122 is electrically connected to the gate of the data transistor 121. In practice, for example, in the embodiment of FIG. 1 , the control transistor 111 and the data transistor 121 of FIG. 1 may both be N-type field effect transistors; or, in other embodiments, the control transistor 111 and the data transistor 121 may also be P-type field effect transistors. Those familiar with this technology should be able to flexibly select one according to actual application.

Furthermore, it should be noted that although the terms "first", "second", etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. For example, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element without departing from the scope of the embodiments.

In FIG. 1 , a source/drain of the control transistor 111 is electrically connected to the bit line BL, another source/drain of the control transistor 111 is electrically connected to a source/drain of the data transistor 121, another source/drain of the control transistor 111 and the source/drain of the data transistor 121 are electrically connected to the match line ML, and another source/drain of the data transistor 121 is electrically connected to the data line DL.

In FIG. 1, in some embodiments of the present invention, the other end of the first variable impedance passive element 112 is electrically connected to the control line CL, and the other end of the second variable impedance passive element 122 is electrically connected to the word line WL. Different variable impedance passive elements are connected to the control line CL and the word line WL, so as to facilitate the subsequent programming operation of the first memory unit 110 and the second memory unit 120.

In FIG. 1, in some embodiments of the present invention, each of the first variable impedance passive element 112 and the second variable impedance passive element 122 can be a variable resistor, a variable capacitor (such as a ferroelectric capacitor), a capacitive element with electron capture capability and a fixed dielectric constant (such as the material of the floating gate in a flash memory), or other materials with variable storage properties.

In summary, the present invention adopts the first variable impedance passive element 112 and the second variable impedance passive element 122, so that the ternary content addressable memory 100 can be used as a non-volatile ternary content addressable memory, which has high stability, a wider memory window, and saves energy.

In a controlled experiment, spin-torque transfer magnetic random access memory (STT-MRAM) was used as ternary content addressable memory, but the memory window between states "0" and "1" was narrow, resulting in degraded signal integrity and high programming current.

In a controlled experiment, a transistor was paired with a resistive random access memory (RRAM) as ternary content addressable memory, but the limited endurance cycle and insufficient memory window of RRAM are inevitable drawbacks.

FIG. 2 is a circuit diagram of a ternary content addressable memory 200 according to another embodiment of the present invention. As shown in FIG. 2, the ternary content addressable memory 200 includes a first memory unit 210 and a second memory unit 220. In terms of architecture, the second memory unit 220 is electrically connected to the first memory unit 210.

In FIG. 2 , the first memory cell 210 includes a control transistor 211 and a first variable impedance passive element 212. In terms of structure, one end of the first variable impedance passive element 212 is electrically connected to the gate of the control transistor 211. Similarly, the second memory cell 220 includes a data transistor 221 and a second variable impedance passive element 222. In terms of structure, the data transistor 221 is connected in series with the control transistor 211, and one end of the second variable impedance passive element 222 is electrically connected to the gate of the data transistor 221. In practice, for example, in the embodiment of FIG. 1, the control transistor 111 and the data transistor 221 of FIG. 1 can both be N-type field effect transistors; or, in other embodiments, the control transistor 211 and the data transistor 221 can also be P-type field effect transistors. Those familiar with this technology should flexibly choose according to actual application.

In Figure 2, a source/drain of the control transistor 211 is electrically connected to the bit line BL, another source/drain of the control transistor 211 is electrically connected to a source/drain of the data transistor 221, another source/drain of the control transistor 211 and the source/drain of the data transistor 221 are electrically connected to the matching line ML, and another source/drain of the data transistor 221 is electrically connected to the data line DL.

In FIG. 2, in some embodiments of the present invention, the other end of the first variable impedance passive element 212 and the other end of the second variable impedance passive element 222 are electrically connected to the word line WL. By sharing the same word line WL, the ternary content addressable memory 200 occupies a smaller area.

For a detailed description of the operation method of the ternary content addressable memory 100, please refer to Figures 1 and 3. Figure 3 is a diagram of setting, resetting and reading in the operation method of the ternary content addressable memory 100 according to an embodiment of the present invention.

In the stage of setting the ternary content addressable memory 100, when programming the first memory cell 110, a programming voltage V _PGM (e.g., about 2 V to 4 V) is applied to the control line CL, the word line WL is floated, the match line ML is floated, a zero voltage (e.g., about 0V) is applied to the bit line BL, and the data line DL is floated. Similarly, when programming the second memory cell 120, the control line CL is floated, a programming voltage V _PGM is applied to the word line WL, the match line ML is floated, the bit line BL is floated, and a zero voltage is applied to the data line DL.

In the stage of resetting the ternary content addressable memory 100, when erasing the first memory cell 110, a zero voltage is applied to the control line CL, the word line WL is floated, the match line ML is floated, an erase voltage V _ERS (e.g., about 2 V to 4 V) is applied to the bit line BL, and the data line DL is floated. Similarly, when erasing the second memory cell 120, the control line CL is floated, a zero voltage is applied to the word line WL, the match line ML is floated, the bit line BL is floated, and an erase voltage V _ERS is applied to the data line DL.

In the stage of reading the ternary content addressable memory 100, when reading the first memory cell 110, a read voltage V _READ (e.g., about 0.8V) is applied to the control line CL, a zero voltage is applied to the word line WL, a zero voltage is applied to the match line ML, a test voltage V _TEST (e.g., about 0.3V) is applied to the bit line BL, and a zero voltage is applied to the data line DL. Similarly, when reading the second memory cell 120, a zero voltage is applied to the control line CL, a read voltage V _READ is applied to the word line WL, a zero voltage is applied to the match line ML, a zero voltage is applied to the bit line BL, and a test voltage V _TEST is applied to the data line DL.

It should be understood that the terms "about", "approximately" or "substantially" used herein are used to modify any quantity that may vary slightly, but such slight variations do not change its essence. If there is no special explanation in the implementation method, the error range of the value modified by "about", "approximately" or "substantially" is generally allowed within 20%, preferably within 10%, and more preferably within 5%.

For a detailed description of the operation method of the ternary content addressable memory 200, please refer to Figures 2 and 5. Figure 5 is a diagram of setting, resetting and reading in the operation method of the ternary content addressable memory 200 according to another embodiment of the present invention.

In the stage of setting the ternary content addressable memory 200, when programming the first memory cell 110 and the second memory cell 120, a programming voltage V _PGM (e.g., about 1.5 V to 4 V) is applied to the word line WL, the match line ML is floated, zero voltage is applied to the bit line BL, and zero voltage is applied to the data line DL. Since the first memory cell 110 and the second memory cell 120 share the same word line WL, the first memory cell 110 and the second memory cell 120 are programmed to the same storage content. However, the storage content of the first memory cell 110 and the storage content of the second memory cell 120 can be different by erasing the first memory cell 110 and the second memory cell 120 to different degrees.

In the stage of resetting the ternary content addressable memory 200, when erasing the first memory cell 110, a zero voltage is applied to the word line WL, the match line ML is floated, an erase voltage V _ERS (e.g., about 1.5 V to 4 V) is applied to the bit line BL, and the data line DL is floated. Similarly, when erasing the second memory cell 120, a zero voltage is applied to the word line WL, the match line ML is floated, the bit line BL is floated, and an erase voltage V _ERS (e.g., about 1.5 V to 4 V) is applied to the data line DL.

In the stage of reading the ternary content addressable memory 200, when reading the first memory cell 110, a read voltage V _READ (e.g., about 0.8V~1V) is applied to the word line WL, the match line ML is floated, a test voltage V _TEST (e.g., about 0.3V~1V) is applied to the bit line BL, and a zero voltage is applied to the data line DL. Similarly, when reading the second memory cell 120, a read voltage V _READ is applied to the word line WL, the match line ML is floated, a zero voltage is applied to the bit line BL, and a test voltage V _TEST is applied to the data line DL.

In order to specifically explain the search phase of the operation method of the ternary content addressable memory 100, please refer to Figures 1, 3, and 4 at the same time. Figure 4 is a diagram of the search in the operation method of the ternary content addressable memory 100 according to an embodiment of the present invention. In Figure 1, one end of the first variable impedance passive element 112 is electrically connected to the gate of the control transistor 111, and one end of the second variable impedance passive element 122 is electrically connected to the gate of the data transistor 121.

When searching the ternary content addressable memory 100, a working voltage _Vdd is applied to the other end of the first variable impedance passive element 112 and the other end of the second variable impedance passive element 122, and the current value of the bit line BL is read to determine whether the first memory unit 110 is in a relevant mode or an irrelevant mode, wherein a source/drain of the control transistor 111 is electrically connected to the bit line BL.

Regarding the specific mechanism of applying the working voltage V _dd , in some embodiments of the present invention, the other end of the first variable impedance passive device 112 is electrically connected to the control line CL, and the other end of the second variable impedance passive device 122 is electrically connected to the word line WL. The step of applying the working voltage V _dd to the other end of the first variable impedance passive device 112 and the other end of the second variable impedance passive device 122 may include: applying the working voltage V _dd to both the control line CL and the word line WL.

Regarding the specific method of determining whether the first memory unit 110 is in the relevant mode or the irrelevant mode, in some embodiments of the present invention, if the current value of the bit line BL is greater than a preset current threshold value, the first memory unit 110 is in the relevant mode; on the contrary, if the current value of the bit line BL (e.g., close to zero current) is less than or equal to the preset current threshold value, the first memory unit 110 is in the irrelevant mode. In practice, for example, the preset current threshold value can be set according to actual experience or experimental data.

In the irrelevant mode, the channel resistance R _ctr of the control transistor 111 is in the first resistance state GRS, and the channel resistance R _data of the data transistor 121 is in the second resistance state HRS or the fourth resistance state LRS. In the relevant mode, the channel resistance R _ctr of the control transistor 111 is in the third resistance state MRS, and the channel resistance R _data of the data transistor 121 is in the second resistance state HRS or the fourth resistance state LRS. The first resistance state GRS is greater than the second resistance state HRS, the second resistance state HRS is greater than the third resistance state MRS, and the third resistance state MRS is greater than the fourth resistance state LRS.

In practice, for example, after the first variable impedance passive element 112 is programmed/erased, the resistance state of the channel resistance R _ctr of the control transistor 111 during operation is affected. Similarly, after the second variable impedance passive element 122 is programmed/erased, the resistance state of the channel resistance R _data of the data transistor 121 during operation is affected.

Next, when the first memory unit 110 is in the correlation mode, a first voltage is applied to the data line DL, a second voltage complementary to the first voltage is applied to the bit line BL, and the information stored in the second memory unit 120 is determined to correspond to the first search result or the second search result according to the voltage value of the match line ML, and the second search result is opposite to the first search result. In some embodiments of the present invention, the first search result is a match, and the second search result is a mismatch. Alternatively, it can also be defined inversely, in some embodiments of the present invention, the first search result is a mismatch, and the second search result is a match.

In some embodiments of the present invention, the channel resistance R _data of the data transistor 121 is in the fourth resistance state LRS. If the first voltage of the data line DL is approximately zero voltage (0V) and the second voltage of the bit line BL is approximately the operating voltage V _dd , the voltage value of the match line ML is approximately zero voltage, and the information stored in the second memory unit 120 corresponds to the first search result. Conversely, if the first voltage of the data line DL is approximately the operating voltage V _dd and the second voltage of the bit line BL is approximately zero voltage (0V), the voltage value of the match line ML is approximately a voltage higher than one-third of the operating voltage V _dd or is approximately the operating voltage V _dd , and the information stored in the second memory unit 120 corresponds to the second search result.

Alternatively, in some embodiments of the present invention, the channel resistance R _data of the data transistor 121 is in the second resistance state HRS, if the first voltage of the data line DL is approximately zero voltage and the second voltage of the bit line BL is approximately the operating voltage V _dd , the voltage value of the match line ML is approximately a voltage higher than one-third of the operating voltage V _dd or is approximately the operating voltage V _dd , and the information stored in the second memory unit 120 corresponds to the second search result; conversely, if the first voltage of the data line DL is approximately the operating voltage V _dd and the second voltage of the bit line BL is approximately zero voltage, the voltage value of the match line ML is approximately a voltage lower than one-third of the operating voltage V _dd or is approximately zero voltage, and the information stored in the second memory unit 120 corresponds to the first search result.

In order to specifically explain the search phase of the operation method of the ternary content addressable memory 200, please refer to Figures 2, 5, and 6. Figure 6 is a diagram of the search in the operation method of the ternary content addressable memory 200 according to another embodiment of the present invention. In Figure 2, one end of the first variable impedance passive element 212 is electrically connected to the gate of the control transistor 211, and one end of the second variable impedance passive element 222 is electrically connected to the gate of the data transistor 221.

When searching the ternary content addressable memory 200, a working voltage _Vdd is applied to the other end of the first variable impedance passive element 212 and the other end of the second variable impedance passive element 222, and the current value of the bit line BL is read to determine whether the first memory unit 210 is in a relevant mode or an irrelevant mode, wherein a source/drain of the control transistor 211 is electrically connected to the bit line BL.

Regarding the specific mechanism of applying the working voltage V _dd , the other end of the first variable impedance passive device 212 and the other end of the second variable impedance passive device 222 are electrically connected to the word line WL. The step of applying the working voltage V _dd to the other end of the first variable impedance passive device 212 and the other end of the second variable impedance passive device 222 includes: applying the working voltage V _dd to the word line WL.

Regarding the specific method of determining whether the first memory unit 210 is in the relevant mode or the irrelevant mode, in some embodiments of the present invention, if the current value of the bit line BL is greater than a preset current threshold value, the first memory unit 210 is in the relevant mode; on the contrary, if the current value of the bit line BL (e.g., close to zero current) is less than or equal to the preset current threshold value, the first memory unit 210 is in the irrelevant mode. In practice, for example, the preset current threshold value can be set according to actual experience or experimental data.

In the irrelevant mode, the channel resistance R _ctr of the control transistor 211 is in the first resistance state GRS, and the channel resistance R _data of the data transistor 221 is in the second resistance state HRS or the fourth resistance state LRS. In the relevant mode, the channel resistance R _ctr of the control transistor 211 is in the third resistance state MRS, and the channel resistance R _data of the data transistor 221 is in the second resistance state HRS or the fourth resistance state LRS. The first resistance state GRS is greater than the second resistance state HRS, the second resistance state HRS is greater than the third resistance state MRS, and the third resistance state MRS is greater than the fourth resistance state LRS.

In practice, for example, after the first variable impedance passive element 212 is programmed/erased, the resistance state of the channel resistance R _ctr of the control transistor 211 during operation is affected. Similarly, after the second variable impedance passive element 222 is programmed/erased, the resistance state of the channel resistance R _data of the data transistor 221 during operation is affected.

Next, when the first memory unit 210 is in the correlation mode, a first voltage is applied to the data line DL, a second voltage complementary to the first voltage is applied to the bit line BL, and the information stored in the second memory unit 120 is determined to correspond to the first search result or the second search result according to the voltage value of the match line ML, and the second search result is opposite to the first search result. In some embodiments of the present invention, the first search result is a match, and the second search result is a mismatch. Alternatively, it can also be defined inversely, in some embodiments of the present invention, the first search result is a mismatch, and the second search result is a match.

In some embodiments of the present invention, the channel resistance R _data of the data transistor 221 is in the fourth resistance state LRS. If the first voltage of the data line DL is approximately zero voltage (0V) and the second voltage of the bit line BL is approximately the operating voltage V _dd , the voltage value of the match line ML is approximately zero voltage, and the information stored in the second memory unit 220 corresponds to the first search result. Conversely, if the first voltage of the data line DL is approximately the operating voltage V _dd and the second voltage of the bit line BL is approximately zero voltage (0V), the voltage value of the match line ML is approximately the operating voltage V _dd , and the information stored in the second memory unit 220 corresponds to the second search result.

Alternatively, in some embodiments of the present invention, the channel resistance R _data of the data transistor 221 is in the second resistance state HRS, if the first voltage of the data line DL is approximately zero voltage and the second voltage of the bit line BL is approximately the operating voltage V _dd , the voltage value of the match line ML is approximately the operating voltage V _dd , and the information stored in the second memory unit 220 corresponds to the second search result; conversely, if the first voltage of the data line DL is approximately the operating voltage V _dd and the second voltage of the bit line BL is approximately zero voltage, the voltage value of the match line ML is approximately zero voltage, and the information stored in the second memory unit 220 corresponds to the first search result.

FIG. 7 is an equivalent circuit diagram of a memory array circuit 700 according to an embodiment of the present invention. As shown in FIG. 7 , the memory array circuit 700 includes a plurality of ternary content addressable memories 100, the plurality of ternary content addressable memories 100 are arranged in an array, each of the plurality of ternary content addressable memories 100 includes a first memory unit 110 and a second memory unit 120, and the second memory unit 120 is electrically connected to the first memory unit 110. The first memory cell 110 includes a control transistor 111 and a first variable impedance passive element 112, one end of the first variable impedance passive element 112 is electrically connected to the gate of the control transistor 111; similarly, the second memory cell 120 includes a data transistor 121 and a second variable impedance passive element 122, the data transistor 121 is connected in series to the control transistor 111, and one end of the second variable impedance passive element 122 is electrically connected to the gate of the data transistor 121.

In FIG. 7 , a source/drain of the control transistor 111 is electrically connected to one of the plurality of bit lines BL ₀ to BL _n , another source/drain of the control transistor 111 is electrically connected to a source/drain of the data transistor 121, another source/drain of the control transistor 111 and the source/drain of the data transistor 121 are electrically connected to one of the plurality of match lines ML ₀ to ML _n , another source/drain of the data transistor 121 is electrically connected to one of the plurality of data lines DL ₀ to DL _n , the plurality of bit lines BL ₀ to BL _n and the plurality of data lines DL ₀ to DL _n are electrically connected to a first circuit 710, and the plurality of match lines ML ₀ to ML _n are electrically connected to a second circuit 720.

In some embodiments of the present invention, the first circuit 710 may include a bit line driver, a data line driver, a control circuit, a peripheral circuit, and a sense amplifier. When in use, the control circuit controls the bit line driver to apply a suitable voltage (such as: erase voltage, test voltage, zero voltage, floating connection, etc.) to the bit line, and the control circuit controls the data line driver to apply a suitable voltage (such as: erase voltage, test voltage, zero voltage, floating connection, etc.) to the bit line. The sense amplifier can sense the current value on the bit line, and the control circuit can determine the relevant or irrelevant mode based on the current value.

In some embodiments of the present invention, the second circuit 720 may include a match line driver, a control circuit, a peripheral circuit, and a read circuit. When in use, the control circuit controls the match line driver to apply a suitable voltage (such as zero voltage, floating, etc.) to the match line, and the read circuit can read the voltage value on the match line. The control circuit can determine the search result based on the voltage value.

In FIG. 7 , the other end of the first variable impedance passive element 112 is electrically connected to one of the plurality of control lines CL ₀ ~CL _n , the other end of the second variable impedance passive element 122 is electrically connected to one of the plurality of word lines WL ₀ ~WL _n , the plurality of word lines WL ₀ ~WL _n are electrically connected to the third circuit 730, and the plurality of control lines CL ₀ ~CL _n are electrically connected to the fourth circuit 740.

In some embodiments of the present invention, the third circuit 730 may include a word line driver, a control circuit, and a peripheral circuit. When in use, the control circuit controls the word line driver to apply a suitable voltage (such as programming voltage, read voltage, zero voltage, floating, etc.) to the word line.

In some embodiments of the present invention, the fourth circuit 740 may include a control line driver, a control circuit, and a peripheral circuit. When in use, the control circuit controls the control line driver to apply a suitable voltage (such as programming voltage, read voltage, zero voltage, floating connection, etc.) to the control line.

FIG8 is an equivalent circuit diagram of a memory array circuit 800 according to another embodiment of the present invention. As shown in FIG8, the memory array circuit 800 includes a plurality of ternary content addressable memories 200, the plurality of ternary content addressable memories 200 are arranged in an array, each of the plurality of ternary content addressable memories 200 includes a first memory unit 210 and a second memory unit 220, and the second memory unit 220 is electrically connected to the first memory unit 210. The first memory cell 210 includes a control transistor 211 and a first variable impedance passive element 212, one end of the first variable impedance passive element 212 is electrically connected to the gate of the control transistor 211; similarly, the second memory cell 220 includes a data transistor 221 and a second variable impedance passive element 222, the data transistor 221 is connected in series to the control transistor 211, and one end of the second variable impedance passive element 222 is electrically connected to the gate of the data transistor 221.

In FIG. 8 , a source/drain of the control transistor 211 is electrically connected to one of the plurality of bit lines BL ₀ to BL _n , another source/drain of the control transistor 211 is electrically connected to a source/drain of the data transistor 221, another source/drain of the control transistor 211 and the source/drain of the data transistor 221 are electrically connected to one of the plurality of match lines ML ₀ to ML _n , another source/drain of the data transistor 221 is electrically connected to one of the plurality of data lines DL ₀ to DL _n , the plurality of bit lines BL ₀ to BL _n and the plurality of data lines DL ₀ to DL _n are electrically connected to the first circuit 810, and the plurality of match lines ML ₀ to ML _n are electrically connected to the second circuit 820.

In some embodiments of the present invention, the first circuit 810 may include a bit line driver, a data line driver, a control circuit, a peripheral circuit, and a sense amplifier. When in use, the control circuit controls the bit line driver to apply a suitable voltage (such as: erase voltage, test voltage, zero voltage, floating connection, etc.) to the bit line, and the control circuit controls the data line driver to apply a suitable voltage (such as: erase voltage, test voltage, zero voltage, floating connection, etc.) to the bit line. The sense amplifier can sense the current value on the bit line, and the control circuit can determine the relevant or irrelevant mode based on the current value.

In some embodiments of the present invention, the second circuit 820 may include a match line driver, a control circuit, a peripheral circuit, and a read circuit. When in use, the control circuit controls the match line driver to apply a suitable voltage (such as zero voltage, floating, etc.) to the match line, and the read circuit can read the voltage value on the match line. The control circuit can determine the search result based on the voltage value.

In FIG. 8 , the other end of the first variable impedance passive device 212 and the other end of the second variable impedance passive device 222 are both electrically connected to one of a plurality of word lines WL ₀ -WL _n , and the plurality of word lines WL ₀ -WL _n are electrically connected to a third circuit 830 .

In some embodiments of the present invention, the third circuit 830 may include a word line driver, a control circuit, and a peripheral circuit. When in use, the control circuit controls the word line driver to apply a suitable voltage (such as programming voltage, read voltage, zero voltage, etc.) to the word line.

In summary, the technical solution of the present invention has obvious advantages and beneficial effects compared with the prior art. By means of the technical solution of the present invention, the ternary content addressable memory 100 is a non-volatile ternary content addressable memory, which has high stability, a wider memory window, and saves energy.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention. Anyone skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined in the attached patent application.

100, 200: ternary content addressable memory 110, 210: first memory cell 111, 211: control transistor 112, 212: first variable impedance passive element 120, 220: second memory cell 121, 221: data transistor 122, 222: second variable impedance passive element 700, 800: memory array circuit 710, 810: first circuit 720, 820: second circuit 730, 830: third circuit 740: fourth circuit BL, _BL0 ~ _BLn : bit lines CL, _CL0 ~ _CLn : control lines DL, _DL0 ~ _DLn : data lines GRS: first resistance state HRS: second resistance state LRS: fourth resistance state MRS: third resistance state _Rdata : channel resistance _Rctr : Channel resistance V _dd : Operating voltage V _ERS : Erase voltage V _PGM : Programming voltage V _READ : Read voltage V _TEST : Test voltage ML, ML ₀ ~ML _n : Matching lines WL, WL ₀ ~WL _n : Word lines

In order to make the above and other purposes, features, advantages and embodiments of the present invention more clearly understandable, the attached drawings are described as follows: FIG. 1 is a circuit diagram of a ternary content addressable memory according to an embodiment of the present invention; FIG. 2 is a circuit diagram of a ternary content addressable memory according to another embodiment of the present invention; FIG. 3 is a diagram of setting, resetting and reading in a method for operating a ternary content addressable memory according to an embodiment of the present invention; FIG. 4 is a diagram of searching in a method for operating a ternary content addressable memory according to an embodiment of the present invention; FIG. 5 is a diagram of setting, resetting and reading in a method for operating a ternary content addressable memory according to another embodiment of the present invention; FIG. 6 is a diagram of a search in a method of operating a ternary content addressable memory according to another embodiment of the present invention; FIG. 7 is an equivalent circuit diagram of a memory array circuit according to an embodiment of the present invention; and FIG. 8 is an equivalent circuit diagram of a memory array circuit according to another embodiment of the present invention.

100: Ternary content addressable memory

110: First memory unit

111: Control transistor

112: First variable impedance passive element

120: Second memory unit

121: Data transistor

122: Second variable impedance passive element

BL: Bit Line

CL: Control line

DL: Data Line

ML: Matching Line

WL: character line

Claims (19)

A ternary content addressable memory comprises: a first memory cell comprising a control transistor and a first variable impedance passive element, one end of the first variable impedance passive element being electrically connected to a gate of the control transistor; and a second memory cell electrically connected to the first memory cell, the second memory cell comprising a data transistor and a second variable impedance passive element, the data transistor being connected in series to the control transistor, one end of the second variable impedance passive element being electrically connected to a gate of the data transistor, One source/drain of the control transistor is electrically connected to a bit line, the other source/drain of the control transistor is electrically connected to a source/drain of the data transistor, the other source/drain of the control transistor and the source/drain of the data transistor are electrically connected to a matching line, and the other source/drain of the data transistor is electrically connected to a data line. A ternary content addressable memory as described in claim 1, wherein the other end of the first variable impedance passive element is electrically connected to a control line, and the other end of the second variable impedance passive element is electrically connected to a word line. A ternary content addressable memory as described in claim 1, wherein the other end of the first variable impedance passive element and the other end of the second variable impedance passive element are electrically connected to a word line. A ternary content addressable memory as described in claim 1, wherein each of the first variable impedance passive element and the second variable impedance passive element is a variable resistor, a variable capacitor, or a capacitive element with electron capturing capability and a fixed dielectric constant. A memory array circuit comprises: A plurality of ternary content addressable memories arranged in an array, each of the ternary content addressable memories comprising: A first memory cell comprising a control transistor and a first variable impedance passive element, one end of the first variable impedance passive element being electrically connected to a gate of the control transistor; and A second memory cell electrically connected to the first memory cell, the second memory cell comprising a data transistor and a second variable impedance passive element, the data transistor being connected in series to the control transistor, one end of the second variable impedance passive element being electrically connected to a gate of the data transistor, A source/drain of the control transistor is electrically connected to one of a plurality of bit lines, another source/drain of the control transistor is electrically connected to a source/drain of the data transistor, the other source/drain of the control transistor and the source/drain of the data transistor are electrically connected to one of a plurality of match lines, and another source/drain of the data transistor is electrically connected to one of a plurality of data lines. A memory array circuit as described in claim 5, wherein the bit lines and the data lines are electrically connected to a first circuit, and the matching lines are electrically connected to a second circuit. A memory array circuit as described in claim 6, wherein the other end of the first variable impedance passive element is electrically connected to one of a plurality of control lines, the other end of the second variable impedance passive element is electrically connected to one of a plurality of word lines, the word lines are electrically connected to a third circuit, and the control lines are electrically connected to a fourth circuit. The memory array circuit as described in claim 6, wherein the other end of the first variable impedance passive element and the other end of the second variable impedance passive element are both electrically connected to one of a plurality of word lines, and the word lines are electrically connected to a third circuit. A method for operating a ternary content addressable memory, the ternary content addressable memory comprises a first memory unit and a second memory unit, the first memory unit comprises a control transistor and a first variable impedance passive element, one end of the first variable impedance passive element is electrically connected to a gate of the control transistor, the second memory unit comprises a data transistor and a second variable impedance passive element, the data transistor is connected in series to the control transistor, one end of the second variable impedance passive element is electrically connected to a gate of the data transistor, the method comprises the following steps: When searching the ternary content addressable memory, a working voltage is applied to the other end of the first variable impedance passive element and the other end of the second variable impedance passive element, and a current value of a bit line is read to determine whether the first memory unit is in a relevant mode or an irrelevant mode, wherein a source/drain of the control transistor is electrically connected to the bit line, in the irrelevant mode, the channel resistance of the control transistor is a first resistance state, and in the relevant mode, the channel resistance of the control transistor is a third resistance state, and the channel resistance of the data transistor is a third resistance state. Two resistance states or a fourth resistance state, the first resistance state is greater than the second resistance state, the second resistance state is greater than the third resistance state, and the third resistance state is greater than the fourth resistance state, wherein a source/drain of the control transistor is electrically connected to a bit line, another source/drain of the control transistor is electrically connected to a source/drain of the data transistor, the other source/drain of the control transistor and the source/drain of the data transistor are electrically connected to a matching line, and another source/drain of the data transistor is electrically connected to a data line. The operating method as described in claim 9, wherein the other source/drain of the control transistor is electrically connected to a source/drain of the data transistor, the other source/drain of the control transistor and the source/drain of the data transistor are electrically connected to a matching line, and the other source/drain of the data transistor is electrically connected to a data line, and the operating method further includes: When the first memory unit is in the relevant mode, a first voltage is applied to the data line, a second voltage complementary to the first voltage is applied to the bit line, and the information stored in the second memory unit is judged to correspond to a first search result or a second search result based on the voltage value of the matching line, and the second search result is opposite to the first search result. An operating method as described in claim 10, wherein the channel resistance of the data transistor is in the fourth resistance state, if the first voltage of the data line is zero voltage and the second voltage of the bit line is the operating voltage, the voltage value of the match line is zero voltage, and the information stored in the second memory unit corresponds to the first search result; if the first voltage of the data line is the operating voltage and the second voltage of the bit line is zero voltage, the voltage value of the match line is a voltage higher than one-third of the operating voltage, and the information stored in the second memory unit corresponds to the second search result. An operating method as described in claim 10, wherein the channel resistance of the data transistor is in the second resistance state, if the first voltage of the data line is zero voltage and the second voltage of the bit line is the operating voltage, the voltage value of the match line is a voltage higher than one-third of the operating voltage, and the information stored in the second memory unit corresponds to the second search result; if the first voltage of the data line is the operating voltage and the second voltage of the bit line is zero voltage, the voltage value of the match line is a voltage lower than one-third of the operating voltage, and the information stored in the second memory unit corresponds to the first search result. The operating method as described in claim 10, wherein the other end of the first variable impedance passive element is electrically connected to a control line, and the other end of the second variable impedance passive element is electrically connected to a word line, and the step of applying the operating voltage to the other end of the first variable impedance passive element and the other end of the second variable impedance passive element includes: Applying the operating voltage to both the control line and the word line. The operating method as described in claim 13 further includes: When programming the first memory cell, a programming voltage is applied to the control line, the word line is floated, the match line is floated, a zero voltage is applied to the bit line, and the data line is floated; and When programming the second memory cell, the control line is floated, the programming voltage is applied to the word line, the match line is floated, the bit line is floated, and the zero voltage is applied to the data line. The operation method as described in claim 14 further includes: When erasing the first memory cell, applying the zero voltage to the control line, floating the word line, floating the match line, applying an erase voltage to the bit line, and floating the data line; and When erasing the second memory cell, floating the control line, applying the zero voltage to the word line, floating the match line, floating the bit line, and applying the erase voltage to the data line. The operating method as described in claim 14 further includes: When reading the first memory cell, applying a read voltage to the control line, applying the zero voltage to the word line, applying the zero voltage to the match line, applying a test voltage to the bit line, and applying the zero voltage to the data line; and When reading the second memory cell, applying the zero voltage to the control line, applying the read voltage to the word line, applying the zero voltage to the match line, applying the zero voltage to the bit line, and applying the test voltage to the data line. The operating method as described in claim 10, wherein the other end of the first variable impedance passive element and the other end of the second variable impedance passive element are electrically connected to a word line, and the step of applying the operating voltage to the other end of the first variable impedance passive element and the other end of the second variable impedance passive element includes: Applying the operating voltage to the word line. The operation method as described in claim 17 further includes: When programming the first memory cell and the second memory cell, a programming voltage is applied to the word line, the match line is floated, a zero voltage is applied to the bit line, and the zero voltage is applied to the data line; When erasing the first memory cell, the zero voltage is applied to the word line, the match line is floated, an erase voltage is applied to the bit line, and the data line is floated; and When erasing the second memory cell, the zero voltage is applied to the word line, the match line is floated, the bit line is floated, and the erase voltage is applied to the data line. The operating method as described in claim 18 further includes: When reading the first memory cell, applying a read voltage to the word line, floating the match line, applying a test voltage to the bit line, and applying the zero voltage to the data line; and When reading the second memory cell, applying a read voltage to the word line, floating the match line, applying the zero voltage to the bit line, and applying the test voltage to the data line.

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