TWI855679B - Memory device - Google Patents

Abstract

The embodiment provides a memory device with improved yield. The memory device of the embodiment comprises: a first conductive layer and a second conductive layer, which are arranged in a first direction and spaced apart from each other; a memory pillar, which extends in the first direction in the region where the second conductive layer overlaps with the first conductive layer when viewed in the first direction, and the first portion intersecting the first conductive layer functions as a first memory cell, and the second portion intersecting the second conductive layer functions as a second memory cell. The first insulating member is disposed between the first conductive layer and the second conductive layer in a region where the second conductive layer does not overlap with the first conductive layer when viewed in the first direction; and the second insulating member is extended in the first direction in a manner crossing the first conductive layer in a region where the second conductive layer overlaps with the first insulating member when viewed in the first direction. The upper end of the second insulating member is separated from the lower end of the first insulating member.

Description

Memory device

As a memory device that can store data non-volatilely, NAND (Not-AND) flash memory is known. In memory devices such as NAND flash memory, a three-dimensional memory structure is adopted for high integration and large capacity.

As a memory device that can store data non-volatilely, NAND (Not-AND) flash memory is known. In memory devices such as NAND flash memory, a three-dimensional memory structure is adopted for high integration and large capacity.

The problem that the present invention aims to solve is to provide a memory device that can improve the yield.

The memory device of the embodiment has a first conductive layer and a second conductive layer, a memory conductive post, a first insulating member, and a second insulating member. The first conductive layer and the second conductive layer are arranged in a first direction and spaced apart from each other. The memory conductive post extends in the first direction in a region where the second conductive layer overlaps the first conductive layer when viewed in the first direction, and the first portion intersecting the first conductive layer functions as a first memory cell, and the second portion intersecting the second conductive layer functions as a second memory cell. The first insulating member is disposed between the first conductive layer and the second conductive layer in a region where the second conductive layer does not overlap with the first conductive layer when viewed in the first direction. The second insulating member extends in the first direction in a manner intersecting the first conductive layer in a region where the second insulating member overlaps with the first insulating member when viewed in the first direction. The upper end of the second insulating member is separated from the lower end of the first insulating member.

1: Memory system

2: Memory controller

3: Memory device

10: Memory cell array

11: Instruction register

12: Address register

13: Sequencer

14:Driver module

15: Column decoder module

16: Sensor amplifier module

20: Semiconductor substrate

21~27: Conductive layer

30~39: Insulating body layer

40: Core membrane

41:Semiconductor film

42: Laminated film

43: Tunnel insulation film

44: Charge storage membrane

45: Barrier insulation film

51:Semiconductor layer

52: Insulating layer

53: Sacrifice layer

54: Insulating layer

55:Semiconductor layer

56: Sacrifice layer

57: Sacrifice layer

58: Sacrifice layer

59: Anti-corrosion agent layer

60: Insulating layer

61: Sacrifice layer

62: Insulating layer

63: Sacrifice layer

64: Sacrifice layer

65: Sacrifice layer

66: Anti-corrosion agent layer

67: Insulating layer

ADD: Address information

BAd: Block address

BHR: bottom

BL0~BLm: bit line

BL: Bit Line

BLK: Block

BLK0~BLKn: Block

BLKe: Block

BLKo: Block

BMP: bottom

CC: Contact

CAd: row address

CM: Surplus

CM’: margin

CMD: Command

CU: Unit Group

CV: Contact

DAT: Data

H0~H9: Hole

HA1: Lead-out area

HA2: Lead-out area

HR: Support pillars

HRa: Support guide post

HRb: Support guide post

HRc: Support guide post

HRc’: Support guide post

JHR: Joint

JMP: junction

LHR: Lower part

LI: Contact

LMP: Lower part

MA: Memory Area

MP: memory guide pin

MT0~MT7: memory cell transistors

NS:NAND string

PAd: page address

SGD: Select gate line

SGD0~SGD4: select gate line

SGS: Selecting gate lines

SHE: Components

SL: Source line

SLT:Components

SP: Spacer

ST1: Select transistor

ST2: Select transistor

SU0~SU4: string unit

UHR: Upper

UMP: Upper part

VO:Void

WL0~WL7: character line

FIG1 is a block diagram showing the configuration of a memory system including a memory device of an implementation form.

FIG2 is a circuit diagram showing an example of the circuit structure of a memory cell array provided in a memory device of an implementation form.

FIG3 is a top view showing an example of a planar layout of an area including a memory cell array provided in a memory device of an embodiment.

FIG4 is a top view showing an example of a detailed planar layout of a memory area of a memory device of an implementation form.

FIG5 shows an example of the cross-sectional structure of the memory area of the memory device of the embodiment, and is a cross-sectional view along the V-V line of FIG4.

FIG6 shows an example of the cross-sectional structure of a memory guide pillar of a memory device of an implementation form, and is a cross-sectional view along the VI-VI line of FIG5 .

FIG. 7 is a top view showing an example of a detailed plan layout of a lead-out area of a memory device of an implementation form.

FIG8 shows an example of the cross-sectional structure of the lead-out region of the memory device of the embodiment, and is a cross-sectional view along the VIII-VIII line of FIG7 .

FIG9 is a cross-sectional view showing an example of a cross-sectional structure of a memory device in the middle of manufacturing of an implementation form.

FIG10 is a cross-sectional view showing an example of a cross-sectional structure of a memory device in the middle of manufacturing of an implementation form.

FIG11 is a cross-sectional view showing an example of a cross-sectional structure of a memory device in the middle of manufacturing of an implementation form.

FIG12 is a cross-sectional view showing an example of a cross-sectional structure of a memory device in the middle of manufacturing of an implementation form.

FIG13 is a cross-sectional view showing an example of a cross-sectional structure of a memory device in the middle of manufacturing of an implementation form.

FIG14 is a cross-sectional view showing an example of a cross-sectional structure of a memory device in the middle of manufacturing of an implementation form.

FIG15 is a cross-sectional view showing an example of a cross-sectional structure of a memory device in the middle of manufacturing of an implementation form.

FIG16 is a cross-sectional view showing an example of a cross-sectional structure of a memory device in the middle of manufacturing of an implementation form.

FIG17 is a cross-sectional view showing an example of a cross-sectional structure of a memory device in the middle of manufacturing of an implementation form.

FIG18 is a cross-sectional view showing an example of a cross-sectional structure of a memory device in the middle of manufacturing of an implementation form.

FIG. 19 is a cross-sectional view showing an example of a cross-sectional structure of a memory device in the middle of manufacturing of an implementation form.

FIG. 20 is a cross-sectional view showing an example of a cross-sectional structure of a memory device in the middle of manufacturing of an implementation form.

FIG. 21 is a cross-sectional view showing an example of a cross-sectional structure of a memory device in the middle of manufacturing of an implementation form.

FIG. 22 is a cross-sectional view showing an example of a cross-sectional structure of a memory device of an embodiment during manufacturing.

FIG. 23 is a cross-sectional view showing an example of a cross-sectional structure of a memory device in the middle of manufacturing of an implementation form.

FIG24 is a cross-sectional view showing an example of a cross-sectional structure of a memory device in the middle of manufacturing of an implementation form.

FIG. 25 is a top view showing an example of the margin of contacts in the platform region of a memory device of an embodiment.

FIG. 26 is a top view showing an example of the margin of the contact in the platform area of the memory device of the comparative example.

FIG27 is a cross-sectional view showing an example of the cross-sectional structure of the lead-out region of the memory device of the embodiment.

The following is an explanation of the implementation form with reference to the drawings. The dimensions and ratios in the drawings may not be the same as in reality.

In addition, in the following description, the same symbols are used for components with roughly the same function and structure. In order to distinguish between components with the same structure, different letters or numbers may be added to the end of the same symbol.

1. Composition

1.1 Memory system

FIG. 1 is a block diagram for explaining the configuration of a memory system of an embodiment. The memory system is a memory device configured in a manner connected to an external host (not shown). The memory system is, for example, a memory card such as an SD ^TM card, a UFS (universal flash storage), or an SSD (solid state drive). The memory system 1 includes a memory controller 2 and a memory device 3.

The memory controller 2 is composed of an integrated circuit such as a SoC (system-on-a-chip). The memory controller 2 controls the memory device 3 based on a request from the host. Specifically, for example, the memory controller 2 writes the data requested to be written by the host into the memory device 3. In addition, the memory controller 2 reads the data requested to be read from the host from the memory device 3 and sends it to the host.

The memory device 3 is a memory for non-volatile memory data. The memory device 3 is, for example, a NAND flash memory.

The communication between the memory controller 2 and the memory device 3 is based on, for example, an SDR (single data rate) interface, a switched DDR (double data rate) interface, or ONFI (Open NAND flash interface).

1.2 Memory device

Next, referring to the block diagram shown in FIG1 , the internal structure of the memory device of the embodiment is described. The memory device 3 has, for example, a memory cell array 10, an instruction register 11, an address register 12, a sequencer 13, a driver module 14, a column decoder module 15, and a sense amplifier module 16.

The memory cell array 10 includes a plurality of blocks BLK0 to BLKn (n is an integer greater than 1). The block BLK is a collection of a plurality of memory cells that can store data non-volatilely, for example, used as a data erase unit. In addition, a plurality of bit lines and a plurality of word lines are provided in the memory cell array 10. Each memory cell is associated with, for example, one bit line and one word line. The detailed structure of the memory cell array 10 will be described later.

The command register 11 stores the command CMD received by the memory device 3 from the memory controller 2. The command CMD includes, for example, a command for the sequencer 13 to execute a read action, a write action, an erase action, etc.

The address register 12 stores the address information ADD received by the memory device 3 from the memory controller 2. The address information ADD includes, for example, a block address BAd, a page address PAd, and a row address CAd. For example, the block address BAd, the page address PAd, and the row address CAd are used to select a block BLK, a word line, and a bit line, respectively.

The sequencer 13 controls the entire operation of the memory device 3. For example, the sequencer 13 controls the driver module 14, the column decoder module 15, and the sense amplifier module 16 based on the instruction CMD stored in the instruction register 11 to perform read operations, write operations, erase operations, etc.

The driver module 14 generates voltages used for read operations, write operations, erase operations, etc. Furthermore, the driver module 14 applies the generated voltage to the signal line corresponding to the selected word line based on, for example, the page address PAd stored in the address register 12.

The row decoder module 15 selects a block BLK in the corresponding memory cell array 10 based on the block address BAd stored in the address register 12. And, the row decoder module 15 transmits, for example, a voltage applied to a signal line corresponding to the selected word line to the selected word line in the selected block BLK.

During the write operation, the sense amplifier module 16 applies the desired voltage to each bit line according to the write data DAT received from the memory controller 2. In addition, during the read operation, the sense amplifier module 16 determines the data stored in the memory cell based on the voltage of the bit line, and transmits the determination result as the read data DAT to the memory controller 2.

1.3 Circuit structure of memory cell array

FIG2 is a circuit diagram showing an example of the circuit structure of a memory cell array provided in a memory device of an implementation form. FIG2 shows one block BLK among a plurality of blocks BLK contained in the memory cell array 10. As shown in FIG2, the block BLK includes, for example, 5 string units SU0~SU4.

Each string unit SU includes a plurality of NAND strings NS respectively associated with bit lines BL0~BLm (m is an integer greater than 1). Each NAND string NS includes, for example, memory cell transistors MT0~MT7, and selection transistors ST1 and ST2. Each memory cell transistor MT includes a control gate and a charge storage film, and non-volatile memory data. The selection transistors ST1 and ST2 are each used to select the string unit SU during various actions.

In each NAND string NS, the memory cell transistors MT0~MT7 are connected in series. The drain of the selection transistor ST1 is connected to the associated bit line BL, and the source of the selection transistor ST1 is connected to one end of the memory cell transistors MT0~MT7 connected in series. The drain of the selection transistor ST2 is connected to the other end of the memory cell transistors MT0~MT7 connected in series. The source of the selection transistor ST2 is connected to the source line SL.

In the same block BLK, the control gates of the memory cell transistors MT0~MT7 are connected to the word lines WL0~WL7 respectively. The gates of the select transistors ST1 in the string units SU0~SU4 are connected to the select gate lines SGD0~SGD4 respectively. The gates of the multiple select transistors ST2 are connected to the select gate line SGS.

Different row addresses are assigned to bit lines BL0~BLm. Each bit line BL is shared by NAND strings NS that are assigned the same row address among multiple blocks BLK. Word lines WL0~WL7 are each set according to each block BLK. The source line SL is shared among multiple blocks BLK, for example.

A collection of multiple memory cell transistors MT connected to a common word line WL in a string unit SU is called a unit group CU. For example, the memory capacity of a unit group CU including memory cell transistors MT each storing 1 bit of data is defined as "1 page of data". The unit group CU may have a memory capacity of more than 2 pages of data depending on the number of bits of data stored in the memory cell transistors MT.

In addition, the circuit structure of the memory cell array 10 of the memory device 3 of the embodiment is not limited to the structure described above. For example, the number of string units SU included in each block BLK can be designed to be any number. The number of memory cell transistors MT and selection transistors ST1 and ST2 included in each NAND string NS can be designed to be any number respectively.

1.4 Structure of memory cell array

The following is an example of the structure of a memory cell array provided in a memory device of an implementation form. In addition, in the following referenced figures, the X direction corresponds to the extension direction of the word line WL. The Y direction corresponds to the extension direction of the bit line BL. The XY plane corresponds to the surface of the semiconductor substrate 20 used to form the memory device 3. The Z direction (corresponding to the first direction) corresponds to the vertical direction relative to the XY plane. In the top view, hatching is appropriately added for easy observation of the figure. The hatching added to the top view is not necessarily related to the material or characteristics of the constituent element to which the hatching is added. In the cross-sectional view, the diagram of the constituent is appropriately omitted for easy observation of the figure.

1.4.1 Overview of floor plan

FIG3 is a top view showing an example of the plane layout of the memory cell array provided in the memory device of the embodiment. In FIG3, the area corresponding to the four blocks BLK0 to BLK3 is shown. As shown in FIG3, the plane layout of the memory cell array 10 is divided into a memory area MA and lead areas HA1 and HA2, for example, in the X direction. In addition, the memory cell array 10 includes a plurality of components SLT and SHE.

The memory area MA is arranged between the lead-out area HA1 and the lead-out area HA2. The memory area MA is an area including a plurality of NAND strings NS. The lead-out areas HA1 and HA2 are each an area used for connection between stacked wiring (e.g., word lines WL0 to WL7, and select gate lines SGD and SGS) and the row decoder module 15.

A plurality of components SLT extend in the X direction and are arranged in the Y direction. Each component SLT crosses the memory area MA and the lead areas HA1 and HA2 in the X direction in the boundary area between adjacent blocks BLK. In addition, each component SLT has a structure such as an embedded insulator or a plate-shaped contact. Moreover, each component SLT separates the adjacent multilayer wiring of the component SLT.

A plurality of components SHE extend in the X direction and are arranged in the Y direction. In this example, four components SHE are arranged between adjacent components SLT. Each component SHE crosses the memory area MA in the X direction. Both ends of each component SHE are included in the lead-out areas HA1 and HA2, respectively. In addition, each component SHE has a structure such as an insulator embedded therein. Moreover, each component SHE disconnects the selection gate line SGD adjacent to the component SHE.

In the above-described planar layout of the memory cell array 10, each area divided by the component SLT corresponds to one block BLK. In addition, each area divided by the components SLT and SHE corresponds to one string unit SU. In addition, in the memory cell array 10, a layout such as that shown in FIG. 3 is repeatedly arranged in the Y direction.

In addition, the plane layout of the memory cell array 10 provided in the memory device 3 of the embodiment is not limited to the layout described above. For example, the number of components SHE arranged between adjacent components SLT can be designed to be an arbitrary number. The number of string units SU formed between adjacent components SLT can be changed based on the number of components SHE arranged between adjacent components SLT.

1.4.2 Memory area

(Floor layout)

FIG4 is a top view showing an example of a detailed planar layout of a memory area MA of a memory device of an implementation form. FIG4 shows an area including a block BLK (i.e., string units SU0-SU4) and two components SLT sandwiching the block. As shown in FIG4, in the memory area MA, a memory cell array 10 includes a plurality of memory pillars MP, a plurality of contacts CV, and a plurality of bit lines BL. In addition, each component SLT includes a contact LI and a spacer SP.

Each memory pillar MP functions as, for example, one NAND string NS. A plurality of memory pillars MP are arranged in a staggered pattern of, for example, 24 rows in the area between two adjacent components SLT. And, for example, counting from the top of the paper, one component SHE overlaps with each of the memory pillars MP in the 5th row, the memory pillars MP in the 10th row, the memory pillars MP in the 15th row, and the memory pillars MP in the 20th row.

A plurality of bit lines BL extend in the Y direction and are arranged in the X direction. Each bit line BL is arranged to overlap with at least one memory pillar MP for each string unit SU. In the example of FIG. 4 , two bit lines BL are arranged to overlap with one memory pillar MP. One bit line BL among the plurality of bit lines BL overlapping with the memory pillar MP is electrically connected to the corresponding one memory pillar MP via a contact CV.

For example, the memory pillar MP in contact with the component SHE and the contact CV between the bit line BL are omitted. In other words, the contact CV between the memory pillar MP in contact with two different selection gate lines SGD and the bit line BL is omitted. The number and arrangement of the memory pillars MP or components SHE between adjacent components SLT are not limited to the configuration described using FIG. 4 and can be appropriately changed. The number of bit lines BL overlapping each memory pillar MP can be designed to be an arbitrary number.

The contact LI is a conductor extending in the XZ plane. The spacer SP is an insulator disposed on the side of the contact LI. In other words, the contact LI is surrounded by the spacer SP when viewed from above.

(Section structure)

FIG5 shows an example of a cross-sectional structure of a memory area MA of a memory device of an implementation form, and is a cross-sectional view along the V-V line of FIG4. As shown in FIG5, the memory cell array 10 further includes a semiconductor substrate 20, conductive layers 21 to 26, and insulating layers 30 to 37.

The semiconductor substrate 20 is, for example, a P-type semiconductor. An insulating layer 30 is provided on the upper surface of the semiconductor substrate 20. The semiconductor substrate 20 and the insulating layer 30 include circuits not shown. The circuits included in the semiconductor substrate 20 and the insulating layer 30 correspond to the column decoder module 15 or the sense amplifier module 16, etc. A conductive layer 21 (corresponding to the third conductive layer) is provided on the upper surface of the insulating layer 30.

The conductive layer 21 is, for example, a plate-shaped conductive body extending along the XY plane. The conductive layer 21 is used as a source line SL. The conductive layer 21 includes, for example, silicon doped with phosphorus.

On the upper surface of the conductive layer 21, the insulating layer 31 and the conductive layer 22 are sequentially stacked. The conductive layer 22 is formed into a plate shape extending along the XY plane. The conductive layer 22 is used as a selection gate line SGS. The conductive layer 22 contains, for example, tungsten. The insulating layer 31 contains, for example, silicon oxide.

On the upper surface of the conductive layer 22, the insulating layer 32 and the conductive layer 23 (corresponding to the first conductive layer) are alternately stacked in sequence. The conductive layer 23 is formed into a plate shape extending along the XY plane, for example. The stacked multiple conductive layers 23 are used as word lines WL0~WL3 in sequence from the side of the semiconductor substrate 20. The conductive layer 23 includes, for example, tungsten. The insulating layer 32 includes, for example, silicon oxide.

An insulator layer 33 is provided on the upper surface of the topmost conductive layer 23. The film thickness of the insulator layer 33 is thicker than that of the insulator layer 32. The insulator layer 33 includes, for example, silicon oxide.

On the upper surface of the insulating layer 33, the insulating layer 34 and the conductive layer 24 (corresponding to the second conductive layer) are alternately stacked in sequence. The conductive layer 24 is formed into a plate shape extending along the XY plane. The stacked multiple conductive layers 24 are used as word lines WL4 to WL7 in sequence from the side of the semiconductor substrate 20. The conductive layer 24 includes, for example, tungsten. The insulating layer 34 includes, for example, silicon oxide.

On the upper surface of the topmost conductive layer 24, an insulating layer 35, a conductive layer 25, and an insulating layer 36 are sequentially stacked. The conductive layer 25 is formed into a plate shape extending along the XY plane, for example. The conductive layer 25 is used as a selection gate line SGD. The conductive layer 25 includes, for example, tungsten. The insulating layers 35 and 36 include, for example, silicon oxide.

On the upper surface of the insulating layer 36, the conductive layer 26 is provided via the insulating layer 37. The conductive layer 26 is formed into a line extending in the Y direction, for example, and is used as the bit line BL. That is, in an area not shown, a plurality of conductive layers 26 are arranged in the X direction. The conductive layer 26 includes, for example, copper. The insulating layer 37 covers the conductive layer 26. The insulating layer 37 includes, for example, silicon oxide.

Each memory pillar MP includes a bottom BMP (corresponding to the 4th part), a lower LMP (corresponding to the 1st part), a junction JMP (corresponding to the 3rd part), and an upper UMP (corresponding to the 2nd part). The bottom BMP is disposed in the conductive layer 21. The lower LMP is connected to the upper end of the bottom BMP and extends in the Z direction in a manner intersecting the conductive layers 22 and 23. The junction JMP is connected to the upper end of the lower LMP and is disposed in the insulating layer 33. The upper UMP is connected to the upper end of the junction JMP and extends in the Z direction in a manner intersecting the conductive layers 24 and 25. The upper end of the upper UMP is aligned with the upper surface of the insulating layer 36.

The cross-sectional area (XY cross-sectional area) of the bottom BMP cut in the XY plane is larger than the XY cross-sectional area of the lower end of the lower LMP. The XY cross-sectional area of the junction JMP is larger than the XY cross-sectional area of the upper end of the lower LMP and the XY cross-sectional area of the lower end of the upper UMP.

The extension lines of the side surface of the bottom BMP and the side surface of the lower LMP are offset from each other and do not coincide. The extension lines of the side surface of the junction JMP and the side surface of the lower LMP, as well as the extension lines of the side surface of the upper UMP, are offset from each other and do not coincide. This offset of the side surface is not limited to the YZ section shown in Figure 5, but also occurs in any section including the Z direction.

In addition, each memory pillar MP includes, for example, a core film 40, a semiconductor film 41, and a laminate film 42. The core film 40 extends in the Z direction. For example, the upper end of the core film 40 is located above the conductive layer 25, and the lower end of the core film 40 is located in the same layer as the conductive layer 21. The semiconductor film 41 covers the periphery of the core film 40. In the bottom BMP, the side surface of the semiconductor film 41 is in contact with the conductive layer 21. The laminate film 42 covers the side surface and bottom surface of the semiconductor film 41 except for the portion where the semiconductor film 41 contacts the conductive layer 21. The core film 40 includes an insulator such as silicon oxide. The semiconductor film 41 includes, for example, silicon.

The portion where the memory pillar MP intersects with the conductive layer 22 functions as a selection transistor ST2. The portion where the memory pillar MP intersects with one conductive layer 23 or one conductive layer 24 functions as a memory cell transistor MT. The portion where the memory pillar MP intersects with the conductive layer 25 functions as a selection transistor ST1.

A columnar contact CV is provided on the upper surface of the semiconductor film 41 in the memory pillar MP. In the illustrated area, one contact CV corresponding to one of the two memory pillars MP is shown in each cross-sectional area divided by the components SLT and SHE. In the memory area MA, in the memory pillar MP that does not overlap with the component SHE and is not connected to the contact CV, the corresponding contact CV is connected in the unillustrated area.

One conductive layer 26, that is, one bit line BL is connected to the upper surface of the contact CV. One conductive layer 26 is connected to one contact CV in each space divided by the components SLT and SHE. That is, in each conductive layer 26, the memory pillar MP disposed between the adjacent components SLT and SHE is electrically connected to the memory pillar MP disposed between two adjacent components SHE.

The component SLT separates the conductive layers 22 to 25. The contact LI in the component SLT is arranged along the spacer SP. The upper end of the contact LI is located between the conductive layer 25 and the conductive layer 26. The lower end of the contact LI is connected to the conductive layer 21. The spacer SP is arranged between the contact LI and the conductive layer 22 to 25. The contact LI and the conductive layer 22 to 25 are separated and insulated by the spacer SP.

Component SHE separates the conductive layer 25. The upper end of component SHE is located in a layer between conductive layer 25 and conductive layer 26. The lower end of component SHE is located in a layer between the uppermost conductive layer 24 and conductive layer 25. Component SHE includes an insulator such as silicon oxide. The upper end of component SHE may be aligned with or not aligned with the upper end of component SLT. Furthermore, the upper end of component SHE may be aligned with or not aligned with the upper end of memory pillar MP. Furthermore, the number of each conductive layer 22~25 may be arbitrary. For example, when a plurality of conductive layers 25 are provided, the lower end of the component SHE is located between the uppermost conductive layer 24 and the lowermost conductive layer 25. That is, the lower end of the component SHE becomes deeper according to the number of conductive layers 25.

FIG6 shows an example of a cross-sectional structure of a memory pillar of a memory device of an embodiment, and is a cross-sectional view along the VI-VI line of FIG5. More specifically, FIG6 shows a cross-sectional structure of a memory pillar MP in a layer parallel to the XY plane and including the conductive layer 23. As shown in FIG6, the laminated film 42 includes, for example, a tunnel insulating film 43, a charge storage film 44, and a blocking insulating film 45.

In a cross section including the conductive layer 23, the core film 40 is provided, for example, at the center of the memory pillar MP. The semiconductor film 41 surrounds the side of the core film 40. The tunnel insulating film 43 surrounds the side of the semiconductor film 41. The charge storage film 44 surrounds the side of the tunnel insulating film 43. The blocking insulating film 45 surrounds the side of the charge storage film 44. The conductive layer 23 surrounds the side of the blocking insulating film 45.

The semiconductor film 41 is used as a channel (current path) for the memory cell transistors MT0 to MT7 and the selection transistors ST1 and ST2. The tunnel insulating film 43 and the blocking insulating film 45 each include, for example, silicon oxide. The charge storage film 44 has a function of storing charge and includes, for example, silicon nitride. Thus, each memory pillar MP can function as a NAND string NS.

1.4.3 Lead-out area

(Floor layout)

In the memory device 3 of the embodiment, the structure of the even-numbered blocks BLK in the lead-out area HA1 is similar to the structure of the odd-numbered blocks BLK in the lead-out area HA2. Furthermore, the structure of the even-numbered blocks BLK in the lead-out area HA2 is similar to the structure of the odd-numbered blocks BLK in the lead-out area HA1.

Specifically, for example, the plane layout of block BLK0 in lead-out area HA2 is the same as the layout in which the structure of block BLK1 in lead-out area HA1 is reversed in the X direction and the Y direction. The plane layout of block BLK1 in lead-out area HA2 is the same as the layout in which the structure of block BLK0 in lead-out area HA1 is reversed in the X direction and the Y direction. Hereinafter, even-numbered blocks BLK are referred to as "BLKe", and odd-numbered blocks BLK are referred to as "BLKo".

FIG. 7 is a top view showing an example of a detailed planar layout of a lead-out area of a memory device of an implementation form. In FIG. 7, in addition to the area corresponding to the adjacent blocks BLKe and BLKo in the lead-out area HA1, a portion of the nearby memory area MA is also shown. Below, based on the planar layout of the blocks BLKe and BLKo in the lead-out area HA1 shown in FIG. 7, the planar layout of the block BLK in the lead-out areas HA1 and HA2 is described.

As shown in FIG. 7 , in the lead-out area HA1, the selection gate line SGS, the word lines WL0 to WL7, and the selection gate line SGD each have a portion (platform portion) that does not overlap with the upper wiring layer (conductive layer) in the stacked wiring. In addition, the memory cell array 10 in the lead-out area HA1 includes a plurality of contacts CC and a plurality of support pillars HR.

The shape of the portion of the lead-out area HA1 that does not overlap with the upper wiring layer is similar to a step, a terrace, a rimstone, etc. Specifically, steps are set between the selection gate line SGS and the word line WL0, between the word line WL0 and the word line WL1, ... between the word line WL6 and the word line WL7, and between the word line WL7 and the selection gate line SGD. In the example of FIG. 7, the end of the word lines WL0 to WL7 is set to have a single step in the Y direction, and a two-row step shape with multiple steps in the X direction is formed.

In the area where the lead-out area HA1 overlaps with the block BLKe, a plurality of contacts CC are respectively disposed on the platform portion of the selection gate line SGS, the word lines WL0~WL7, and the selection gate lines SGD0~SGD4. In addition, in the area where the lead-out area HA1 overlaps with the block BLKo, a plurality of contacts CC relative to the stacked wiring are omitted.

On the other hand, although not shown in the figure, in the area where the lead-out area HA2 overlaps with the block BLKo, a plurality of contacts CC are respectively set on the platform portion of each of the selection gate line SGS, the word lines WL0~WL7, and the selection gate lines SGD0~SGD4. In addition, in the area where the lead-out area HA2 overlaps with the block BLKe, a plurality of contacts CC relative to the stacked wiring are omitted.

The selection gate line SGS, word lines WL0~WL7, and selection gate lines SGD0~SGD4 are electrically connected to the column decoder module 15 via the corresponding contact CC. That is, a voltage is applied to the selection gate line SGS, word lines WL0~WL7, and selection gate lines SGD0~SGD4 from, for example, the contact CC configured in either of the lead-out areas HA1 and HA2. In addition, in each wiring layer, the contact CC can also be connected to each of the lead-out areas HA1 and HA2. In this case, for example, a voltage is applied to the word line WL from both sides of the contact CC in the lead-out area HA1 and the contact CC in the lead-out area HA2.

In the lead-out areas HA1 and HA2, a plurality of support guide posts HR are appropriately arranged in areas other than the portions forming the component SLT and the contact CC.

(Section structure)

FIG8 shows an example of the cross-sectional structure of the lead-out region and the memory region of the memory cell array of the memory device of the embodiment, and is a cross-sectional view along the VIII-VIII line of FIG7. In addition, in FIG8, for the convenience of explanation, the structure below the conductive layer 21 is omitted and illustrated.

As shown in FIG8 , a plurality of conductive layers 27 are provided in the lead-out area HA1. Also, the end of the conductive layer 22 corresponding to the selection gate line SGS, the ends of the plurality of conductive layers 23 and 24 corresponding to the word line WL, and the end of the conductive layer 25 corresponding to the selection gate line SGD are provided in a stepped shape. An insulating layer 38 is provided on the upper surface of the platform area of the conductive layers 22 and 23. An insulating layer 39 is provided on the upper surface of the platform area of the conductive layer 24.

A plurality of contacts CC are respectively disposed on the platform portion of each of the selection gate line SGS, the word lines WL0~WL7, and the selection gate line SGD. A conductive layer 27 is disposed on each contact CC. Each conductive layer 27 is electrically connected to the column decoder module 15, and is included in, for example, the same layer as the conductive layer 26. Thus, each of the conductive layers 22~25 is electrically connected to the column decoder module 15 via the contact CC and the conductive layer 27. Each of the conductive layers 22~25 can also be electrically connected to the column decoder module 15 via a wiring layer (not shown) above the conductive layer 27.

Each support guide post HR has a structure in which an insulator is embedded. The support guide post HR includes a bottom BHR, a lower LHR, a junction JHR, and an upper UHR. The bottom BHR is disposed in the conductive layer 21. The lower LHR is connected to the upper end of the bottom BHR, and extends in the Z direction between the insulator layer 31 and the insulator layer 33. The junction JHR is disposed in the insulator layer 33. The upper UHR is connected to the upper end of the junction JHR, and extends in the Z direction between the insulator layer 33 and the insulator layer 36. Each support guide post HR may have a gap VO separated from each other at the bottom BHR, the lower LHR, the junction JHR, and the upper UHR.

The XY cross-sectional area of the bottom BHR is larger than the XY cross-sectional area of the lower end of the lower LHR. The XY cross-sectional area of the junction JHR is larger than the XY cross-sectional area of the upper end of the lower LHR and the XY cross-sectional area of the lower end of the upper UHR.

The extension lines of the side surface of the bottom BHR and the side surface of the lower LHR are offset from each other and are not consistent. The extension lines of the side surface of the junction JHR and the side surface of the lower LHR and the side surface of the upper UHR are offset from each other and are not consistent. This kind of side surface offset is not limited to the XZ section shown in Figure 8, but also occurs in any section including the Z direction.

The support guide pins HR are classified into three types of support guide pins HRa, HRb, and HRc according to the positions where they are set. The support guide pin HRa is a support guide pin HR set at a position overlapping with the conductive layer 25 when viewed in the Z direction. The support guide pin HRb is a support guide pin HR set at a position overlapping with the platform area of the conductive layer 24 or the platform area of the top conductive layer 23 when viewed in the Z direction. The support guide pin HRc is a support guide pin HR set at a position overlapping with the platform area of the conductive layer 24 other than the top conductive layer 24 when viewed in the Z direction. In the following, when the support guide pins HRa, HRb, and HRc are not distinguished from each other, they are simply recorded as "support guide pin HR".

The lower portion LHR of the support guide post HRa extends in the Z direction in a manner intersecting the conductive layers 22 and 23. The joint portion JHR of the support guide post HRa (corresponding to the third insulating member) is connected to the upper end of the lower portion LHR of the support guide post HRa (corresponding to the fourth insulating member). The upper portion UHR of the support guide post HRa (corresponding to the fifth insulating member) extends in the Z direction in a manner intersecting the conductive layers 24 and 25. The upper end of the upper portion UHR of the support guide post HRa is aligned with the upper surface of the insulating layer 36.

The lower portion LHR of the support guide post HRb extends in the Z direction in a manner intersecting the conductive layers 22 and 23. The joint portion JHR of the support guide post HRb is connected to the upper end of the lower portion LHR of the support guide post HRb. The upper portion UHR of the support guide post HRb extends in the Z direction to the lower surface of the conductive layer 24 or 25 one layer above the corresponding platform area. That is, the upper portion UHR of the support guide post HRb does not intersect the conductive layers 24 and 25 above the corresponding platform area.

The lower portion LHR of the support guide post HRc (corresponding to the second insulating member) extends in the Z direction to the lower surface of the conductive layer 23 one layer above the corresponding platform area. That is, the lower portion LHR of the support guide post HRc does not intersect with the conductive layer 23 above the corresponding platform area. The junction JHR of the support guide post HRc (corresponding to the first insulating member) is separated from the upper end of the lower portion LHR of the support guide post HRc. The upper portion UHR of the support guide post HRc extends in the Z direction to the lower surface of the lowest conductive layer 25. That is, the upper portion UHR of the support guide post HRc does not intersect with the conductive layers 24 and 25.

2. Manufacturing method of memory device

Figures 9 to 24 each show an example of a planar layout or cross-sectional structure of a memory device of an implementation form during manufacturing. The cross-sectional structure shown corresponds to Figure 8. Below, an example of the manufacturing steps of the memory cell array 10 in the memory device 3 is described.

First, as shown in FIG. 9 , an insulating layer 30 is formed on the upper surface of the semiconductor substrate 20. On the upper surface of the insulating layer 30, a semiconductor layer 51, an insulating layer 52, a sacrificial layer 53, an insulating layer 54, and a semiconductor layer 55 are sequentially stacked. The semiconductor layers 51 and 55 include, for example, polycrystalline silicon. The insulating layers 52 and 54 include, for example, silicon oxide. The sacrificial layer 53 includes, for example, amorphous silicon. Next, a mask is formed by photolithography or the like to open the area corresponding to the bottom BMP of the memory pillar MP and the bottom BHR of the support pillar HR. Then, by anisotropic etching using the mask, a plurality of holes H0 and H1 are formed, for example, through the semiconductor layer 55, the insulator layer 54, the sacrificial layer 53, and the insulator layer 52. The holes H0 and H1 correspond to the bottom BMP of the memory pillar MP and the bottom BHR of the support pillar HR, respectively. In the bottom of each of the plurality of holes H0 and H1, a portion of the semiconductor layer 51 is exposed. For the anisotropic etching step, for example, RIE (Reactive Ion Etching) is used.

Next, as shown in FIG. 10 , a sacrificial layer 56 is embedded inside the plurality of holes H0 and H1. The sacrificial layer 56 includes, for example, carbon. The upper surface of the laminated structure is flattened by, for example, CMP (Chemical Mechanical Polishing). Thereafter, an insulating body layer 31 and a sacrificial layer 57 are sequentially laminated on the upper surfaces of the semiconductor layer 55 and the sacrificial layer 56. On the upper surface of the sacrificial layer 57, an insulating body layer 32 and a sacrificial layer 58 are repeatedly laminated in sequence. On the upper surface of the uppermost sacrificial layer 58, an insulating body layer 33 is formed. The sacrificial layers 57 and 58 include, for example, silicon nitride.

Next, as shown in FIG. 11 , a mask is formed by photolithography or the like to open the region corresponding to the lower portion LMP of the memory guide pillar MP and the lower portion LHR of the support guide pillar HR. And, by anisotropic etching using the mask, a plurality of holes H2 and H3 are formed, for example, through the insulating layers 31, 32, and 33 and the sacrificial layers 57 and 58. The holes H2 and H3 correspond to the lower portion LMP of the memory guide pillar MP and the lower portion LHR of the support guide pillar HR, respectively. At the bottom of each of the plurality of holes H2 and H3, a portion of the sacrificial layer 56 is exposed. In addition, in the anisotropic etching step, the sacrificial layer 56 functions as a stopper material having an etching rate lower than that of the insulating body layers 31, 32, and 33, and the sacrificial layers 57 and 58. For the anisotropic etching step, for example, RIE is used.

Next, as shown in FIG. 12 , the sacrificial layer 56 is removed through the plurality of holes H2 and H3. The plurality of holes H2 are covered by the anti-etching agent layer 59. And, the plurality of holes H3 are embedded by the insulating body layer 60. The insulating body layer 60 includes, for example, silicon oxide. Inside the insulating body layer 60, for example, separate gaps VO are formed in the region corresponding to the bottom BHR and the region corresponding to the lower LHR. After the plurality of holes H3 are embedded by the insulating body layer 60, the anti-etching agent layer 59 is removed.

Next, as shown in FIG. 13 , a plurality of holes H2 are embedded by a sacrificial layer 61. The sacrificial layer 61 includes, for example, carbon. The upper surface of the laminate structure is planarized by, for example, CMP. Thereafter, an insulating layer 62 is formed on the upper surface of the insulating layers 33 and 60 and the sacrificial layer 61. The insulating layer 62 includes, for example, silicon oxide.

Next, as shown in FIG. 14, the ends of the sacrificial layers 57 and 58 of the stack are processed into a step shape in the lead-out areas HA1 and HA2. By this step, the portion above the platform area in the insulator layer 60 corresponding to the support guide post HRc is removed. Afterwards, the step portion in the lead-out areas HA1 and HA2 is embedded by the insulator layer 38. The upper surface of the stacked structure is flattened by, for example, CMP.

Next, as shown in FIG. 15 , a mask is formed by photolithography or the like to open the region corresponding to the junction JHR of the support guide post HR. And, by anisotropic etching using the mask, a plurality of holes H4 are formed, for example, through the insulator layer 62. The hole H4 corresponds to the junction JHR of the support guide post HR. At the bottom of each of the plurality of holes H4 corresponding to the support guide posts HRa and HRb, a portion of the insulator layer 60 is exposed. At the bottom of each of the plurality of holes H4 corresponding to the support guide post HRc, a portion of the insulator layer 38 is exposed. In the anisotropic etching step, for example, RIE is used.

Next, as shown in FIG. 16 , the sacrificial layer 61 is exposed by etching back the insulating body layer 62. Next, a plurality of holes H5 are formed by etching back a portion of the exposed sacrificial layer 61. The hole H5 corresponds to the junction JMP of the memory pillar MP. Thereafter, the plurality of holes H4 and H5 are expanded by, for example, wet etching. Thus, the diameter of each of the plurality of holes H4 and H5 is enlarged. In addition, the bottom of the hole H5 after the wet etching step is located above the sacrificial layer 58, the same as the bottom of the hole H4, for example.

Next, as shown in FIG. 17 , a plurality of holes H4 and H5 are embedded by a sacrificial layer 63. The sacrificial layer 63 includes, for example, carbon. The upper surface of the laminate structure is planarized by, for example, CMP.

Next, as shown in FIG. 18 , an insulating body layer 34 and a sacrificial layer 64 are sequentially stacked on the upper surfaces of the insulating body layers 33 and 38 and the sacrificial layer 63. An insulating body layer 35 and a sacrificial layer 65 are repeatedly stacked on the upper surface of the sacrificial layer 64. An insulating body layer 36 is formed on the upper surface of the uppermost sacrificial layer 65. The sacrificial layers 64 and 65 include, for example, silicon nitride.

Next, as shown in FIG. 19 , a mask is formed by photolithography or the like to open the region corresponding to the upper portion UMP of the memory guide pillar MP and the upper portion UHR of the support guide pillar HR. And, by anisotropic etching using the mask, a plurality of holes H6 and H7 are formed, for example, through the insulating layers 34, 35, and 36 and the sacrificial layers 64 and 65. The holes H6 and H7 correspond to the upper portion UMP of the memory guide pillar MP and the upper portion UHR of the support guide pillar HR, respectively. At the bottom of each of the plurality of holes H6 and H7, a portion of the sacrificial layer 63 is exposed. In addition, in the anisotropic etching step, the sacrificial layer 63 functions as a stopper material having an etching rate lower than that of the insulating body layers 34, 35, and 36, and the sacrificial layers 64 and 65. For the anisotropic etching step, for example, RIE is used.

Next, as shown in FIG. 20 , while the sacrificial layers 61 and 63 are removed through the plurality of holes H6, the sacrificial layer 63 is removed through the plurality of holes H7. The plurality of holes H6 are covered by the anti-etching agent layer 66. And, the plurality of holes H7 are embedded by the insulating body layer 67. The insulating body layer 67 includes, for example, silicon oxide. Inside the insulating body layer 67, for example, separate gaps VO are formed in the region corresponding to the junction JHR and the region corresponding to the upper UHR. After the plurality of holes H7 are embedded by the insulating body layer 67, the anti-etching agent layer 66 is removed.

Next, as shown in FIG. 21 , a blocking insulating film 45, a charge storage film 44, a tunnel insulating film 43, a semiconductor film 41, and a core film 40 are sequentially formed in the plurality of holes H6. The core film 40 is embedded in the plurality of holes H6. Afterwards, a portion of the core film 40 disposed on the upper portion of the hole H6 is removed, and a semiconductor film 41 is formed on the portion. The upper surface of the multilayer structure is flattened by, for example, CMP.

Next, as shown in FIG. 22, the ends of the sacrificial layers 64 and 65 of the stack are processed into a step shape in the lead-out areas HA1 and HA2. By this step, the portion above the platform area in the insulator layer 67 corresponding to the support guide posts HRb and HRc is removed. Thereafter, the step portion in the lead-out areas HA1 and HA2 is embedded by the insulator layer 39. After the upper surface of the stacked structure is flattened by, for example, CMP, the insulator layer 37 is formed. In this way, the support guide posts HRa, HRb, and HRc are formed.

Next, as shown in FIG. 23 , a replacement process is performed. In the replacement process, the replacement process of the source line SL, the replacement process of the selection gate lines SGS and SGD, and the replacement process of the word lines WL0 to WL7 are performed in sequence.

In the replacement process for replacing the source line SL, first, a mask is formed by photolithography or the like to open the region corresponding to the component SLT. Then, by anisotropic etching using the mask, a plurality of slits (not shown) are formed, for example, through the insulating body layers 31 to 37 and each of the sacrificial layers 57, 58, 64, and 65. The sacrificial layer 53 is selectively removed through the slits by, for example, wet etching. Then, the insulating body layers 52 and 54 and a portion of the stacking film 42 are selectively removed through the slits by, for example, wet etching. Furthermore, a semiconductor layer (such as silicon) is embedded in the space between the sacrificial layer 53 and the insulating layers 52 and 54. The semiconductor layer and the semiconductor layers 51 and 55 form a conductive layer 21 that functions as a source line SL. The conductive layer 21 is electrically connected to the semiconductor film 41 by being in contact with the side surface of the semiconductor film 41. In this way, a memory pillar MP is formed.

In the replacement process of replacing word lines WL0 to WL7, the sacrificial layers 57, 58, 64, and 65 are selectively removed through the slits by wet etching with hot phosphoric acid or the like. Furthermore, the conductor is embedded in the space after the sacrificial layers 57, 58, 64, and 65 are removed through the slits. In this step, CVD (Chemical Vapor Deposition) is used, for example, to form the conductor. Thereafter, the conductor formed inside the slits is removed by etching back. Thus, the conductor formed inside the slits is separated into a plurality of conductor layers. Thus, a conductive layer 22 that functions as a selection gate line SGS, a plurality of conductive layers 23 that function as word lines WL0 to WL3, a plurality of conductive layers 24 that function as word lines WL4 to WL7, and a conductive layer 25 that functions as a selection gate line SGD are formed. The conductive layers 22, 23, 24, and 25 formed in this step may also include a barrier metal. In this case, when a conductor is formed after removing the sacrificial layers 57, 58, 64, and 65, for example, titanium nitride is formed as a barrier metal, and then tungsten is formed.

Next, as shown in FIG. 24 , a mask is formed by photolithography or the like to open the regions corresponding to the plurality of contacts CC. And, by anisotropic etching using the mask, a plurality of holes H8 are formed, for example, through each of the insulating layers 32 to 39. The holes H8 correspond to the contacts CC. At the bottom of each of the plurality of holes H8, a portion of the conductive layer 22 to 25 is exposed. In the anisotropic etching step, for example, RIE is used. Thereafter, by embedding the conductor into the hole H8, the contacts CC are formed.

The memory cell array 10 is formed by the manufacturing steps described above. In addition, the manufacturing steps described above are only an example and are not limited thereto. For example, other processing can be inserted between each manufacturing step, and some steps can be omitted or integrated. In addition, each manufacturing step can also be replaced within a possible range.

3. Effects of this implementation form

According to the implementation form, the support conductor HRc has a junction JHR having an XY cross-sectional area larger than that of the upper UHR. A sacrificial layer 63 is embedded in the hole H4 corresponding to the junction JHR. The material of the sacrificial layer 63 is selected to have a lower etching rate than the insulating layers 34, 35, and 36 and the carbon of the sacrificial layers 64 and 65 when the hole H7 corresponding to the upper UHR is formed. Thereby, when the hole H7 is formed, it is possible to suppress the hole H7 from reaching below the sacrificial layer 63. Therefore, in the platform region of the conductive layers 21 and 22, the junction JHR of the support conductor HRc can be suppressed from connecting to the lower LHR. Therefore, the margin of the contact CC in the platform region of the conductive layers 21 and 22 relative to the support conductor HR can be ensured. Below, this effect is explained using Figures 25 and 26.

FIG. 25 is a top view showing an example of a margin of a contact of a memory device of an implementation form. FIG. 26 is a top view showing an example of a margin of a contact of a memory device of a comparative example. The example of FIG. 25 corresponds to a case where a joint JHR is formed between the upper portion UHR and the lower portion LHR of the support guide post HR, whereas the example of FIG. 26 corresponds to a case where a joint JHR is not formed between the upper portion UHR and the lower portion LHR of the support guide post HR. FIG. 25 and FIG. 26 show an example of the positional relationship of the lower portion LHR of the support guide post HR, the upper portion UHR, and the hole H9 corresponding to the contact CC in the platform region of the conductive layer 21 and 22. FIG. 25(A) and FIG. 26(A) show a situation where the positional offset between the lower portion LHR and the upper portion UHR of the support guide post HR is small. FIG. 25(B) and FIG. 26(B) show a situation where the positional offset between the lower portion LHR and the upper portion UHR of the support guide post HR is large.

As shown in FIG. 26(A) and FIG. 26(B), in the comparative example, the hole H7 reaches the platform area of the conductive layers 21 and 22. Thus, when there is a large positional offset between the lower portion LHR and the upper portion UHR of the supporting pillar HR, the margin CM' of the contact CC relative to the supporting pillar HR is smaller than the margin CM. In addition, assuming that the hole H7 corresponding to the contact CC contacts the supporting pillar HR on the upper surface of the platform area of the conductive layers 21 and 22, the hole H7 can reach the conductive layer below the conductive layers 21 and 22 through the supporting pillar HR. In this way, in the comparative example, the possibility of a plurality of word lines WL being short-circuited through the contact CC increases, which is not good.

In this regard, as shown in FIG. 25(A) and FIG. 25(B), in the embodiment, the sacrificial layer 63 is used to prevent the hole H7 from reaching the platform area of the conductive body layers 21 and 22. Thus, regardless of whether there is a positional offset between the lower portion LHR and the upper portion UHR of the supporting pillar HR, the margin CM of the contact CC relative to the supporting pillar HR remains unchanged. Therefore, the possibility of the hole H7 corresponding to the contact CC contacting the supporting pillar HR on the upper surface of the platform area of the conductive body layers 21 and 22 can be suppressed. Therefore, in the embodiment, the possibility of a plurality of word lines WL being short-circuited through the contact CC can be reduced, and the yield of the memory device 3 can be improved.

4. Variations, etc.

In the above-mentioned embodiment, the case where the joint JHR and the upper UHR of the support guide post HRc remain has been described, but it is not limited to this. For example, the joint JHR and the upper UHR of the support guide post HRc may not be manufactured.

FIG27 is a cross-sectional view showing an example of the cross-sectional structure of the lead-out region of the memory device of the variation. FIG27 corresponds to FIG8 of the implementation form.

As shown in FIG. 27 , among the support guide posts HR arranged in the X direction, the support guide posts HRc' separated from the support guide post HRb having the upper UHR connected to the conductive layer 24 by a plurality of (for example, two) support guide posts may not have the junction JHR and the upper UHR. The reason is that, assuming that the support guide post HRc has the junction JHR and the upper UHR, the junction JHR and the upper UHR do not have the function of supporting the layered structure during the replacement process of the conductive layers 22 to 25.

In addition, among the support guide posts HR arranged in the X direction, a plurality of (for example, two) support guide posts HRc adjacent to the support guide post HRb having the upper UHR penetrating the conductive layer 24 remain in the form of a joint JHR and an upper UHR. The reason is that among the plurality of support guide posts HR processed simultaneously, the support guide posts HR located at the end may fail to meet the requirements of size and shape due to deterioration of processability. In this way, by leaving the plurality of (for example, two) support guide posts HRc adjacent to the support guide post HRb having the upper UHR penetrating the conductive layer 24 as the end of the plurality of support guide posts HR, the deterioration of processability of the upper UHR of the support guide post HRb having the function of supporting the laminated structure during the replacement process can be suppressed.

In addition, in the above-mentioned embodiment, the case where a gap VO is formed in the support guide post HR is used as an example for explanation, but it is not limited to this. For example, the support guide post HR can also be set in a manner that the gap VO is not formed inside.

In addition, in the above-mentioned embodiment, the case where the component SLT has a structure including the contact LI has been used as an example for explanation, but it is not limited to this. For example, the component SLT may also have a structure that does not include the contact LI but is embedded by an insulator.

In addition, in each of the above-mentioned embodiments, the memory device 3 has been described as having a structure formed on one chip, but it is not limited to this. For example, the memory device 3 may also be a structure in which a chip having a sense amplifier module 16 and the like is bonded to a chip having a memory cell array 10.

Although several embodiments of the present invention have been described, these embodiments are provided as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms and can be omitted, replaced, or modified in various ways without departing from the main idea of the invention. These embodiments or their variations are included in the scope or main idea of the invention and are included in the invention described in the scope of the patent application and its equivalent.

References to related applications

This application enjoys the priority of the Japanese Patent Application No. 2022-122636 (filing date: August 1, 2022). This application includes all the contents of the basic application by reference to the basic application

21: Conductive layer

22: Conductive layer

23: Conductive layer

24: Conductive layer

25: Conductive layer

26: Conductive layer

27: Conductive layer

31: Insulating layer

32: Insulating layer

33: Insulating layer

34: Insulating layer

35: Insulating body layer

36: Insulating body layer

37: Insulating layer

38: Insulating layer

39: Insulating layer

BHR: bottom

BL: Bit Line

CC: Contact

CV: Contact

HRa: Support guide post

HRb: Support guide post

HRc: Support guide post

JHR: Joint

LHR: Lower part

MP: memory guide pin

SGD: Select Gate Line

SGS: Selecting gate lines

SL: Source line

UHR: Upper

VO:Void

WL0~WL7: character line

Claims (17)

A memory device, comprising: a first conductive layer and a second conductive layer, which are arranged in a first direction and spaced apart from each other; a memory pillar, which extends in the first direction in a region where the second conductive layer overlaps the first conductive layer when viewed in the first direction, and the first portion crossing the first conductive layer functions as a first memory cell, and the second portion crossing the second conductive layer functions as a second memory cell; a first insulating A member disposed between the first conductive layer and the second conductive layer in a region where the second conductive layer does not overlap with the first conductive layer when viewed in the first direction; and a second insulating member extending in the first direction in a manner intersecting with the first conductive layer in a region where the second conductive layer overlaps with the first conductive layer when viewed in the first direction; and the upper end of the second insulating member is separated from the lower end of the first insulating member. The memory device of claim 1 further comprises: a third insulating member disposed between the first conductive layer and the second conductive layer in a region where the second conductive layer overlaps with the first conductive layer when viewed in the first direction; and a fourth insulating member extending in the first direction in a region where the third insulating member overlaps with the first conductive layer when viewed in the first direction in a manner intersecting the first conductive layer; and the upper end of the fourth insulating member is connected to the lower end of the third insulating member. The memory device of claim 2 further comprises: a fifth insulating member, which extends in the first direction in a manner crossing the second conductive layer in the region overlapping with the third insulating member when viewed in the first direction, and the lower end of the fifth insulating member is connected to the upper end of the third insulating member. A memory device as claimed in claim 1, wherein the cross-sectional area of the first insulating member along the first plane intersecting the first direction is greater than the cross-sectional area of the second insulating member along the first plane. A memory device as claimed in claim 2, wherein the cross-sectional area of the third insulating member along the first plane intersecting the first direction is greater than the cross-sectional area of the fourth insulating member along the first plane. A memory device as claimed in claim 3, wherein the cross-sectional area of the third insulating member along the first plane intersecting the first direction is greater than the cross-sectional area of the fifth insulating member along the first plane. A memory device as claimed in claim 1, wherein the first insulating member has a first gap inside, and the second insulating member has a second gap inside, and the second gap is separated from the first gap. A memory device as claimed in claim 2, wherein the third insulating member has a third gap inside, the fourth insulating member has a fourth gap inside, and the fourth gap is separated from the third gap. A memory device as claimed in claim 3, wherein the third insulating member has a third gap inside, and the fifth insulating member has a fifth gap inside, and the fifth gap is separated from the third gap. A memory device as claimed in claim 1, wherein the memory guide further includes a third part connecting the first part and the second part, the cross-sectional area of the third part along the first plane intersecting the first direction is larger than the cross-sectional area of the first part along the first plane, and the cross-sectional area of the third part along the first plane is larger than the cross-sectional area of the second part along the first plane. The memory device of claim 1 further comprises: a third conductive layer, which is arranged in the first direction spaced apart from the first conductive layer on the opposite side of the first conductive layer and the second conductive layer, and the memory pillar further comprises a fourth portion connected to the third conductive layer and the first portion, and the cross-sectional area of the fourth portion along the first plane intersecting the first direction is larger than the cross-sectional area of the first portion along the first plane. The memory device of claim 11 further comprises: a sixth insulating member connected to the third conductive layer and connected to the second insulating member, and the cross-sectional area of the sixth insulating member along the first surface is larger than the cross-sectional area of the second insulating member along the first surface. A memory device as claimed in claim 1, wherein the side surface of the first insulating member and the extension lines of the side surface of the second insulating member are offset from each other. A memory device as claimed in claim 2, wherein the side surface of the third insulating member and the extension lines of the side surface of the fourth insulating member are offset from each other. A memory device as claimed in claim 3, wherein the side surface of the third insulating member and the extension lines of the side surface of the fifth insulating member are offset from each other. A memory device as claimed in claim 10, wherein the side surface of the third part and the extension line of the side surface of the first part are offset from each other, and the side surface of the third part and the extension line of the side surface of the second part are offset from each other. The memory device of claim 1 further comprises: a contact point, which is connected to the first conductive layer in a region where the second conductive layer does not overlap with the first conductive layer when viewed in the first direction, and does not overlap with the second insulating member, and extends in the first direction in a manner that crosses the second conductive layer.