TWI855654B - Voltage detector device having trimming mechanism and voltage detection method - Google Patents

Abstract

A voltage detection method includes: outputting a corresponding one of voltages to be an input voltage according to a clock signal, a first detection signal, a reset signal, and first bits; generating the reset signal according to the clock signal and currents, in which the voltages and the currents are generated based on a power voltage; comparing the input voltage with a reference voltage to generate a second detection signal, and generating the first detection signal according to the second detection signal and an enable signal; and adjusting, by a digital circuit, the first bits according to the second detection signal during a trimming phase to determine the first bits, outputting, by the digital circuit, the first bits and resetting the digital circuit according to the first detection signal during a voltage detection phase.

Description

Voltage detection device and voltage detection method with trimming mechanism

This case is about a voltage detection device, and in particular, about a voltage detection device and a voltage detection method with a trimming mechanism.

In existing electronic devices, if the power supply voltage or its internal voltage drops momentarily due to sudden power on/off, the circuit in the electronic device may fail or operate incorrectly. In existing technologies, a voltage detection device compares a reference voltage with the power supply voltage (or a voltage generated based on the power supply voltage) to confirm whether the power supply voltage has excessive voltage drop. Since the reference voltage may be offset due to process variation, in these technologies, the voltage detection device uses a high-precision bias circuit to generate a reference voltage or an additional correction circuit to correct the reference voltage, which will significantly increase the circuit cost.

In some implementations, one of the purposes of this case is to provide a voltage detection device and a voltage detection method with a trimming mechanism to improve the deficiencies of the prior art.

In some embodiments, the voltage detection device includes a reference voltage selection circuit, a reset signal generation circuit, a voltage detector, and a digital circuit. The reference voltage selection circuit outputs a voltage corresponding to one of a plurality of first voltages of a preset voltage as an input voltage according to a clock signal, a first detection signal, a reset signal, and a plurality of first bits, wherein the first voltages are generated based on a power supply voltage. The reset signal generation circuit generates the reset signal according to the clock signal and a plurality of currents, wherein the currents are generated based on the power supply voltage. The voltage detector compares the input voltage with a reference voltage to generate a second detection signal, and generates the first detection signal according to the second detection signal and an enable signal. The digital circuit adjusts the first bits according to the second detection signal during a trimming period to determine the values of the first bits, and outputs the first bits during a voltage detection period and selectively resets them according to the first detection signal.

In some embodiments, the voltage detection method includes the following operations: outputting a voltage corresponding to one of a plurality of first voltages as an input voltage according to a clock signal, a first detection signal, a reset signal and a plurality of first bits, wherein the first voltages are generated based on a power voltage; generating the reset signal according to the clock signal and a plurality of currents, wherein the currents are generated based on the power voltage; ; compare the input voltage with a reference voltage to generate a second detection signal, and generate the first detection signal according to the second detection signal and an enable signal; and adjust the first bits according to the second detection signal during a trimming period by a digital circuit to determine the values of the first bits, and output the first bits during a voltage detection period and selectively reset them according to the first detection signal.

The features, implementation and effects of this case are described in detail below with reference to the diagrams for a preferred embodiment.

100: Chip system

110: Voltage detection device

111: Reference voltage selection circuit

112: Reset signal generating circuit

113: Voltage detector

114: Digital Circuits

120: Low voltage differential regulator

130: Pulse generator

140: Bias generator

301: Trigger

301A: Logical Gate

301B: Inverter

302[0]~302[M-1]: Flip-flop

303,304:Multiplexer

401: Clock flag generator

402: Power-on flag generator

402A: Buffer

403:Logical Gate

411: Delay circuit

412:Logical Gate

413: Switching capacitor circuit

413A: Inverter

501: Comparator

502:Logical Gate

800: Voltage detection method

B1[0]~B1[M-1],B2[0]~B2[M-1]: bits

C1,C2: Capacitors

CKD:Signal

CKF: Clock flag signal

CLK: clock signal

EN: Enable signal

I1,I2: current

N1, N2: Node

PSF: Power-on flag signal

S1:Signal

S610, S620, S630, S640, S650: Operation

S710, S720, S730, S740: Operation

S810, S820, S830, S840: Operation

SD1: Reset signal

SP1, SPT: Detection signal

SS: Switching signal

ST: trigger signal

SW1: switch

VD: Default voltage

VDD: power supply voltage

VDD[0]~VDD[N-1],VDD[i]: voltage

VIN: Input voltage

VREF: reference voltage

FIG. 1 is a schematic diagram of a chip system according to some embodiments of the present invention; FIG. 2 is a schematic diagram of a voltage detection device in FIG. 1 according to some embodiments of the present invention; FIG. 3 is a schematic diagram of a reference voltage selection circuit in FIG. 2 according to some embodiments of the present invention; FIG. 4A is a schematic diagram of a reset signal generation circuit in FIG. 2 according to some embodiments of the present invention; FIG. 4B is a schematic diagram of a clock flag generator in FIG. 4A according to some embodiments of the present invention; FIG. 4C is a schematic diagram of a clock signal generator in FIG. 4B according to some embodiments of the present invention; FIG. 〔FIG. 5〕is a schematic diagram of the power-on flag generator in FIG. 2 according to some embodiments of the present invention; 〔FIG. 6〕is a flow chart of multiple operations performed by the voltage detection device in FIG. 2 during the trimming period according to some embodiments of the present invention; 〔FIG. 7〕is a flow chart of multiple operations performed by the voltage detection device in FIG. 2 during the voltage detection period according to some embodiments of the present invention; and 〔FIG. 8〕is a flow chart of a voltage detection method according to some embodiments of the present invention.

All terms used in this article have their usual meanings. The definitions of the above terms in commonly used dictionaries and the use examples of any term discussed herein in the content of this case are only examples and should not limit the scope and meaning of this case. Similarly, this case is not limited to the various embodiments shown in this specification.

As used herein, "coupling" or "connection" may refer to two or more components making physical or electrical contact directly or indirectly, or two or more components operating or acting on each other. As used herein, the term "circuit" may refer to a device that is composed of at least one transistor and/or at least one active and passive component connected in a certain manner to process signals.

FIG1 is a schematic diagram of a chip system 100 according to some embodiments of the present invention. In some embodiments, the chip system 100 can be used in applications such as a real-time clock (RTC) generator and/or power enable control, but the present invention is not limited thereto. The chip system 100 can include a voltage detection device 110, a low-drop output regulator (LDO) 120, a clock generator 130, and a bias generator 140.

The low voltage difference regulator 120, the clock generator 130, and the bias generator 140 may be powered by the power voltage VDD to provide corresponding signals. For example, the low voltage difference regulator 120 may be powered by the power voltage VDD to provide current I1 and current I2 to the voltage detection device 110. In some embodiments, the low voltage difference regulator 120 may generate a voltage (not shown) based on the power voltage VDD, and provide this voltage to power the voltage detection device 110, the clock generator 130, and/or the bias generator 140. The clock generator 130 can be powered by the power voltage VDD (or the voltage generated by the low voltage difference regulator 120 based on the power voltage VDD) to provide the clock signal CLK. The bias generator 140 can be powered by the power voltage VDD (or the voltage generated by the low voltage difference regulator 120 based on the power voltage VDD) to generate a reference voltage VREF, and divide the power voltage VDD to generate multiple voltages VDD[0]~VDD[N-1], where the value N can be a positive integer greater than 1.

The voltage detection device 110 can receive the current I1, the current I2, the clock signal CLK, the reference voltage VREF, a plurality of voltages VDD[0]~VDD[N-1] and the enable signal EN. In some embodiments, when the enable signal EN has a first logic value (such as, but not limited to, logic value 1), the voltage detection device 110 operates in a trimming period to select a voltage corresponding to one of the plurality of voltages VDD[0]~VDD[N-1] using a plurality of bits B1[0]~B1[M-1] (as shown in FIG. 2 ), wherein the value M can be a positive integer greater than 1. After selecting the corresponding voltage, the voltage detection device 110 stores the values of the multiple bits B1[0]~B1[M-1] selected for the corresponding voltage. When the enable signal EN has a second logic value different from the first logic value (for example, but not limited to, logic value 0), the voltage detection device 110 operates in the voltage detection period to use the previously stored multiple bits B1[0]~B1[M-1] to generate the corresponding voltage, thereby detecting whether the power supply voltage VDD is abnormal based on the corresponding voltage and the reference voltage VREF. The related operations during the trimming period and the voltage detection period will be described in sequence with reference to the various figures below.

FIG2 is a schematic diagram of the voltage detection device 110 in FIG1 according to some embodiments of the present invention. The voltage detection device 110 includes a reference voltage selection circuit 111, a reset signal generation circuit 112, a voltage detector 113, and a digital circuit 114. The reference voltage selection circuit 111 outputs an input voltage VIN according to the clock signal CLK, the detection signal SP1, the reset signal SD1, and a plurality of bits B1[0]~B1[M-1]. For example, the reference voltage selection circuit 111 can output a corresponding voltage among a plurality of voltages VDD[0]~VDD[N-1] as the input voltage VIN or output a preset voltage VD as the input voltage VIN according to the plurality of signals. The setting method of the reference voltage selection circuit 111 will be described later with reference to FIG. 3 .

The reset signal generating circuit 112 generates a reset signal SD1 according to the clock signal CLK and multiple currents I1 and I2, wherein the multiple currents I1 and I2 are generated by the low voltage difference regulator 120 of FIG. 1 based on the power supply voltage VDD. The setting method of the reset signal generating circuit 112 will be described later with reference to FIG. 4A to FIG. 4C.

The voltage detector 113 can compare the input voltage VIN with the reference voltage VREF to generate a detection signal SPT, and generate a detection signal SP1 according to the detection signal SPT and the enable signal EN. During the voltage detection period, the voltage detector 113 can compare the input voltage VIN with the reference voltage VREF to confirm whether the power supply voltage VDD has been stabilized at the target level, thereby detecting whether the power supply voltage VDD has an abnormal voltage drop. The setting method of the voltage detector 113 will be described later with reference to FIG. 5.

The digital circuit 114 may adjust the multiple bits B1[0]~B1[M-1] according to the detection signal SPT during the trimming period to determine the values of the multiple bits B1[0]~B1[M-1], and output the multiple bits B1[0]~B1[M-1] during the voltage detection period and selectively reset them according to the detection signal SP1. For example, during the trimming period, the digital circuit 114 may perform a binary search algorithm according to the detection signal SPT and sequentially adjust the multiple bits B1[0]~B1[M-1] to determine the values of the multiple bits B1[0]~B1[M-1]. During the voltage detection period, the digital circuit 114 can output a plurality of bits B1[0]~B1[M-1] determined during the trimming period, so that the reference voltage selection circuit 111 can output the corresponding input voltage VIN to the voltage detector 113. In this way, the voltage detector 113 can use the input voltage VIN to compare with the reference voltage VREF to detect whether the power supply voltage VDD has reached the target level. If the power supply voltage VDD has an abnormal voltage drop and the input voltage VIN is too low, the detection signal SP1 will change state to instruct the digital circuit 114 to reset. Under this condition, the digital circuit 114 can be reset (for example, clearing the internal circuit settings) to prevent the internal circuit from erroneously causing an abnormal voltage drop. In some embodiments, the digital circuit 114 can be controlled by software and/or hardware in the system to perform the above-mentioned related operations. In some embodiments, the digital circuit 114 can be set in a control circuit, a central processing unit, etc. in the system. The related operations of the digital circuit 114 will be described later with reference to FIG. 6 and FIG. 7, respectively.

By means of the above configuration, the voltage detection device 110 can select an input voltage VIN suitable for comparison with the reference voltage VREF during the trimming period to ensure that the voltage detection device 110 can have a more accurate detection result during the voltage detection period, thereby improving the operational reliability of the overall system. Since the reference voltage may be offset due to the influence of process variation, the voltage detection device in some related technologies uses a bias circuit with high precision to generate a reference voltage and/or uses an additional correction mechanism to correct the level of the reference voltage to improve the accuracy of voltage detection. In other words, in these technologies, the voltage detection device needs to use an additional calibration circuit and/or a high-precision bias circuit, which will significantly increase the overall cost. Different from the above-mentioned technologies, in some embodiments of the present case, the voltage detection device 110 does not calibrate the reference voltage VREF, but instead trims the input voltage VIN that is compared with the reference voltage VREF, wherein the circuit portion for adjusting the input voltage VIN and the circuit portion for detecting the power supply voltage VDD are a common circuit (for example, the reference voltage selection circuit 111 and the voltage detector 113), so there is no need to use a high-precision bias circuit or an additional calibration circuit. In this way, the overall circuit cost can be reduced.

FIG3 is a schematic diagram of the reference voltage selection circuit 111 in FIG2 according to some embodiments of the present invention. The reference voltage selection circuit 111 includes a trigger 301, a plurality of flip-flops 302[0] to 302[M-1], a multiplexer 303, and a multiplexer 304. The trigger 301 generates a trigger signal ST according to a clock signal CLK and a detection signal SP1. Specifically, in some embodiments, the trigger 301 includes a logic gate 301A and an inverter 301B. In some embodiments, the logic gate 301A may be, but is not limited to, an NAND gate, which may generate a signal S1 according to the clock signal CLK and the detection signal SP1. Inverter 301B can generate a trigger signal ST according to signal S1.

The plurality of flip-flops 302[0]~302[M-1] may be, but are not limited to, D-type flip-flops. The plurality of flip-flops 302[0]~302[M-1] may output the plurality of bits B1[0]~B1[M-1] as the plurality of bits B2[0]~B2[M-1] according to the trigger signal ST, and may reset the plurality of bits B2[0]~B2[M-1] according to the reset signal SD1. Taking the flip-flop 302[0] as an example, the flip-flop 302[0] may output the bit B1[0] as the bit B2[0] according to the trigger signal ST. Alternatively, when the reset signal SD1 has a preset value (such as, but not limited to, a logical value 0), the flip-flop 302[0] may reset the bit B2[0] to the logical value 0. The corresponding relationship and operation between the remaining flip-flops 302[1]~302[M-1], the remaining bits B1[1]~B1[M-1] and the remaining bits B2[1]~B2[M-1] can refer to the flip-flop 302[0], so it will not be repeated here.

The multiplexer 303 selects a corresponding voltage VDD[i] from a plurality of voltages VDD[0]~VDD[N-1] according to some bits in the plurality of bits B2[0]~B2[M-1] (for example, but not limited to, a plurality of bits B2[0]~B2[M-2]), wherein the value i can be any positive integer between the value 0 and the value N-1. The multiplexer 304 selects to output the corresponding voltage VDD[i] or the preset voltage VD as the input voltage VIN according to the remaining bits in the plurality of bits B2[0]~B2[M-1] (for example, but not limited to, the bit B2[M-2]).

FIG4A is a schematic diagram of the reset signal generating circuit 112 in FIG2 according to some embodiments of the present invention. In some embodiments, the reset signal generating circuit 112 may include a clock flag generator 401, a power-on flag generator 402, and a logic gate 403. The clock flag generator 401 generates a clock flag signal CKF according to the clock signal CLK and the current I1. The power-on flag generator 402 generates a power-on flag signal PSF according to the current I2. The logic gate 403 may generate a reset signal SD1 according to the clock flag signal CKF and the power-on flag signal PSF. In some embodiments, the logic gate 403 may be, but is not limited to, an AND gate. In some embodiments, the reset signal SD1 can be used to indicate whether the clock generator 130 of FIG. 1 has been operating in a stable state after power-on (i.e., can stably generate a clock signal CLK with a preset period). The clock generator 130 will start to oscillate and start to generate the clock signal CLK after the power voltage VDD is powered on. The clock signal CLK may be in an unstable state for a short period of time after the power voltage VDD is powered on, so that the clock flag signal CKF also has an unstable state during this period. Therefore, by using the logic gate 403 to generate the reset signal SD1 according to the clock flag signal CKF and the power-on flag signal PSF, it is possible to prevent the reset signal SD1 from being affected by the unstable clock flag signal CKF and incorrectly continuing to have the same logic value during a period after the power-on process of the power voltage VDD begins.

FIG4B is a schematic diagram of the clock flag generator 401 in FIG4A according to some embodiments of the present invention. The clock flag generator 401 includes a delay circuit 411, a logic gate 412, and a switching capacitor circuit 413. The delay circuit 411 can delay the clock signal CLK to generate a signal CKD (which is equivalent to a delay of the clock signal CLK). In some embodiments, the delay circuit 411 can be implemented by a plurality of digital circuits coupled in series. The logic gate 412 generates a switching signal SS according to the clock signal CLK and the signal CKD. In some embodiments, the logic gate 412 can be, but is not limited to, a mutex or gate. The switching capacitor circuit 413 adjusts the level of the node N1 according to the current I1 and the switching signal SS, and generates the clock flag signal CKF according to the level of the node N1. For example, the switching capacitor circuit 413 includes a capacitor C1, a switch SW1, and an inverter 413A. The capacitor C1 is coupled between the node N1 and the ground, and is charged by the current I1 to increase the level of the node N1. The switch SW1 is coupled between the node N1 and the ground, and is selectively turned on according to the switching signal SS to bypass the current I1 to the ground and discharge the capacitor C through the switch SW1, thereby reducing the level of the node N1. The inverter 413A is coupled to the node N1 and generates the clock flag signal CKF according to the level of the node N1.

In detail, after the power supply voltage VDD is powered on, the low-voltage difference regulator 120 starts to generate current I1, so that the capacitor C1 is charged by the current I1 and the level of the node N1 is increased. Under this condition, the inverter 413A outputs a clock flag signal CKF with a low level. Then, when the logic gate 412 outputs a switching signal SS with a high level, the switch SW1 is turned on to reduce the level of the node N1. As the number of times the switch SW1 is turned on increases, the level of the node N1 will become lower and lower. When the level of the node N1 is lower than a critical value, the output of the inverter 413A will transition to generate a clock flag signal CKF with a high level.

FIG4C is a schematic diagram of the power-on flag generator 402 in FIG4A according to some embodiments of the present invention. In some embodiments, the power-on flag generator 402 includes a capacitor C2 and a buffer 402A. The capacitor C2 is coupled between the node N2 and the ground, and is charged by the current I2 to increase the level of the node N2. The buffer 402A is coupled to the node N2, and generates a power-on flag signal PSF according to the level of the node N2. In some embodiments, the buffer 402A can be implemented by, but not limited to, an even number of inverters connected in series. When the power supply voltage VDD is powered on, the low voltage difference regulator 120 starts to generate the current I2, so that the capacitor C2 is charged by the current I2 to increase the level of the node N2. When the level of node N2 is still below a critical value, buffer 402A will generate a power-on flag signal PSF with a low level. Alternatively, when the level of node N2 begins to be higher than the critical value, buffer 402A will switch to continuously generate a power-on flag signal PSF with a high level.

FIG5 is a schematic diagram of the voltage detector 113 in FIG2 according to some embodiments of the present invention. In some embodiments, the voltage detector 113 includes a comparator 501 and a logic gate 502. The comparator 501 compares the input voltage VIN with the reference voltage VREF to generate a detection signal SPT. The logic gate 502 can generate a detection signal SP1 according to the detection signal SPT and an enable signal. In some embodiments, the logic gate 502 may be, but is not limited to, a gate or a gate, which may output a detection signal SP1 that continues to have a logic value of 1 when the enable signal EN has a logic value of 1 (i.e., during the trimming period), thereby preventing the digital circuit 114 from being reset. On the other hand, when the enable signal EN has a logic value of 0 (i.e., during the voltage detection period), the logic gate 502 may respond to the enable signal EN and output the detection signal SPT as the detection signal SP1.

FIG6 is a flow chart of multiple operations performed by the voltage detection device 110 of FIG2 during the trimming period according to some embodiments of the present invention. In operation S610, an enable signal EN having a first logic value is received to generate a detection signal SP1 having a first logic value. As mentioned above, during the trimming period, the enable signal EN has a logic value of 1 (equivalent to the aforementioned first logic value). Under this condition, the voltage detector 113 responds to the enable signal EN and generates a detection signal SP1 having a logic value of 1, thereby preventing the digital circuit 114 from being reset.

In operation S620, the power voltage VDD is adjusted to a target level. For example, if the normal operating level of the power voltage VDD is approximately 1.6 volts to 3.63 volts, the target level can be set to approximately 1.5 volts. In some embodiments, this target level is a level sufficient to allow the clock generator 130 of FIG. 1 to oscillate and start generating the clock signal CLK. In some embodiments, the digital circuit 114 can send at least one signal to other circuits (e.g., the low voltage difference regulator 120) or a power management circuit (not shown) in the system to perform operation S620.

In operation S630, the multiple bits B1[0]~B1[M-1] are output as multiple bits B2[0]~B2[M-1] according to the trigger signal ST. As described above, the clock generator 130 can start to generate the clock signal CLK at the power supply voltage VDD with the target level. Therefore, the trigger 301 in Figure 3 can generate the trigger signal ST that switches with the clock signal CLK. Under this condition, the multiple flip-flops 302[0]~302[M-1] will output the multiple bits B1[0]~B1[M-1] as multiple bits B2[0]~B2[M-1] according to the trigger signal ST.

In operation S640, a binary search algorithm is executed according to the detection signal SPT to determine the values of the plurality of bits B1[0]~B1[M-1]. For example, the digital circuit 114 may first generate a first group of bits B1[0]~B1[M-1] (which corresponds to one of the multiple voltages VDD[0]~VDD[N-1] with an intermediate level), and the reference voltage selection circuit 111 may select the one with the intermediate level (i.e., the corresponding voltage VDD[i]) from the multiple voltages VDD[0]~VDD[N-1] according to the group of bits B1[0]~B1[M-1] as the input voltage VIN, and the reference voltage selection circuit 111 may compare the input voltage VIN with the reference voltage VREF. If the input voltage VIN is higher than the reference voltage VREF, the detection signal SPT has a logical value of 1. Then, the digital circuit 114 can change to output the second group of bits B1[0]~B1[M-1], so that the reference voltage selection circuit 111 can select a next voltage lower than the aforementioned middle level from multiple voltages VDD[0]~VDD[N-1], and output the next voltage as the input voltage VIN. If the input voltage VIN becomes lower than the reference voltage VREF, the detection signal SPT will switch to have a logical value of 0. In this way, the digital circuit 114 can determine that the value of a group of bits B1[0]~B1[M-1] suitable for this reference voltage VREF may be the aforementioned first group of bits or the second group of bits.

Alternatively, if the input voltage VIN corresponding to the first group of bits B1[0]~B1[M-1] is lower than the reference voltage VREF, the detection signal SPT has a logical value of 0. Then, the digital circuit 114 can change to output the third group of bits B1[0]~B1[M-1], so that the reference voltage selection circuit 111 can select a next voltage higher than the aforementioned middle level from a plurality of voltages VDD[0]~VDD[N-1], and output the next voltage as the input voltage VIN. If the input voltage VIN becomes higher than the reference voltage VREF, the detection signal SPT will switch to have a logical value of 1. In this way, the digital circuit 114 can determine that the value of a group of bits B1[0]~B1[M-1] suitable for the reference voltage VREF may be the aforementioned first group of bits or the third group of bits. Similarly, by repeatedly executing the above process, the digital circuit 114 can determine the values of multiple bits B1[0]~B1[M-1] according to the detection signal SPT. It should be understood that the adjustment method described above is a simple binary search algorithm, but the present case is not limited to this. Various suitable adjustment methods of binary search algorithms are also covered by the present case.

In operation S650, the values of the multiple bits B1[0]~B1[M-1] are stored. In some embodiments, the digital circuit 114 may include at least one storage circuit (such as, but not limited to, a register), which can store the values of the multiple bits B1[0]~B1[M-1] determined in operation S640.

FIG. 7 is a flowchart of multiple operations performed by the voltage detection device 110 of FIG. 2 during the voltage detection period according to some embodiments of the present invention. In operation S710, in the first period after the power supply voltage VDD is powered on, multiple bits B2[0]~B2[M-2] are reset to a logical value of 0 to output a preset voltage VD as the input voltage VIN. For example, in an initial period of the power supply voltage VDD power-on process, the reset signal SD1 is a logical value of 0 (because the level of the node N2 in FIG. 3 is not high enough), so that multiple flip-flops 302[0]~302[M-1] reset multiple bits B2[0]~B2[M-2] to a logical value of 0. Since bit B2[M-2] has a logical value of 0, multiplexer 304 will output the preset voltage VD as the input voltage VIN.

In operation S720, during the second period after the power voltage VDD is powered on, the multiple flip-flops 302[0]~302[M-1] output the multiple bits B1[0]~B1[M-1] as multiple bits B2[0]~B2[M-1]. For example, during a period after the power voltage VDD is powered on, when the level of the node N2 in FIG3 is high enough, the reset signal SD1 will switch to the logic value 1, so that the multiple flip-flops 302[0]~302[M-1] do not reset but start to output the multiple bits B1[0]~B1[M-1] as multiple bits B2[0]~B2[M-1] according to the trigger signal ST.

In operation S730, the digital circuit 114 outputs the previously stored multiple bits B1[0]~B1[M-1] to output the corresponding voltage VDD[i] as the input voltage VIN. In operation S740, the input voltage VIN is compared with the reference voltage VREF to detect whether the power supply voltage VDD has an abnormal voltage drop. For example, the digital circuit 114 can output the multiple bits B1[0]~B1[M-1] stored in operation S650 of FIG6 , so that the reference voltage selection circuit 111 can output the input voltage VIN suitable for the reference voltage VREF, thereby starting to confirm whether the power supply voltage VDD has an abnormal voltage drop by comparing the reference voltage VREF with the input voltage VIN.

FIG8 is a flow chart of a voltage detection method 800 according to some embodiments of the present invention. In operation S810, a voltage corresponding to one of a plurality of first voltages is output as an input voltage according to a clock signal, a first detection signal, a reset signal and a plurality of first bits, wherein the first voltages are generated based on a power supply voltage. In operation S820, the reset signal is generated according to the clock signal and a plurality of currents, wherein the currents are generated based on the power supply voltage. In operation S830, the input voltage is compared with a reference voltage to generate a second detection signal, and the first detection signal is generated according to the second detection signal and an enable signal. In operation S840, a digital circuit adjusts the first bits according to the second detection signal during a trimming period to determine the values of the first bits, and outputs the first bits during a voltage detection period and selectively resets them according to the first detection signal.

The multiple operations of the voltage detection method 800 can refer to the description of the aforementioned embodiments, so they will not be repeated here. The multiple operations of the voltage detection method 800 are only examples and are not limited to be executed in the order in this example. Without violating the operation mode and scope of each embodiment of the present case, the various operations under the voltage detection method 800 can be appropriately added, replaced, omitted or executed in a different order (for example, they can be executed simultaneously or partially simultaneously).

In summary, the voltage detection device and the voltage detection method in some embodiments of the present invention can use the voltage trimming mechanism to find a voltage suitable for the current reference voltage, and use this voltage and the reference voltage to detect whether the power supply voltage is abnormal. In this way, the voltage detection can be performed more accurately without using a high-precision reference voltage generator or a reference voltage correction mechanism, thereby improving the system reliability and reducing the overall circuit cost.

Although the embodiments of this case are described above, these embodiments are not used to limit this case. People with ordinary knowledge in this technical field can make variations to the technical features of this case based on the explicit or implicit content of this case. All these variations may fall within the scope of patent protection sought by this case. In other words, the scope of patent protection of this case shall be subject to the scope of patent application defined in this specification.

800: Voltage detection method

S810, S820, S830, S840: Operation

Claims (12)

A voltage detection device comprises: A reference voltage selection circuit, which outputs a voltage corresponding to one of a plurality of first voltages as an input voltage according to a clock signal, a first detection signal, a reset signal and a plurality of first bits, wherein the first voltages are generated based on a power supply voltage; A reset signal generating circuit, which generates the reset signal according to the clock signal and a plurality of currents, wherein the currents are generated based on the power supply voltage; A voltage detector, which compares the input voltage with a reference voltage to generate a second detection signal, and generates the first detection signal according to the second detection signal and an enable signal; and A digital circuit adjusts the first bits according to the second detection signal during a trimming period to determine the values of the first bits, and outputs the first bits during a voltage detection period and selectively resets them according to the first detection signal. The voltage detection device of claim 1, wherein the reset signal generating circuit comprises: a clock flag generator, generating a clock flag signal according to the clock signal and a first current among the currents; a power-on flag generator, generating a power-on flag signal according to a second current among the currents; and a first logic gate, generating the reset signal according to the clock flag signal and the power-on flag signal. The voltage detection device of claim 2, wherein the clock flag generator comprises: a delay circuit, delaying the clock signal to generate a first signal; a second logic gate, generating a switching signal according to the clock signal and the first signal; and a switching capacitor circuit, adjusting the level of a node according to the first current and the switching signal, and generating the clock flag signal according to the level of the node. A voltage detection device as claimed in claim 3, wherein the switching capacitor circuit comprises: a capacitor coupled to the node and charged by the first current to increase the level of the node; a switch coupled between the node and ground and selectively turned on according to the switching signal to reduce the level of the node; and an inverter to generate the clock flag signal according to the level of the node. A voltage detection device as claimed in claim 2, wherein the power-on flag generator comprises: a capacitor coupled to a node and charged by the second current to increase the level of the node; and a buffer generating the power-on flag signal according to the level of the node. The voltage detection device of claim 1, wherein the reference voltage selection circuit comprises: a trigger, generating a trigger signal according to the clock signal and the first detection signal; a plurality of flip-flops, outputting the first bits as a plurality of second bits according to the trigger signal, and resetting the second bits according to the reset signal; a first multiplexer, selecting the corresponding voltage from the first voltages according to a portion of the second bits; and a second multiplexer, outputting the corresponding voltage or a preset voltage as the input voltage according to a remaining bit of the second bits. A voltage detection device as claimed in claim 6, wherein the trigger comprises: a logic gate, generating a first signal according to the clock signal and the first detection signal; and an inverter, generating the trigger signal according to the first signal. A voltage detection device as claimed in claim 1, wherein the enable signal has a first logic value during the trimming period, and the voltage detector generates the first detection signal having the first logic value in response to the enable signal during the trimming period to prevent the digital circuit from being reset during the trimming period. A voltage detection device as claimed in claim 8, wherein the enable signal has a second logical value different from the first logical value during the voltage detection period, and the voltage detector outputs the second detection signal as the first detection signal in response to the enable signal during the voltage detection period. A voltage detection device as claimed in claim 1, wherein the voltage detector comprises: a comparator, comparing the input voltage with the reference voltage to generate the second detection signal; and a logic gate, generating the first detection signal according to the second detection signal and the enable signal. A voltage detection device as claimed in claim 1, wherein the digital circuit executes a binary search algorithm according to the second detection signal during the trimming period to determine the values of the first bits. A voltage detection method, comprising: Outputting a voltage corresponding to one of a plurality of first voltages as an input voltage according to a clock signal, a first detection signal, a reset signal and a plurality of first bits, wherein the first voltages are generated based on a power supply voltage; Generating the reset signal according to the clock signal and a plurality of currents, wherein the currents are generated based on the power supply voltage; Comparing the input voltage with a reference voltage to generate a second detection signal, and generating the first detection signal according to the second detection signal and an enable signal; and A digital circuit adjusts the first bits according to the second detection signal during a trimming period to determine the values of the first bits, and outputs the first bits during a voltage detection period and selectively resets them according to the first detection signal.

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