TWI665552B - Circuit for recovering from power loss and electronic device using the same circuit and method thereof - Google Patents

Abstract

A circuit for recovering from power loss, and an electronic device and method using the same. The circuit includes, but is not limited to, a memory circuit including a first memory element outputting a first memory output voltage and a second memory element outputting a second memory output voltage; a logic comparator circuit connected to the memory circuit, It also includes a first logic comparator that compares the first memory output voltage with a first power supply voltage to generate a first logic comparator output voltage, and compares a second memory output voltage with a second power supply voltage to generate a first logic comparator. A second logic comparator with two logic comparator output voltages; and a logic circuit electrically connected to the logic comparator circuit and receiving the first logic comparator output voltage and the second logic comparator output voltage to perform a first logic operation, the first Logic operations are used at least in part to generate a power-on reset voltage.

Description

Circuit for recovering from power loss and electronic device and method using the same

The present invention relates to a technology for power loss testing, and in particular, to a circuit for recovering from power loss, and an electronic device and method using the same.

The power loss test may be one of the tests required for a wafer or an integrated circuit (IC) manufactured when the wafer is evaluated on an assembly line or in a laboratory. For example, a mobile phone running on a battery pack might perform this test. When the chip experiences sudden power loss from an internal or external power source, the power level may gradually decrease to a certain level but not directly to zero, which may not trigger a power on reset (POR) to generate a reset Signal to reset the chip's power circuit. If the POR is not triggered to reset the chip, the memory element may be in an unknown state.

As shown in Figure 1, after the POR 101 has been triggered, the chip's power can be changed from 0 volts to a normal bias VCC. However, assuming that the power supply of the chip drops abruptly as shown in the power loss region 102, if the power supply drops below the minimum threshold but does not directly reach a voltage of about 0 volts to trigger the POR as shown in the dead band region 103, The memory element may enter an unknown state. The dead zone 103 refers to the range of the power supply voltage, within which the memory element will not be guaranteed to maintain its recording state, and POR will not be triggered at the same time.

The reason the chip will probably be in an unknown state is that when the power level drops too slowly, the recording state of the memory element is lost. When the power supply level drops to the dead zone region 103, memory elements such as flip-flops, latches, etc. may not be able to maintain their recording state, and thus the chip enters an unknown state. After the wafer enters an unknown state, the wafer may fail because the state machine will not be able to enter the expected state. Therefore, an unknown state of the wafer caused by the power source entering the dead zone 103 may be a problem that needs to be solved.

The invention provides a circuit for recovering from power loss, and an electronic device and method using the same.

The invention discloses a circuit for recovering from power loss. The circuit should include, but is not limited to, a memory circuit including a first memory element that outputs a first memory output voltage and a second memory element that outputs a second memory output voltage. A second memory element; a logic comparator circuit, electrically connected to the memory circuit, and including a first circuit that compares the first memory output voltage with a first power supply voltage to generate a first logic comparator output voltage A logic comparator, and a second logic comparator that compares the second memory output voltage with a second power supply voltage that is higher than the first power supply voltage to generate a second logic comparator output voltage; and a logic circuit, Electrically connected to the logic comparator circuit and receiving a first logic comparator output voltage and a second logic comparator output voltage to perform a first logic operation, the first logic operation is at least partially used to generate a power-on reset voltage.

The present invention discloses an electronic device using a circuit for recovering from power loss. The electronic device should include but is not limited to: a power supply circuit; and a circuit electrically connected to the power supply circuit for freely from the power supply. Recovery from power loss caused by an output voltage drop of a circuit, wherein the circuit includes a memory circuit, a first memory element having a first memory output voltage, and a second memory having a second memory output voltage Element; a logic comparator circuit electrically connected to the memory circuit, and including comparing the first memory output voltage with a first power supply voltage received from the power supply circuit to generate a first logic comparator output voltage A first logic comparator, and comparing the second memory output voltage with a second power supply voltage received from the power supply circuit and higher than the first power supply voltage to generate a second logic comparator output voltage A second logic comparator; and a logic circuit electrically connected to the logic comparator circuit and receiving the output voltage of the first logic comparator And the second logic comparator output voltage to perform a first logic operation, the first logic operation is used at least in part to generate a power-on reset voltage, the power-on reset voltage is responsive to all power from the power supply circuit The output voltage drops to reset the memory circuit.

The invention discloses a method for recovering from power loss used by a power supply device. The method should include, but is not limited to, receiving a first memory output voltage from a first memory element and receiving a second memory element from a second memory element. Two memory output voltages; comparing the first memory output voltage with a first power supply voltage received from the power supply circuit to generate a first logic comparator output voltage; comparing the second memory output voltage with a slave output voltage The second power supply voltage received by the power supply circuit and higher than the first power supply voltage is compared to generate a second logic comparator output voltage; by using the first logic comparator output voltage and the second logic A comparator output voltage to perform a first logic operation; and generating a power-on reset voltage based at least in part on the first logic operation for resetting the power supply in response to a power loss of the power supply.

In order to make the foregoing features and advantages of the present disclosure easy to understand, embodiments with accompanying drawings are described in detail below. It should be understood that the foregoing general description and the following detailed description are exemplary and are intended to provide further explanation of the claimed disclosure.

Reference will now be made in detail to the current embodiment of the present disclosure.

In the present disclosure, a method and a circuit suitable for an electronic device to detect the dead zone region 103 and restore the state of an unknown memory element caused by the dead zone region 103 to a known memory element state are described. When the dead zone 103 has been detected, a power on reset (POR) will be issued to reset the power of the electronic device, thereby restoring to a known state. A technique for detecting the dead zone 103 will include comparing the expected value loaded into the memory element with a predetermined value of the power supply voltage.

During the power-on state, values from non-volatile memory are loaded into the memory elements. These values are called DZD modes, and these values are analog voltages that can be, for example, high voltage, low voltage, or bandgap voltage used to test the supply voltage using a comparator. The memory element may be, for example, a latch, a flip-flop, a virtual memory, or the like. The DZD mode can be hard-wired inside the IC or loaded into the IC from an external power source. After the power-on sequence has been completed, the value from the memory element is compared with a power supply voltage that can be a predetermined value. Under normal operating conditions, these values are matched by the comparator to produce a matching result, and the matching result does not trigger a POR. In the case of power loss and / or memory element depreciation, when the power supply voltage is restored, the matching result may trigger a POR. After the POR is triggered, the power-on sequence will start.

In one aspect, the present disclosure provides a circuit that will solve the above-mentioned problem of recovering from power loss caused by an output voltage drop from a power supply circuit. Referring to FIG. 2, the circuit is electrically connected to a power supply circuit, and both the circuit and the power supply circuit can be disposed in an electronic device. The circuit 200 will include, but is not limited to, a memory circuit 201, a logic comparator circuit 202, a logic circuit 203 that outputs a POR signal line, and the like.

The memory circuit 201 may include, but is not limited to, a first memory element that outputs a first memory output voltage, and a second memory element that outputs a second memory output voltage. The logic comparator circuit 202 electrically connected to the memory circuit 201 may include, but is not limited to, a first logic that compares a first memory output voltage with a first power supply voltage received from a power supply circuit to generate a first logic comparator output voltage. A comparator, and a second logic comparator that compares the second memory output voltage with a second power supply voltage received from the power supply circuit to generate a second logic comparator output voltage. A logic circuit 203 electrically connected to the logic comparator circuit 202 will receive a first logic comparator output voltage and a second logic comparator output voltage to perform a first logic operation, the first logic operation being at least partially used to generate a An electrical reset (POR) voltage that resets the memory circuit in response to an output voltage drop from a power circuit.

In an embodiment, the output voltage of the first memory has a binary value opposite to the output voltage of the second memory. When the power supply operates normally without power loss, the output voltage of the first memory and the second memory The output voltage is such that the first logic comparator output voltage and the second logic comparator output voltage output the same first binary value. However, when the power source experiences a power loss caused by an output voltage drop from the power supply circuit, at least one of the first logic comparator output voltage and the second logic comparator output voltage outputs a second two that is opposite to the first binary value. Carry value.

In an embodiment, the first logic operation may be an inverse operation performed by the first logic operation circuit. The operation outputs a second binary value when the power supply normally operates without power loss, and the The first binary value is output when the power loss is caused by the output voltage drop from the power circuit.

In one embodiment, the logic comparator circuit 202 may further include, but is not limited to, a third logic comparator that compares the output voltage of the third memory with the first power voltage received from the power circuit to generate a third logic comparator. An output voltage; a fourth logic comparator that compares the fourth memory output voltage with a second power supply voltage to generate a fourth logic comparator output voltage; and a second logic operation circuit that receives the third logic comparator output voltage and the first The four logic comparator output voltages perform a second logic operation on the third logic comparator output voltage and the fourth logic comparator output voltage, and the second logic operation may be, for example, an invert operation.

In an embodiment, the logic circuit 203 may further include, but is not limited to, a third logic operation circuit that receives the inverse operation of the first logic operation circuit and the inverse operation of the second logic operation circuit to perform The third logic operation generates a power-on reset (POR) voltage.

In an embodiment, the first memory element of the memory circuit 201 may be a virtual memory element dedicated to the circuit (that is, not used as a general-purpose storage medium used by a processor, a controller, or the like). Alternatively, the first memory element may be a first SR flip-flop set by a power-on reset, and the second memory element may be a second SR flip-flop reset by a power-on reset.

The present disclosure also provides a method for use by an electronic device having a circuit 200 for recovering from power loss of a power source as described in the present disclosure. This disclosure will include, but is not limited to, the steps described below. In step S301, the circuit may receive the first memory output voltage from the first memory element and receive the second memory output voltage from the second memory element. In step S302, the circuit may compare the output voltage of the first memory with the first power voltage received from the power circuit to generate a first logic comparator output voltage. In step S303, the circuit may compare the second memory output voltage with the second power supply voltage received from the power supply circuit to generate a second logic comparator output voltage. In step S304, the circuit may perform a first logic operation by using the first logic comparator output voltage and the second logic comparator output voltage. In step S305, the circuit may generate a power-on reset voltage based at least in part on a first logic operation for resetting the memory circuit in response to a power loss of the power supply.

In an embodiment, the output voltage of the first memory may have a binary value opposite to the output voltage of the second memory. When the power supply operates normally without power loss, the output voltage of the first memory and the second memory The bulk output voltage causes the first logic comparator output voltage and the second logic comparator output voltage to output the same first binary value. When the power source experiences a power loss caused by an output voltage drop from the power supply circuit, at least one of the first logic comparator output voltage and the second logic comparator output voltage may output a second binary opposite to the first binary value value.

In an embodiment, the first logic operation may be an inverse operation, which outputs a second binary value when the power supply normally operates without power loss, and when the power supply undergoes The first binary value is output when the power loss caused by the output voltage drop.

To further clarify the above concepts, the present disclosure provides several embodiments as disclosed in FIGS. 4 to 6 and their corresponding written descriptions. The method may include, but is not limited to, the steps described below. In step S401, the electronic device performs a power-on operation, which may include turning on the electronic device, waking the electronic device from a sleep mode, and the like. In step S402, the electronic device may optionally perform a fuse read operation, which will allow the electronic device to obtain a DZD mode for comparison. In step S403, the electronic device will obtain a DZD mode. The DZD mode can be obtained from the fuse reading in step S402. Alternatively, the DZD mode can be pre-existing because it can be fixed to the circuit or memory element of the electronic device. In addition, the DZD mode may alternatively be obtained from an external power source such as a central processing unit (CPU) or an external controller. In step S404, once the DZD mode is obtained, the electronic device loads the DZD mode into a memory element such as a virtual memory element, a latch, and a flip-flop. Alternatively, the DZD mode can be pre-existed in the memory device or programmed into the memory device from an external power source. In step S405, the circuit should compare the DZD mode with a predetermined voltage value from the power source through one or more comparators to generate a POR signal. The comparison will be continuous because the circuit will keep monitoring the dead zone 103. Once the comparison between the DZD mode and the predetermined voltage value does not produce an expected value, the process will continue at step S401, which will trigger a POR reset.

5, the circuit may include, but is not limited to, a plurality of memory elements 501 to 504 which are part of the memory circuit 201, a plurality of comparators 511 to 514 which are part of the logic comparator circuit 202, and a plurality of Each of the logic gates 521 to 523 is a part of the logic circuit 203. The logic circuit will be configured to generate a POR in response to a power supply voltage falling below a certain threshold (ie, the dead-time region 103).

The plurality of memory elements 501 to 504 can be virtual memory elements, which means that the virtual memory elements are not used as actual memory, but the circuit of FIG. 5 is dedicated to store the DZD mode for subsequent comparisons. The virtual memory element will include a first memory element 501 that outputs a first memory output voltage 501o, a second memory element 502 that outputs a second memory output voltage 502o, and a third memory that outputs a third memory output voltage 503o A body element 503 and a fourth memory element 504 that outputs a fourth memory output voltage 504o. In this embodiment, the DZD mode may be a sequence of high and low (eg, 1 0 1 0) voltages respectively loaded into the virtual memory element 501 to the virtual memory element 504, but it should be understood that the present disclosure is not limited thereto Specific sequence set. Therefore, the output voltage 501o, the output voltage 502o, the output voltage 503o, and the output voltage 504o will be high or low (for example, 1 0 1 0).

The logic comparator circuit 202 electrically connected to the memory circuit 201 may include, but is not limited to, comparing the first memory output voltage 501o with a first power supply voltage (eg, a ground voltage or Vss) received from the power supply circuit to generate a first The first logic comparator 511 of the logic comparator output voltage 511o, the second memory output voltage 502o, and a second power supply voltage (for example, Vcc) to compare the second logical comparator 512 to generate the second logical comparator output voltage 512o, and compare the third memory output voltage 503o to the first power supply voltage (eg, ground voltage or Vss) received from the power supply circuit The third logic comparator 513 generates a third logic comparator output voltage 513o, and the fourth memory comparator output voltage 504o is compared with a second power supply voltage (for example, Vcc) to generate a fourth logic comparator output voltage 514o. Four logic comparator 514.

The second logic comparator 512 may be an inverse OR gate that compares the second memory output voltage 502o with a second power supply voltage (such as Vcc) by performing an NOR operation to generate a second logic comparator output voltage 512o. Similarly, the fourth logic comparator 514 may be an inverse OR gate of the fourth logic comparator output voltage 514o by comparing the fourth memory output voltage 504o with a fourth power supply voltage (such as Vcc) by performing an NOR operation.

The comparators 511 to 514 will generate a high voltage or a low voltage based on the comparison result. It should be noted that the actual voltage levels used by the comparators (511 to 514) for high or low voltage output need not be the same as the high and low voltages of the virtual memory elements (501 to 504). Under normal operating conditions, the first logic comparator output voltage 511o can be configured as a high voltage (eg, 1) because the comparison between the first memory output voltage 501o and the first power supply voltage (eg, ground voltage or Vss) The result is configured to generate high voltage. The second logic comparator output voltage 512o may be configured as a high voltage (for example, 1) because the comparison result between the second memory output voltage 502o and the second power supply voltage (for example, Vcc) is configured to generate a high voltage. The third logic comparator output voltage 513o may be configured as a high voltage (for example, 1) because the comparison result between the third memory output voltage 503o and the first power supply voltage (such as a ground voltage or Vss) is configured to generate a high voltage . The fourth logic comparator output voltage 514o is configured as a high voltage (for example, 1) because the comparison result between the fourth memory output voltage 504o and the second power supply voltage (for example, Vcc) is configured to generate a high voltage. It should be noted that since the DZD mode is programmable, the actual logic gate and output values can be arbitrary.

In an embodiment, assuming that the DZD mode is 1010, the first logic comparator 511 may be an AND gate, the second logic comparator 512 may be an inclusive OR gate, the third logic comparator 513 may be an AND gate, and the fourth The logic comparator 514 may be an inverting OR gate. For example, under normal operating conditions, the first memory output voltage 501o will output a high voltage (eg, 1), and therefore the first logic comparator output voltage 511o will also output a high voltage. However, assuming that the dead band phenomenon has occurred, causing the first memory output voltage 501o to output a low voltage, the first logic comparator output voltage 511o will also be a low voltage.

In addition, for example, under normal operating conditions, it is assumed that the second memory output voltage 502o is configured to output a low voltage, so as a result of comparison with a reference voltage (eg, low voltage), a second logic comparator outside the OR gate The output voltage of 512o will also output high voltage. However, assuming that an abnormal operating condition has occurred, causing the second memory output voltage 502o to output a high voltage, the second logic comparator output voltage 512o will also be a low voltage. The third logic comparator circuit 513 and the fourth logic comparator circuit 514 will operate in a similar manner to the first logic comparator circuit 511 and the second logic comparator circuit 512, respectively.

However, in the event of power loss in the dead zone, the voltage Vcc will drop but will not reach zero anytime soon. The drop in Vcc will cause the voltage of at least the second power supply voltage (for example, Vcc) in the second logic comparator 512 to drop. For example, the voltage compared with the second memory output voltage 502o may generate a low voltage (for example, 0). Similarly, the drop in Vcc will cause the voltage of at least the second power supply voltage (eg, Vcc) in the fourth logic comparator 514 to drop. For example, the comparison with the fourth memory output voltage 504o may generate a low voltage (eg, 0). In addition, because the power loss can cause the voltage of the virtual memory element 501 to the memory element 504 to be unstable, the comparison results of the first logical comparator 511 and the third logical comparator 513 may not produce the expected high voltage (for example, 1) As a result, a low voltage (for example, 0) may be output instead.

The logic circuit 203 may include a first logic operation circuit 521, a second logic operation circuit 522, and a third logic operation circuit 523. In this embodiment, the first logic operation circuit 521 and the second logic operation circuit 522 are both circuits that can perform an inverse operation (such as an inverse AND gate), and the third logic operation circuit 523 is an executable or operation (such as or Brake) circuit. Under normal operating conditions, since the output voltage of the first logic comparator 511o and the output voltage of the second logic comparator 512o are both high voltages, the output of the first logic operation circuit 521o will be a low voltage (for example, 0), and due to the third logic comparison The output voltage 513o of the comparator and the output voltage 514o of the fourth logic comparator are both high voltages, so the output 522o of the second logic operation circuit will also be low voltage (for example, 0).

However, under abnormal operating conditions, for example, when the dead zone 103 has occurred, at least one or more of the comparator output voltage 511o, the comparator output voltage 512o, the comparator output voltage 513o, and the comparator output voltage 514o may be Low pressure. As long as any of the output voltage 511o, output 512o, output voltage 513o, output voltage 514o can be a low voltage, the first logic operation circuit outputs 521o and the second logic operation circuit outputs 522o due to the inverse operation principle At least one will be high voltage. As long as any of the first logic operation circuit output 521o and the second logic operation circuit output 522o is high voltage, the output of the third logic operation circuit 523 will be high voltage due to the operation principle of the OR gate. The high voltage of the third logic operation circuit 523 will trigger a POR.

Conceptually, the first memory output voltage 501o has a binary value opposite to the second memory output voltage 502o. When the power supply operates normally without power loss, the first memory output voltage 501o and the second memory The bulk output voltage 502o makes the first logic comparator output voltage 511o and the second logic comparator output voltage 512o output the same high voltage. However, when the power supply experiences a power loss caused by an output voltage drop from the power supply circuit, at least one of the first logic comparator output voltage 511o and the second logic comparator output voltage 512o will output a low voltage. Any one of the comparators 511 to 514 outputting a low voltage will be processed by the logic circuit 203 to trigger a POR.

In an embodiment, as an alternative to the memory elements 501 to 504 which are virtual memory elements, the memory elements may be other types of memory elements, such as latches, flip-flops, and the like. Referring to FIG. 6, the memory element may be implemented by using a plurality of SR flip-flops, which may include, but is not limited to, receiving the first voltage of the DZD mode from the S terminal of the first SR flip-flop. A first SR flip-flop 601 and a second SR flip-flop 602 that receives a second voltage in a DZD mode from the R terminal of a second SR flip-flop (eg, 602). FIG. 6 also shows a third SR flip-flop 603 and a fourth SR flip-flop 604 which are the same as the first SR flip-flop 601 and the second SR flip-flop 602. In this way, the DZD mode can be received from the outside and programmed into the SR flip-flop according to the typical operating principle of the SR flip-flop. The operation principle of the rest of FIG. 7 will be the same as that of FIG. 6, because the DZ_POR terminal of FIG. 6 will trigger a POR after the polarity of the DZ_POR output is switched.

FIG. 7 illustrates that the state of the memory element of the electronic device should be in a known state under normal operating conditions. However, when the dead zone 701 has occurred, the state of the memory element of the electronic device may become an unknown state. By using the circuit of FIG. 6, since Vcc of the power supply of the electronic device has recovered to a certain level, the output of the POR signal line (DZ_POR) will switch polarity to trigger POR 702. After POR 702 occurs, the state of the memory elements of the electronic device will return to a known state.

In view of the foregoing description, the present disclosure is applicable to an electronic device and is capable of detecting a power loss state to generate a power-on reset during the power loss state, thereby changing a state of a memory element of the electronic device from an unknown state to a known state. By using the present invention, the electronic device (1) can recover from an unknown state when the power supply falls below a certain level to a "dead zone" (2) can be a monitor and detect by comparing the output voltage of the memory element Power loss (3) will increase application reliability in the case of power loss, especially in mobile applications (4) It can be used to generate IC weights when a hacker tries to put the IC chip in an unknown state to attack it To increase safety (5) and save power, use less power for the provided design than an accurate VCC level detector.

Those skilled in the art will appreciate that various modifications and changes can be made to the structure of the disclosed embodiments without departing from the scope or spirit of the present disclosure. In light of the foregoing, it is intended that the present disclosure cover the modifications and variations of this disclosure that fall within the scope of the appended claims and their equivalents.

101, 702‧‧‧ Power-on reset

102‧‧‧Power loss area

103, 701‧‧‧ dead zone

200‧‧‧circuit

201‧‧‧Memory Circuit

202‧‧‧Logic Comparator Circuit

203‧‧‧Logic Circuit

S301- S305, S401- S405‧‧‧ steps

501‧‧‧first memory element / memory element / virtual memory element

501o‧‧‧First memory output voltage / output voltage

502‧‧‧Second memory element

502o‧‧‧Second memory output voltage / output voltage

503‧‧‧Third memory element

503o‧‧‧Third memory output voltage / output voltage

504‧‧‧Fourth Memory Element / Memory Element / Virtual Memory Element

504o‧‧‧Fourth memory output voltage / output voltage

511‧‧‧first logic comparator / comparator / first logic comparator circuit

 511o‧‧‧First logic comparator output voltage / comparator output voltage / output voltage

512‧‧‧Second Logic Comparator / Second Logic Comparator Circuit

512o‧‧‧Second logic comparator output voltage / comparator output voltage / output voltage

513‧‧‧Third Logic Comparator / Third Logic Comparator Circuit

513o‧‧‧Third logic comparator output voltage / comparator output voltage / output voltage

514‧‧‧Fourth logic comparator / comparator / fourth logic comparator circuit

514o‧‧‧ Fourth logical comparator output voltage / comparator output voltage / output voltage

521‧‧‧First logic operation circuit / logic gate

521o‧‧‧First logic operation circuit output

522‧‧‧Second logic operation circuit

522o‧‧‧Second logic operation circuit output

523‧‧‧Third logic operation circuit / logic gate

601‧‧‧The first SR flip-flop

602‧‧‧Second SR flip-flop

603‧‧‧The third SR flip-flop

604‧‧‧Fourth SR flip-flop

POR‧‧‧ Power-on reset / signal

PORb, DZ_POR, PWV_POR, PUMP_LEVEL_DETECTOR‧‧‧Signal

The accompanying drawings are included to provide a further understanding of the disclosure, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the present disclosure and, together with the description, serve to explain principles of the present disclosure. FIG. 1 illustrates a phenomenon in a “dead zone” region that may cause a wafer to malfunction. FIG. 2 is a block diagram showing hardware of a circuit for recovering from power loss of a power source in an electronic device. FIG. 3 illustrates a method for recovering from a power loss of a power source used by a power feeding sub-device as described in the present disclosure. FIG. 4 illustrates an embodiment of a method for recovering from a power loss of a power source used by a power supply device. FIG. 5 illustrates a circuit for recovering from power loss of a power source in an electronic device according to an embodiment of the present disclosure. FIG. 6 illustrates another circuit for recovering from power loss of a power source within an electronic device according to an embodiment of the present disclosure. FIG. 7 illustrates a phenomenon diagram of moving a memory state of an electronic device from an unknown state to a known state by using the circuit of FIG. 6 in an embodiment according to the present disclosure.

Claims (12)

An electronic device using a circuit for recovering from power loss, comprising: a power circuit; and a circuit electrically connected to the power circuit for recovering from power loss caused by an output voltage drop from the power circuit The circuit includes: a memory circuit including a first memory element outputting a first memory output voltage and a second memory element outputting a second memory output voltage; a logic comparator circuit electrically connected to the The memory circuit includes a first logic comparator that compares the first memory output voltage with a first power supply voltage received from the power supply circuit to generate a first logic comparator output voltage, and A second logic comparator that compares an output voltage of the second memory with a second power voltage received from the power circuit to generate a second logic comparator output voltage; and a logic circuit that is electrically connected to the logic comparator circuit and Receiving the first logic comparator output voltage and the second logic comparator output voltage to perform a first logic operation, so A first logical operation at least partly used to generate power on reset voltage, the power-on reset voltage in response to the drop in output voltage from the power supply circuit and resetting the memory circuit. The electronic device according to item 1 of the scope of patent application, wherein the output voltage of the first memory has a binary value opposite to the output voltage of the second memory, and when the power supply is normal without the power loss During operation, the first memory output voltage and the second memory output voltage cause the first logic comparator output voltage and the second logic comparator output voltage to output the same first binary value. The electronic device according to item 2 of the scope of patent application, wherein when the power source experiences the power loss caused by the output voltage drop from the power circuit, the first logic comparator output voltage and the At least one of the second logic comparator output voltages outputs a second binary value opposite to the first binary value. The electronic device according to item 3 of the scope of patent application, wherein the first logic operation includes an inverse operation performed by a first logic operation circuit, and the operation is performed when the power source does not have the power loss. The second binary value is output during normal operation, and the first binary value is output when the power source experiences the power loss caused by the output voltage drop from the power circuit. The electronic device according to item 4 of the scope of patent application, wherein the logic comparator circuit further includes a third logic comparator that compares the third memory output voltage with the first power supply voltage received from the power supply circuit. Performing a comparison to generate a third logic comparator output voltage; a fourth logic comparator to compare a fourth memory output voltage with the second power supply voltage to generate a fourth logic comparator output voltage; and a second logic operation circuit Receiving the third logic comparator output voltage and the fourth logic comparator output voltage to perform a second logic operation on the third logic comparator output voltage and the fourth logic comparator output voltage, said The second logical operation is an inverse operation. The electronic device according to item 5 of the patent application scope, wherein the logic circuit further includes a third logic operation circuit, and the third logic operation circuit receives the inverse operation of the first logic operation circuit and the The inverse operation of the second logic operation circuit performs a third logic operation, thereby generating the power-on reset voltage. The electronic device according to item 6 of the patent application scope, wherein the third logical operation is an OR operation. The electronic device according to item 1 of the patent application scope, wherein the first power supply voltage received from the power supply circuit is a reference voltage, and the second power supply voltage received from the power supply circuit is relative to the Reference voltage for operating voltage. The electronic device according to item 1 of the scope of patent application, wherein the first memory element of the memory circuit is a memory element dedicated to the circuit. The electronic device according to item 1 of the patent application scope, wherein the first memory element is a first SR flip-flop set by a power-on reset, and the second memory element is reset by a power-on reset The second SR flip-flop. A circuit for recovering from power loss, the circuit includes: a memory circuit including a first memory element outputting a first memory output voltage and a second memory element outputting a second memory output voltage; A logic comparator circuit electrically connected to the memory circuit and including a first logic comparator that compares the first memory output voltage with a first power supply voltage to generate a first logic comparator output voltage, and A second logic comparator that compares the second memory output voltage with a second power supply voltage to generate a second logic comparator output voltage; and a logic circuit that is electrically connected to the logic comparator circuit and receives the first A logic comparator output voltage and the second logic comparator output voltage to perform a first logic operation, the first logic operation being used at least in part to generate a power-on reset voltage. A method for recovering power loss of a power circuit of an electronic device used by a power supply device, the method includes: receiving a first memory output voltage from a first memory element and receiving a second memory from a second memory element Output voltage; comparing the output voltage of the first memory with the first power voltage received from the power circuit to generate a first logic comparator output voltage; comparing the output voltage of the second memory with the power from the power source The second power supply voltage received by the circuit and higher than the first power supply voltage is compared to generate a second logic comparator output voltage; by using the first logic comparator output voltage and the second logic comparator output Voltage to perform a first logic operation; and generating a power-on reset voltage based at least in part on the first logic operation for resetting the power circuit in response to the power loss of the power circuit.