TWI855317B - Method for preparing semiconductor device structure having features of different depths - Google Patents

Abstract

A method for preparing a semiconductor device structure includes forming a target layer over a semiconductor substrate, and forming a first energy-sensitive pattern over the target layer. The method also includes forming a lining layer covering the first energy-sensitive pattern, and forming a second energy-sensitive pattern over the lining layer. The first energy-sensitive pattern and the second energy-sensitive pattern are staggered. The method further includes performing an etching process to form a first opening and a second opening in the target layer. The first opening and the second opening have different depths.

Description

Method for preparing semiconductor device structure with different depth features

This application claims priority to U.S. Patent Application Nos. 17/571,259 and 17/573,160 (i.e., priority dates are "January 7, 2022 and January 11, 2022"), the contents of which are incorporated herein by reference in their entirety.

The present disclosure relates to a method for preparing a semiconductor device structure, and more particularly to a method for preparing a semiconductor device structure having openings of different depths.

Semiconductor components are indispensable for many modern applications. With the advancement of electronic technology, the size of semiconductor components has become smaller and smaller, while providing better functions and containing a larger number of integrated circuits. Due to the miniaturization of semiconductor components, different types and sizes of semiconductor components with different functions are integrated and packaged in a single module. Furthermore, many manufacturing steps are performed in the integration of various types of semiconductor devices.

However, the manufacturing and integration of these semiconductor devices involve many complex steps and operations. The integration in these semiconductor devices becomes increasingly complex. The increase in the complexity of the manufacturing and integration of these semiconductor devices may cause a number of defects. Accordingly, there is a need to continuously improve the manufacturing process of these semiconductor devices in order to solve these problems.

The above “prior art” description only provides background technology, and does not admit that the above “prior art” description discloses the subject matter of the present disclosure, does not constitute the prior art of the present disclosure, and any description of the above “prior art” should not be regarded as any part of the present case.

One embodiment of the present disclosure provides a method for preparing a semiconductor device structure. The preparation method includes forming a target layer on a semiconductor substrate; and forming a first energy-sensitive pattern on the target layer. The preparation method also includes forming a liner to cover the first energy-sensitive pattern; and forming a second energy-sensitive pattern on the liner. The first energy-sensitive pattern and the second energy-sensitive pattern are arranged in an alternating manner. The preparation method also includes performing an etching process to form a first opening and a second opening in the target layer. The first opening and the second opening have different depths.

In one embodiment, the first opening and the second opening are arranged in a staggered manner. In one embodiment, the second energy-sensitive pattern is separated from the first energy-sensitive pattern by the lining layer. In one embodiment, an upper surface and each sidewall of the first energy-sensitive pattern are covered by the lining layer. In one embodiment, a lower surface of the second energy-sensitive pattern is higher than a lower surface of the first energy-sensitive pattern. In one embodiment, an upper surface of the second energy-sensitive pattern is higher than an upper surface of the first energy-sensitive pattern.

In one embodiment, an upper surface of the first energy sensitive pattern is higher than a lower surface of the second energy sensitive pattern. In one embodiment, the liner comprises an organic polymer material. In one embodiment, during the etching process, the first energy sensitive pattern, the second energy sensitive pattern and the liner are removed. In one embodiment, the first energy sensitive pattern and the second energy sensitive pattern comprise different materials.

In one embodiment, a material of the first energy sensitive pattern is the same as a material of the second energy sensitive pattern. In one embodiment, the preparation method further includes performing an energy treatment process to convert an upper portion of the first energy sensitive pattern into a treatment portion before the liner is formed. In one embodiment, during the etching process, an etching rate of the treatment portion is different from an etching rate of the second energy sensitive pattern. In one embodiment, the preparation method further includes performing an energy treatment process to convert an upper portion of the second energy sensitive pattern into a treatment portion before the etching process. In one embodiment, during the etching process, an etching rate of the treatment portion is different from an etching rate of the first energy sensitive pattern.

Another embodiment of the present disclosure provides a method for preparing a semiconductor device structure. The preparation method includes forming a target layer on a semiconductor substrate; and forming a plurality of first energy-sensitive patterns on the target layer. The preparation method also includes forming a liner layer to conformally cover the first energy-sensitive patterns. A first opening is formed on the liner layer and between the first energy-sensitive patterns. The preparation method also includes filling the first opening with a second energy-sensitive pattern; and performing an etching process to form a plurality of second openings and a third opening in the target layer, wherein the third opening is located between the second openings, and the second openings and the third opening have different depths.

In one embodiment, the depths of the second openings are substantially the same. In one embodiment, the first energy-sensitive pattern comprises a first material, the second energy-sensitive pattern comprises a second material, and the first material is different from the second material. In one embodiment, during the etching, the first energy-sensitive patterns have a first etching rate, the second energy-sensitive pattern has a second etching rate, and the second etching rate is different from the first etching rate. In one embodiment, during the etching process, the liner has a third etching rate, and the first etching rate and the second etching rate are each greater than the third etching rate.

In one embodiment, a material of the first energy sensitive pattern and a material of the second energy sensitive pattern are the same. In one embodiment, the preparation method further includes performing an energy treatment process to convert at least a portion of each first energy sensitive pattern into a processing portion before the liner is formed. In one embodiment, each upper surface and each sidewall of the processing portions are covered by the liner. In one embodiment, the preparation method further includes performing an energy treatment process to convert at least a portion of the second energy sensitive pattern into a processing portion before the etching process is performed. In one embodiment, the preparation method further includes performing an energy treatment process on each first energy sensitive pattern before the liner is formed; and performing another energy treatment process on the second energy sensitive pattern before the etching process is performed.

The present disclosure provides some embodiments of a method for preparing a semiconductor device structure. The preparation method includes forming a first energy-sensitive pattern on a target layer; forming a liner layer to cover the first energy-sensitive pattern; and forming a second energy-sensitive pattern on the liner layer. In some embodiments, the first energy-sensitive pattern and the second energy-sensitive pattern are arranged in an alternating manner. The preparation method also includes performing an etching process to form a plurality of openings in the target layer, and the openings have different depths. Since the openings with different depths can be formed simultaneously, the manufacturing cost and time of the semiconductor device structure can be reduced, and better design flexibility can be achieved.

The above has been a fairly broad overview of the technical features and advantages of the present disclosure, so that the detailed description of the present disclosure below can be better understood. Other technical features and advantages that constitute the subject matter of the patent application scope of the present disclosure will be described below. Those with ordinary knowledge in the technical field to which the present disclosure belongs should understand that the concepts and specific embodiments disclosed below can be easily used to modify or design other structures or processes to achieve the same purpose as the present disclosure. Those with ordinary knowledge in the technical field to which the present disclosure belongs should also understand that such equivalent constructions cannot deviate from the spirit and scope of the present disclosure as defined by the attached patent application scope.

Specific examples of components and configurations are described below to simplify the embodiments of the present disclosure. Of course, these embodiments are for illustration only and are not intended to limit the scope of the present disclosure. For example, the description of a first component formed on a second component may include embodiments in which the first and second components are in direct contact, and may also include embodiments in which additional components are formed between the first and second components so that the first and second components are not in direct contact. In addition, the embodiments of the present disclosure may refer to reference numbers and/or letters repeatedly in many examples. The purpose of these repetitions is for simplification and clarity, and unless otherwise specified in the text, they do not in themselves represent a specific relationship between the various embodiments and/or configurations discussed.

Furthermore, for ease of explanation, spatially relative terms such as "beneath," "below," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or feature shown in the figures to another (other) element or feature. The spatially relative terms are intended to encompass different orientations of the elements in use or operation in addition to the orientation depicted in the figures. The device may have other orientations (rotated 90 degrees or in other orientations) and the spatially relative descriptors used herein may be interpreted accordingly.

FIG. 1 is a schematic flow chart illustrating a method 10 for preparing a semiconductor device structure 100 according to some embodiments of the present disclosure, and the method 10 includes steps S11, S13, S15, S17, and S19. Steps S11 to S19 of FIG. 1 are briefly introduced first, and then described in conjunction with FIG. 5 to FIG. 12. As shown in FIG. 1, the method 10 begins at step S11, which is a target layer formed on a semiconductor substrate.

Next, in step S13, a plurality of first energy-sensitive patterns are formed on the target layer. In some embodiments, the first energy-sensitive patterns are separated from each other. In some embodiments, the first energy-sensitive patterns include a cross-linking compound having a cross-linking functional group. In some embodiments, the cross-linking functional group includes a double bond.

In step S15, a lining layer is formed to cover the first energy sensitive patterns, and in step S17, a plurality of second energy sensitive patterns are formed on the lining layer. In some embodiments, the first energy sensitive patterns and the second energy sensitive patterns are arranged in an alternating manner. In some embodiments, the first energy sensitive patterns and the second energy sensitive patterns are separated from each other by the lining layer.

Next, an etching process is performed to form a plurality of first openings and a plurality of second openings in the target layer. In some embodiments, the first openings and the second openings have different depths. For example, each first opening has a first depth, the first depths are substantially the same, and each second opening has a second depth, the second depths are substantially the same, and the second depths are different from the first depths.

In some embodiments, the first openings and the second openings are arranged in a staggered manner. In some embodiments, the first openings and the second openings are separated from each other. In some embodiments, the first openings and the second openings with different depths are formed in the target layer at the same time. For example, the first openings and the second openings are formed using the same process and at the same stage. After step S19, the semiconductor device structure 100 is obtained.

FIG. 2 is a schematic flow chart illustrating a method 30 for preparing a semiconductor device structure 100 according to some embodiments of the present disclosure, and the method 30 includes steps S31, S33, S35, S37, S39, and S41. Steps S31 to S41 of FIG. 2 are briefly introduced first, and then described in conjunction with FIG. 13 to FIG. 15 or FIG. 16 to FIG. 18. Steps S31 and S33 are similar to steps S11 and S13 of FIG. 1.

After the first energy sensitive patterns are formed, in step S35, an energy processing process is performed to convert at least a portion of each first energy sensitive pattern into a processing portion. In some embodiments, each upper portion of the first energy sensitive patterns is converted into a plurality of processing portions. In some embodiments, the first energy sensitive patterns are completely converted into a plurality of processing portions. Furthermore, in some embodiments, the energy processing process includes an electron beam (e-beam) writing process. However, any other suitable process, such as an ion beam writing process, may be used instead.

Next, step S37 is similar to step S15 of FIG. 1. In some embodiments, the processed portions formed by step S35 are covered by the lining layer. Steps S39 and S41 are similar to steps S17 and S19 of FIG. 1. As described above, the first openings and the second openings having different depths are formed in the target layer at the same time. For example, the first openings and the second openings are formed using the same process and at the same stage.

FIG3 is a schematic flow chart illustrating a method 50 for preparing a semiconductor device structure 100 according to some embodiments of the present disclosure, and the method 50 includes steps S51, S53, S55, S57, S59, and S61. Steps S51 to S61 of FIG3 are briefly introduced first, and then described in conjunction with FIG19 or FIG20.

Steps S51 to S57 of FIG. 3 are similar to steps S11 to S17 of FIG. 1 . After the second energy sensitive patterns are formed, in step S59, an energy processing process is performed to convert at least a portion of each second energy sensitive pattern into a processing portion. In some embodiments, each upper portion of the second energy sensitive patterns is converted into a plurality of processing portions. In some embodiments, the second energy sensitive patterns are completely converted into a plurality of processing portions. Furthermore, in some embodiments, the energy processing process includes an electron beam writing process. However, any other suitable process, such as an ion beam writing process, may be used instead.

Next, step S61 is similar to step S19 of Fig. 1. As described above, the first openings and the second openings having different depths are formed in the target layer at the same time. For example, the first openings and the second openings are formed using the same process and at the same stage.

FIG4 is a schematic flow chart illustrating a method 70 for preparing a semiconductor device structure 100 according to some embodiments of the present disclosure, and the method 70 includes steps S71, S73, S75, S77, S79, S81, and S83. Steps S71 to S83 of FIG4 are briefly introduced first, and then described in conjunction with FIG21.

Steps S71 and S73 are similar to steps S11 and S13 of FIG. 1 . After the first energy sensitive patterns are formed, in step S75, an energy processing process is performed to convert at least a portion of each first energy sensitive pattern into a processing portion. In some embodiments, each upper portion of the second energy sensitive patterns is converted into a plurality of processing portions. In some embodiments, the second energy sensitive patterns are completely converted into a plurality of processing portions. Furthermore, in some embodiments, the energy processing process includes an electron beam writing process. However, any other suitable process, such as an ion beam writing process, may be used instead.

Next, step S77 is similar to step S15 of FIG. 1 . In some embodiments, the processing portions formed by step S75 are covered by the liner. Step S79 for forming the second energy sensitive patterns is similar to step S17 of FIG. 1 , and its details are not repeated. After the second energy sensitive patterns are formed, in step S81 , another energy processing process is performed to convert at least a portion of each second energy processing pattern into a processing portion.

In some embodiments, each upper portion of the second energy sensitive patterns is converted into a plurality of processing portions. In some embodiments, the second energy sensitive patterns are completely converted into a plurality of processing portions. Similar to the energy processing process performed on the first energy sensitive patterns in step S75, the energy processing process performed on the second energy sensitive patterns may include an electron beam writing process. However, any other suitable process, such as an ion beam writing process, may be used instead.

Next, step S83 is similar to step S19 of Fig. 1. As described above, the first openings and the second openings having different depths are formed in the target layer at the same time. For example, the first openings and the second openings are formed using the same process and at the same stage.

5 to 12 are cross-sectional schematic diagrams illustrating different stages of forming a semiconductor device structure 100 ( FIG. 12 ) by the preparation method 10 of FIG. 1 in some embodiments of the present disclosure. As shown in FIG. 5 , according to some embodiments, a target layer 103 is formed on a semiconductor substrate 101. The corresponding step is shown in step S11 in the preparation method 10 shown in FIG. 1 .

The semiconductor substrate 101 may be a semiconductor wafer, such as a silicon wafer. Alternatively or in addition, the semiconductor substrate 101 may include an elementary semiconductor material, a compound semiconductor material and/or an alloy semiconductor material. Examples of elementary semiconductor materials may include, but are not limited to, crystalline silicon, polycrystalline silicon, amorphous silicon, germanium and/or diamond. Examples of compound semiconductor materials may include, but are not limited to, silicon carbide, gallium arsenic, gallium phosphide, indium phosphide, indium arsenide and/or indium antimonide. Examples of alloy semiconductor materials may include silicon germanium (SiGe), gallium arsenide phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), gallium indium arsenide (GaInAs), gallium indium phosphide (GaInP) and/or gallium indium arsenide phosphide (GaInAsP), but are not limited thereto.

In some embodiments, the semiconductor substrate 101 includes an epitaxial layer. For example, the semiconductor substrate 101 has an epitaxial layer covering a bulk semiconductor. In some embodiments, the semiconductor substrate 101 is a semiconductor-on-insulator substrate, which may include a substrate, a buried oxide layer and a semiconductor layer, wherein the buried oxide layer is located on the substrate, the semiconductor layer is located on the buried oxide layer, and the semiconductor-on-insulator substrate is, for example, a silicon-on-insulator (SOI) substrate, a silicon germanium-on-insulator (SGOI) substrate or a germanium-on-insulator (GOI) substrate. The semiconductor substrate on insulator may be fabricated using separation by implanted oxygen (SIMOX), wafer bonding, and/or other applicable methods.

In some embodiments, the target layer 103 includes a dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, a low-k dielectric material, or other suitable materials. However, any suitable material may be used. In some embodiments, the manufacturing technique of the target layer 103 may include a deposition process, such as a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, an atomic layer deposition (ALD) process, a spin coating process, or other suitable methods.

Still referring to FIG. 5 , according to some embodiments, an energy sensitive layer 105 is formed on the target layer 103, and a patterned hard mask 107 having a plurality of openings 110 is formed on the energy sensitive layer 105. In some embodiments, the energy sensitive layer 105 includes a crosslinking compound having a crosslinking functional group. In some embodiments, the crosslinking functional group includes a double bond. In some embodiments, the crosslinking compound has a hydrogen-bonding group, a polymerizable diacetylene group, or a combination thereof. Similar to the method used to form the target layer 103, the manufacturing technique of the energy sensitive layer 105 may include a deposition process, such as a CVD process, a PVD process, an ALD process, a spin coating process or other suitable methods.

In addition, the manufacturing technique of the patterned hard mask 107 may include a process including deposition and patterning. In some embodiments, the patterned hard mask 107 includes a plurality of openings 110 that expose the energy sensitive layer 105, and the patterned hard mask 107 is used as a mask for a subsequent etching process. In some embodiments, the patterned hard mask 107 includes silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbon nitride, metal oxide or other suitable materials. In some embodiments, the patterned hard mask 107 selects an etching rate that is lower than that of the energy sensitive layer 105.

Next, as shown in FIG6 , according to some embodiments, an etching process is performed on the energy sensitive layer 105 using the patterned hard mask 107 as a mask to form a plurality of first energy sensitive patterns 115 and a plurality of openings 120. The corresponding step is shown in step S13 of the preparation method 10 shown in FIG1 . In some embodiments, the first energy sensitive patterns 115 are separated from each other by the openings 120, and the target layer 103 is exposed by the openings 120. The etching process can be a wet etching process, a dry etching process, or a combination thereof.

7 , according to some embodiments, the patterned hard mask 107 is removed after the openings 120 are formed between the first energy sensitive patterns 115. In some embodiments, the patterned hard mask 107 is removed by a stripping process, an ashing process, an etching process, or other suitable processes.

Then, as shown in FIG8 , according to some embodiments, a liner layer 123 is conformally formed to cover the first energy sensitive patterns 115 and the target layer 105. The corresponding step is shown in step S15 of the preparation method 10 shown in FIG1 . In some embodiments, a plurality of openings 130 are formed on the liner layer 123 and between the first energy sensitive patterns 115.

In some embodiments, the sidewalls 115S and the upper surfaces 115T of the first energy sensitive patterns 115 and the upper surface 103T (see FIG. 7 ) of the target layer 103 exposed through the openings 120 are covered by a liner 123. In some embodiments, the liner 123 includes an organic polymer material, such as resin, benzocyclobutene (BCB), or other suitable materials. In some embodiments, the manufacturing technology of the liner 123 includes a deposition process, such as a CVD process, a PVD process, an ALD process, or other suitable methods.

Next, as shown in FIG9 , according to some embodiments, a plurality of second energy sensitive patterns 137 are formed on the liner 123. In some embodiments, the openings 130 on the liner 123 and between the first energy sensitive patterns 115 are filled with the second energy sensitive patterns 137. In some embodiments, the first energy sensitive patterns 115 and the second energy sensitive patterns 137 are arranged in an alternating pattern. The corresponding step is shown in step S17 of the preparation method 10 shown in FIG1 .

Some materials used to form the second energy sensitive patterns 137 may be similar to or the same as the materials used to form the first energy sensitive patterns 115, and will not be repeated herein. In the present embodiment, the first energy sensitive patterns 115 and the second energy sensitive patterns 130 comprise different materials. In some embodiments, the manufacturing techniques of the second energy sensitive patterns 137 include a deposition process and a subsequent planarization process. For example, an energy sensitive layer (not shown) is formed to cover the structure of FIG. 8 , and the energy sensitive layer is planarized until the liner 123 is exposed. The planarization process may include a polishing process, a chemical mechanical polishing (CMP) process, an etching process, or a combination thereof.

In some embodiments, each lower surface 137B of the second energy sensitive patterns 137 is higher than each lower surface 115B of the first energy sensitive patterns 115. In some embodiments, each upper surface 137T of the second energy sensitive patterns 137 is higher than each upper surface 115T of the first energy sensitive patterns 115. In some embodiments, the upper surface 115T of the first energy sensitive patterns 115 is higher than each lower surface 137B of the second energy sensitive patterns 137.

Next, as shown in FIG. 10 to FIG. 12, according to some embodiments, an etching process is performed to form a plurality of first openings 180 and a plurality of second openings 170 in the target layer 103. The corresponding step is shown in step S19 of the preparation method 10 shown in FIG. 1. FIG. 10 to FIG. 12 respectively show different stages in the etching process according to some embodiments.

In some embodiments, during the etching process, the etching rates of the first energy sensitive patterns 115 and the second energy sensitive patterns 137 are each greater than the etching rate of the liner 123, and because they include different materials, the etching rate of the first energy sensitive patterns 115 is different from the etching rate of the second energy sensitive patterns 137. In this embodiment, the etching rate of the first energy sensitive patterns 115 is greater than the etching rate of the second energy sensitive patterns 137, but the disclosure is not limited thereto. In an alternative embodiment, the etching rate of the second energy sensitive patterns 137 is greater than the etching rate of the first energy sensitive patterns 115.

As shown in FIG10 , according to some embodiments, during the first stage of the etching process, a plurality of openings 140 are formed between every two adjacent first energy sensitive patterns 115 because the etching rate of the second energy sensitive patterns 137 is higher than the etching rate of the liner 123. Then, as shown in FIG11 , according to some embodiments, during the second stage of the etching process, the openings 140 are deepened to form a plurality of openings 150, and the first energy sensitive patterns 115 are etched to form a plurality of openings 160.

In some embodiments, since the etching rate of the first energy sensitive patterns 115 is greater than the etching rate of the liner layer 123, the lower surfaces of the openings 150 are higher than the lower surfaces of the openings 160. In some embodiments, the openings 160 reach the target layer 103. For example, the upper surface 103T of the target layer 103 is partially exposed by the openings 160, but is not exposed by the openings 150.

Next, as shown in FIG. 12 , according to some embodiments, during the final stage of the etching process, the openings 160 and 150 are deepened to form the first openings 180 and the second openings 170 in the target layer 103. Since the etching rates of the first energy sensitive patterns 115 and the second energy sensitive patterns 137 are different, the openings 170 and 180 have different depths. For example, each first opening 180 has a first depth D1, which are substantially the same, and each second opening 170 has a second depth D2, which are substantially the same, and the second depths D2 are different from the first depths D1.

As described above, in the present embodiment, since the etching rate of the first energy sensitive patterns 115 is greater than the etching rate of the second energy sensitive patterns 137, each first depth D1 of the first openings 180 is greater than each second depth D2 of the second openings 170. However, in an alternative embodiment, since the etching rate of the second energy sensitive patterns 137 is greater than the etching rate of the first energy sensitive patterns 115, each second depth D2 of the second openings 170 is greater than each first depth D1 of the first openings 180. After the first openings 180 and the first openings 170 are formed in the target layer 103, the semiconductor device structure 100 is obtained.

13 to 15 are schematic cross-sectional views illustrating different stages of forming the semiconductor device structure 100 ( FIG. 12 ) by the preparation method 30 of FIG. 2 according to some embodiments of the present disclosure. As shown in FIG. 13 , according to some embodiments, after the target layer 103 and the first energy sensitive patterns 115 are formed (corresponding to steps S31 and S33 of FIG. 2 , and the details thereof have been discussed in the embodiments with reference to FIG. 5 to FIG. 7 ), an energy treatment process is performed to transform the upper portions of the first energy sensitive patterns 115 into a plurality of treatment portions 209. The corresponding step is shown in step S35 of the preparation method 30 shown in FIG. 2 .

In some embodiments, the energy treatment process includes an electron beam writing process, an ion beam writing process or other suitable processes. Furthermore, in some embodiments, the energy source of the energy treatment process includes an electron beam, an ion beam, visible light, ultraviolet light (UV), deep ultraviolet light (DUV), extreme ultraviolet light (EUV), X-ray or other suitable energy sources.

Next, as shown in FIG. 14 , according to some embodiments, a liner 123 is conformally formed to cover the first energy sensitive patterns 115. The corresponding step is shown in step S37 of the preparation method 30 shown in FIG. 2 . In some embodiments, each upper surface 209T and each sidewall 209S of the processing portions 209 are covered by the liner 123. In some embodiments, the openings 130 are formed on the liner 123 and between any two adjacent first energy sensitive patterns 115 (or between any two adjacent processing portions 209). The details of the liner 123 are substantially the same as those in FIG. 8 , and therefore are not repeated herein.

Then, as shown in FIG. 15 , according to some embodiments, the second energy sensitive patterns 137 are formed on the liner layer 123. The corresponding step is shown in step S39 of the preparation method 30 shown in FIG. 2 . In some embodiments, the openings 130 are filled with the second energy sensitive patterns 137. In some embodiments, the first energy sensitive patterns 115 (or the processing portions 209) and the second energy sensitive patterns 137 are arranged in a staggered configuration.

The details of the second energy sensitive patterns 137 are substantially the same as those in FIG9 and are therefore not repeated herein. In this embodiment, the first energy sensitive patterns 115 (eg, the material of the unprocessed portions of the first energy sensitive patterns 115) and the second energy sensitive patterns 137 are substantially the same.

After the second energy sensitive patterns 137 are formed, an etching process is performed in multiple stages using the processes described above, which are not repeated. In some embodiments, during the etching process, the etching rate of the processing portions 209 is different from the etching rates of the first energy sensitive patterns 115 and the second energy sensitive patterns 137. In the present embodiment, the etching rate of the processing portions 209 is greater than the etching rates of the first energy sensitive patterns 115 and the second energy sensitive patterns 137, but the present disclosure is not limited thereto. In an alternative embodiment, the etching rate of the processing portions 209 is less than the etching rates of the first energy sensitive patterns 115 and the second energy sensitive patterns 137.

As shown in FIG. 12 , according to some embodiments, after the etching process is performed, the first openings 180 and the second openings 170 are formed in the target layer 103. The details of the openings in the target layer 103 are not repeated. The corresponding step is shown in step S41 of the preparation method 30 shown in FIG. 2 . After the first openings 180 and the second openings 170 are formed, the semiconductor device structure 100 is obtained.

16 to 18 are schematic cross-sectional views illustrating different stages of forming the semiconductor device structure 100 ( FIG. 12 ) by the fabrication method 30 of FIG. 2 according to some alternative embodiments of the present disclosure. The fabrication method described in FIG. 16 to 18 is similar to or the same as the fabrication method described in FIG. 13 to 15 , except that the first energy sensitive patterns 115 are completely converted into a plurality of processed portions 309. In other words, after the energy processing process is performed, no unprocessed portions are left in the first energy sensitive patterns 115.

As shown in FIG. 16 , according to some embodiments, similar to the steps shown in FIG. 13 , after the target layer 103 and the first energy sensitive patterns 115 are formed (corresponding to steps S31 and S33 of FIG. 2 , the details of which have been discussed in the embodiments with reference to FIGS. 5 to 7 ), an energy treatment process is performed to completely transform the first energy sensitive patterns 115 into the treatment portions 309. The corresponding step is step S35 in the preparation method 30 shown in FIG. 2 .

As shown in FIG. 17 , in some embodiments, after the processing portions 309 are formed, a liner 123 is conformally formed to cover each upper surface 309T and each sidewall 309S of the processing portions 309. The corresponding step is shown in step S37 of the preparation method 30 shown in FIG. 2 . Then, as shown in FIG. 18 , according to some embodiments, the second energy sensitive patterns 137 are formed on the liner 123. The corresponding step is shown in step S39 of the preparation method 30 shown in FIG. 2 . In some embodiments, the processing portions 309 (converted from the first energy sensitive patterns 115) and the second energy sensitive patterns 137 are arranged in a staggered configuration.

In the present embodiment, the materials of the first energy sensitive patterns 115 (e.g., the material of the first energy sensitive patterns 115 before processing) and the second energy sensitive patterns 137 are substantially the same. After the second energy sensitive patterns 137 are formed, an etching process is performed in multiple stages using the processes described above (refer to FIGS. 10 to 12 ), which are not repeated. In some embodiments, during the etching process, the etching rate of the processing portions 309 is different from the etching rate of the second energy sensitive patterns 137. In the present embodiment, the etching rate of the processing portions 309 is greater than the etching rate of the second energy sensitive patterns 137, but the present disclosure is not limited thereto. In an alternative embodiment, the etching rate of the processing portions 309 is less than the etching rate of the second energy sensitive patterns 137 .

As shown in FIG. 12 , according to some embodiments, after the etching process is performed, the first openings 180 and the second openings 170 are formed in the target layer 103. The details of the openings in the target layer 103 are not repeated. The corresponding step is shown in step S41 in the preparation method 30 shown in FIG. 2 . After the first openings 180 and the second openings 170 are formed in the target layer 103, the semiconductor device structure 100 is obtained.

FIG. 19 is a schematic cross-sectional view illustrating an intermediate stage of forming the semiconductor device structure 100 ( FIG. 12 ) by the preparation method 50 of FIG. 3 in some embodiments of the present disclosure. As shown in FIG. 19 , the target layer 103, the first energy sensitive patterns 115, the liner layer 123, and the second energy sensitive patterns 137 are formed corresponding to steps S51 to S57 of FIG. 3 , and the details have been discussed in the embodiments with reference to FIGS. 5-9 . In the present embodiment, the materials of the first energy sensitive patterns 115 and the second energy sensitive patterns 137 are substantially the same.

Next, according to some embodiments, an energy treatment process is performed on the second energy sensitive patterns 137 so that each upper portion of the second energy sensitive patterns 137 is converted into a plurality of treatment portions 409. The corresponding step is shown in step S59 of the preparation method 50 shown in FIG. 3. In some embodiments, the energy treatment process includes an electron beam writing process, an ion beam writing process, or other suitable processes. In addition, in some embodiments, the energy source of the energy treatment process includes an electron beam, an ion beam, visible light, UV, DUV, EUV, X-ray, or other suitable energy sources.

After the processing portions 409 are formed, an etching process is performed in multiple stages using the processes described above (refer to FIGS. 10 to 12 ), which will not be repeated. In some embodiments, after the etching process, the etching rate of the processing portions 409 is different from the etching rates of the first energy sensitive patterns 115 and the second energy sensitive patterns 137. In the present embodiment, the etching rate of the processing portions 409 is less than the etching rate of the first energy sensitive patterns 115 and the etching rate of the second energy sensitive patterns 137 (e.g., the etching rate of the unprocessed portions of the second energy sensitive patterns 137), but the present disclosure is not limited thereto. In an alternative embodiment, the etching rate of the processing portions 409 is greater than the etching rate of the first energy sensitive patterns 115 and the etching rate of the second energy sensitive patterns 137 .

As shown in FIG. 12 , according to some embodiments, after the etching process is performed, the first openings 180 and the second openings 170 are formed in the target layer 103. The details of the openings in the target layer 103 are not repeated. The corresponding step is shown in step S61 of the preparation method 50 shown in FIG. 3 . After the first openings 180 and the second openings 170 are formed in the target layer 103, the semiconductor device structure 100 is obtained.

FIG20 is a cross-sectional schematic diagram illustrating an intermediate stage of forming the semiconductor device structure 100 (FIG. 12) by the fabrication method 50 of FIG3 according to some alternative embodiments of the present disclosure. The fabrication method described in FIG20 is similar to or the same as the fabrication method in FIG19, except that the second energy sensitive patterns 137 are completely converted into a plurality of processed portions 509. In other words, after the energy processing process is performed, no unprocessed portions are left in the first energy sensitive patterns 115.

As shown in Fig. 20, the target layer 103, the first energy sensitive patterns 115, the liner layer 123, and the second energy sensitive patterns 137 are formed corresponding to steps S51 to S57 of Fig. 3, and the details have been discussed in the embodiments with reference to Fig. 5 to Fig. 9. In this embodiment, the materials of the first energy sensitive patterns 115 and the second energy sensitive patterns 137 (e.g., the materials of the second energy sensitive patterns 137 before processing) are substantially the same.

Then, according to some embodiments, an energy treatment process is performed to completely transform the second energy sensitive patterns 137 into a plurality of treatment portions 509. The corresponding step is shown in step S59 of the preparation method 50 shown in FIG3. After the treatment portions 509 are formed, an etching process is performed in multiple stages using the processes described above (refer to FIGS. 10 to 12), which will not be repeated.

In some embodiments, during the etching process, the etching rate of the processing portions 509 is different from the etching rate of the first energy sensitive patterns 115. In the present embodiment, the etching rate of the processing portions 509 is less than the etching rate of the first energy sensitive patterns 115, but the present disclosure is not limited thereto. In an alternative embodiment, the etching rate of the processing portions 509 is greater than the etching rate of the first energy sensitive patterns 115.

As shown in FIG. 12 , according to some embodiments, after the etching process is performed, the first openings 180 and the second openings 170 are formed in the target layer 103. The details of the openings in the target layer 103 are not repeated. The corresponding step is shown in step S61 of the preparation method 50 shown in FIG. 3 . After the first openings 180 and the second openings 170 are formed, the semiconductor device structure 100 is obtained.

FIG. 21 is a cross-sectional schematic diagram illustrating an intermediate stage of forming the semiconductor device structure 100 ( FIG. 12 ) by the preparation method 70 of FIG. 4 according to some alternative embodiments of the present disclosure. As shown in FIG. 21 , according to some embodiments, after the target layer 103 and the first energy sensitive patterns 115 are formed (corresponding to steps S71 and S73 of FIG. 4 , and the details thereof have been discussed in the embodiments of FIG. 5 to FIG. 7 ), an energy treatment process is performed on the first energy sensitive patterns 115 to convert the upper portions of the first energy sensitive patterns 115 into a plurality of treatment portions 609. The corresponding step is shown in step S75 of the preparation method 70 shown in FIG. 4 . The details of the energy treatment process will not be repeated.

Then, a liner 123 is formed in parallel to cover the first energy sensitive patterns 115, the processing parts 609 and the target layer 103, and the second energy sensitive patterns 137 are formed on the liner 123. The corresponding steps are shown in steps S77 and S79 in the preparation method 70 shown in FIG. 4. In some embodiments, the upper surface 609T and the side walls 609S of the processing parts 609 are covered by the liner 123. In this embodiment, the material of the first energy sensitive patterns 115 (e.g., the material of the first energy sensitive patterns 115 before processing) and the material of the second energy sensitive patterns 137 are substantially the same.

Next, according to some embodiments, another energy treatment process is performed on the second energy sensitive patterns 137 to convert the upper portions of the second energy sensitive patterns 137 into a plurality of treatment portions 619. The corresponding step is shown in step S81 of the preparation method 70 shown in FIG4 . In some embodiments, the parameters of the energy treatment process performed on the second energy sensitive patterns 137 are different from the parameters of the energy treatment process performed on the first energy sensitive patterns 115. For example, the energy levels applied to the two energy treatment processes are different.

After the processing portions 619 are formed, an etching process is performed in multiple stages using the processes described above (refer to Figures 10 to 12), which will not be repeated. In some embodiments, during the etching process, the etching rate of the processing portions 609 is different from the etching rate of the processing portions 619. As shown in Figure 12, according to some embodiments, after the etching process is performed, the first openings 180 and the second openings 170 are formed in the target layer 103. The details of the openings in the target layer 103 are not repeated. The corresponding step is shown in step S83 in the preparation method 70 shown in Figure 4. After the first openings 180 and the second openings 170 are formed, the semiconductor device structure 100 is obtained.

In the present disclosure, a method for preparing a semiconductor device structure having multiple openings with different depths (e.g., depth D1 is different from depth D2) is provided. The preparation method includes forming a first energy-sensitive pattern (e.g., one of the first energy-sensitive patterns 115) on a target layer (e.g., target layer 103), forming a liner layer (e.g., liner layer 123) to cover the first energy-sensitive pattern, and forming a second energy-sensitive pattern (e.g., one of the second energy-sensitive patterns 137) on the liner layer. In some embodiments, the first energy-sensitive pattern and the second energy-sensitive pattern are arranged in an alternating manner. The preparation method also includes performing an etching process to form multiple openings (e.g., the openings 170 and 180) in the target layer, and the openings have different depths.

In some embodiments, before the lining layer is formed, an energy treatment process is performed on the first energy sensitivity pattern to convert at least a portion of the first energy sensitivity pattern into a treatment portion. In some embodiments, before the etching process is performed, an energy treatment process is performed on the second energy sensitivity pattern to convert at least a portion of the second energy sensitivity pattern into a treatment portion. In some embodiments, before the lining layer is formed, an energy treatment process is performed on the first energy sensitivity pattern to convert at least a portion of the first energy sensitivity pattern into a treatment portion, and before the etching process is performed, another energy treatment process is performed on the second energy sensitivity pattern to convert at least a portion of the second energy sensitivity pattern into a treatment portion. Since the etching rates of the processing portions are different from those of the first and second energy sensitive patterns, the openings with different depths can be formed in the target layer through the etching process. Therefore, the manufacturing cost and time of the semiconductor device structure (such as the semiconductor device structure 100) can be reduced, and better design flexibility can be enhanced.

One embodiment of the present disclosure provides a method for preparing a semiconductor device structure. The preparation method includes forming a target layer on a semiconductor substrate; and forming a first energy-sensitive pattern on the target layer. The preparation method also includes forming a liner to cover the first energy-sensitive pattern; and forming a second energy-sensitive pattern on the liner. The first energy-sensitive pattern and the second energy-sensitive pattern are arranged in an alternating manner. The preparation method also includes performing an etching process to form a first opening and a second opening in the target layer. The first opening and the second opening have different depths.

Another embodiment of the present disclosure provides a method for preparing a semiconductor device structure. The preparation method includes forming a target layer on a semiconductor substrate; and forming a plurality of first energy-sensitive patterns on the target layer. The preparation method also includes forming a liner layer to conformally cover the first energy-sensitive patterns. A first opening is formed on the liner layer and between the first energy-sensitive patterns. The preparation method also includes filling the first opening with a second energy-sensitive pattern; and performing an etching process to form a plurality of second openings and a third opening in the target layer, wherein the third opening is located between the second openings, and the second openings and the third opening have different depths.

The embodiments of the present disclosure have some advantageous features. By forming the liner layer and the first and second energy sensitive patterns on the target layer, the openings with different depths can be formed in the target layer at the same time. Therefore, the manufacturing cost and time can be reduced, and better design flexibility can be achieved.

Although the present disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions and replacements can be made without departing from the spirit and scope of the present disclosure as defined by the scope of the patent application. For example, many of the above processes can be implemented in different ways, and other processes or combinations thereof can be used to replace many of the above processes.

Furthermore, the scope of this application is not limited to the specific embodiments of the processes, machines, manufactures, material compositions, means, methods, and steps described in the specification. A person skilled in the art can understand from the disclosure of this disclosure that existing or future developed processes, machines, manufactures, material compositions, means, methods, or steps that have the same functions or achieve substantially the same results as the corresponding embodiments described herein can be used according to this disclosure. Accordingly, such processes, machines, manufactures, material compositions, means, methods, or steps are included in the scope of the patent application of this application.

10: Preparation method 100: Semiconductor device structure 101: Semiconductor substrate 103: Target layer 103T: Upper surface 105: Energy sensitive layer 107: Patterned hard mask 110: Opening 115: First energy sensitive pattern 115B: Lower surface 115T: Upper surface 115S: Sidewall 115T: Upper surface 120: Opening 123: Lining layer 130: Opening 137: Second energy sensitive pattern 137B: Lower surface 137T: Upper surface 140: Opening 150: Opening 160: Opening 170: Second opening 180: First opening 209: Processing unit 209S: side wall 209T: upper surface 30: preparation method 309: processing part 309S: side wall 309T: upper surface 409: processing part 50: preparation method 509: processing part 609: processing part 609S: side wall 609T: upper surface 619: processing part D1: first depth D2: second depth S11: step S13: step S15: step S17: step S19: step S31: step S33: step S35: step S37: step S39: step S41: step S51: step S53: step S55: step S57: step S59: step S61: step S71: step S73: step S75: step S77: step S79: step S81: step S83: step

When referring to the embodiments and the scope of the patent application together with the drawings, a more comprehensive understanding of the disclosure of the present application can be obtained. The same element symbols in the drawings refer to the same elements. FIG. 1 is a flow diagram illustrating a method for preparing a semiconductor element structure of some embodiments of the present disclosure. FIG. 2 is a flow diagram illustrating a method for preparing a semiconductor element structure of some embodiments of the present disclosure. FIG. 3 is a flow diagram illustrating a method for preparing a semiconductor element structure of some embodiments of the present disclosure. FIG. 4 is a flow diagram illustrating a method for preparing a semiconductor element structure of some embodiments of the present disclosure. FIG. 5 is a cross-sectional diagram illustrating an intermediate stage of sequentially forming a target layer, an energy sensitive layer, and a patterned hard mask on a semiconductor substrate during the formation of a semiconductor element structure in some embodiments of the present disclosure. FIG. 6 is a schematic cross-sectional view illustrating an intermediate stage of etching the energy-sensitive layer using the patterned hard mask as a mask during the formation of the semiconductor device structure to form a plurality of first energy-sensitive patterns in some embodiments of the present disclosure. FIG. 7 is a schematic cross-sectional view illustrating an intermediate stage of removing the patterned hard mask during the formation of the semiconductor device structure in some embodiments of the present disclosure. FIG. 8 is a schematic cross-sectional view illustrating an intermediate stage of forming a liner to cover the first energy-sensitive patterns during the formation of the semiconductor device structure in some embodiments of the present disclosure. FIG. 9 is a schematic cross-sectional view illustrating an intermediate stage of forming a plurality of second energy-sensitive patterns on the liner during the formation of the semiconductor device structure in some embodiments of the present disclosure. FIG. 10 to FIG. 12 are schematic cross-sectional views illustrating an intermediate stage of performing an etching process to form a plurality of openings in the target layer during the formation of a semiconductor device structure in some embodiments of the present disclosure. FIG. 13 is a schematic cross-sectional view illustrating an intermediate stage of performing an energy treatment process to convert each upper portion of the first energy sensitive patterns into a plurality of treatment portions during the formation of a semiconductor device structure in some embodiments of the present disclosure. FIG. 14 is a schematic cross-sectional view illustrating an intermediate stage of forming a liner to cover the first energy sensitive patterns and the treatment portions during the formation of a semiconductor device structure in some embodiments of the present disclosure. FIG. 15 is a schematic cross-sectional view illustrating an intermediate stage of forming a plurality of second energy-sensitive patterns on the liner during the formation of the semiconductor device structure in some embodiments of the present disclosure. FIG. 16 is a schematic cross-sectional view illustrating an intermediate stage of performing an energy processing process to convert the first energy-sensitive patterns into a plurality of processing portions during the formation of the semiconductor device structure in some embodiments of the present disclosure. FIG. 17 is a schematic cross-sectional view illustrating an intermediate stage of forming a liner to cover the processing portions during the formation of the semiconductor device structure in different embodiments of the present disclosure. FIG. 18 is a schematic cross-sectional view illustrating an intermediate stage of forming a plurality of second energy-sensitive patterns on the liner during the formation of the semiconductor device structure in some embodiments of the present disclosure. FIG. 19 is a schematic cross-sectional view illustrating an intermediate stage of performing an energy treatment process during the formation of a semiconductor device structure to convert each upper portion of the second energy sensitive patterns into the processing portions according to some embodiments of the present disclosure. FIG. 20 is a schematic cross-sectional view illustrating an intermediate stage of performing an energy treatment process during the formation of a semiconductor device structure to convert each upper portion of the second energy sensitive patterns into the processing portions according to some embodiments of the present disclosure. FIG. 21 is a schematic cross-sectional view illustrating an intermediate stage of performing an energy treatment process during the formation of a semiconductor device structure to convert each upper portion of the first energy sensitive patterns into the processing portions, and performing another energy treatment process to convert each upper portion of the second energy sensitive patterns into the processing portions according to some embodiments of the present disclosure.

100:Semiconductor device structure

101:Semiconductor substrate

103: Target layer

170: Second opening

180: First opening

D1: First Depth

D2: Second Depth

Claims (15)

A method for preparing a semiconductor device structure includes: forming a target layer on a semiconductor substrate; forming a first energy sensitive pattern on the target layer; forming a liner layer to cover the first energy sensitive pattern; forming a second energy sensitive pattern on the liner layer, wherein the first energy sensitive pattern and the second energy sensitive pattern are arranged in a staggered manner; and performing an etching process to remove the first energy sensitive pattern to form a first opening and remove the second energy sensitive pattern to form a second opening in the target layer, wherein the first opening and the second opening have different depths. A method for preparing a semiconductor device structure as described in claim 1, wherein the first opening and the second opening are arranged in an alternating manner. A method for preparing a semiconductor device structure as described in claim 1, wherein the second energy sensitive pattern is separated from the first energy sensitive pattern by the liner layer. A method for preparing a semiconductor device structure as described in claim 1, wherein an upper surface and each side wall of the first energy sensitive pattern are covered by the liner. A method for preparing a semiconductor device structure as described in claim 1, wherein a lower surface of the second energy-sensitive pattern is higher than a lower surface of the first energy-sensitive pattern. A method for preparing a semiconductor device structure as described in claim 1, wherein an upper surface of the second energy-sensitive pattern is higher than an upper surface of the first energy-sensitive pattern. A method for preparing a semiconductor device structure as described in claim 1, wherein an upper surface of the first energy-sensitive pattern is higher than a lower surface of the second energy-sensitive pattern. A method for preparing a semiconductor device structure as described in claim 1, wherein the lining layer comprises an organic polymer material. A method for preparing a semiconductor device structure as described in claim 1, wherein during the etching process, the first energy sensitive pattern, the second energy sensitive pattern and the lining layer are removed. A method for preparing a semiconductor device structure as described in claim 1, wherein the first energy-sensitive pattern and the second energy-sensitive pattern comprise different materials. A method for preparing a semiconductor device structure as described in claim 1, wherein a material of the first energy-sensitive pattern is the same as a material of the second energy-sensitive pattern. The method for preparing a semiconductor device structure as described in claim 11 further includes performing an energy treatment process to convert an upper portion of the first energy sensitive pattern into a treatment portion before the liner is formed. A method for preparing a semiconductor device structure as described in claim 12, wherein during the etching process, an etching rate of the processing portion is different from an etching rate of the second energy sensitive pattern. The method for preparing a semiconductor device structure as described in claim 11 further includes performing an energy treatment process to convert an upper portion of the second energy treatment pattern into a treatment portion before the etching process. A method for preparing a semiconductor device structure as described in claim 14, wherein during the etching process, an etching rate of the processing portion is different from an etching rate of the first energy sensitive pattern.