TWI853495B - Electronic package module and method for fabrication of the same - Google Patents
Electronic package module and method for fabrication of the same Download PDFInfo
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本發明有關於一種電子封裝模組,特別是指一種元件內嵌的封裝模組及其製造方法。The present invention relates to an electronic packaging module, in particular to a component embedded packaging module and a manufacturing method thereof.
表面黏著技術(surface mount technology, SMT)是通過線路基板表面的焊料,將電子元件設置於線路基板表面上的一種製程。SMT使電子元件的大小不再受到傳統焊腳的最小尺寸限制,而可以縮得更小,進而大幅提升電子產品的輕薄性。不過,即便電子元件的尺寸因SMT的發展而得以縮小,但在實際應用上,仍有瓶頸難以突破。Surface mount technology (SMT) is a process that places electronic components on the surface of a circuit substrate through solder on the surface of the circuit substrate. SMT allows the size of electronic components to be smaller, rather than limited by the minimum size of traditional solder pins, thereby greatly improving the lightness and thinness of electronic products. However, even though the size of electronic components has been reduced due to the development of SMT, there are still bottlenecks that are difficult to break through in actual applications.
封裝模組中包含了尺寸相對較小的主動元件(active element)以及尺寸相對較大的被動元件(passive element),當大小不同的電子元件設置於同一個線路基板的表面上,會導致各元件頂端的高度不一致。而為了使塑封層(encapsulation)能覆蓋到較高的電子元件,封裝模組整體的尺寸(即厚度)會受限於較大的電子元件的高度而不易縮小。The package module contains relatively small active elements and relatively large passive elements. When electronic components of different sizes are placed on the surface of the same circuit substrate, the height of the top of each component will be inconsistent. In order to allow the plastic encapsulation layer to cover the taller electronic components, the overall size (thickness) of the package module will be limited by the height of the larger electronic components and is not easy to shrink.
另一方面,若將被動元件與主動元件分開設置於不同平面上,例如將被動元件設置於主板上,而主動元件則設置於主板上的線路基板上。在這種情形下,為了完全電磁屏蔽這些電子元件,電磁屏蔽層除了覆蓋到線路基板外,尚須包覆蓋主板的一部分。如此一來,不僅增加封裝模組的體積,也提升製作電磁屏蔽層的難度。On the other hand, if the passive components and active components are separately placed on different planes, for example, the passive components are placed on the mainboard, and the active components are placed on the circuit substrate on the mainboard. In this case, in order to completely electromagnetically shield these electronic components, the electromagnetic shielding layer must not only cover the circuit substrate, but also cover part of the mainboard. This not only increases the volume of the package module, but also increases the difficulty of making the electromagnetic shielding layer.
因此,本發明提供了一種電子封裝模組以及其製造方法,藉以減少電子封裝模組的厚度。Therefore, the present invention provides an electronic packaging module and a manufacturing method thereof, so as to reduce the thickness of the electronic packaging module.
本發明提供了一種電子封裝模組的製造方法,包含形成一承載線路板,此承載線路板包含一第一表面與一第二表面,其中第一表面與第二表面分別位於承載線路板的兩側;移除承載線路板的一部分,以形成一開口,此開口沿著承載線路板的法線方向而延伸,並且連通第一表面與第二表面;在承載線路板上設置一固著物,其中固著物與開口重疊;在承載線路板的第一表面上,設置一第一電子元件;在固著物上,設置一第二電子元件,使第二電子元件穿過開口;將第二電子元件電性連接承載線路板;以及在電性連接第二電子元件以及承載線路板之後,在承載線路板上形成一第一密封層,而此第一密封層包覆第一電子元件以及第二電子元件。The present invention provides a manufacturing method of an electronic packaging module, comprising forming a carrier circuit board, the carrier circuit board comprising a first surface and a second surface, wherein the first surface and the second surface are respectively located on two sides of the carrier circuit board; removing a portion of the carrier circuit board to form an opening, wherein the opening extends along the normal direction of the carrier circuit board and connects the first surface and the second surface; arranging a fixture on the carrier circuit board, wherein the fixture overlaps with the opening; arranging a first electronic component on the first surface of the carrier circuit board; arranging a second electronic component on the fixture, so that the second electronic component passes through the opening; electrically connecting the second electronic component to the carrier circuit board; and after electrically connecting the second electronic component and the carrier circuit board, forming a first sealing layer on the carrier circuit board, wherein the first sealing layer covers the first electronic component and the second electronic component.
本發明還提供一種電子封裝模組,包含一承載線路板,此承載線路板包含一開口、一第一表面以及相對於第一表面的一第二表面,且開口連通承載線路板的第一表面與第二表面。電子封裝模組還包含一第一電子元件以及一第二電子元件,第一電子元件位於承載線路板的第一表面上,第二電子元件位於開口內,並且電性連接承載線路板。電子封裝模組還包含一第一密封層,包覆第一電子元件以及第二電子元件,其中第一電子元件的厚度小於第二電子元件的厚度。The present invention also provides an electronic packaging module, comprising a supporting circuit board, the supporting circuit board comprising an opening, a first surface and a second surface opposite to the first surface, and the opening connects the first surface and the second surface of the supporting circuit board. The electronic packaging module also comprises a first electronic component and a second electronic component, the first electronic component is located on the first surface of the supporting circuit board, the second electronic component is located in the opening, and is electrically connected to the supporting circuit board. The electronic packaging module also comprises a first sealing layer, covering the first electronic component and the second electronic component, wherein the thickness of the first electronic component is less than the thickness of the second electronic component.
基於上述,本發明將厚度較大的電子元件設置在承載線路板的開口內,並且電性連接於承載線路板,而其他厚度較小的電子元件則設置於承載線路板表面。如此一來,能減少這兩種電子元件的頂面之間的差距,進而減少密封層的厚度,達成薄化電子封裝模組的功效。Based on the above, the present invention places thicker electronic components in the opening of the supporting circuit board and electrically connects to the supporting circuit board, while other thinner electronic components are placed on the surface of the supporting circuit board. In this way, the gap between the top surfaces of the two electronic components can be reduced, thereby reducing the thickness of the sealing layer and achieving the effect of thinning the electronic packaging module.
本發明至少一實施例揭露一種電子封裝模組的製造方法,由圖1A至圖1G中的一系列步驟來說明本發明的至少一實施例。請參考圖1A,首先,提供線路基板100,此線路基板100具有表面100f以及相對於表面100f的表面100s。接著,如圖1B所示,在線路基板100上設置電子元件102以及中介基板103。其中電子元件102以及中介基板103皆位於表面100s上,並且在本實施例的圖式中,繪示出兩個電子元件102作為說明。然而本發明不限於此,電子元件102的數量可以是一個以上,例如一個或三個。At least one embodiment of the present invention discloses a method for manufacturing an electronic package module, and at least one embodiment of the present invention is illustrated by a series of steps in FIG. 1A to FIG. 1G. Referring to FIG. 1A, first, a
在部分的實施例中,線路基板100還可包含至少一層防焊層(solder mask,未繪示),此防焊層可以覆蓋線路基板100的表面100s並暴露出多個接墊(pad,未繪示)在表面100s上。而電子元件102則是通過這些接墊,以多個焊點104焊接於線路基板100上,以使電子元件102與線路基板100電性連接。這些焊點104可以是錫球、銅柱或適用於電性連接的各種連接結構。此外,在其他實施例中,還可以利用打線(wire-bonding)的方式將電子元件102與線路基板100電性連接。其中電子元件102可以是已封裝的晶片(chip)或者未經封裝的晶粒(die)。In some embodiments, the
請繼續參考圖1B,與電子元件102連接線路基板100的方式相同,中介基板103也是通過暴露於線路基板100上的接墊(未繪示),以多個焊點104與線路基板100電性連接。中介基板103包含接面103i,此接面103i背對於線路基板100的表面100s。在本實施例中,中介基板103的數量為一個,並且包含一個開口103o,而電子元件102則是設置於開口103o中。在本發明的其他實施例中,中介基板103的數量不限於一個,且每一個中介基板103可以包含一個以上(例如一個)的開口103o。Please continue to refer to FIG. 1B . Similar to the way in which the
請參考圖1C,在線路基板100上設置電子元件102以及中介基板103之後,在表面100s上形成密封層106。密封層106包覆電子元件102以及中介基板103,並且具有遠離線路基板100的表面106s。此密封層106的材料可以包含有機樹脂(如環氧樹脂)等絕緣材料或其相似物。至此,形成了包含線路基板100、電子元件102、中介基板103以及密封層106的承載線路板10。如圖1C所示,表面100f以及表面106s分別位於承載線路板10的兩側,換言之,承載線路板10包含彼此相對的表面100f以及表面106s。Referring to FIG. 1C , after the
請接著參考圖1D,可以通過例如機械切割、雷射切割或離子束切割等方式,移除承載線路板10的一部分,以形成開口120。開口120是沿著承載線路板10的法線方向N1而延伸,並且連通表面100f以及表面106s。具體而言,移除線路基板100的一部分以及密封層106的一部分,且移除的這兩個部分在法線方向N1上互相重疊,以形成完全穿透承載線路板10的開口120。Referring to FIG. 1D , a portion of the
如圖2的承載線路板10的上視圖所示,在本實施例中,開口120的數量為一個,且開口120與表面100f(以及表面106s)交會的界線120d可圍繞成長方形。然而本發明中,承載線路板10中開口120的數量不限於一個,可以是一個以上,且與表面100f(以及表面106s)交會的界線120d可以是任意形狀,例如圍繞成圓形或者正方形。此外,在其他的實施例中,開口120也可以呈非封閉的條狀。As shown in the top view of the
請參考圖1E,形成開口120之後,在承載線路板10上設置固著物140,且此固著物140與開口120重疊。舉例而言,本實施例是在承載線路板10的表面106s上貼合膠帶(即圖1E的固著物140),且此膠帶覆蓋開口120。為了能貼附於表面106s,本實施例中的膠帶會完全覆蓋開口120,並且超出界線120d。值得一提的是,在本發明的其他實施例中,固著物140並不限於膠帶,亦可以是其他具有固定功能的裝置。Please refer to FIG. 1E . After the
接下來,如圖1F所示,在承載線路板10的表面100f上,設置電子元件160a。此外,圖1F的步驟還包含在固著物140上設置電子元件160b,並且使電子元件160b穿過開口120。其中電子元件160b可直接接觸於固著物140。例如,電子元件160b貼附於膠帶(即圖1E的固著物140)上,並且被膠帶固定住。Next, as shown in FIG. 1F , an
在本實施例中,電子元件160b的厚度大於承載線路板10的厚度。因此,將電子元件160b設置於固著物140上,會使得電子元件160b的頂部凸出於表面100f。然而,本發明不限於此,電子元件160b的厚度也可以小於或者等於承載線路板10的厚度。應特別注意,電子元件160a以及電子元件160b的數量不限於本實施例中(例如圖1F)所繪示的數量。In this embodiment, the thickness of the
在本發明部分實施例中,電子元件160a小於電子元件160b。舉例而言,主動元件的體積通常會小於被動元件的體積,電子元件160a可以是例如電晶體(transistor)等主動元件,而電子元件160b則可以是例如電感(inductor)或者電容(capacitor)等被動元件。然而,在本發明的其他實施例中,各個電子元件160a以及電子元件160b的種類並不受限於此。In some embodiments of the present invention, the
請繼續參考圖1F,與電子元件102連接線路基板100的方式相同,電子元件160a也是以多個焊點104,通過暴露於線路基板100上的多個接墊(未繪示),電性連接線路基板100,而這些接墊是位於線路基板100的表面100f上。在其他實施例中,還可以利用打線(wire-bonding)的方式將電子元件160a與線路基板100電性連接。Please continue to refer to FIG. 1F. Similar to the way in which the
另一方面,通過焊接將電子元件160b電性連接承載線路板10。具體而言,在本實施中,是通過噴錫(solder jetting)的方式,以焊接材料170連接電子元件160b以及承載線路板10上的接墊108,其中焊接材料170可以包含例如銅膏、銀膏等焊料。然而,本發明在承載線路板10上連接電子元件160b的方式不限於噴錫,也可以是其他焊接的方法。On the other hand, the
在電性連接電子元件160b以及承載線路板10之後,在承載線路板10的表面100f上形成密封層180。請參考圖1G,密封層180包覆電子元件160a以及電子元件160b。在本實施例中,除了電子元件160a與焊點104之間的連接處以外,密封層180完全包覆電子元件160a。然而,在本發明其他實施例中,電子元件160a的其他部分,例如圖1F中的電子元件160a的上表面,也可以暴露於密封層180外。After the
另一方面,由於電子元件160b的底部直接接觸固著物140,密封層180是包覆除了電子元件160b的底部以及與焊接材料170連接處以外的其他部分。在本發明其他實施例中,電子元件160b的其他部分也可以暴露於密封層180外。密封層180的材料可以包含有機樹脂(如環氧樹脂)等絕緣材料或其相似物,並且可以相同於密封層106的材料。On the other hand, since the bottom of the
請參考圖3A,在形成密封層180之後,移除固著物140(即本實施例的膠帶)。然而,本發明不限於此,也可以不移除固著物140,使固著物140保留在表面106s上。接著,可以通過例如機械切割、雷射切割或離子束切割等方式,切割線路基板100、密封層106、密封層180以及中介基板103,以形成如圖3A所示的電子封裝單體30’。Referring to FIG. 3A , after the
在完成切割步驟之後,如圖3B所示,在密封層180上沉積導電層190。為了達到電磁屏蔽的功效,導電層190必須覆蓋電子元件160a以及電子元件160b。具體而言,在本實施例中,導電層190是完全覆蓋密封層180,進而完全覆蓋電子元件160a以及電子元件160b。除此之外,導電層190也完全覆蓋於電子封裝單體30’的側壁30w,使電子元件160a以及電子元件160b的側面也能受到屏蔽。導電層190的材料可以包含金屬(例如銅、鎳或合金)、導電膠或其他材料,並且可以通過噴塗、濺鍍、化學鍍膜或類似的方式沉積而成。After the cutting step is completed, as shown in FIG3B , a
至此,本發明亦揭露一種電子封裝模組,其至少一實施例的結構請參考圖3B所示,此實施例的電子封裝模組30包含承載線路板10、電子元件160a、電子元件160b以及密封層180。承載線路板10包含了線路基板100、電子元件102、中介基板103以及密封層106,其中線路基板100具有表面100f以及相對於表面100f的表面100s,而電子元件102及中介基板103皆位於線路基板100的表面100s。密封層106也位於線路基板100的表面100s,並且包覆電子元件102。At this point, the present invention also discloses an electronic package module, and the structure of at least one embodiment thereof is shown in FIG. 3B . The
請繼續參考圖3B,承載線路板10還包含開口120、表面100f以及相對於表面100f的表面106s,而開口120連通承載線路板10的表面100f與表面106s。電子元件160a位於承載線路板10的表面100f上,其中電子元件160a、電子元件102以及中介基板103都是通過焊點104電性連接線路基板100。另一方面,電子元件160b位於承載線路板10的開口120內,並且通過焊接材料170連接線路基板100上的接墊108,以電性連接承載線路板10。Continuing to refer to FIG. 3B , the
雖然在如圖3B所示的實施例中,電子封裝模組30包含了密封層180以及密封層106,其中密封層180包覆電子元件160a以及電子元件160b,而密封層106則包覆電子元件102。但實質上,由於密封層180以及密封層106通常包含相同材料,故可以忽略兩者之間的分界,並將兩者視為一個密封結構320。Although in the embodiment shown in FIG. 3B , the
應特別注意,在本發明的各實施例中,電子元件160a的厚度T1小於電子元件160b的厚度T2。此外,當本發明的其他實施例包含電子元件102時,電子元件102的厚度T3亦小於電子元件160b的厚度T2。值得一提的是,本發明另一實施例的電子封裝模組30還包含固著物140,位於開口120的一端,並且重疊於開口120。固著物140連接電子元件160b,且固著物140可直接接觸於電子元件160b。It should be particularly noted that in each embodiment of the present invention, the thickness T1 of the
請回到圖3B,電子封裝模組30還包含導電層190,此導電層190位於密封層180上,並且完全覆蓋電子元件160a以及電子元件160b。然而,在本發明的其他實施例中,電子封裝模組也可以不包含導電層。所以,電子封裝模組30不限制要包括導電層190。Please return to FIG. 3B , the
請參考圖4,在本發明的另一實施例中,電子封裝模組40還包含了主板401,此主板401通過多個焊點404電性連接承載線路板10。這些焊點404相似於焊點104,可以是錫球、銅柱或適用於電性連接的各種連接結構。更詳細而言,焊點404連接於中介基板103的接面103i,並且通過暴露於主板401上的接墊(未繪示),將中介基板103電性連接至主板401,其中中介基板103的接面103i是面向於主板401。此外,在本實施例中的電子封裝模組40也可以包含固著物140。Please refer to FIG. 4 . In another embodiment of the present invention, the
雖然上述圖1A至圖1C的實施例中,形成承載線路板10的步驟包含了在線路基板100上設置電子元件102及中介基板103,也包含了在線路基板100上形成密封層106。但在本發明的另一實施例中,上述這些步驟皆可以省略。換言之,承載線路板10可以只包含線路基板100,並且直接對線路基板100執行後續圖1D至圖1G以及圖3A的步驟。在經過這些步驟之後,形成如圖5所示的電子封裝模組50。Although in the above-mentioned embodiment of FIG. 1A to FIG. 1C, the steps of forming the
電子封裝模組50與電子封裝模組30的主要差異在於,電子封裝模組30為雙面封裝(double side encapsulation)模組,而電子封裝模組50則是單面封裝(single side encapsulation)模組。亦即,在圖3B的電子封裝模組30中,線路基板100的兩側(表面100f及表面100s)皆設有電子元件(電子元件160a以及電子元件102),而圖5中的電子封裝模組50則只有在線路基板100的一側(表面100f)設置電子元件160a。此外,電子封裝模組50也可以包含如電子封裝模組30中的導電層190,以電磁屏蔽電子元件160a及電子元件160b。The main difference between the
電子封裝模組50還可以包含如圖4所示的主板401。應特別注意,由於此實施例的承載線路板10只包含線路基板100,故圖1C中的承載線路板10相對兩側的表面相當於圖5中的線路基板100相對兩側的表面100f以及表面100s。因此,承載線路板10是通過多個焊點404電性連接至主板401,且這些焊點404設置於線路基板100的表面100s上。此外,電子封裝模組50還可以包含固著物140,而固著物140必須設置於線路基板100的表面100s上。The
綜上所述,本發明中位於線路基板表面的電子元件厚度較小,而位於承載線路板的開口中的電子元件厚度較大。如此配置,使得厚度較大的電子元件的頂面不會凸出厚度較小的電子元件的頂面太多,甚至可以齊平或低於厚度較小的電子元件的頂面。當電子元件頂面之間的差距縮小,便不再需要為了覆蓋較凸出的電子元件而增加密封層的厚度。據此,得以減少電子封裝模組的厚度,進而達成電子裝置輕薄化的效果,且有助於節省密封層的材料成本。In summary, in the present invention, the electronic components located on the surface of the circuit substrate are thinner, while the electronic components located in the opening of the circuit board are thicker. With such a configuration, the top surface of the thicker electronic components will not protrude too much from the top surface of the thinner electronic components, and can even be flush with or lower than the top surface of the thinner electronic components. When the gap between the top surfaces of the electronic components is reduced, it is no longer necessary to increase the thickness of the sealing layer in order to cover the protruding electronic components. Accordingly, the thickness of the electronic packaging module can be reduced, thereby achieving the effect of making the electronic device lighter and thinner, and helping to save the material cost of the sealing layer.
雖然本發明已以實施例揭露如上,然其並非用以限定本發明,本發明所屬技術領域中具有通常知識者,在不脫離本發明精神和範圍內,當可作些許更動與潤飾,因此本發明保護範圍當視後附的申請專利範圍所界定者為準。Although the present invention has been disclosed as above by way of embodiments, they are not intended to limit the present invention. A person having ordinary knowledge in the technical field to which the present invention belongs may make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the attached patent application.
10: 承載線路板
100: 線路基板
100f、100s、106s: 表面
102、160a、160b: 電子元件
103: 中介基板
103i: 接面
103o、120: 開口
104、404: 焊點
106、180: 密封層
108: 接墊
120d: 界線
140: 固著物
170: 焊接材料
190: 導電層
30、40、50: 電子封裝模組
30w: 側壁
30’: 電子封裝單體
320: 密封結構
401: 主板
N1: 法線方向
T1、T2、T3: 厚度
10: Carrier circuit board
100:
圖1A至圖1G繪示本發明一實施例的電子封裝模組製造方法的剖視圖。 圖2繪示圖1D的上視圖。 圖3A至圖3B繪示本發明一實施例的電子封裝模組製造方法的剖視圖。 圖4繪示本發明另一實施例的電子封裝模組的剖視圖。 圖5繪示本發明另一實施例的電子封裝模組的剖視圖。 Figures 1A to 1G are cross-sectional views of a method for manufacturing an electronic package module according to an embodiment of the present invention. Figure 2 is a top view of Figure 1D. Figures 3A to 3B are cross-sectional views of a method for manufacturing an electronic package module according to an embodiment of the present invention. Figure 4 is a cross-sectional view of an electronic package module according to another embodiment of the present invention. Figure 5 is a cross-sectional view of an electronic package module according to another embodiment of the present invention.
國內寄存資訊(請依寄存機構、日期、號碼順序註記) 無 國外寄存資訊(請依寄存國家、機構、日期、號碼順序註記) 無 Domestic storage information (please note in the order of storage institution, date, and number) None Foreign storage information (please note in the order of storage country, institution, date, and number) None
10: 承載線路板
100: 線路基板
100f、100s、106s: 表面
102、160a、160b: 電子元件
103: 中介基板
104: 焊點
106、180: 密封層
108: 接墊
120: 開口
170: 焊接材料
190: 導電層
30: 電子封裝模組
30w: 側壁
320: 密封結構
T1、T2、T3: 厚度
10: Carrier circuit board
100:
Claims (11)
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310155449.4A CN116190325A (en) | 2023-02-13 | 2023-02-13 | Electronic packaging module and manufacturing method thereof |
| CN2023101554494 | 2023-02-13 |
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| CN119626993A (en) * | 2024-02-26 | 2025-03-14 | 芯爱科技(南京)有限公司 | Electronic packaging and method of manufacturing the same |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101246881A (en) * | 2007-02-16 | 2008-08-20 | 乾坤科技股份有限公司 | Electronic Package Structure |
| TW200933868A (en) * | 2008-01-28 | 2009-08-01 | Orient Semiconductor Elect Ltd | Stacked chip package structure |
| TW201701416A (en) * | 2012-12-20 | 2017-01-01 | 英帆薩斯公司 | Structure for a microelectronic package having a bonding element to an encapsulation surface |
| CN112185903A (en) * | 2019-07-03 | 2021-01-05 | 矽品精密工业股份有限公司 | Electronic package and manufacturing method thereof |
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| KR20000074351A (en) * | 1999-05-20 | 2000-12-15 | 마이클 디. 오브라이언 | semi-conductor package and manufacturing method thereof |
| KR100679834B1 (en) * | 2000-12-29 | 2007-02-07 | 앰코 테크놀로지 코리아 주식회사 | Manufacturing method of semiconductor package |
| US6399418B1 (en) * | 2001-07-26 | 2002-06-04 | Amkor Technology, Inc. | Method for forming a reduced thickness packaged electronic device |
| KR101548799B1 (en) * | 2013-06-24 | 2015-08-31 | 삼성전기주식회사 | Electric component module and manufacturing method threrof |
| KR20170124769A (en) * | 2016-05-03 | 2017-11-13 | 삼성전기주식회사 | Electric component module and manufacturing method threrof |
| US10535612B2 (en) * | 2017-12-15 | 2020-01-14 | Advanced Semiconductor Engineering, Inc. | Semiconductor device package and method of manufacturing the same |
| US10804254B2 (en) * | 2018-06-29 | 2020-10-13 | Taiwan Semiconductor Manufacturing Company, Ltd. | Fan-out package with cavity substrate |
-
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101246881A (en) * | 2007-02-16 | 2008-08-20 | 乾坤科技股份有限公司 | Electronic Package Structure |
| TW200933868A (en) * | 2008-01-28 | 2009-08-01 | Orient Semiconductor Elect Ltd | Stacked chip package structure |
| TW201701416A (en) * | 2012-12-20 | 2017-01-01 | 英帆薩斯公司 | Structure for a microelectronic package having a bonding element to an encapsulation surface |
| CN112185903A (en) * | 2019-07-03 | 2021-01-05 | 矽品精密工业股份有限公司 | Electronic package and manufacturing method thereof |
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