TWI852595B - Driving circuit and driving method thereof - Google Patents

Abstract

The application discloses a driving circuit and a driving method. The driving circuit includes: a shift register and a sweep signal generating circuit. The shift register is for controlling a signal output sequence from the driving circuit. The shift register generates a (n+1)-th start signal based on a n-th start signal, a plurality of clock signals, a first reference voltage and a second reference voltage, wherein n is an integer larger than or equal to 0. The sweep signal generating circuit is coupled to the shift register. The sweep signal generating circuit generates a (n+1) sweep signal based on a (n+m)-th start signal, a square pulse signal, a third reference voltage and the second reference voltage wherein m is a positive integer larger than or equal to 2.

Description

Driving circuit and driving method thereof

The present invention relates to a driving circuit and a driving method thereof.

Micro LED has smaller crystals, so it is better than large size in terms of bending and extension. In addition, Micro LED panels can accommodate more small crystals and have advantages such as high resolution and high transparency. In addition, a single Micro LED has high brightness and can also achieve power saving effects.

Mobile devices are becoming more and more popular with the rapid development of technology, and people's demand for mobile phones and tablets is also increasing. In recent years, the gate driver circuit has been highly integrated on the lower glass substrate, and the technology of using gate-driver on array (GOA) has also become the focus of the development of medium and large-sized displays.

With current technology, the integrated circuit in the display needs to output a sweep signal to the GOA driver circuit, which then outputs it to the active display area of the display. However, this approach will increase the number of IC output signals, thereby increasing the complexity of IC design and circuit layout. In addition, the currently used GOA driver circuit cannot adjust the output pulse width by itself.

Therefore, the industry is developing a new GOA driving circuit and its driving method in order to improve the above or other shortcomings of the existing technology.

According to an example of the present case, a driving circuit is proposed, including: a shift register for controlling an output signal sequence of the driving circuit, the shift register generates an n+1th starting signal according to an nth starting signal, a plurality of clock signals, a first reference voltage and a second reference voltage, wherein n is an integer greater than or equal to 0; and a sweep signal generating circuit coupled to the shift register, the sweep signal generating circuit generates an n+1th sweep signal according to an n+mth starting signal, a square wave signal, a third reference voltage and the second reference voltage, wherein m is a positive integer greater than or equal to 2.

According to another embodiment of the present invention, a driving method is provided for a driving circuit including a shift register and a frequency sweep signal generating circuit. The driving method includes: in a first stage, the shift register generates a logically high n+1th start signal according to an nth start signal, a plurality of clock signals, a first reference voltage and a second reference voltage. signal, and the sweep signal generating circuit generates a logically higher n+1th sweep signal according to an n+mth starting signal, a square wave signal, a third reference voltage and the second reference voltage, wherein the n+1th sweep signal is equal to the third reference voltage, n is an integer greater than or equal to 0, and m is a positive integer greater than or equal to 2; in a second In the first stage, the shift register generates the n+1th start signal of logically low logic, and the sweep signal generating circuit outputs the n+1th sweep signal of logically high logic, and the n+1th sweep signal is equal to the third reference voltage; in the third stage, the shift register generates the n+1th start signal of logically high logic, and the sweep signal generates The circuit generates the floating n+1th sweep signal, and through a capacitive coupling effect, the potential of the n+1th sweep signal gradually decreases; and in a fourth stage, the shift register generates the logically high n+1th start signal, and the sweep signal generating circuit pulls the n+1th sweep signal back from floating to the third reference voltage.

In order to better understand the above and other aspects of the present invention, the following is a specific example and a detailed description with the attached drawings as follows:

100:Drive circuit

110: Shift register

120: Sweep signal generating circuit

T1~T13: Transistor

C1~C2: Capacitor

P1~P4: Stage

300:Drive circuit

310: Shift register

320: Sweep signal generating circuit

322:Multiplexer

510~540: Steps

Figure 1 shows a circuit diagram of a driving circuit according to an embodiment of the present invention.

Figures 2A to 2D show the stage operation diagrams of the driving circuit according to an embodiment of the present invention.

Figure 3 shows a circuit diagram of a driving circuit according to another embodiment of the present invention.

Figures 4A to 4I show various simulation diagrams according to an embodiment of the present invention.

Figure 5 shows a flow chart of a driving method according to an embodiment of the present invention.

The technical terms in this manual refer to the customary terms in this technical field. If this manual explains or defines some terms, the interpretation of these terms shall be based on the explanation or definition in this manual. Each embodiment disclosed in this disclosure has one or more technical features. Under the premise of possible implementation, a person with ordinary knowledge in this technical field can selectively implement some or all of the technical features in any embodiment, or selectively combine some or all of the technical features in these embodiments.

FIG. 1 shows a circuit diagram of a driver circuit according to an embodiment of the present invention. The driver circuit 100 according to an embodiment of the present invention includes: a shift register 110 and a scanning signal generating circuit 120. In an embodiment of the present invention, the driver circuit 100 is, for example but not limited to, a GOA driver circuit applied to a micro LED panel. However, in other embodiments of the present invention, the driver circuit 100 can also be used as a driver circuit for other types of display panels, or a driver circuit in other types of electronic devices (not limited to display panels).

The shift register 110 is used to control the sequence of the GOA output signal of the driver circuit 100. The shift register 110 can generate the n+1th start signal STV[n+1] according to the nth start signal STV[n] (n is an integer greater than or equal to 0), a plurality of clock signals CK1/CK2/CK3, a high reference voltage VGH (also referred to as the first reference voltage) and a low reference voltage VGL (also referred to as the second reference voltage). The driver circuit 100 can also be referred to as an nth stage driver circuit.

The sweep signal generating circuit 120 is coupled to the shift register 110. The sweep signal generating circuit 120 is used to generate and output a sweep signal. The sweep signal generating circuit 120 can generate the n+1th sweep signal EMOUT[n+1] according to the n+mth start signal STV[n+m] (m is a positive integer greater than or equal to 2), the high-frequency square wave signal XCK, the reference voltage VrefP (also referred to as the third reference voltage) and the low reference voltage VGL. The reference voltage VrefP is, for example but not limited to, greater than 0V. The n+1th sweep signal EMOUT[n+1] is, for example but not limited to, a triangular wave signal. The high-frequency square wave signal XCK, for example but not limited to, has a frequency of MHz level, a period of 1~2μs, and a duty cycle of 50%.

The shift register 110 includes transistors T1 to T9.

The transistor T1 includes: a first end receiving the nth start signal STV[n], a second end, and a control end coupled to the first end.

The transistor T2 includes: a first end receiving a low reference voltage VGL, a second end, and a control end receiving one of the clock signals CK2/CK3/CK1. In an embodiment of the present case, when n=0, 3, 6, ..., the control end of the transistor T2 of the driving circuit 100 receives the clock signal CK2; when n=1, 4, 7, ..., the control end of the transistor T2 of the driving circuit 100 receives the clock signal CK3; and when n=2, 5, 8, ..., the control end of the transistor T2 of the driving circuit 100 receives the clock signal CK1.

Transistor T3 includes: a first end coupled to the second end of transistor T2, a second end, and a control end coupled to the second end of transistor T1.

Transistor T4 includes: a first end coupled to the second end of transistor T3, a second end receiving a high reference voltage VGH, and a control end coupled to the second end of transistor T1.

Transistor T5 includes: a first end coupled to the second end of transistor T1, a second end, and a control end coupled to the second end of transistor T2.

Transistor T6 includes: a first end coupled to the second end of transistor T5, a second end receiving a high reference voltage VGH, and a control end coupled to the second end of transistor T2.

The transistor T7 includes: a first end receiving one of the clock signals CK1/CK2/CK3, a second end outputting the n+1th start signal STV[n+1], and a control end coupled to the second end of the transistor T1. In an embodiment of the present case, when n=0, 3, 6, ..., the first end of the transistor T7 of the driving circuit 100 receives the clock signal CK1; when n=1, 4, 7, ..., the first end of the transistor T7 of the driving circuit 100 receives the clock signal CK2; and when n=2, 5, 8, ..., the first end of the transistor T7 of the driving circuit 100 receives the clock signal CK3.

Transistor T8 includes: a first end outputting the n+1th start signal STV[n+1], a second end receiving a high reference voltage VGH, and a control end coupled to the second end of transistor T2.

Transistor T9 includes: a first end coupled to the second end of transistor T2, a second end, and a control end coupled to the second end of transistor T9.

The sweep signal generating circuit 120 includes transistors T10~T13, a first capacitor C1 and a second capacitor C2.

Transistor T10 includes: a first end receiving a low reference voltage VGL, a second end coupled to the second end of transistor T9, and a control end receiving an n+mth start signal STV[n+m].

Transistor T11 includes: a first end receiving a reference voltage VrefP, a second end, and a control end coupled to the second end of transistor T1.

Transistor T12 includes: a first end receiving a reference voltage VrefP, a second end coupled to the second end of transistor T11, and a control end coupled to the second end of transistor T9.

Transistor T13 includes: a first end coupled to the second end of transistor T11, a second end outputting the n+1th frequency sweep signal EMOUT[n+1], and a control end receiving the high-frequency square wave signal XCK. In an embodiment of the present case, since the frequency of the high-frequency square wave signal XCK is relatively high, basically, transistor T13 can be regarded as substantially always turned on.

The first capacitor C1 is used for voltage stabilization. The first capacitor C1 is coupled between the second end of the transistor T9 and the high reference voltage VGH.

The second capacitor C2 is used to control the charging and discharging speed of the n+1th scanning signal EMOUT[n+1]. The second capacitor C2 is coupled between the reference voltage VrefP and the second end of the transistor T11.

Figures 2A to 2D show the stage operation diagrams of the driving circuit 100 according to an embodiment of the present invention. The driving circuit 100 of the embodiment of the present invention has 4 stage operations, which are marked as P1~P4 respectively.

In phase P1, the nth start signal STV[n] is logically low and turns on transistor T1. Therefore, the nth start signal STV[n] can pass through transistor T1 to turn on transistor T7 and transistor T11. At the same time, the nth start signal STV[n] can pass through transistor T1 to turn on transistor T3 and transistor T4. The high reference voltage VGH turns off transistors T5, T6, T8, and T12 through the turned-on transistors T3 and T4. Since transistor T7 is turned on, transistor T7 generates the logically high n+1th start signal STV[n+1] (CK1(H)=STV[n+1](H)). Since transistors T11 and T13 are turned on, transistor T13 outputs the n+1th sweep signal EMOUT[n+1] which is equal to the reference voltage VrefP (EMOUT[n+1]=VrefP), where VrefP>0V.

In phase P2, the nth start signal STV[n] turns to a logical high, so transistor T1 is turned off. However, the turning off of transistor T1 does not affect the gate voltage of transistors T7 and T11, so transistors T7 and T11 are still turned on. Since transistor T7 is turned on, transistor T7 generates a logically low n+1th start signal STV[n+1] (CK1(L)=STV[n+1](L)). Since transistors T11 and T13 are turned on, transistor T13 outputs the n+1th sweep signal EMOUT[n+1] equal to the reference voltage VrefP (EMOUT[n+1]=VrefP).

In phase P3, the clock signal CK2 is logically low while the clock signals CK1 and CK3 are logically high. The nth start signal STV[n] is still logically high, so the transistor T1 is off. Since the clock signal CK2 is logically low, the transistor T2 is on. Since the transistor T2 is on, the low reference voltage VGL passes through the transistor T2 to turn on the transistors T5, T6 and T8. Since the transistors T5 and T6 are on, the high reference voltage VGH passes through the transistors T5 and T6 to turn off the transistors T7 and T11. Since transistor T8 is turned on, the high reference voltage VGH is output as the logically high n+1th start signal STV[n+1] (VGH=STV[n+1](H)) through transistor T8. Since transistors T11 and T12 are turned off, the n+1th sweep signal EMOUT[n+1] is floating. Through the high-speed switching of transistor T13, the potential of the n+1th sweep signal EMOUT[n+1] gradually decreases due to the coupling effect of the second capacitor C2, becoming a signal with a slope.

In phase P4, the clock signal CK3 is switched to a logical low and the clock signals CK1 and CK2 are logical high, and the transistor T2 is turned off. Here, m=2 is used for illustration, but it should be noted that the present invention is not limited thereto. Other embodiments of the present invention can be applied to other m values, which are all within the spirit of the present invention. m=2, since the n+2 start signal STV[n+2] is a logical low, the transistor T10 is turned on, so that the low reference voltage VGL passes through the transistor T10 and turns on the transistors T12, T9, T8, T5 and T6. Since the transistors T5 and T6 are turned on, the high reference voltage VGH passes through the transistors T5 and T6, so that the transistors T7 and T11 are still turned off. Transistor T8 is turned on, so the high reference voltage VGH is output as the logically high n+1th start signal STV[n+1] (VGH=STV[n+1](H)) through transistor T8. Since transistor T12 is turned on, the reference voltage VrefP passes through transistors T12 and T13 to pull the n+1th sweep signal EMOUT[n+1] from the floating state back to the reference voltage VrefP (EMOUT[n+1]=VrefP).

In an embodiment of the present invention, the n+mth start signal STV[n+m] can determine when the transistor T10 is turned on, and when the transistor T10 is turned on, the sweep signal EMOUT will stop falling. That is, in an embodiment of the present invention, the timing of the sweep signal EMOUT stopping falling depends on the n+mth start signal STV[n+m]. Specifically, the timing of the sweep signal EMOUT stopping falling depends on the transition of the n+mth start signal STV[n+m] to a logical low. When the n+mth start signal STV[n+m] transitions to a logical low, the sweep signal EMOUT stops falling and rises to the reference voltage VrefP. Therefore, the timing at which the sweep signal EMOUT stops falling and rises to the reference voltage VrefP may not be within phase P4.

As for the drain voltage of transistor T10 (that is, the gate voltage of transistor T12), it can be protected by transistor T9, that is, when transistor T9 is turned off, the drain voltage of transistor T10 (the gate voltage of transistor T12) will not be affected by the gate voltage of transistor T8.

From the above, it can be seen that in an embodiment of the present case, the n+1th sweep signal EMOUT[n+1] of a triangular wave can be generated through the 4-stage operation of the driving circuit 100.

FIG. 3 shows a circuit diagram of a driver circuit according to another embodiment of the present invention. The driver circuit 300 according to an embodiment of the present invention includes: a shift register 310 and a scanning signal generating circuit 320. In an embodiment of the present invention, the driver circuit 300 is, for example but not limited to, a GOA driver circuit applied to a micro LED panel. However, in other embodiments of the present invention, the driver circuit 300 can also be used as a driver circuit for other types of display panels, or a driver circuit in other types of electronic devices (not limited to display panels).

The shift register 310 of FIG. 3 is substantially the same as or similar to the shift register 110 of FIG. 1 , and thus its details are omitted here.

The difference between the sweep signal generating circuit 320 and the sweep signal generating circuit 120 is that the multiplexer 322 of the sweep signal generating circuit 320 is used to replace the transistor T10 of the sweep signal generating circuit 120.

The multiplexer 322 is controlled by the multiplexer switching signal MUX_SW to select one from a plurality of start signals MULTI_STV, wherein the plurality of start signals MULTI_STV include, for example: the n+2th start signal STV[n+2] to the n+mth start signal STV[n+m]. Alternatively, the plurality of start signals MULTI_STV can also be referred to as a plurality of different start signals.

The operation principle of the driving circuit 300 is the same or similar to that of the driving circuit 100 in FIG. 1, so the details are omitted here. However, at the stage P4 of the driving circuit 300, the clock signal CK3 is switched to a logical low and the clock signals CK1 and CK2 are logically high, and the transistor T2 is turned off. When one of the n+2 start signals STV[n+2] to the n+m start signals STV[n+m] is selected by the multiplexer switching signal MUX_SW, the multiplexer 322 allows the low reference voltage VGL to pass through the multiplexer 322 to turn on the transistors T12, T9, T8, T5 and T6. Since transistors T5 and T6 are turned on, the high reference voltage VGH passes through transistors T5 and T6, making transistors T7 and T11 still turned off. Transistor T8 is turned on, so the high reference voltage VGH passes through transistor T8 and outputs the logically high n+1th start signal STV[n+1] (VGH=STV[n+1](H)). Since transistor T12 is turned on, the reference voltage VrefP passes through transistors T12 and T13 and pulls the n+1th sweep signal EMOUT[n+1] from the floating state back to the reference voltage VrefP (EMOUT[n+1]=VrefP). In Figure 3, the ending falling timing of the n+1th sweep signal depends on one of the different starting signals selected by the multiplexer switching signal.

In the embodiment of FIG. 3, a multiplexer 322 is used to replace transistor T10, and the m value is selected from multiple candidate values as needed (e.g., by programming), thereby improving adjustability.

Figures 4A to 4I show various simulation diagrams according to an embodiment of the present invention. In Figures 4A to 4I, there are 2 different variables (m value and high-frequency square wave signal XCK), and each variable has 3 different changes.

In Figures 4A to 4C, there are 3 different m values but the high-frequency square wave signal XCK is the same. In Figures 4A to 4C, the m values are m=2, m=3 and m=4 respectively. In Figures 4A to 4C, the high-frequency square wave signal XCK can make the n+1th sweep signal EMOUT[n+1] have a high falling slope.

In Figures 4D to 4F, there are 3 different m values but the high-frequency square wave signal XCK is the same. In Figures 4D to 4F, the m values are m=2, m=3 and m=4 respectively. In Figures 4D to 4F, the high-frequency square wave signal XCK can make the n+1th sweep signal EMOUT[n+1] have a medium downward slope.

In Figures 4G to 4I, there are 3 different m values but the high-frequency square wave signal XCK is the same. In Figures 4G to 4I, the m values are m=2, m=3 and m=4 respectively. In Figures 4G to 4I, the high-frequency square wave signal XCK can make the n+1th sweep signal EMOUT[n+1] have a low falling slope.

As can be seen from Figures 4A to 4I, in an embodiment of the present invention, the larger the m value, the wider the width of the sweep signal EMOUT.

FIG. 5 is a flow chart of a driving method according to an embodiment of the present invention. The driving method is applied to a driving circuit including a shift register and a sweep signal generating circuit. The driving method includes: (510) in a first stage, the shift register generates a logically high n+1th start signal according to an nth start signal, a plurality of clock signals, a first reference voltage and a second reference voltage, and the sweep signal generating circuit generates a logically high n+1th start signal according to an n+mth start signal, a square wave signal, A third reference voltage and the second reference voltage are used to generate a logically high n+1th sweep signal, wherein the n+1th sweep signal is equal to the third reference voltage, n is an integer greater than or equal to 0, and m is a positive integer greater than or equal to 2; (520) in a second stage, the shift register generates a logically low n+1th sweep signal The n+1th start signal is generated by the shift register, and the n+1th start signal is generated by the sweep signal generating circuit, and the n+1th sweep signal is equal to the third reference voltage; (530) in a third stage, the n+1th start signal is generated by the shift register, and the n+1th start signal is generated by the sweep signal generating circuit. 1 sweep signal, through a capacitive coupling effect, the potential of the n+1 sweep signal gradually decreases; and, (540) in a fourth stage, the shift register generates the n+1 start signal of logical high, and the sweep signal generating circuit pulls the n+1 sweep signal back from floating to the third reference voltage.

In addition, in an embodiment of the present case, the factors that change the falling slope of the sweep signal EMOUT include, for example but not limited to, the frequency and/or voltage and/or duty cycle of the high-frequency square wave signal XCK, the number of transistors T13, the aspect ratio (W/L) of the transistor T13, and the capacitance value of the second capacitor C2. In addition, in an embodiment of the present case, a plurality of transistors T13 can be connected in parallel.

As mentioned above, in one embodiment of the present invention, the sweep signal generating circuit of the driving circuit can generate and output the sweep signal by itself, thereby reducing the complexity of the integrated circuit design in the electronic device (such as a micro LED display panel).

In addition, in an embodiment of the present case, the pulse width of the sweep signal EMOUT can be adjusted through different m values, so that the driving circuit of the embodiment of the present case can have greater application possibilities.

In addition, in an embodiment of the present case, the falling slope of the frequency sweep signal EMOUT can be adjusted in a variety of ways, so that the driving circuit of the embodiment of the present case can have greater application possibilities.

In one embodiment of the present invention, the driving circuits can all use the same type of MOS transistors, thereby saving the number of process steps. PMOS transistors are used in Figures 1 and 3, but the present invention is not limited to this.

In summary, although the present invention has been disclosed as above by the embodiments, it is not intended to limit the present invention. Those with common knowledge in the technical field to which the present invention belongs can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be subject to the scope defined in the attached patent application.

510-540: Steps

Claims (12)

A driving circuit includes: a shift register for controlling an output signal sequence of the driving circuit, the shift register generates an n+1th starting signal according to an nth starting signal, a plurality of clock signals, a first reference voltage and a second reference voltage, wherein n is an integer greater than or equal to 0; and a sweep signal generating circuit coupled to the shift register, the sweep signal generating circuit generates an n+1th sweep signal according to an n+mth starting signal, a square wave signal, a third reference voltage and the second reference voltage, wherein m is a positive integer greater than or equal to 2. A driving circuit as described in claim 1, wherein the third reference voltage is greater than 0V, and the n+1th frequency sweep signal is a triangle wave signal. The driving circuit as described in claim 1, wherein the shift register includes: a first to a ninth transistor, the first transistor includes: a first end receiving the nth start signal, a second end, and a control end coupled to the first end of the first transistor; the second transistor includes: a first end receiving the third reference voltage, a second end, and a control end receiving a first clock signal of the clock signals; the third transistor includes: a first end coupled to the second end of the second transistor, a second end, and a control end coupled to the second end of the first transistor; the fourth transistor includes: a first end coupled to the second end of the third transistor, a second end receiving the first reference voltage, a second end, and a control end coupled to the second end of the first transistor. voltage, and a control terminal coupled to the second terminal of the first transistor; the fifth transistor includes: a first terminal coupled to the second terminal of the first transistor, a second terminal, and a control terminal coupled to the second terminal of the second transistor; the sixth transistor includes: a first terminal coupled to the second terminal of the fifth transistor, a second terminal receiving the first reference voltage, and a control terminal coupled to the second terminal of the second transistor; the seventh transistor includes: a first terminal receiving a second clock signal of the clock signals, a second terminal outputting the n+1th start signal, and a control terminal coupled to the second terminal of the first transistor; the eighth transistor includes: a first terminal outputting the n+1th start signal signal, a second end receiving the first reference voltage, and a control end coupled to the second end of the second transistor; the ninth transistor includes: a first end coupled to the second end of the second transistor, a second end, and a control end coupled to the second end of the ninth transistor; the sweep signal generating circuit includes a tenth to a thirteenth transistor, a first capacitor and a second capacitor; the tenth transistor includes: a first end receiving the second reference voltage, a second end coupled to the second end of the ninth transistor, and a control end receiving the n+mth start signal; the eleventh transistor includes: a first end receiving the third reference voltage, a second end, and a control end coupled to the first transistor The second end of the twelfth transistor includes: a first end receiving the third reference voltage, a second end coupled to the second end of the eleventh transistor, and a control end coupled to the second end of the ninth transistor; the thirteenth transistor includes: a first end coupled to the second end of the eleventh transistor, a second end outputting the n+1th scanning signal, and a control end receiving the square wave signal; the first capacitor is used for voltage regulation, the first capacitor is coupled between the second end of the ninth transistor and the first reference voltage; and the second capacitor is used to control a charge and discharge speed of the n+1th scanning signal, the second capacitor is coupled between the third reference voltage and the second end of the eleventh transistor. A driving circuit as described in claim 3, wherein, in a first stage, the nth start signal turns on the first transistor, the nth start signal turns on the seventh and eleventh transistors through the first transistor, the nth start signal turns on the third transistor and the fourth transistor through the transistor, the first reference voltage turns off the fifth, the sixth, the eighth and the twelfth transistors through the turned-on third transistor and the fourth transistor, the turned-on seventh transistor generates the n+1th start signal, the thirteenth transistor outputs the n+1th sweep signal, The n+1th scanning signal is equal to the third reference voltage; in a second stage, the nth start signal turns off the first transistor, the seventh and the eleventh transistors are still turned on, and the seventh transistor generates the n+1th start signal, the thirteenth transistor outputs the n+1th scanning signal, and the n+1th scanning signal is equal to the third reference voltage; in a third stage, the nth start signal turns off the first transistor, the first clock signal turns on the second transistor, and the second reference voltage passes through the second transistor to turn on the fifth, the sixth and the eighth transistors, The first reference voltage turns off the seventh and eleventh transistors through the fifth and sixth transistors, and the first reference voltage is output as the n+1th start signal through the turned-on eighth transistor. The eleventh and twelfth transistors are turned off, and the n+1th sweep signal is floating. The thirteenth transistor is switched on, and the potential of the n+1th sweep signal gradually decreases due to the coupling effect of the second capacitor; and in a fourth stage, the first clock signal turns off the second transistor, and the n+mth start signal turns on the tenth transistor, so that the The second reference voltage passes through the tenth transistor to turn on the twelfth, ninth, eighth, fifth and sixth transistors, the first reference voltage passes through the fifth and sixth transistors to turn off the seventh and eleventh transistors, the first reference voltage passes through the eighth transistor to output as the n+1th start signal, the third reference voltage passes through the twelfth and thirteenth transistors to pull the n+1th sweep signal back from floating to the third reference voltage, wherein the end falling timing of the n+1th sweep signal depends on the n+mth start signal. A driving circuit as described in claim 1, wherein the shift register includes: a first to a ninth transistor, the first transistor includes: a first end receiving the nth start signal, a second end, and a control end coupled to the first end of the first transistor; the second transistor includes: a first end receiving the third reference voltage, a second end, and a control end receiving a first clock signal of the clock signals; the third transistor includes: a first end coupled to the second end of the second transistor, a second end, and a control end coupled to the second end of the first transistor; the fourth transistor includes: a first end coupled to the second end of the third transistor, a second end receiving The first reference voltage, and a control terminal coupled to the second terminal of the first transistor; the fifth transistor includes: a first terminal coupled to the second terminal of the first transistor, a second terminal, and a control terminal coupled to the second terminal of the second transistor; the sixth transistor includes: a first terminal coupled to the second terminal of the fifth transistor, a second terminal receiving the first reference voltage, and a control terminal coupled to the second terminal of the second transistor; the seventh transistor includes: a first terminal receiving a second clock signal of the clock signals, a second terminal outputting the n+1th start signal, and a control terminal coupled to the second terminal of the first transistor; the eighth transistor includes: a first terminal receiving a second clock signal of the clock signals, a second terminal outputting the n+1th start signal, and a control terminal coupled to the second terminal of the first transistor The first transistor of the present invention comprises a first terminal for outputting the n+1th start signal, a second terminal for receiving the first reference voltage, and a control terminal coupled to the second terminal of the second transistor; the ninth transistor comprises: a first terminal coupled to the second terminal of the second transistor, a second terminal, and a control terminal coupled to the second terminal of the ninth transistor; the sweep signal generating circuit comprises a multiplexer, an eleventh to a thirteenth transistor, a first capacitor and a second capacitor; the multiplexer is controlled by a multiplexer switching signal to select one from a plurality of different start signals; the eleventh transistor comprises: a first terminal for receiving the third reference voltage, a second terminal, and a control terminal coupled to the second terminal of the first transistor; the The twelfth transistor includes: a first end receiving the third reference voltage, a second end coupled to the second end of the eleventh transistor, and a control end coupled to the second end of the ninth transistor; the thirteenth transistor includes: a first end coupled to the second end of the eleventh transistor, a second end outputting the n+1th scanning signal, and a control end receiving the square wave signal; the first capacitor is used for voltage stabilization, the first capacitor is coupled between the second end of the ninth transistor and the first reference voltage; and the second capacitor is used to control a charge and discharge speed of the n+1th scanning signal, the second capacitor is coupled between the third reference voltage and the second end of the eleventh transistor. The driving circuit as described in claim 5, wherein, in a first stage, the nth start signal turns on the first transistor, the nth start signal turns on the seventh and eleventh transistors through the first transistor, the nth start signal turns on the third transistor and the fourth transistor through the transistor, the first reference voltage turns off the fifth, sixth, eighth and twelfth transistors through the turned-on third transistor and the fourth transistor, the turned-on seventh transistor generates the n+1th start signal, the thirteenth transistor outputs the n+1th sweep signal, the n+1th The scanning signal is equal to the third reference voltage; in a second stage, the nth start signal turns off the first transistor, the seventh and the eleventh transistors are still turned on, and the seventh transistor generates the n+1th start signal, the thirteenth transistor outputs the n+1th scanning signal, and the n+1th scanning signal is equal to the third reference voltage; in a third stage, the nth start signal turns off the first transistor, the first clock signal turns on the second transistor, the second reference voltage passes through the second transistor to turn on the fifth, the sixth and the eighth transistors, and the first reference voltage passes through The fifth and sixth transistors are turned off to turn off the seventh and eleventh transistors, the first reference voltage is output as the n+1th start signal through the turned-on eighth transistor, the eleventh and twelfth transistors are turned off, the n+1th sweep signal is floating, and the potential of the n+1th sweep signal is gradually reduced by the coupling effect of the second capacitor through the switching of the thirteenth transistor; and in a fourth stage, the first clock signal turns off the second transistor, and when one of the different start signals is selected by the multiplexer switching signal, the second reference voltage is output as the n+1th start signal. The twelfth, ninth, eighth, fifth and sixth transistors are turned on through the multiplexer, the first reference voltage passes through the fifth and sixth transistors to turn off the seventh and eleventh transistors, the first reference voltage passes through the eighth transistor to output as the n+1th start signal, the third reference voltage passes through the twelfth and thirteenth transistors to pull the n+1th sweep signal from floating to the third reference voltage, wherein an end falling timing of the n+1th sweep signal depends on one of the different start signals selected by the multiplexer switching signal. A driving method is applied to a driving circuit including a shift register and a frequency sweep signal generating circuit. The driving method includes: in a first stage, the shift register generates a logically high n+1th start signal according to an nth start signal, a plurality of clock signals, a first reference voltage and a second reference voltage, and The sweep signal generating circuit generates a logically high n+1th sweep signal according to an n+mth starting signal, a square wave signal, a third reference voltage and the second reference voltage, wherein the n+1th sweep signal is equal to the third reference voltage, n is an integer greater than or equal to 0, and m is a positive integer greater than or equal to 2; in a second stage, The shift register generates the n+1th start signal of logically low logic, and the sweep signal generating circuit outputs the n+1th sweep signal of logically high logic, and the n+1th sweep signal is equal to the third reference voltage; in a third stage, the shift register generates the n+1th start signal of logically high logic, and the sweep signal generating circuit outputs the n+1th sweep signal of logically high logic. The n+1th scanning signal is generated as floating, and the potential of the n+1th scanning signal gradually decreases through a capacitive coupling effect; and in a fourth stage, the shift register generates a logically high n+1th start signal, and the scanning signal generating circuit pulls the n+1th scanning signal back from floating to the third reference voltage. The driving method as described in claim 7, wherein the third reference voltage is greater than 0V, and the n+1th scanning signal is a triangular wave signal. The driving method as described in claim 7, wherein the shift register includes: a first to a ninth transistor, the first transistor includes: a first end receiving the nth start signal, a second end, and a control end coupled to the first end of the first transistor; the second transistor includes: a first end receiving the third reference voltage, a second end, and a control end receiving a first clock signal of the clock signals; the third transistor includes: a first end coupled to the second end of the second transistor, a second end, and a control end coupled to the second end of the first transistor; the fourth transistor includes: a first end coupled to the second end of the third transistor, a second end receiving the first reference voltage, a second end, and a control end receiving the first clock signal of the clock signals. voltage, and a control terminal coupled to the second terminal of the first transistor; the fifth transistor includes: a first terminal coupled to the second terminal of the first transistor, a second terminal, and a control terminal coupled to the second terminal of the second transistor; the sixth transistor includes: a first terminal coupled to the second terminal of the fifth transistor, a second terminal receiving the first reference voltage, and a control terminal coupled to the second terminal of the second transistor; the seventh transistor includes: a first terminal receiving a second clock signal of the clock signals, a second terminal outputting the n+1th start signal, and a control terminal coupled to the second terminal of the first transistor; the eighth transistor includes: a first terminal outputting the n+1th start signal signal, a second end receiving the first reference voltage, and a control end coupled to the second end of the second transistor; the ninth transistor includes: a first end coupled to the second end of the second transistor, a second end, and a control end coupled to the second end of the ninth transistor; the sweep signal generating circuit includes a tenth to a thirteenth transistor, a first capacitor and a second capacitor; the tenth transistor includes: a first end receiving the second reference voltage, a second end coupled to the second end of the ninth transistor, and a control end receiving the n+mth start signal; the eleventh transistor includes: a first end receiving the third reference voltage, a second end, and a control end coupled to the first transistor The second end of the twelfth transistor includes: a first end receiving the third reference voltage, a second end coupled to the second end of the eleventh transistor, and a control end coupled to the second end of the ninth transistor; the thirteenth transistor includes: a first end coupled to the second end of the eleventh transistor, a second end outputting the n+1th scanning signal, and a control end receiving the square wave signal; the first capacitor is used for voltage regulation, the first capacitor is coupled between the second end of the ninth transistor and the first reference voltage; and the second capacitor is used to control a charge and discharge speed of the n+1th scanning signal, the second capacitor is coupled between the third reference voltage and the second end of the eleventh transistor. The driving method as described in claim 9, wherein, in the first stage, the nth start signal turns on the first transistor, the nth start signal turns on the seventh and eleventh transistors through the first transistor, the nth start signal turns on the third transistor and the fourth transistor through the transistor, the first reference voltage turns off the fifth, the sixth, the eighth and the twelfth transistors through the turned-on third transistor and the fourth transistor, the turned-on seventh transistor generates the n+1th start signal, the thirteenth transistor outputs the n+1th sweep signal, The n+1th scanning signal is equal to the third reference voltage; in the second stage, the nth start signal turns off the first transistor, the seventh and the eleventh transistors are still turned on, and the seventh transistor generates the n+1th start signal, the thirteenth transistor outputs the n+1th scanning signal, and the n+1th scanning signal is equal to the third reference voltage; in the third stage, the nth start signal turns off the first transistor, the first clock signal turns on the second transistor, and the second reference voltage passes through the second transistor to turn on the fifth, the sixth and the eighth transistors, The first reference voltage turns off the seventh and eleventh transistors through the fifth and sixth transistors, and the first reference voltage is output as the n+1th start signal through the turned-on eighth transistor. The eleventh and twelfth transistors are turned off, and the n+1th sweep signal is floating. The thirteenth transistor is switched on, and the potential of the n+1th sweep signal gradually decreases due to the coupling effect of the second capacitor; and in the fourth stage, the first clock signal turns off the second transistor, and the n+mth start signal turns on the tenth transistor, so that the The second reference voltage passes through the tenth transistor to turn on the twelfth, ninth, eighth, fifth and sixth transistors, the first reference voltage passes through the fifth and sixth transistors to turn off the seventh and eleventh transistors, the first reference voltage passes through the eighth transistor to output as the n+1th start signal, the third reference voltage passes through the twelfth and thirteenth transistors to pull the n+1th sweep signal back from floating to the third reference voltage, wherein the end falling timing of the n+1th sweep signal depends on the n+mth start signal. The driving method as described in claim 7, wherein the shift register includes: a first to a ninth transistor, the first transistor includes: a first end receiving the nth start signal, a second end, and a control end coupled to the first end of the first transistor; the second transistor includes: a first end receiving the third reference voltage, a second end, and a control end receiving a first clock signal of the clock signals; the third transistor includes: a first end coupled to the second end of the second transistor, a second end, and a control end coupled to the second end of the first transistor; the fourth transistor includes: a first end coupled to the second end of the third transistor, a second end receiving The first reference voltage, and a control terminal coupled to the second terminal of the first transistor; the fifth transistor includes: a first terminal coupled to the second terminal of the first transistor, a second terminal, and a control terminal coupled to the second terminal of the second transistor; the sixth transistor includes: a first terminal coupled to the second terminal of the fifth transistor, a second terminal receiving the first reference voltage, and a control terminal coupled to the second terminal of the second transistor; the seventh transistor includes: a first terminal receiving a second clock signal of the clock signals, a second terminal outputting the n+1th start signal, and a control terminal coupled to the second terminal of the first transistor; the eighth transistor includes: a first terminal receiving a second clock signal of the clock signals, a second terminal outputting the n+1th start signal, and a control terminal coupled to the second terminal of the first transistor The first transistor of the present invention comprises a first terminal for outputting the n+1th start signal, a second terminal for receiving the first reference voltage, and a control terminal coupled to the second terminal of the second transistor; the ninth transistor comprises: a first terminal coupled to the second terminal of the second transistor, a second terminal, and a control terminal coupled to the second terminal of the ninth transistor; the sweep signal generating circuit comprises a multiplexer, an eleventh to a thirteenth transistor, a first capacitor and a second capacitor; the multiplexer is controlled by a multiplexer switching signal to select one from a plurality of different start signals; the eleventh transistor comprises: a first terminal for receiving the third reference voltage, a second terminal, and a control terminal coupled to the second terminal of the first transistor; the The twelfth transistor includes: a first end receiving the third reference voltage, a second end coupled to the second end of the eleventh transistor, and a control end coupled to the second end of the ninth transistor; The thirteenth transistor includes: a first end coupled to the second end of the eleventh transistor, a second end outputting the n+1th scanning signal, and a control end receiving the square wave signal; the first capacitor is used for voltage stabilization, the first capacitor is coupled between the second end of the ninth transistor and the first reference voltage; and the second capacitor is used to control a charge and discharge speed of the n+1th scanning signal, the second capacitor is coupled between the third reference voltage and the second end of the eleventh transistor. The driving method as described in claim 11, wherein, in the first stage, the nth start signal turns on the first transistor, the nth start signal passes through the first transistor to turn on the seventh and eleventh transistors, the nth start signal passes through the transistor to turn on the third transistor and the fourth transistor, the first reference voltage passes through the turned-on third transistor and the fourth transistor to turn off the fifth, sixth, eighth and twelfth transistors, the turned-on seventh transistor generates the n+1th start signal, the thirteenth transistor outputs the n+1th sweep signal, the n+ 1 sweep signal is equal to the third reference voltage; in the second stage, the nth start signal turns off the first transistor, the seventh and the eleventh transistors are still turned on, and the seventh transistor generates the n+1th start signal, the thirteenth transistor outputs the n+1th sweep signal, and the n+1th sweep signal is equal to the third reference voltage; In the third stage, the nth start signal turns off the first transistor, the first clock signal turns on the second transistor, the second reference voltage passes through the second transistor to turn on the fifth, the sixth and the eighth transistors, and the first reference voltage The seventh and eleventh transistors are turned off through the fifth and sixth transistors, the first reference voltage is output as the n+1th start signal through the turned-on eighth transistor, the eleventh and twelfth transistors are turned off, the n+1th sweep signal is floating, and the potential of the n+1th sweep signal is gradually reduced by the coupling effect of the second capacitor through the switching of the thirteenth transistor; and in the fourth stage, the first clock signal turns off the second transistor, and when one of the different start signals is selected by the multiplexer switching signal, the second reference voltage The twelfth, ninth, eighth, fifth and sixth transistors are turned on through the multiplexer, the first reference voltage turns off the seventh and eleventh transistors through the fifth and sixth transistors, the first reference voltage is output as the n+1th start signal through the eighth transistor, the third reference voltage pulls the n+1th sweep signal from floating to the third reference voltage through the twelfth and thirteenth transistors, wherein the end falling timing of the n+1th sweep signal depends on one of the different start signals selected by the multiplexer switching signal.

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