TWI852481B - Memory device and method of forming the same - Google Patents

Abstract

A memory device can be applied to a 3D AND flash memory. The memory device includes a substrate, a first stacked structure, a second stacked structure, a channel structure, an insulating pillar, a through via and a conductive layer. The substrate has a memory array region and a staircase region. The first stacked structure is disposed on the substrate in the memory array region and includes first dielectric layers and gates alternately stacked. The second stacked structure is disposed on the substrate in the staircase region and includes second dielectric layers and stairs alternately stacked. The channel structure penetrates through the first stacked structure in the memory array region. The insulating pillar penetrates through the second stacked structure in the staircase region. The through via penetrates through the insulating pillar in the staircase region. The conductive layer surrounds the sidewall of the insulating pillar.

Description

Memory element and method of forming the same

The present invention relates to a semiconductor device and a method for forming the same, and in particular to a memory device and a method for forming the same.

Non-volatile memory devices (such as flash memory) have the advantage that the stored data will not disappear even after power failure, so they have become a type of memory device widely used in personal computers and other electronic devices.

The flash memory arrays commonly used in the industry include NOR flash memory and NAND flash memory. Since the structure of NAND flash memory is to connect each memory cell in series, its integration and area utilization are better than NOR flash memory, and it has been widely used in many electronic products. In addition, in order to further improve the integration of memory components, a three-dimensional NAND flash memory has been developed. However, there are still many challenges related to three-dimensional NAND flash memory.

The present invention provides a memory element and a method for forming the same, which can simplify the manufacturing process and improve the reliability of the manufactured memory element.

The present invention provides a memory element, which includes a substrate, a first stacking structure, a second stacking structure, a channel structure, an insulating column, a through hole and a conductive layer. The substrate has a memory array region and a step region. The first stacking structure is configured on the substrate in the memory array region, wherein the first stacking structure includes a plurality of alternately stacked first dielectric layers and a plurality of gates. The second stacking structure is configured on the substrate in the step region, wherein the second stacking structure includes a plurality of alternately stacked second dielectric layers and a plurality of steps. The channel structure penetrates the first stacking structure in the memory array region. The insulating column penetrates the second stacking structure in the step region. The via penetrates the insulating pillar in the step region. The conductive layer surrounds the side walls of the insulating pillar.

The present invention further provides a method for forming a memory element, comprising the following steps. A substrate is provided, wherein the substrate has a memory array region and a step region. A stacking structure is formed on the substrate, wherein the stacking structure includes a plurality of dielectric layers and a plurality of intermediate layers stacked alternately, and the stacking structure in the step region has a step profile. A channel structure penetrating the stacking structure is formed in the memory array region, and a dummy structure penetrating the stacking structure is formed in the step region. A trench penetrating the stacking structure is formed in the memory array region, and a hole penetrating the stacking structure is formed in the step region. Multiple intermediate layers in the memory array region are replaced with multiple gates, and multiple intermediate layers in the step region are replaced with multiple steps. Insulation walls are formed in the trenches, and insulation pillars are formed in the holes. Through holes are formed in the step region, and the through holes penetrate the insulation pillars in the holes.

Based on the above, the present invention provides a memory element and a method for forming the same, which can simultaneously define trenches for the replacement process and holes for through-holes, and then fill the trenches and holes with a single oxide layer to form insulating walls and insulating pillars respectively, and then form through-holes that penetrate the insulating pillars. The above-mentioned simultaneous definition of trenches/openings can simplify the process. In addition, the above-mentioned single oxide layer can avoid the known short circuit problem between the through-hole and the underlying internal connection structure caused by incomplete etching during the etching of the through-hole opening, thereby improving the reliability of the manufactured memory element.

10: Memory components

100: Base

100a: memory array area

100b: Stairway area

102: Component layer

103a, 103b: Stop pattern

104: Insulation layer

105: Isolation layer

107, 107a, 107b: dielectric layer

108, 204a, 204b: stacking structure

109: Middle layer

110: Top cover

122a, 122b: semiconductor layer

124a, 124b: Isolation columns

126: Dielectric pillar

130a: Insulation wall

130b: Insulation Pillar

200S: Source column

200D: Drain column

201: Composite dielectric layer

201a: Charge storage structure

201b: Staircase protection layer

202: Conductor layer

202G: Gate

202ST: Stairs

DV: Virtual structure

DVH: Virtual structural hole

MC: Memory Cell

SLT: Channels

VC: Channel structure

VCH: channel structure holes

TVH: Hole

TV:Through hole

W1, W2: size

Figures 1 to 9 are cross-sectional schematic diagrams of a method for forming a memory element according to an embodiment of the present invention.

Figure 10 is a simplified top view schematic diagram of some formation stages of various memory elements according to some embodiments of the present invention.

The following examples are listed and illustrated in detail, but the examples provided are not intended to limit the scope of the present invention. In addition, the drawings are for illustration purposes only and are not drawn in original size. For ease of understanding, the same components will be indicated by the same symbols in the following description.

The terms "include", "including", "have" and so on used in this article are all open terms, which means "including but not limited to".

Directional terms used herein, such as "upper", "lower", etc., are only used to refer to the directions of the drawings and are not used to limit the present invention. Therefore, it should be understood that "upper" can be used interchangeably with "lower", and when an element such as a layer or a film is placed "on" another element, the element can be placed directly on the other element, or there can be an intermediate element. On the other hand, when an element is said to be placed "directly" on another element, there is no intermediate element between the two.

Figures 1 to 9 are cross-sectional schematic diagrams of a manufacturing process of a memory element according to an embodiment of the present invention.

Referring to FIG. 1 , a substrate 100 is provided. In one embodiment, the substrate 100 includes a semiconductor substrate, such as a silicon-containing substrate. The substrate 100 has a memory array region 100a and a step region 100b. Then, a device layer 102 is formed on the substrate 100. In one embodiment, the device layer 102 may include various semiconductor devices that are generally known. In one embodiment, the device layer 102 may include a metal oxide semiconductor (MOS) transistor formed at the surface of the substrate 100 and an internal connection structure electrically connected to the metal oxide semiconductor transistor, but the present invention is not limited thereto. The internal connection structure includes a plurality of dielectric layers and a plurality of internal connections in the plurality of dielectric layers. In other embodiments, the device layer 102 may further include other semiconductor devices that are well known to those skilled in the art. In addition, the method for forming the device layer 102 is well known to those skilled in the art and will not be further described here.

Then, an insulating layer 104 is formed on the device layer 102. In one embodiment, the insulating layer 104 has a plurality of separate stop patterns 103a and 103b. More specifically, the stop pattern 103a is formed in the insulating layer 104 of the memory array region 100a, and the stop pattern 103b is formed in the insulating layer 104 of the step region 100b. In one embodiment, the stop patterns 103a and 103b are embedded in the insulating layer 104 and are covered by the insulating layer 104. In one embodiment, the insulating layer 104 includes silicon oxide, and the stop patterns 103a and 103b include polysilicon. However, the present invention is not limited thereto. Depending on the actual situation, in other embodiments, the stop pattern can be continuously formed and cross the memory array area 100a and the step area 100b to form a sandwich structure including a lower insulating layer, a middle stop layer, and an upper insulating layer. The formation method of the insulating layer 104 and the stop patterns 103a and 103b is well known to those skilled in the art and will not be further described here.

Next, a grounding layer 106 is formed on the insulating layer 104 of the memory array region 100a, and an isolation layer 105 is formed on the insulating layer 104 of the step region 100b. The grounding layer 106 can be used to conduct charges generated in subsequent processes to the substrate 100. In one embodiment, the grounding layer 106 includes a polysilicon layer, and the isolation layer 105 includes a silicon oxide layer, but the present invention is not limited thereto. In other embodiments, the grounding layer 106 can be other conductive layers, such as a metal layer. Depending on the actual situation, in other embodiments, the isolation layer 105 may be omitted, and the ground layer 106 may be formed continuously and across the memory array region 100a and the step region 100b. When the ground layer 106 is formed continuously on the memory array region 100a and the step region 100b, the formation of the stop pattern may also be omitted depending on the situation.

2 , a stacked structure 108 is formed on the ground layer 106 and the isolation layer 105. In one embodiment, the stacked structure 108 includes a plurality of dielectric layers 107 and a plurality of intermediate layers 109 alternately stacked on the substrate 100. The present invention does not limit the number of the dielectric layers 107 and the intermediate layers 109. In one embodiment, the dielectric layer 107 includes an oxide layer, and the intermediate layer 109 includes a nitride layer, but the present invention is not limited thereto. In other embodiments, the dielectric layer 107 and the intermediate layer 109 may be other dielectric material layers, as long as there is an etching selectivity between the dielectric layer 107 and the intermediate layer 109. In one embodiment, the middle layer 109 is used as a sacrificial layer and a subsequent replacement process is performed. In another embodiment, when the middle layer 109 is a doped polysilicon layer, no subsequent replacement process is performed. In addition, in the step region 100b, the stacking structure 108 has a step profile. The method of forming the stacking structure 108 to have a step profile is well known to those skilled in the art and will not be described further herein.

Then, a top cap layer 110 is formed on the stacked structure 108. The top cap layer 110 covers the stacked structure 108 and has a flat top surface. In one embodiment, the top cap layer 110 includes an oxide layer, but the present invention is not limited thereto. The method for forming the top cap layer 110 includes forming a top cap material layer on the stacked structure 108 and then performing a planarization process, such as a chemical mechanical polishing (CMP) process.

Referring to FIG. 3 and FIG. 4 , a channel structure VC penetrating the stacking structure 108 is formed in the memory array region 100a, and a dummy structure DV penetrating the stacking structure 108 is formed in the step region 100b.

In one embodiment, as shown in FIG. 3 , a channel structure hole VCH penetrating the stacking structure 108 is formed in the memory array region 100a, and a dummy structure hole DVH penetrating the stacking structure 108 is formed in the step region 100b. The method of forming the channel structure hole VCH and the dummy structure hole DVH includes a lithography etching process. In one embodiment, the channel structure hole VCH and the dummy structure hole DVH can be defined by the same mask, as shown in FIG. 10 or FIG. 12 . The process of etching the channel structure hole VCH and the dummy structure hole DVH uses the stop patterns 103a and 103b below as etching stop layers.

The channel structure hole VCH has a size W1, and the virtual structure hole DVH has a size W2. In one embodiment, the size W1 is substantially equal to the size W2. The step of forming the channel structure hole VCH is a critical process. When holes VCH and DVH of a single size are formed in the memory array area 100a and the step area 100b, the process window of the channel structure hole can be increased. However, the present invention is not limited to this. In another embodiment, the size W1 is different from the size W2. For example, when the size W2 is larger than the size W1, the virtual structure formed subsequently can provide better structural support for the step area.

Next, a semiconductor layer 122a is formed on the sidewall of the channel structure hole VCH, and a semiconductor layer 122b is formed on the sidewall of the virtual structure hole DVH. In one embodiment, the semiconductor layer 122a serves as a channel layer of a memory array. The method for forming the semiconductor layers 122a and 122b includes conformally forming a semiconductor material layer on the top cap layer 110, filling the channel structure hole VCH and the virtual structure hole DVH, and then performing an anisotropic etching process to remove part of the semiconductor material layer. In one embodiment, the semiconductor material layer includes a polycrystalline silicon layer, such as a non-doped polycrystalline silicon layer.

Continuing to refer to FIG. 3 , an isolation column 124a is filled in the channel structure hole VCH, and an isolation column 124b is filled in the dummy structure hole DVH. The method for forming the isolation column 124a and the isolation column 124b includes forming an isolation material layer on the top cap layer 110 to fill the channel structure hole VCH and the dummy structure hole DVH, and then performing a planarization process to remove the isolation material layer outside the channel structure hole VCH and the dummy structure hole DVH. In one embodiment, the isolation material layer includes a silicon oxide layer.

Then, a dielectric column 126 is formed in the isolation column 124a. The method of forming the dielectric column 126 includes forming a hole in the isolation column 124a by a photolithography process, forming a dielectric material layer on the cap layer 110 to fill the hole, and then performing a planarization process to remove the dielectric material layer outside the hole. In one embodiment, the dielectric material layer includes a silicon nitride layer.

In another embodiment, when the size W1 of the channel structure hole VCH is larger than the size W2 of the dummy structure hole DVH, the isolation material layer only fills the dummy structure hole DVH but does not fill the channel structure hole VCH. Then, the dielectric material layer can be used to fill the channel structure hole VCH to form the above structure.

Referring to FIG. 4 , a source column 200S and a drain column 200D are formed in the isolation column 124a, wherein the source column 200S and the drain column 200D are separated from each other by a dielectric column 126. The method for forming the source column 200S and the drain column 200D includes forming two holes in each isolation column 124a, and the process of etching the holes uses the lower stop pattern 103a as the etching stop layer. Then, a conductive layer is formed on the top cap layer 110 to fill the holes, and then a planarization process is performed to remove the conductive layer outside the holes. In one embodiment, the conductive layer includes a doped polysilicon layer. In one embodiment, the vertical channel structure VC includes a semiconductor layer 122a as a channel layer, a dielectric column 126, and a source column 200S and a drain column 200D.

Referring to FIG. 5 , a trench SLT (referred to as a “slit” in some embodiments) penetrating the stacking structure 108 is formed in the memory array region 100a, and a hole TVH penetrating the stacking structure 108 is formed in the step region 100b. More specifically, the trench SLT is formed to cross the memory array region 100a and the step region 100b, as shown in FIG. 11 or FIG. 13 . The method of forming the trench SLT and the hole TVH includes a lithography process. In one embodiment, the trench SLT and the hole TVH can be defined by the same mask, as shown in FIG. 11 or FIG. 13 . In one embodiment, the trench SLT may penetrate the ground layer 106 and extend into a portion of the insulating layer 104. In one embodiment, the hole TVH may penetrate the isolation layer 105 and the stop pattern 103b. More specifically, the hole TVH may extend into the insulating layer 104 below the stop pattern 103b, but does not penetrate the insulating layer 104. The trench SLT and the hole TVH expose the dielectric layer 107 and the intermediate layer 109 of the stacked structure 108.

In one embodiment, the size of the hole TVH is larger than the size of the virtual structure hole DVH, as shown in FIG. 11 and FIG. 13, but the present invention is not limited thereto. In another embodiment, the size of the hole TVH may be equal to or smaller than the size of the virtual structure hole DVH as required by the process.

6 , the plurality of intermediate layers 109 in the memory array region 100a and the stair region 100b are replaced with a plurality of gates 202G and a plurality of stairs 202ST. More specifically, after the replacement process, the stacking structure 204a on the memory array region 100a includes a plurality of dielectric layers 107a and a plurality of gates 202G alternately stacked on the substrate 100, and the stacking structure 204b on the stair region 100b includes a plurality of dielectric layers 107b and a plurality of stairs 202ST alternately stacked on the substrate 100. In one embodiment, when the middle layer 109 is doped polysilicon, the above replacement step can be omitted depending on the situation.

In one embodiment, a selective etching process is performed to allow the etchant to contact the middle layer 109 of the stacked structure 108 exposed by the trench SLT and the hole TVH. Thereby, the middle layer 109 of the stacked structure 108 is etched and removed to form a plurality of horizontal openings (not shown). The selective etching process may be an isotropic etching, such as a wet etching process. The etchant used in the wet etching process is, for example, hot phosphoric acid. Then, a composite dielectric layer 201 and a conductive layer 202 are sequentially formed in the trench SLT, the hole TVH, and the horizontal opening.

In one embodiment, the composite dielectric layer 201 and the conductor layer 202 cover the surface of the top cap layer 110, the sidewalls and bottom of the trench SLT, the sidewalls and bottom of the hole TVH and fill the horizontal opening. In one embodiment, the composite dielectric layer 201 includes an oxide/nitride/oxide (ONO) composite layer. In one embodiment, the conductor layer 202 includes a barrier layer and a metal layer. In one embodiment, the material of the barrier layer includes titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN) or a combination thereof. The material of the metal layer includes tungsten (W).

The composite dielectric layer 201 of the memory array region 100a serves as a charge storage structure 201a, and the composite dielectric layer 201 of the step region 100b serves as a step protection layer 201b of the step 202ST. The conductive layer 202 of the memory array region 100a forms a plurality of gates 202G, and the conductive layer 202 of the step region 100b forms a plurality of conductive steps 202ST. In one embodiment, each memory cell MC in the memory array includes a gate 202G, a charge storage structure 201a, a semiconductor channel layer 122a, a source column 200S, and a drain column 200D.

Referring to FIG. 7 , an etching back process is performed to remove the conductive layer 202 on the surface of the top cap layer 110, the bottom of the trench SLT, and the bottom of the hole TVH. The remaining conductive layer 202 is disposed on the sidewalls of the trench SLT and the sidewalls of the hole TVH. In one embodiment, the etching back process includes an anisotropic etching process.

Referring to FIG. 8 , an insulating wall 130a is formed in the trench SLT, and an insulating column 130b is formed in the hole TVH. The method for forming the insulating wall 130a and the insulating column 130b includes forming an insulating material layer on the cap layer 110 to fill the trench SLT and the hole TVH, and then performing a planarization process to remove the insulating material layer outside the trench SLT and the hole TVH. In one embodiment, the insulating material layer includes a silicon oxide layer, such as a low-temperature silicon oxide layer. More specifically, the insulating material layer is a single oxide layer.

Referring to FIG. 9 , a through hole TV is formed in the step region 100 b, and the through hole TV penetrates the insulating pillar 130 b in the hole TVH. The method for forming the through hole TV includes forming a through hole opening in each insulating pillar 130 b, then filling the through hole opening with a conductive layer, and then performing a planarization process to remove the conductive layer outside the hole. Since the insulating pillar 130 b has a single oxide layer, the known short circuit problem between the through hole and the underlying internal connection structure caused by incomplete etching during the etching of the through hole opening can be avoided, thereby improving the reliability of the manufactured memory element. In one embodiment, the conductive layer includes tungsten. The above-mentioned hole will penetrate the insulating layer 104 and extend into a portion of the component layer 102. More specifically, the via TV can be landed on the top metal layer (not shown) in the internal connection structure of the component layer 102. The via TV is connected to the internal connection structure, so it can also be called a signal contact. At this point, the memory structure 10 of the present invention is formed.

The memory device of the present invention will be described below with reference to FIG9, FIG11 and FIG13. In one embodiment, the memory device 10 includes a substrate 100, a stacking structure 204a, a stacking structure 204b, a channel structure VC, an insulating pillar 130b and a through hole TV. The substrate 100 has a memory array region 100a and a step region 100b. The stacking structure 204a is disposed on the substrate 100 in the memory array region 100a, wherein the stacking structure 204a includes a plurality of alternately stacked dielectric layers 107a and a plurality of gates 202G. The stacking structure 204b is disposed on the substrate 100 in the step region 100b, wherein the stacking structure 204b includes a plurality of dielectric layers 107b and a plurality of steps 202ST that are alternately stacked. The channel structure VC penetrates the stacking structure 204a in the memory array region 100a. The insulating pillar 130b penetrates the stacking structure 204b in the step region 100b. The through hole TV penetrates the insulating pillar 130b in the step region 100b. The conductive layer 202 surrounds the sidewall of the insulating pillar 130b. In one embodiment, the conductive layer 202 may be referred to as a conductive ring, connected to a plurality of gates 202G and a plurality of steps 202ST.

In one embodiment, the memory device 10 further includes a ground layer 106, which is disposed between the substrate 100 and the stacked structure 204a, wherein the channel structure VC further penetrates the ground layer 106.

In one embodiment, the memory device 10 further includes an insulating layer 104 disposed between the substrate 100 and the stacked structure 204b. In one embodiment, the memory device 10 further includes a plurality of stop patterns 103b disposed in the insulating layer 104, wherein the through hole TV penetrates one of the stop patterns 103b.

In one embodiment, the channel structure VC includes a dielectric column 126, a source column 200S, a drain column 200D, and a semiconductor layer 122a. The source column 200S and the drain column 200D are separated from each other by the dielectric column 126. The semiconductor layer 122a is disposed between the source column 200S and the corresponding gate 202G and between the drain column 200D and the corresponding gate 202G. The semiconductor layer 122a can be called a channel ring or a channel layer. In one embodiment, the semiconductor layer 122a is a continuous channel layer, which is arranged on the side walls of multiple gates 202G and multiple dielectric layers 107a, but the present invention is not limited to this. In another embodiment, the semiconductor layer 122a includes multiple discontinuous and separated channel blocks, which are only arranged on the side walls of multiple gates 202G. A composite dielectric layer serving as a charge storage structure 201a is further arranged between the semiconductor layer 122a and the gate 202G.

In one embodiment, the memory device 10 further includes a virtual structure DV that penetrates the stacking structure 204b in the step region 100b and is adjacent to the insulating pillar 130b. In one embodiment, the memory device 10 further includes an insulating layer 104 that is disposed between the substrate 100 and the stacking structure 204b. In one embodiment, the memory device 10 further includes a plurality of stop patterns 103b that are disposed in the insulating layer 104, wherein the virtual structure DV does not penetrate one of the stop patterns 103b. More specifically, the virtual structure DV lands on one of the stop patterns 103b.

In one embodiment, the virtual structure DV includes an isolation column 124b and a semiconductor layer 122b surrounding the sidewall of the isolation column 124b. The semiconductor layer 122b can be referred to as a semiconductor ring and is connected to the step protection layer 201b.

In one embodiment, the size of the channel structure VC is substantially equal to the size of the virtual structure DV. In one embodiment, the size of the channel structure VC is not equal to the size of the virtual structure DV.

In one embodiment, the memory element 10 further includes an insulating wall 130a, which penetrates the stacking structure 204a in the memory array region 100a and is adjacent to the channel structure VC. In one embodiment, the insulating wall 130a formed in the trench SLT is further extended to the step region 100b, as shown in FIG. 11 and FIG. 13.

In summary, the present invention provides a memory element and a method for forming the same, which can simultaneously define trenches for replacement process and holes for through-holes, and then fill the trenches and holes with a single oxide layer to form insulating walls and insulating pillars respectively, and then form through-holes penetrating the insulating pillars. The above-mentioned steps of defining trenches/holes simultaneously can simplify the process. In addition, the above-mentioned single oxide layer can avoid the known short circuit problem between the through-hole and the underlying internal connection structure caused by incomplete etching during the etching of the through-hole opening, thereby improving the reliability of the manufactured memory element.

Although the present invention has been disclosed as above by the embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the relevant technical field can make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the attached patent application.

10: Memory components

100: Base

100a: memory array area

100b: Stairway area

102: Component layer

103a, 103b: Stop pattern

104: Insulation layer

105: Isolation layer

107a, 107b: dielectric layer

110: Top cover

122a, 122b: semiconductor layer

124b: Isolation column

126: Dielectric pillar

130a: Insulation wall

130b: Insulation Pillar

200S: Source column

200D: Drain column

201: Composite dielectric layer

201a: Charge storage structure

201b: Staircase protection layer

202: Conductor layer

202G: Gate

202ST: Stairs

204a, 204b: stacking structure

DVH: Virtual structural hole

DV: Virtual structure

MC: Memory Cell

SLT: Channels

VC: Channel structure

VCH: channel structure holes

TV:Through hole

TVH: Hole

W1, W2: size

Claims (11)

A memory element comprises: a substrate having a memory array region and a step region; a first stacking structure disposed on the substrate in the memory array region, wherein the first stacking structure comprises a plurality of first dielectric layers and a plurality of gates stacked alternately; a second stacking structure disposed on the substrate in the step region, wherein the second stacking structure comprises a plurality of second dielectric layers and a plurality of steps stacked alternately; a channel structure penetrating the first stacking structure in the memory array region; an insulating column penetrating the second stacking structure in the step region; a through hole penetrating the insulating column in the step region; and A conductive layer surrounds the side walls of the insulating column. The memory device as described in claim 1 further includes: an insulating layer disposed between the substrate and the second stacking structure; and a plurality of stop patterns disposed in the insulating layer, wherein the through hole penetrates one of the stop patterns. A memory device as described in claim 1, wherein the channel structure includes: a dielectric column; a source column and a drain column separated from each other by the dielectric column; and a first semiconductor layer disposed between the source column and the gate and between the drain column and the gate. The memory device as described in claim 1 further includes: A virtual structure penetrating the second stacking structure in the step region and adjacent to the insulating column. The memory device as described in claim 4 further includes: an insulating layer disposed between the substrate and the second stacking structure; and a plurality of stop patterns disposed in the insulating layer, wherein the dummy structure does not penetrate one of the stop patterns. A memory device as described in claim 4, wherein the virtual structure includes: an isolation pillar; and a second semiconductor layer surrounding the sidewall of the isolation pillar. The memory device as described in claim 1 further includes: An insulating wall that penetrates the first stacking structure in the memory array area and is adjacent to the channel structure. A memory device as described in claim 7, wherein the insulating wall is further extended into the step region. A method for forming a memory element, comprising: Providing a substrate, wherein the substrate has a memory array region and a step region; Forming a stacking structure on the substrate, wherein the stacking structure includes a plurality of dielectric layers and a plurality of intermediate layers stacked alternately, and the stacking structure in the step region has a step profile; Forming a channel structure penetrating the stacking structure in the memory array region, and forming a dummy structure penetrating the stacking structure in the step region; Forming a trench penetrating the stacking structure in the memory array region, and forming a hole penetrating the stacking structure in the step region; Replacing the plurality of intermediate layers in the memory array region with a plurality of gates, and replacing the plurality of intermediate layers in the step region with a plurality of steps; Forming an insulating wall in the trench, and forming an insulating column in the hole; and Forming a through hole in the step region, wherein the through hole penetrates the insulating column. A method for forming a memory device as described in claim 9, wherein during the step of replacing the plurality of intermediate layers with the gate and the step, a conductive layer is further formed on the sidewalls and the bottom of the trench and the hole. The method for forming a memory device as described in claim 9, wherein the trench is further formed to cross over into the step region, and the insulating wall formed in the trench further extends into the step region.

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