TWI760094B - Memory device, flash memory controller and associated access method - Google Patents

Abstract

The invention discloses a control method applied to a flash memory controller, which includes the following steps: creating a write time table, wherein the write time table records block numbers of blocks having data stored therein and corresponding first time and second time; referring to the write time table to determine whether there is at least one first block in the flash memory module whose first time is earlier than a first threshold, and if so, recording the at least one first block into an expired block table; referring to the write time table to determine whether there is at least one second block in the flash memory module whose second time is earlier than a second threshold, and if so, recording the at least one second block into the expired block table; and referring to the expired block table to perform an expired block recycling operation.

Description

Memory device, flash memory controller and access method thereof

The present invention relates to a flash memory controller and a related control method.

With the development of three-dimensional flash memory technology, more and more layers are stacked in the flash memory chip. In addition, the current flash memory module will contain many triple-level storage (Triple-Level Cell, TLC) or Quad-Level Cell (QLC) blocks, therefore, the quality of the data stored in the flash memory is getting worse and worse, even after a few weeks after the data is written. The rapid slide down makes subsequent decoding difficult or even impossible to read. In order to solve this problem, the flash memory controller can use the idle time to read part of the content of each block in the flash memory module to determine the quality of each block. However, the above method will consume A lot of time, and if the flash memory controller is always busy, the access efficiency and block quality cannot be taken into account.

Therefore, one of the objectives of the present invention is to provide a flash memory controller and a related control method, which can efficiently pre-process the blocks in the flash memory module that may have problems in quality, so as to solve the problem of previous problems. Issues described in the technique.

In one embodiment of the present invention, a control method applied to a flash memory controller is disclosed, wherein the flash memory controller is used to access a flash memory module, the flash memory module The group includes a plurality of blocks, and each block includes a plurality of data pages, and the control method includes: when data is written into any block of the flash memory module, a first data page, record a first time in the first data page; when data is written to at least one intermediate data page of any block of the flash memory module, record a first time in the at least one intermediate data page second time; when data is written to a last data page of any block of the flash memory module, record the first time and the second time in the last data page; create a write time record Table, wherein the write time record table records the block number of the block in which data is written in the flash memory module and the corresponding first time, or records the block number in the flash memory module The block number of the block in which data is written and the corresponding first time and the second time; refer to the write time record table to determine whether there is the first time of the block in the flash memory module Earlier than a first threshold, if the first time of at least one first block in the flash memory module is earlier than the first threshold, recording the at least one first time in an expired block table a block; refer to the write time record table to determine whether the second time of a block in the flash memory module is earlier than a second threshold, if there is at least one block in the flash memory module The second time of the second block is earlier than the second threshold, the at least one second block is recorded in the expired block table; and the at least one first area recorded in the expired block table An expired block recovery operation is performed on the block and the at least one second block, so as to sequentially move the valid data in the at least one first block and the at least one second block to at least one blank block.

In another embodiment of the present invention, a flash memory controller is disclosed, wherein the flash memory controller is used to access a flash memory module, and the flash memory controller includes There is a ROM, a microprocessor and a buffer memory. When the microprocessor writes data to a first data page of any block of the flash memory module, a first time is recorded in the first data page; when the microprocessor writes When data is written to at least one intermediate data page of any block of the flash memory module, a second time is recorded in the at least one intermediate data page; when the microprocessor writes data to the flash memory In the last data page of any block of the memory module, the first time and the second time are recorded in the last data page; the microprocessor also establishes a writing time record table, wherein the writing time The record table records the block number of the block in which data is written in the flash memory module and the corresponding first time, or records the block in which data is written in the flash memory module and the corresponding first time and the second time. In addition, the microprocessor refers to the writing time record table to determine whether the first time of a block in the flash memory module is earlier than a first threshold value, if there is a block in the flash memory module If the first time of at least one first block is earlier than the first threshold value, the at least one first block is recorded in an expired block table; the microprocessor refers to the writing time record table to determine the Whether the second time of a block in the flash memory module is earlier than a second threshold, if the second time of at least one second block in the flash memory module is earlier than the second time threshold value, record the at least one second block in the expired block table; and perform expired block recovery according to the at least one first block and the at least one second block recorded in the expired block table The operation is to sequentially move the valid data in the at least one first block and the at least one second block to at least one blank block.

In another embodiment of the present invention, a memory device is disclosed, which includes a flash memory module and a flash memory controller. When the flash memory controller writes data to a first data page of any block of the flash memory module, a first time is recorded in the first data page; When the flash memory controller writes data to at least one intermediate data page of any block of the flash memory module, a second time is recorded in the at least one intermediate data page; when the flash memory control When the device writes data to a last data page of any block of the flash memory module, the first time and the second time are recorded in the last data page; the flash memory controller creates another a write time record table, wherein the write time record table records the block number of the block in which data is written in the flash memory module and the corresponding first time, or records the flash memory module The memory module has the block number of the block in which data is written and the corresponding first time and the second time; in addition, the flash memory controller refers to the write time record table to determine the flash memory Whether the first time of a block in the memory module is earlier than a first threshold, if the first time of at least one first block in the flash memory module is earlier than the first threshold , the at least one first block is recorded in an expired block table; the flash memory controller refers to the write time record table to determine whether there is the second block of the block in the flash memory module The time is earlier than a second threshold. If the second time of at least one second block in the flash memory module is earlier than the second threshold, the at least one block is recorded in the expired block table. the second block; and performing an expired block recovery operation according to the at least one first block and the at least one second block recorded in the expired block table, so as to order the at least one first block and the at least one second block in sequence. Valid data in at least one second block is moved to at least one blank block.

FIG. 1 is a schematic diagram of a memory device 100 according to an embodiment of the present invention. The electronic device 100 includes a flash memory module 120 and a flash memory controller 110 , and the flash memory controller 110 is used for accessing the flash memory module 120 . According to this embodiment, the flash memory controller 110 includes a microprocessor 112 , a read only memory (ROM) 112M, a control logic 114 , a buffer memory 116 , and an interface logic 118 . The ROM 112M is used to store a code 112C, and the microprocessor 112 is used to execute the code 112C to control access to the flash memory module 120 . The control logic 114 includes an encoder 132 and a decoder 134, wherein the encoder 132 is used to encode the data written into the flash memory module 120 to generate a corresponding check code (or error correction code). code (Error Correction Code, ECC), and the decoder 134 is used for decoding the data read from the flash memory module 120 .

In a typical situation, the flash memory module 120 includes a plurality of flash memory chips, and each flash memory chip includes a plurality of blocks, and the flash memory controller 110 controls the flash memory. The operation of erasing data by the memory module 120 is performed in units of blocks. In addition, a block can record a specific number of data pages, wherein the operation of the flash memory controller 110 to write data to the flash memory module 120 is performed in units of data pages. In this embodiment, the flash memory module 120 is a three-dimensional NAND-type flash memory (3D NAND-type flash) module.

In practice, the flash memory controller 110 that executes the code 112C through the microprocessor 112 can use its own internal components to perform various control operations. For example, the control logic 114 is used to control the flash memory module 120. Access operations (especially access operations to at least one block or at least one data page), use the buffer memory 116 to perform required buffering, and use the interface logic 118 to communicate with a Host Device 130 . The buffer memory 116 is implemented by random access memory (Random Access Memory, RAM). For example, the buffer memory 116 may be a static random access memory (Static RAM, SRAM), but the invention is not limited thereto. In addition, the flash memory controller 110 is coupled to a dynamic random access memory (Dynamic Random Access Memory, DRAM).

In one embodiment, the memory device 100 may be a portable memory device (eg, a memory card conforming to SD/MMC, CF, MS, XD standards), and the host device 130 is an electronic device that can be connected to the memory device 100 , such as mobile phones, laptops, desktops...etc. In another embodiment, the memory device 100 may be a solid state drive or an embedded storage conforming to Universal Flash Storage (UFS) or Embedded Multi Media Card (EMMC) specifications The main device 130 can be a processor of the mobile phone, notebook computer, and desktop computer.

FIG. 2 is a schematic diagram of a block 200 in the flash memory module 120 according to an embodiment of the present invention, wherein the flash memory module 120 is a three-dimensional NAND type flash memory. As shown in FIG. 2, the block 200 includes a plurality of memory cells (such as the floating thyristor 202 shown in the figure or other charge trap devices), which pass through a plurality of bit lines (the figure only BL1-BL3) and a plurality of word lines (eg, WL0-WL2, WL4-WL6 are shown) are shown to form a three-dimensional NAND-type flash memory structure. In Figure 2, taking the uppermost plane as an example, all the floating thyristors on the word line WL0 constitute at least one data page, and all the floating thyristors on the word line WL1 constitute at least another data page page, and all the floating thyristors of word line WL2 constitute at least one other data page . . . and so on. In addition, the definition between the word line WL0 and the data page (logical data page) is also different according to the different writing methods of the flash memory. , SLC), all floating thyristors on the word line WL0 only correspond to a single logical data page; when using the Multi-Level Cell (MLC) method, the word All floating thyristors on line WL0 correspond to two logical data pages; when using triple-level storage (TLC) to write, all floating thyristors on word line WL0 correspond to three logical data pages ; and when using the quad-level storage (QLC) method to write, all floating gate transistors on the word line WL0 correspond to four logical data pages. Since those skilled in the art should be able to understand the structure of the 3D NAND flash memory and the relationship between word lines and data pages, the relevant details are omitted here.

FIG. 3 is a flow chart of establishing a writing time record table according to an embodiment of the present invention. At step 300, the process starts, the flash memory controller 110 is powered on and the initialization operation is completed. In step 302, the flash memory controller 110 selects a block from a plurality of blank blocks of the flash memory module 120, and prepares to write the data from the master device 130 into the block. In step 304, the flash memory controller 110 starts writing data from the first data page of the block, and writes the current time information to the first data page and the middle data page when the data is written into the first data page and the middle data page. in the spare area. Specifically, referring to the schematic diagram of the flash memory module 120 shown in FIG. 4, assuming that the block B1 includes a plurality of data pages P1-P256, the flash memory controller 110 transfers the data from the first page of the block B1 A data page P1 starts to write data from the host device 130 in sequence, wherein when the flash memory controller 110 is ready to write data to the data page P1, the flash memory controller 110 will simultaneously retrieve the current data The time information T1_1, for example, can be generated by the built-in timer or the absolute time from the host device 130 (for example, 2:00 pm on May 11, 2020) to generate the corresponding time information, and the data from the host device can be correlated with the relevant time information. The time information T1_1 is also written into the data page P1, wherein the time information T1_1 can be written into the spare area located at the rear end of the data page P1. Next, the flash memory controller 110 writes data to the data pages P2, P3, . . . in sequence until the flash memory controller 110 prepares to write data to the intermediate data page P128, The device 110 will simultaneously retrieve the current time information T1_M and write the data from the host device together with the related time information T1_M into the data page P128, wherein the time information T1_M can be written to the spare area at the back end of the data page P128 . It should be noted that, the data pages P2 to P127 between the first data page P1 and the intermediate data page P128 do not need to write any time information, so as to reduce the burden on the flash memory controller 110 . It should be noted that the above-mentioned spare area of the data page can also be called a management area, that is, used to store some management data, such as logical addresses, etc.

It should be noted that, in the embodiment of FIG. 4 , the data page P128 is used as the intermediate data page, but this is only an example rather than a limitation of the present invention. In other embodiments, the data page P127 may also be used as the intermediate data page, or the data pages P127 and P128 may be simultaneously used as the intermediate data pages. In addition, in another embodiment, the number of intermediate data pages may be multiple data pages. For example, four data pages P126, P127, P128, and P129 are all used as the multiple intermediate data pages described in this embodiment. Pages, that is, the spare areas of data pages P126, P127, P128, and P129 all store corresponding time information.

Next, the flash memory controller 110 sequentially writes data to data pages P129, P130, . . . until when the flash memory controller 110 is ready to write data to the last data page (ie, data page P256) , the flash memory controller 110 writes the time information T1_1 of the previous data page P1 and the time information T1_M of the data page P128 together with the data from the host device 130 into the data page P256, wherein the time information T1_M can be written to the spare area located at the back end of data page P256.

In step 306, during the process of data writing in block B1, the flash memory controller 110 will synchronously create the writing time record table 500 in the DRAM 140 as shown in FIG. The time record table 500 records the block number B1 and the corresponding time information T1_1 and T1_M. It should be noted that the writing time record table 500 records the time information T1_1 of the first data page P1 and the time information T1_M of the intermediate data page (eg, the data page P128 ), and if it is described in the previous paragraph, each time When multiple intermediate data pages are set in a block, for example, when four data pages P126, P127, P128, and P129 are used as intermediate data pages at the same time, the writing time record table 500 can be written according to the data pages P126, P127, P128. , Multiple time information recorded by P129 to generate a single time information of the intermediate data page, for example, the multiple time information recorded in the data pages P126, P127, P128, P129 are averaged or the intermediate value is taken to obtain the intermediate data The single time information corresponding to the page.

It should be noted that, for some memory devices that do not have the DRAM 140 , the above-mentioned writing time record table 500 can also be stored in the buffer memory 116 .

In step 308, the microprocessor 112 determines whether all the data pages of the current block B1 are filled with data, if not, the process returns to step 304 to continue writing data to the remaining data pages of the block B1; if so, the process Return to step 302 to select the next blank block, such as the block B2 shown in FIG. 4, and then, similar to the data writing process of the flash memory controller 110 to the block B1, when the flash memory controller When 110 is ready to write data to the data page P1 of the block B2, the flash memory controller 110 will simultaneously retrieve the current time information T2_1, and write the data from the host device together with the relevant time information T2_1 into In the data page P1 of the block B2; when the flash memory controller 110 prepares to write data into the data page P128 of the block B2, the flash memory controller 110 will simultaneously retrieve the current time information T2_M, and Write the data from the master device together with the related time information T2_M into the data page P128 of the block B2; and when the flash memory controller 110 is ready to write data to the data page P256, the flash memory control The server 110 writes the time information T2_1 of the previous data page P1 and the time information T2_M of the data page P128 into the data page P256 together with the data from the host device 130 . In addition, the microprocessor 112 updates the writing time record table 500 to record the block number B2 and the corresponding time information T2_1 and T2_M.

Whenever there is a blank block in the flash memory module 120 for data writing, the microprocessor 112 will update the write time record table 500, that is, the write time record table 500 records the flash memory module The time information of the first data page P1 of each block in 120 and the time information of the intermediate data pages (eg, data page P128 ).

In addition, the write time record table 500 will be resident in the DRAM 140 to facilitate the subsequent use of expired block determination and garbage collection operations. When the memory device 100 needs to be powered off, the microprocessor 112 will first The write time record table 500 is written into the flash memory module 120 , and after the memory device 100 is powered on, the write time record table 500 in the flash memory module 120 is read again and loaded into the DRAM 140 for subsequent use.

However, the memory device 100 may be suddenly powered off due to various reasons, resulting in the loss of the write time record table 500 stored in the DRAM 140 . Therefore, after the memory device 100 is powered on again, the writing time record table 500 needs to be re-created in the DRAM 140 . Specifically, referring to FIG. 6 is a flowchart of creating a write time record table 500 in the DRAM 140 after the memory device according to an embodiment of the present invention is powered on. At step 600, the flow begins, and the memory device 100 is powered on and begins an initialization operation. In step 602 , the microprocessor 112 determines whether the power outage of the memory device 100 before the power-on is abnormal (sudden power outage), if not, the process proceeds to step 604 to read data from the flash memory module 120 The writing time record table 500 is retrieved and temporarily stored in the DRAM 140 ; if yes, the flow goes to step 606 . For example, when the memory device 100 is normally shut down/powered off, the flash memory controller 110 will store a plurality of temporary tables and data stored in the buffer memory 116 to the flash memory module 120 includes a flag used to indicate whether the memory device 100 is shut down normally, so the flash memory controller 110 can read and store the memory in the flash memory module 120 after power-on to determine whether the memory device 100 has encountered an abnormal power outage before, for example, when the above-mentioned tag is not correctly set, it is determined that an abnormal power outage has been encountered previously. In step 606 , the microprocessor 112 sequentially reads the last data page (eg, the data page P256 shown in FIG. 4 ) of each block in which data is written in the flash memory module 120 to obtain The time information of the first data page of each block and the time information of the intermediate data pages. For example, referring to FIG. 4 at the same time, the microprocessor 112 can directly read the last data page P256 of the block B1 to obtain the time information T1_1 of the first data page P1 and the time information T1_M of the intermediate data page P128, and It is also possible to directly read the last data page P256 of the block B2 to obtain the time information T2_1 of the first data page P1 and the time information T2_M of the intermediate data page P128. In addition, in some special cases, for example, the data of the last data page P256 of the block is damaged, or the last data page P256 of the block has not yet been written with data, then the microprocessor 112 can directly read the above Time information for the first data page and intermediate data pages of the block.

Since the initialization time of the memory device 100 is limited, for example, 1-2 seconds, and the flash memory controller 110 will need to rebuild many other comparison tables/mapping tables during the initialization operation, therefore, due to this The embodiment can obtain the time information of the first data page and the time information of the intermediate data pages only by reading the last data page of the block, so that the reconstructed writing time record table 500 becomes very fast, so as to avoid Timeout for initialization operation.

After obtaining the time information of the first data page and the time information of the intermediate data pages of each block in which data is written, the write time record table 500 can be re-established in the DRAM 140 , and the flow then proceeds to 608 to end the operation.

FIG. 7 is a flowchart of an expired block recovery operation according to an embodiment of the present invention. At step 700, the process starts and the memory device 100 has completed the initialization operation. In step 702 , the microprocessor 112 determines whether the time information of the first data page P1 of any block in the flash memory module 120 is earlier than a first threshold value according to the writing time record table 500 . If yes, the flow goes to step 704 ; if not, the flow goes to step 708 . The first threshold value can be a time determined according to the current time. For example, if the current time is 8:00 pm on May 21, 2020, the first threshold value can be 12 days ago, that is, the first threshold value can be It is May 9, 2020 at 8:00 pm.

In step 704, the microprocessor 112 adds blocks whose time information of the first data page P1 is earlier than a first threshold value to an expired block table (eg, records these blocks in the expired block table) block number), and mark these blocks as pending blocks. In this embodiment, the expired block table is used to record the priority order of the expired block recycling operation, and it has a fixed size (that is, the number of blocks that can be recorded has an upper limit). Therefore, if in step 702 If the number of determined blocks is too large, the block with earlier time information of the first data page P1 is preferentially selected to be added to the expired block table.

In step 706 , the microprocessor 112 determines whether the block recorded in the expired block table has reached the upper limit value, if yes, the flow goes to step 712 ; if not, the flow goes to step 708 .

In step 708 , the microprocessor 112 determines whether there is any intermediate data page (eg, data page P128 in FIG. 4 ) in the flash memory module 120 with earlier time information according to the writing time record table 500 . If there is a second threshold value, the process goes to step 710 ; if not, the process goes to step 712 . The second threshold value may be a time determined according to the current time, and the second threshold value is later than the first threshold value. For example, assuming that the current time is 8:00 pm on May 21, 2020, the second threshold value may be 11 days ago, that is, the first threshold value may be 8:00 pm on May 10, 2020.

In step 710, the microprocessor 112 adds blocks whose time information of the intermediate data page is earlier than a second threshold value to an expired block table, and marks these blocks as pending blocks. In addition, if the number of blocks determined in step 708 is too large, the block with earlier time information of the intermediate data page is preferentially selected to be added to the expired block table.

Regarding the above steps 708 and 710, since the blocks whose time information of the first data page P1 is earlier than the first threshold value have been added to the expired block table in step 704, the steps 708 and 710 are substantially It can be regarded as adding the blocks whose time information of the intermediate data page is between the second threshold value and the first threshold value to the expired block table.

It should be noted that not all the blocks recorded in the above expired block table are determined according to the methods in steps 702 and 708, that is, some of the blocks recorded in the expired block table may be Determined by block quality or other mechanisms.

In step 712, the microprocessor 112 sequentially performs the expired block recovery operation according to the blocks recorded in the expired block table. Specifically, the microprocessor 112 can move the valid data in the block recorded in the expired block table to a blank data page, and mark the block as invalid or after the valid data of the block is completely moved. is to erase. It should be noted that the expired block recovery operation described in step 712 can be performed in the background, that is, when the flash memory controller 110 is in an idle state (eg, does not need to process an access command from the host device 130 ), Then the microprocessor 112 can start to perform the expired block recovery operation until the flash memory controller 110 receives the access command from the host device 130 and needs to start busy.

Due to the increasing unit density of the memory capacity of the 3D NAND type flash memory, the memory performance is deteriorating continuously. The charge will continue to be lost. After a period of time, the charge stored in the gate of some memory cells can no longer reflect the charge of the data originally intended to be stored, resulting in frequent reading errors. These errors usually cause the flash memory controller to start the correction mechanism of changing the read voltage and hard decoding and soft decoding, so that correct data can be read from these expired blocks. These correction mechanisms are usually very time-consuming, Power consumption may also fail to correct errors at all, causing the memory controller to not read the correct data. Therefore, it is necessary to record the writing time of the block to avoid the above problems. It should be noted that the expired block recycling operation described in the above embodiment is not different from the garbage collection operation, and the expired block table in this embodiment is also different from the garbage collection sequence required for the garbage collection operation. Specifically, during the operation of the memory device 100, the flash memory controller 110 will continue to determine the number of valid data pages of each block in the current flash memory module 120, so as to determine which blocks need to be A garbage collection operation is performed. For example, when the number of valid data pages of a block is lower than a threshold, the block will be queued into a garbage collection sequence for subsequent garbage collection operations. However, the expired block table described in this embodiment records the blocks whose writing time is too long, that is, some blocks of these blocks may not meet the standard of garbage collection operation, such as these blocks The number of valid data pages for a block is well above this threshold. In addition, since the data of the blocks recorded in the expired block table is about to deteriorate rapidly, the priority order of the expired block table is higher than the garbage collection sequence, that is, if any block number is recorded in the expired block table, then in the In the case that the garbage collection operation is allowed to be interrupted, the flash memory controller 110 will preferentially stop the garbage collection operation and start the expired block recovery operation. In other words, the flash memory controller 110 immediately performs the expired block recovery operation on the blocks recorded in the expired block table.

In step 714, since block writing and erasing are performed when the expired block recovery operation is performed in step 712, the microprocessor 112 updates the writing time record table 500 according to the writing and erasing of the above-mentioned blocks. . For example, if the block B1 is marked as invalid or erased, the microprocessor 112 can delete the time information about the block B1 in the writing time record table 500 .

The reason why the blocks to be added to the expired block table are determined according to the second threshold value in the above steps 708 and 710 is that the time information of the intermediate data page can better reflect the writing time of the entire block, and by adding the second threshold value The value is set to be later than the first threshold value, and the time information of the intermediate data page is added to the expired block table for the time information of the intermediate data page between the second threshold value and the first threshold value, so that the expired block table can be used at one time. A sufficient number of blocks are added for subsequent expired block recycling operations, without the need to repeat the process in Figure 7 or other mechanisms to pick out blocks that require expired block recycling operations. In addition, in the stereoscopic flash memory, the data stored in the block will deteriorate rapidly over time, but if the block is read or written (writing data to the remaining data pages) In this case, the overall data quality of the block can be slightly improved. Therefore, the above-mentioned use of the second threshold value and the first threshold value as the judgment mechanism allows the blocks with poor quality to be preferentially added to the expired block table. In addition, since the data writing time of the block may vary greatly, that is, the time information of the first data page of the block and the time information of the middle data page may have a large gap. Therefore, by using another The time information of the intermediate data page can better reflect the overall writing time of the block, which can make the judgment of block expiration more accurate.

Referring to the above embodiments in FIGS. 3 to 7, the time information of the first data page and the intermediate data page of each block is recorded by creating a writing time record table 500, and the first threshold value is used. With the second threshold value to select the blocks that need to be reclaimed for expired blocks, on the whole, it can be more efficient and efficient to select the blocks that need to be reclaimed for expired blocks.

The expired block recycling operation needs to cooperate with the logical data page and the physical data page link table to find out all the valid data pages of the block, and move the valid data pages from the expired block to the new block. This behavior causes the data in the valid data page to be rewritten to a new block, which resets the validity period of these data and erases the expired block for use. After moving the valid data, the microprocessor 112 needs to update the link table of the logical data page and the physical data page and the data number table of the valid data page for creating a new block. In order to be cautious, the invalid data in the expired block can also be moved to another new block, and the logical data page and the physical data page link table of the invalid data can be created correspondingly, so as to prevent the host from deleting the data by mistake. rescue data. Please note that in some expired blocks, all data pages may be valid data pages, then all data must be moved to new data to reset the validity period of all data.

In addition, in some applications, the flash memory module 120 may have thousands of blocks and frequent writes. Therefore, the write time record table 500 needs to record many block numbers and associated times. information, thus seriously consuming the storage space of the DRAM 140 . In addition, if the memory device 100 does not have the DRAM 140 and the writing time record table 500 needs to be stored in the buffer memory 116 , then the buffer memory 116 is usually implemented with an expensive SRAM and the capacity is not too large. , thus causing more trouble in the memory configuration of the buffer memory 116 . As mentioned above, in the following embodiment, another compression method of the write time record table 500 is provided, which can write most of the content of the write time record table 500 to the block of the flash memory module 120 in order to reduce the size of the write time record table 500 stored in the DRAM 140 or the buffer memory 116 .

For example, referring to the schematic diagram of the write time record table 800 after compression shown in FIG. 8 , the write time record table 800 after compression can be obtained by simplifying the compression of the write time record table 500 . In FIG. 8, the compressed write time record table 800 includes multiple time ranges and at least one corresponding data page address, wherein the multiple time ranges can be any suitable time ranges, and in this embodiment, the time ranges The range is in one day. In the embodiment of FIG. 8 , the microprocessor 112 sequentially or periodically writes the block numbers and the corresponding time information in the writing time record table 500 to the blocks of the flash memory module 120 , the time range in FIG. 8 is today's situation to illustrate, when the flash memory controller 110 writes data to multiple blocks of the flash memory module 120, and creates a write time record table synchronously After 500, the microprocessor 112 will write the block number and the corresponding time information recorded in the write time record table 500 into the data page P25 of the block B200, and the compressed write time record table 800 will record The data page address "PPA98765" of the data page P25 of the block B200; in addition, since the data page P25 of the block B200 records the content of the writing time record table 500, the microprocessor 112 can record the writing time The relevant data in the table 500 is deleted to free up memory space. Similarly, the time range shown in Figure 8 is that the data page address "PPA33333" recorded in "yesterday" corresponds to the data page P46 of block B201, and the data page P46 of block B201 records the area written yesterday. block and the corresponding time information; similarly, the time range shown in Figure 8 is that the data page address "PPA33445" recorded in "the day before yesterday" corresponds to the data page P37 of the block B202, and the data page P37 of the block B202 The block written the day before yesterday and the corresponding time information are recorded. Therefore, since the content in the write time record table 500 shown in FIG. 5 can be stored in the flash memory module 120 , and the compressed write time record table 800 only needs to be recorded in the flash memory module 120 Therefore, the load on the memory space of the writing time record table 500 can be effectively reduced.

In addition, since the blocks in the flash memory module 120 may be erased and become blank blocks, the microprocessor 112 will update the flash memory when the microprocessor 112 knows that a block has been erased The module 120 and the contents of the compressed time record table 800 are written. For example, assuming that the block B1 written yesterday is erased today, the microprocessor 112 reads the content of the data page P46 of the block B201, deletes the block B1 and the related time information, and rewrites it. Write to another data page, such as data page P47 of block B201; in addition, replace the data page address of data page P46 of block B201 in the compressed write time record table 800 with the data page of block B201 The address of the data page for P47.

In addition, in order to facilitate the management of blocks and data pages, each time range in the compressed write time record table 800 corresponds to a dedicated block, such as the block numbers and times of all blocks in which data was written the day before yesterday. The information is written into block B202, the block number and time information of all blocks where data was written yesterday are written into block B201, and the block number and time of all blocks where data is written today Information is written to block B200, ... and so on. In addition, the above-mentioned exclusive blocks will not be used to store other data.

Summarizing the present invention briefly, in the control method of the present invention applied to a flash memory controller, the time of the first data page and the intermediate data page of each block is recorded by creating a writing time record table In addition, the first threshold value and the second threshold value are used to select the blocks that need to perform the expired block recycling operation, so as to efficiently complete the expired block recycling operation. In addition, by compressing the write time record table, the burden on the memory space of the write time record table can be reduced. The above descriptions are only preferred embodiments of the present invention, and all equivalent changes and modifications made according to the scope of the patent application of the present invention shall fall within the scope of the present invention.

100: Memory Device 110: Flash memory controller 112: Microprocessor 112C: Code 112M: read-only memory 114: Control logic 116: Buffer memory 118: Interface logic 120: Flash memory module 130: Main unit 132: Encoder 134: decoder 140: Dynamic random access memory 300~308: Steps 500: Write time record table 600~608: Steps 700~714: Steps 800: Write time record table after compression B1, B2, B200, B201, B202: Blocks BL1, BL2, BL3: bit lines P1~P256: Information page T1_1, T1_M, T2_1, T2_M: Time information WL0~WL2, WL4~WL6: word lines

FIG. 1 is a schematic diagram of a memory device according to an embodiment of the present invention. FIG. 2 is a schematic diagram of a block in a flash memory module according to an embodiment of the present invention. FIG. 3 is a flow chart of establishing a writing time record table according to an embodiment of the present invention. FIG. 4 shows a schematic diagram of writing time information in a block. FIG. 5 is a schematic diagram of a writing time record table according to an embodiment of the present invention. FIG. 6 shows a flow chart of creating a writing time record table in the DRAM after the memory device according to an embodiment of the present invention is powered on. FIG. 7 is a flowchart of an expired block recovery operation according to an embodiment of the present invention. Figure 8 is a schematic diagram of the post-compression write time record table.

100: Memory Device 110: Flash memory controller 112: Microprocessor 112C: Code 112M: read-only memory 114: Control logic 116: Buffer memory 118: Interface logic 120: Flash memory module 130: Main unit 132: Encoder 134: decoder 140: Dynamic random access memory

Claims (9)

A control method applied to a flash memory controller, wherein the flash memory controller is used to access a flash memory module, and the flash memory module is a three-dimensional flash memory (3D NAND-type flash) module, the flash memory module includes a plurality of flash memory chips, each flash memory chip includes a plurality of blocks, and each block includes a plurality of data pages; Each block includes a plurality of word lines located on a plurality of different planes and a plurality of floating gate transistors controlled by the bit lines, and the floating gate transistors on each word line constitute the plurality of data pages at least one data page in ; and the control method includes: When data is written to a first data page of any block of the flash memory module, recording a first time in the first data page; When data is written to at least one intermediate data page of any block of the flash memory module, recording a second time in the at least one intermediate data page; Create a write time record table, wherein the write time record table records the block number of the block in which data is written in the flash memory module and the corresponding first time, or records the flash memory module. The block number of the block in which data is written in the flash memory module and the corresponding first time and the second time; Referring to the write time record table to determine whether the first time of a block in the flash memory module is earlier than a first threshold, if there is at least one first block in the flash memory module If the first time is earlier than the first threshold, the at least one first block is recorded in an expired block table; Referencing the write time record table to determine whether the second time of the block in the flash memory module is earlier than a second threshold value, if there is at least one second block in the flash memory module If the second time is earlier than the second threshold, the at least one second block is recorded in the expired block table; and Perform an expired block recovery operation according to the at least one first block and the at least one second block recorded in the expired block table, so as to sequentially order the at least one first block and the at least one second block The valid data within is moved to at least one blank block. The control method as described in item 1 of the claimed scope, wherein the time indicated by the second threshold value is later than the time indicated by the first threshold value. The control method as described in claim 1 or 2 of the claimed scope, wherein the first threshold value is determined according to the current time when the control method is executed. A flash memory controller, wherein the flash memory controller is used to access a flash memory module, the flash memory module is a three-dimensional flash memory (3D NAND-type flash memory) ) module, the flash memory module includes a plurality of flash memory chips, each flash memory chip includes a plurality of blocks, and each block includes a plurality of data pages; each block It includes a plurality of floating gate transistors controlled by a plurality of word lines and bit lines respectively located on a plurality of different planes, and the floating gate transistor on each word line constitutes at least one of the plurality of data pages. data page; and the flash controller contains: a ROM, used to store a code; a microprocessor for executing the code to control access to the flash memory module; and a buffer memory; When the microprocessor writes data into a first data page of any block of the flash memory module, a first time is recorded in the first data page; when the microprocessor When writing data into at least one intermediate data page of any block of the flash memory module, a second time is recorded in the at least one intermediate data page; the microprocessor also establishes a writing time record table , wherein the write time record table records the block number of the block in which the data is written in the flash memory module and the corresponding first time, or records that the flash memory module has The block number of the block in which the data is written and the corresponding first time and the second time; Wherein the microprocessor refers to the writing time record table to determine whether the first time of the block in the flash memory module is earlier than a first threshold value, if there is at least one block in the flash memory module When the first time of a first block is earlier than the first threshold, the at least one first block is recorded in an expired block table; the microprocessor refers to the writing time record table to determine the fast block Whether the second time of a block in the flash memory module is earlier than a second threshold, if the second time of at least one second block in the flash memory module is earlier than the second threshold value, record the at least one second block in the expired block table; and perform an expired block recycling operation according to the at least one first block and the at least one second block recorded in the expired block table , so as to sequentially move the valid data in the at least one first block and the at least one second block to at least one blank block. The flash memory controller as described in claim 4, wherein the time indicated by the second threshold value is later than the time indicated by the first threshold value. The flash memory controller as described in claim 4 or 5, wherein the first threshold value is determined according to the current time when the control method is executed. A memory device comprising: A flash memory module, wherein the flash memory module is a three-dimensional flash memory (3D NAND-type flash) module, and the flash memory module includes a plurality of flash memory chips , each flash memory chip contains multiple blocks, each block contains multiple data pages; each block contains multiple word lines and bit lines located in multiple different planes to control a plurality of floating gate transistors, and the floating gate transistors on each word line constitute at least one data page of the plurality of data pages; and a flash memory controller for accessing the flash memory module; Wherein, when the flash memory controller writes data into a first data page of any block of the flash memory module, a first time is recorded in the first data page; when the When the flash memory controller writes data to at least one intermediate data page of any block of the flash memory module, a second time is recorded in the at least one intermediate data page; the flash memory control The device also establishes a write time record table, wherein the write time record table records the block number of the block in which data is written in the flash memory module and the corresponding first time, or records The flash memory module has the block number of the block in which the data is written and the corresponding first time and the second time; Wherein the flash memory controller refers to the write time record table to determine whether the first time of the block in the flash memory module is earlier than a first threshold value, if the flash memory module is the first time If the first time of at least one first block is earlier than the first threshold value, the at least one first block is recorded in an expired block table; the flash memory controller refers to the writing time a record table to determine whether the second time of the block in the flash memory module is earlier than a second threshold, if the second time of the at least one second block in the flash memory module is earlier than the second threshold, record the at least one second block in the expired block table; and record the at least one first block and the at least one second block according to the expired block table An expired block recovery operation is performed to sequentially move the valid data in the at least one first block and the at least one second block to at least one blank block. The memory device as described in claim 7, wherein the time indicated by the second threshold value is later than the time indicated by the first threshold value. The memory device as described in claim 7 or 8, wherein the first threshold value is determined according to the current time when the control method is executed.

Images