TWI851591B - Dielectric passivation for layered structures - Google Patents

Abstract

A passivated semiconductor device structure includes a III-nitride structure and a passivation layer. The III- nitride structure includes a high electron mobility transistor (HEMT). The passivation layer includes a dielectric, which is formed over the structure to provide passivation and forms an interface with the structure. The interface provides a transition between the structure and the dielectric having a thickness of at least two atomic layers. The interface also has a characteristic density of interface states less than a reference density of interface states that corresponds to a thickness of at most one atomic layer. The transition, which constitutes a rough interface, allows a relatively low density of interface states, and thus improves high-frequency performance of the device structure.

Description

Dielectric passivation of layered structures

The present invention relates to a semiconductor manufacturing process.

Common dielectric formation methods include thermal oxidation, sputtering, and chemical vapor deposition. Dielectrics formed using these methods are generally high material density, high resistivity, and are naturally compatible with the underlying semiconductor structure and metal contacts. Silicon dioxide is the most common dielectric in silicon-based electronic devices. It is very compatible with silicon, but has a low dielectric constant and poor compatibility with other semiconductors in the group III nitride class.

As the device's high-frequency characteristics develop, the size of the device structure has been significantly reduced, allowing the device's active layer to be closer to the dielectric layer. Once the dielectric layer is adjacent to the active layer, when the device is operated at high frequencies, the interface defects between the dielectric and the semiconductor must be in a low density state. These defects may form interface energy states, thereby generating parasitic charges or capturing existing charge carriers, causing the device to operate slower. Recently proposed methods for improving the dielectric-semiconductor interface are to first perform chemical cleaning and plasma treatment on the semiconductor surface, and then perform dielectric deposition; another method is to perform semiconductor and dielectric deposition in the same reaction chamber (called in-situ deposition), that is, semiconductor deposition is performed first, and then dielectric deposition is performed immediately, so that the semiconductor is not exposed to the air, and surface contamination and the formation of harmful native oxides are avoided. However, due to the excessive stress and chemical mismatch between the two adjacent materials, there may still be some defects and related interface energy states at the dielectric-semiconductor interface formed in situ.

The present invention relates to a passivated semiconductor device structure. The device structure includes a group III nitride high electron mobility transistor (HEMT) structure and a dielectric layer disposed on the structure for passivation. The interface between the dielectric layer and the structure includes a transition layer having a thickness of at least two atomic layers. The interface energy state density of the interface is lower than a reference interface energy state density of at most one atomic layer thickness. In some embodiments, the thickness of the interface is at least equal to 0.5 nanometers. In another example, the interface energy state density is at most 1×10 ¹¹ cm ^-2 .

In some embodiments, a preparation layer is disposed on the group III nitride structure to provide the surface roughness required by the dielectric layer. In such an embodiment, the interface formed by the preparation layer and the dielectric layer has a thickness of at least two atomic layers, and its interface energy state density is lower than the interface energy state density of at most one atomic layer thickness.

100, 200, 300, 500: Layered structure

102, 202, 302, 502: Group III nitride structures

104, 204, 304, 504: passivation layer

110, 210, 503: Rough interface

203:Preparation layer

303: Smooth interface

350, 550: Structure diagram

400: Side-section transverse electromagnetic wave (TEM) image

700, 800: Process

704, 706, 804, 805, 806: Steps

More than one embodiment of the present invention is described in detail with reference to the following drawings. The drawings are provided for illustrative purposes only and are used to depict typical or exemplary embodiments to facilitate understanding of the concepts of the present invention, but should not be considered to limit the breadth, scope or applicability of these concepts. It should be noted that for the sake of clarity and ease of illustration, these drawings do not need to be drawn to scale.

FIG1 shows a side cross-sectional view of an exemplary layered structure in an embodiment of the present invention, wherein the passivation layer of the layered structure is disposed on the group III nitride structure, and a rough interface is disposed between the two; FIG2 shows a side cross-sectional view of an exemplary layered structure in an embodiment of the present invention, wherein the passivation layer of the layered structure is disposed on the prepared layer, and a rough interface is disposed between the two; FIG3 shows a side cross-sectional TEM image of a layered structure containing a smooth interface, and a diagram corresponding to the layered structure; FIG4 shows the side cross-sectional view of the layered structure in different 400 of the capacitance-voltage characteristic obtained by measuring the layered structure of FIG. 3 at different frequencies; FIG. 5 shows a side cross-sectional TEM image of a layered structure containing a rough interface in some embodiments of the present invention; FIG. 6 shows a capacitance-voltage characteristic image obtained by measuring the layered structure of FIG. 5 at different frequencies in some embodiments of the present invention; FIG. 7 is a flow chart of an exemplary process for manufacturing a layered structure in some embodiments of the present invention; and FIG. 8 is a flow chart of an exemplary process for manufacturing a layered structure containing an intermediate preparatory layer in some embodiments of the present invention.

The present invention provides an improved dielectric passivation layer. In some embodiments, the present invention provides an improved passivated III-nitride high electron mobility transistor (HEMT) structure and a method of forming a passivated multilayer by providing a rough interface between the passivation layer and the top layer of the III-nitride HEMT structure. In one exemplary embodiment, the passivation layer includes silicon nitride (SiN). In another embodiment, the silicon nitride can be deposited in situ in the same reaction chamber as that used for depositing the III-nitride HEMT structure below. Other exemplary dielectric materials include aluminum silicon nitride, silicon dioxide, aluminum oxide, and benzene dioxide.

FIG. 1 shows a side cross-sectional view of an exemplary layered structure 100 in an embodiment of the present invention, wherein a passivation layer 104 of the layered structure 100 is disposed on a III-nitride structure 102, with a rough interface 110 disposed therebetween. The III-nitride structure 102 containing a HEMT structure can be disposed on a suitable substrate, such as gallium nitride, silicon carbide, sapphire, silicon, or any other suitable wafer. The topmost layer of the III-nitride structure is a material such as gallium nitride, aluminum nitride, aluminum gallium nitride, and indium aluminum gallium nitride. The passivation layer 104 containing a dielectric material is disposed on the III-nitride structure 102, with an interface 110 formed therebetween. The interface 110 is rough, a transition layer between the III-nitride structure 102 and the passivation layer 104, and its width exceeds one atomic layer. "Rough" or "roughness" refers to the structural deviation distance perpendicular to the interface plane between the III-nitride structure 102 and the passivation layer 104, and the distance may be a distance of multiple atomic layers or the distance occupied by the transition layer. In contrast, a "smooth" interface is a steep transition layer, that is, the structural deviation from the interface plane is almost zero. Such a smooth interface may induce interface stress and increase the interface energy state density.

FIG. 2 shows a side cross-sectional view of an exemplary layered structure 200 in an embodiment of the present invention, wherein a passivation layer 204 of the layered structure 200 is disposed on a preparation layer 203 with a rough interface 210 disposed therebetween. The III-nitride structure 202 containing a HEMT structure may be disposed on a suitable substrate, such as gallium nitride, silicon carbide, sapphire or a silicon wafer. The preparation layer 203 is disposed on the III-nitride structure 202 to affect the roughness of the subsequently disposed passivation layer 204. The passivation layer 204 containing a dielectric material is disposed on the preparation layer 203 with an interface 210 formed therebetween. The interface 210 is rough and is a transition layer between the preparation layer 203 and the passivation layer 204, and its width exceeds one atomic layer.

As shown in Figures 3 to 6, a passivation layered structure with a relatively rough interface between the passivation layer and the underlying semiconductor structure will reduce the interface energy state density.

FIG3 shows a side cross-sectional TEM image of a layered structure 300 including a smooth interface 303, and a structural diagram 350 corresponding to the layered structure 300. The silicon nitride passivation layer 304 of the layered structure 300 is disposed on the group III nitride structure 302, and a smooth interface 303 is disposed between the two. The smooth interface 303 is a steep transition layer between a semiconductor structure (e.g., the group III nitride structure 302) and a dielectric layer (e.g., the silicon nitride passivation layer 304), and the width of the transition layer is about one atomic layer and the thickness is 0.2 to 0.3 nanometers. As shown in FIG3, the smooth interface 303 does not have any discernible undulations.

In the exemplary embodiment, the top layer (e.g., passivation layer 304) of the structure diagram 350 is disposed on the bottom layer (e.g., group III nitride structure 302), and a relatively smooth interface (e.g., smooth interface 303) is disposed between the two. The exemplary components shown by the circles in the structure diagram 350 may represent an atomic layer or an atomic group layer (e.g., different circles represent different layers of components). As shown in the structure diagram 350, the thickness of the smooth interface 303 is less than about one atomic layer.

FIG4 shows the capacitance-voltage characteristic diagram obtained by measuring the layered structure 300 of FIG3 at different frequencies, including the data of the frequency-dispersed capacitance-voltage (CV) characteristic. The frequency-dispersed CV measurement value can describe the characteristics of the interface energy state of the semiconductor structure. The dispersion of the CV characteristics captured at different frequencies is related to the interface energy state, and the degree of dispersion is related to the interface energy state density (for example, the greater the dispersion, the greater the interface energy state). As shown in FIG4, the greater the dispersion of the CV characteristics of the passivated structure (for example, the layered structure 300), the higher the interface energy state density. The interface energy state density of the layered structure 300 is estimated to be above 1×10 ¹² cm ^-2 .

FIG5 shows a side cross-sectional TEM image of a layered structure 500 including a rough interface 503 in some embodiments of the present invention. The silicon nitride passivation layer 504 of the layered structure 500 is disposed on the group III nitride structure 502, and a rough interface 503 is disposed between the two. The rough interface 503 is a surface gradient transition layer between the semiconductor structure (e.g., the group III nitride structure 502) and the dielectric layer (e.g., the silicon nitride passivation layer 504), which is formed due to the fluctuation of the atomic layer adjacent to the interface plane (e.g., where the rough interface 503 is disposed), and the fluctuation state is uniformly distributed in the interface plane and the fluctuation height is random. As shown in FIG. 5 , the thickness of the transition layer of the exemplary embodiment (e.g., interface roughness) is about 2 to 3 atomic layers, or about 0.5 to 0.7 nanometers. The interface roughness of other exemplary structures and applications of the present invention may be greater.

In the exemplary embodiment, the top layer (e.g., passivation layer 504) of the structure diagram 550 is disposed on the bottom layer (e.g., group III nitride structure 502), and a relatively rough interface (e.g., rough interface 503) is disposed between the two. The exemplary components shown by the circles in the structure diagram 550 may represent an atomic layer or an atomic group layer (e.g., different circles represent different layers of components). As shown in the structure diagram 550, the thickness of the rough interface 503 is about one atomic layer or more.

FIG6 shows the capacitance-voltage characteristic diagram obtained by measuring the layered structure 500 of FIG5 at different frequencies in some embodiments of the present invention. As shown in FIG6, the CV characteristic dispersion of the passivated structure (such as the layered structure 500) containing the rough interface 503 is smaller, which means that the interface energy state density is lower. The interface energy state density of the layered structure 500 is estimated to be less than 1×10 ¹¹ cm ^-2 .

FIG. 7 is a flow chart of an exemplary process 700 for fabricating a layered structure in some embodiments of the present invention. Process 700 includes steps of providing a dielectric passivation layer, a group III nitride structure, and a rough dielectric-semiconductor interface therebetween, wherein the passivation layer is directly deposited on the semiconductor structure, and the rough interface is formed during the dielectric deposition.

In some embodiments, a substrate is loaded into a reaction chamber suitable for placing a III-nitride structure on a substrate. The substrate may include gallium nitride, silicon carbide, sapphire, silicon, or any other suitable substrate having a predetermined crystal orientation. In step 704, the III-nitride structure is placed on the substrate in a reaction chamber. In some embodiments, the III-nitride structure (e.g., a HEMT structure) includes one or more epitaxial layers disposed on the substrate. The deposition conditions of the III-nitride structure are set to form a smooth interface between the structural layers, which is required for high device performance. The top layer of the III-nitride structure may also include a smooth surface, and then a dielectric is deposited thereon.

In step 706, a dielectric passivation layer is disposed on the group III nitride structure with a rough dielectric-semiconductor interface between them. In some embodiments, step 706 is an ex-situ deposition, that is, the deposition of the dielectric passivation layer is performed in a different reaction chamber from step 704. In some embodiments, step 706 is an in-situ deposition, that is, the deposition of the dielectric passivation layer is performed in metal organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE) or other suitable reaction chambers. Step 706 provides a dielectric layer with a thickness. In some embodiments, the thickness of the transition layer at the interface is at least equal to 0.5 nanometers and less than the thickness of the dielectric layer.

In an exemplary embodiment, a silicon nitride layer may be formed in step 706 using chemical precursors (e.g., silane and ammonia, disilane and ammonia, any other suitable precursors, or combinations thereof), wherein the ammonia-silane, or disilane, or nitrogen-silicon molar flow ratio may be in the range of 50 to 3000. The thickness of the passivation layer provided in step 706 may be in the range of 1 to 1000 nanometers. If the growth conditions in process 700 are appropriate, such as in-situ silicon nitride deposition, using a high growth temperature (e.g., above about 1000°C) and a low nitrogen source-to-silicon source ratio (e.g., low nitrogen source flow rate) of less than about 300, then during the dielectric deposition in step 706, interface roughness will be generated between the passivation layer and the III-nitride structure. In the illustrative case, the layered structure 100 of FIG. 1 can be formed using process 700.

In some embodiments, after passivation (e.g., the dielectric layer is provided in step 706), the passivated semiconductor structure is removed from the reaction chamber. In some embodiments, the passivated structure may be moved to a metrology or other process to verify that the structure is operating as desired.

FIG8 is a flowchart of an exemplary process 800 for manufacturing a layered structure including an intermediate preparation layer in some embodiments of the present invention. Process 800 includes steps of providing a dielectric passivation layer, a group III nitride structure, and a rough dielectric-semiconductor interface therebetween, wherein the passivation layer is deposited on a preparation layer (i.e., the intermediate preparation layer) above the semiconductor structure, and the rough interface is formed during the formation of the preparation layer and the subsequent dielectric deposition.

In some embodiments, the substrate is loaded into a reaction chamber suitable for placing a Group III nitride structure on the substrate. In step 804, the Group III nitride structure is placed on the substrate in the reaction chamber.

In step 805, a preparation layer is disposed on the group III nitride structure, and interface roughness is generated or enhanced due to the presence of the preparation semiconductor layer. The preparation layer may include a group III nitride containing weak chemical bonds. In some embodiments, a rough surface is generated at the interface (e.g., outer surface) of the preparation layer-group III nitride structure during the formation of the preparation layer. In some embodiments, roughness is generated at the interface (e.g., outer surface) of the preparation layer-group III nitride structure during the dielectric deposition of step 806. The preparation layer material is, for example, indium nitride, gallium nitride, aluminum gallium nitride, indium aluminum gallium nitride, or other suitable materials, and the thickness of the preparation layer in some embodiments is greater than 0.5 nanometers. In some embodiments, the interface between the underlying III-nitride structure and the preparation layer is smooth (e.g., the inner surface of the preparation layer). The rough outer surface of the preparation layer is used as a template for subsequent dielectric deposition, thereby forming a rough semiconductor-dielectric interface with an intermediate preparation layer in between.

In step 806, a dielectric passivation layer is disposed on the prepared layer with a rough interface between them. In some embodiments, step 806 is non-in-situ deposition, that is, the deposition of the dielectric passivation layer is performed in a different reaction chamber from step 804. In some embodiments, step 806 is in-situ deposition, that is, the deposition of the dielectric passivation layer is performed in metal organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE) or other suitable reaction chambers. Step 806 sets a dielectric layer with a thickness. In some embodiments, the thickness of the transition layer at the interface is at least equal to 0.5 nanometers and less than the thickness of the dielectric layer.

In the illustrative examples of processes 700 and 800, the passivation layer can be deposited directly on the III-nitride structure or a pre-layer grown on the III-nitride structure. The dielectric-semiconductor interface roughness (thickness scale) is 0.5 nanometers or more and is uniformly distributed in the interface plane. In some embodiments, the roughness of the dielectric-III-nitride interface reduces interface stress, stress-induced interface energy state density, or both. When the interface energy state density is low, the III-nitride structure and related devices can have high efficiency characteristics when operating at high frequencies. Therefore, improving dielectric passivation can improve high-frequency device operation.

The growth and/or deposition methods mentioned in this specification may be one or more of chemical vapor deposition (CVD), metal organic chemical vapor deposition (MOCVD), metal organic vapor phase epitaxy (OMVPE), atomic layer deposition (ALD), molecular beam epitaxy (MBE), halogenide vapor phase epitaxy (HVPE), pulsed laser deposition (PLD) and/or physical vapor deposition (PVD).

The layer mentioned in this specification refers to a material with substantially uniform thickness covering a surface. The layer can be continuous or discontinuous (i.e., there are gaps between material regions), that is, the layer can completely or partially cover the surface, or be divided into discrete regions that collectively define the layer (i.e., regions formed using selective area epitaxy).

Monolithic integration refers to the process usually formed by layer deposition on the surface of a substrate.

Disposed means "present on" or "located on" an underlying material or layer. Such a layer may include intermediate layers, such as transition layers, required to ensure a suitable surface. For example, if a material is described as being "disposed on" or "located on" a substrate, it may mean that (1) the material is in intimate contact with the substrate; or (2) the material is in contact with one or more transition layers on the substrate.

Single crystal refers to a crystal structure that essentially contains only one unit lattice. However, a single crystal layer may have some crystal defects, such as stacking layer defects, dislocations or other common crystal defects.

Single crystal means that the crystal structure essentially contains only one unit lattice structure, and the unit lattice essentially contains only one orientation. In other words, single crystal is not a twin crystal or an anti-phase crystal.

Single phase means that the crystal structure is single crystal and single crystal.

Substrate refers to a material on which a deposited layer can be placed. Exemplary substrates include, but are not limited to: bulk gallium nitride wafers, bulk silicon carbide wafers, bulk sapphire wafers, bulk germanium wafers, bulk silicon wafers, where the wafers include a single crystal material of uniform thickness; composite wafers such as silicon-insulating wafers, where the composite wafers are sequentially provided with a silicon layer, a silicon dioxide layer, and a bulk silicon processing wafer from top to bottom; or porous germanium, germanium coated on oxide and silicon, germanium coated on silicon, patterned germanium, germanium tin coated on germanium, etc.; or any other material used as a base layer, on or in which a device is provided. Other exemplary materials suitable for use as substrate layers and bulk substrates include, but are not limited to: aluminum oxide, gallium arsenide, indium phosphide, silicon dioxide, borosilicate glass, and pyres glass. The substrate can be a single wafer or have multiple sub-layers. Specifically, the substrate (e.g., silicon, germanium, etc.) can include multiple discontinuous porous portions of varying density that can be horizontally distributed or vertically layered.

Deviation substrate refers to the substrate surface crystal structure orientation, and there is an angle deviation between the substrate crystal structure orientation. For example, 6° deviation <100> silicon wafer means that there is a 6° deviation between the <100> silicon wafer orientation and another major crystal orientation such as <110>. Usually the deviation is up to about 20°, but not necessarily. Unless otherwise specified, "deviation substrate" includes any deviation wafer of major crystal orientation. That is, <111> wafer will deviate in the <011> direction, <100> wafer will deviate in the <110> direction, and <011> wafer will deviate in the <001> direction.

Semiconductor refers to any solid substance whose electrical conductivity is between that of insulators and most metals. An exemplary semiconductor layer comprises silicon. A semiconductor layer may be a single wafer or may have multiple sub-layers. Specifically, a silicon semiconductor layer may comprise multiple discrete porous portions of varying density that may be arranged horizontally or vertically.

When the first layer is described in this specification as being "configured on", "located on", "formed overlying" or "covering" the second layer, the first layer is adjacent to the second layer, or there is one or more intermediate layers between the first layer and the second layer. If the first layer is described as being "directly located on" or "directly covering" the second layer or substrate, the first layer is adjacent to the second layer without an intermediate layer, except for an intermediate alloy layer disposed therebetween for mixing the first layer with the second layer or substrate. In addition, if the first layer is described as being "located on", "covering" or "directly located on" or "directly covering" the second layer or substrate, the first layer may cover the entire second layer or substrate in whole or in part.

During layer growth, the substrate is placed on a substrate support, so the top surface or upper surface refers to the substrate or layer surface farthest from the substrate support, and the bottom surface or lower surface is the substrate or layer surface closest to the substrate support. Any structure mentioned in this specification may be part of a larger structure and have additional layers above and/or below the substrate. For clarity, these additional layers may be omitted from the drawings of this specification, although they may be part of the disclosed structure. In addition, although not shown in the figure, the structure depicted may be multiple.

It is obvious from the above description that various technologies can be used to implement the concepts mentioned in this specification without departing from the scope of this disclosure. The embodiments mentioned should be regarded as illustrative rather than limiting implementations. It should be understood that the technologies and structures mentioned in this specification are not limited to the specific examples described in this specification, and can be implemented in other examples without departing from the scope of this disclosure. Similarly, although the operating steps described in the attached figures have a specific order, it should be understood that it is not necessary to implement the operating steps in accordance with the specific order or sequential order shown, or to perform all the described operating steps, in order to achieve the desired results.

800:Process

804, 805, 806: Steps

Claims (20)

A passivated semiconductor device structure includes: a group III nitride high electron mobility transistor (HEMT) structure; and a dielectric layer disposed on the HEMT structure for passivation and forming a rough interface with the HEMT structure, wherein: the rough interface includes a rough transition layer having a thickness of at least two atomic layers and having a surface roughness spanning at least two atomic layers, and the rough interface includes interface energy states, wherein a density of the interface energy states is lower than a reference density of interface energy states of a smooth interface with a thickness of at most one atomic layer. A passivated semiconductor device structure as claimed in claim 1, wherein the dielectric layer comprises a material component element comprising silicon nitride, silicon aluminum nitride, silicon dioxide, aluminum oxide and aluminum dioxide. A passivated semiconductor device structure as claimed in claim 1, wherein the dielectric layer is provided using an in-situ deposition technique. A passivated semiconductor device structure as claimed in claim 1, wherein the dielectric layer comprises a thickness ranging from 1 to 1000 nanometers. A passivated semiconductor device structure as claimed in claim 1, wherein the dielectric layer comprises a thickness, and the thickness of the rough transition layer is at least equal to 0.5 nanometers and less than the thickness of the dielectric layer. A passivated semiconductor device structure as claimed in claim 1, wherein the rough transition layer is located in an interface plane, and wherein the thickness of the rough transition layer is substantially uniformly distributed in the interface plane. The passivated semiconductor device structure of claim 1, wherein the interface energy state density is at most 1×10 ¹¹ cm ^-2 . A passivated semiconductor device structure as claimed in claim 1, wherein the dielectric layer is formed by directly depositing on the HEMT structure. A passivated semiconductor device structure as claimed in claim 1, wherein the HEMT structure includes a top layer located at the interface, wherein the top layer includes a material composition element comprising gallium nitride, aluminum nitride, aluminum gallium nitride and indium aluminum gallium nitride. A passivated semiconductor device structure as claimed in claim 1, wherein: the HEMT structure further includes a preparatory layer covering the group III nitride HEMT structure, the dielectric layer is formed by depositing and covering the preparatory layer, and the preparatory layer and the dielectric layer form the rough interface. A passivated semiconductor device structure as claimed in claim 10, wherein the preparation layer comprises a material component element comprising a group III nitride semiconductor, indium nitride, indium gallium nitride, indium aluminum nitride, indium aluminum gallium nitride and gallium nitride. A passivated semiconductor device structure as claimed in claim 10, wherein the preparation layer provides a rough transition at the rough interface. A passivated semiconductor device structure as claimed in claim 10, wherein a thickness of the preparation layer is at least equal to 0.5 nanometers. A passivated semiconductor device structure includes: a III-nitride high electron mobility transistor (HEMT) structure; a preparatory layer, which is arranged to cover the III-nitride HEMT structure and is configured to provide surface roughness; and a dielectric layer, which is arranged to cover the preparatory layer, is used for passivation, and forms an interface between the HEMT structure, wherein: the preparatory layer and the dielectric layer form a rough interface, The rough interface includes a rough transition layer with a thickness of at least two atomic layers and has a surface roughness spanning at least two atomic layers, and the rough interface includes interface energy states, wherein a density of the interface energy states is lower than a reference density of interface energy states of a smooth interface with a thickness of at most one atomic layer. A passivated semiconductor device structure as claimed in claim 14, wherein the dielectric layer comprises a thickness, and the thickness of the rough transition layer is at least equal to 0.5 nanometers and less than the thickness of the dielectric layer. The passivated semiconductor device structure of claim 14, wherein the interface energy state density is at most 1×10 ¹¹ cm ^-2 . A method for manufacturing a passivated semiconductor device structure comprises the steps of: providing a structure including a group III nitride high electron mobility transistor (HEMT) structure; and providing a dielectric layer covering the structure for passivation and forming a rough interface with the group III nitride HEMT structure, wherein: the rough interface includes a rough transition layer having a thickness of at least two atomic layers and having a surface roughness spanning at least two atomic layers, the rough interface includes interface energy states, wherein a density of the interface energy states is lower than a reference density of interface energy states of a smooth interface having a thickness of at most one atomic layer, and the dielectric layer is provided by a direct deposition method. The manufacturing method of the passivated semiconductor device structure of claim 17 further includes the steps of: setting a preparatory layer to cover the group III nitride HEMT structure; and setting the dielectric layer by deposition to cover the preparatory layer, wherein the rough interface is formed between the preparatory layer and the dielectric layer. A method for manufacturing a passivated semiconductor device structure as claimed in claim 17, wherein the step of forming the dielectric layer includes using an in-situ deposition technique. A method for manufacturing a passivated semiconductor device structure as claimed in claim 19, wherein the in-situ deposition technology includes one of metal organic chemical vapor deposition (MOCVD) and molecular beam epitaxy (MBE).

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