TWI850962B - Single chip integrating enhanced aluminum gallium nitride/gallium nitride high electron mobility transistor and low on-voltage diode using regrowth technology and its manufacturing method - Google Patents

Abstract

A single chip and a manufacturing method thereof are provided for integrating an enhanced aluminum gallium nitride/gallium nitride (AlGaN/GaN) high electron mobility transistor and a low on-voltage diode using a regrowth technique. The single chip can be used in a DC/DC boost converter. Furthermore, the present invention mainly etches the original enhanced AlGaN/GaN high electron mobility transistor semiconductor structure to define the transistor region and the diode region, and then performs an etching process, a regrowth process and an electrode layout process, and finally forms an enhanced AlGaN/GaN high electron mobility transistor and a low on-voltage diode in the transistor region and the diode region respectively, so as to complete the production of a single chip integrating an enhanced AlGaN/GaN high electron mobility transistor and a low on-voltage diode using regrowth technology.

Description

Single chip integrating enhanced aluminum gallium nitride/gallium nitride high electron mobility transistor and low on-voltage diode using regrowth technology and its manufacturing method

The present invention relates to a single chip and a manufacturing method thereof that integrates an enhanced aluminum gallium nitride/gallium nitride (AlGaN/GaN) high electron mobility transistor and a low on-voltage diode using a regrowth technique, and in particular to a single chip and a manufacturing method thereof for a DC/DC boost converter.

The inductor of the DC-DC boost converter is mainly used as an energy conversion element for converting magnetic field and electrical energy to each other. When the power switch of the DC-DC boost converter is turned on, the inductor converts the electrical energy into magnetic field energy and stores it temporarily. When the power switch is turned off, the inductor converts the temporarily stored magnetic field energy into electric field energy, and this stored energy will be superimposed with the input voltage, and after filtering by the diode and capacitor of the DC-DC boost converter, a DC voltage can be obtained to provide to the load. Since the output voltage is formed by the superposition of the input voltage and the magnetic field energy of the inductor converted into electrical energy, the output voltage is higher than the input voltage, that is, the boost process is completed.

A power switch is actually a high-power electronic component, and the materials used to make high-power electronic components are mainly silicon (Si), silicon carbide (SiC) and gallium nitride (GaN). The earliest developed components were vertical silicon-based components, which are also the mainstream in the current market. However, due to the inherent disadvantages of silicon materials such as poor heat dissipation, poor collapse electric field and slow carrier movement rate, they cannot be used in high-voltage, high-current high-power components. In addition, because it is not easy to increase the operating frequency of vertically structured silicon-based components, the efficiency of DC-DC converters in current power electronics systems is limited to about 80%.

On the other hand, the mass production maturity of silicon carbide is relatively high, and its thermal conductivity and melting point are excellent, and its collapse electric field is high, so silicon carbide has become one of the main materials used in power components on the market. However, silicon carbide lacks a high polarization effect, so it cannot have a two-dimensional electron gas with a high carrier density. Therefore, the method of manufacturing its components will adopt a method closer to silicon-based power components, so the component area is larger. In addition, the material cost of silicon carbide is expensive, and the cost of manufacturing components is extremely high, so silicon carbide power components are less cost competitive.

Gallium nitride materials have the advantages of high heat resistance, high breakdown voltage, high electron saturation speed and high carrier density generated by excellent polarization effect. The switching rate of components made of them can be increased to the megahertz level, and the conversion and switching efficiency of power electronic systems can be increased to more than 95%. Due to the high current density, the size of components can be greatly reduced. In addition, the price of gallium nitride materials is much cheaper than that of silicon carbide materials. Therefore, the development of components related to gallium nitride materials is currently the main development direction in the market.

For example, the on-resistance of gallium nitride high-speed field-effect transistors is only 2% of that of traditional silicon-based power transistors, making them an excellent choice for future high-speed, high-power switching power supply applications, especially in high-temperature, high-power environments such as power electronics. Their wide bandgap physical properties and higher electron speeds will make power electronics circuits and systems made with this component more reliable and efficient.

In the application of DC-DC boost converters, the traditional gallium nitride switching transistors and high breakdown voltage Schottky diodes are not made in a single chip, but are electrically connected through a cadmium wire. However, the cadmium wire method will make the conversion efficiency lower, so the actual conversion efficiency should be less than 90%, and the device size is relatively large. As for the integrated single-chip gallium nitride switching power supply at home and abroad, there are not many literatures. Related research also generally has technical bottlenecks such as depletion-mode operation of the device and breakdown voltage less than 200V. This operating mode has always been limited by the negative bias of the gate, resulting in a large overall circuit area, reducing its commercial competitiveness.

Based on at least one purpose of the present invention, the present invention provides a single chip integrating an enhanced aluminum gallium nitride/gallium nitride high electron mobility transistor and a low on-voltage diode using a regrowth technology, which includes a buffer layer, a gallium nitride channel layer, a first regrowth barrier layer, a first regrowth p-type cladding layer, a first source, a first drain, a gate electrode, a native barrier layer, a second regrowth barrier layer, a second regrowth p-type cladding layer, a second source, a second drain and an anode electrode. The gallium nitride channel layer is formed on the buffer layer and has a trench to define a transistor region and a diode region on both sides of the trench. Through the re-growth process, a first re-growth barrier layer composed of aluminum gallium nitride material is formed on the gallium nitride channel layer and in the transistor region. The first re-growth p-type cladding layer, the first source and the first drain are insulated from each other and are all located on the first re-growth barrier layer, wherein the first source and the first drain are formed on both sides of the first re-growth p-type cladding layer respectively. The gate electrode is formed on the first re-growth p-type cladding layer. The native barrier layer composed of aluminum gallium nitride material is natively formed on the gallium nitride channel layer and in the diode region. Through the regrowth process, a second regrowth barrier layer made of aluminum gallium nitride material is formed on the native barrier layer and in the diode region. The second regrowth p-type cladding layer, the second source and the second drain are insulated from each other and are all located on the second regrowth barrier layer, wherein the second source and the second drain are formed on both sides of the second regrowth p-type cladding layer respectively. The anode electrode is formed on the first drain, the second drain and the second regrowth p-type cladding layer.

Based on another object of the present invention, the present invention provides a method for manufacturing a single chip integrating an enhanced aluminum gallium nitride/gallium nitride high electron mobility transistor and a low on-voltage diode using a regrowth technique, and the manufacturing method has the following steps: providing a semiconductor structure having an aluminum gallium nitride/gallium nitride high electron mobility transistor, performing a terrace etching on the semiconductor structure, and etching to a portion of the gallium nitride channel layer of the semiconductor structure to form a trench, wherein both sides of the trench define a transistor region and the diode region; etching the transistor region of the semiconductor structure and etching to the gallium nitride channel layer; etching the diode region of the semiconductor structure and etching to the native barrier layer of the semiconductor structure; performing a re-growth process to sequentially form a first re-growth barrier layer and a first re-growth p-type cap layer on the gallium nitride channel layer of the transistor region, and sequentially forming a second re-growth barrier layer and a second re-growth p-type cap layer on the native barrier layer of the diode region; etching the first re-growth p-type cap layer and A second regrown p-type cap layer is formed to expose the first regrown barrier layer on both sides of the first regrown p-type cap layer, and the second regrown barrier layer is exposed on both sides of the second regrown p-type cap layer; a passivated insulating layer is formed to cover the first regrown barrier layer, the first regrown p-type cap layer, the gallium nitride channel layer in the trench, the second regrown barrier layer and the second regrown p-type cap layer, and a portion of the passivated insulating layer is etched to the first regrown barrier layer and the second regrown barrier layer to define the transistor A source region and a drain region of each of the region and the diode region; and a first source and a first drain are formed in the source region and the drain region of the transistor region, respectively, and a second source and a second drain are formed in the source region and the drain region of the diode region, respectively, a gate electrode is formed to cover the first regenerated p-type cladding layer, and an anode electrode is formed to cover the first drain, the second drain and the second regenerated p-type cladding layer; wherein the native barrier layer, the first regenerated barrier layer and the first regenerated p-type cladding layer are composed of aluminum gallium nitride material.

In short, the present invention provides a single chip and a manufacturing method thereof that integrates enhanced AlGaN/GaN high electron mobility transistors and low on-voltage diodes using regrowth technology, which can apply excellent power components and rectifier characteristics to DC-DC converters and realize the solution of integrating enhanced AlGaN/GaN high electron mobility transistors and low on-voltage diodes in a single chip. Overall, in addition to reducing costs and chip area, it can also solve the problems of packaging and mismatch between circuit integration. Furthermore, since the enhanced AlGaN/GaN high electron mobility transistor and the low on-voltage diode do not need to be connected through a nickel wire, the problem of wire bonding loss can also be solved. Therefore, the single chip and manufacturing method of the present invention have great research and commercial development potential.

In order to help the examiner understand the technical features, contents and advantages of the present invention and the effects that can be achieved, the present invention is described in detail as follows with the accompanying drawings and in the form of embodiments. The drawings used therein are only for illustration and auxiliary description, and may not be the true proportions and precise configurations after the implementation of the present invention. Therefore, it should not be interpreted based on the proportions and configurations of the attached drawings to limit the scope of rights of the present invention in actual implementation.

DC-to-DC boost converters are widely used in computers, communications, military and aerospace equipment, and can provide stable and efficient performance. The present invention is to manufacture p-type enhanced AlGaN/GaN high electron mobility transistors and low on-voltage diodes on the existing AlGaN/GaN high electron mobility transistor semiconductor structure through epitaxial structure design and re-growth technology, and the enhanced AlGaN/GaN high electron mobility transistor and low on-voltage diode are integrated into a single chip.

The above-mentioned single chip is to etch the semiconductor structure of the existing AlGaN/GaN high electron mobility transistor in the epitaxial layer of the defined transistor area to the GaN channel layer, and then use digital etching to etch the epitaxial layer of the defined diode area to the AlGaN/GaN barrier layer (that is, the AlN stop layer and the p-type GaN capping layer thereon are etched away), and then proceed The regrowth process uses metal organic chemical vapor deposition (MOCVD) to simultaneously form a regrowth AlGaN barrier layer (whose thickness is, for example, 12 nanometers) and a regrowth p-type GaN cap layer (whose thickness is, for example, 60 nanometers) in the diode region and the transistor region, and then configures the source, drain and electrode to achieve the integration of the enhanced AlGaN/GaN high electron mobility transistor and the low on-voltage diode.

For the enhanced AlGaN/GaN high electron mobility transistor in a single chip, a p-n junction depletion region is formed under the regrown p-type GaN cap layer (used as a p-type gate), so that the channel normally-off characteristic can be achieved, making the enhanced AlGaN/GaN high electron mobility transistor have low on-resistance and good reliability. Since the enhanced AlGaN/GaN high electron mobility transistor operates under a forward voltage, it can avoid negative on-voltage and single voltage supply.

In the diode region, the total thickness of the regrown aluminum gallium nitride barrier layer and the native aluminum gallium nitride barrier layer is, for example, 18 nanometers, so that the critical voltage can be around 0V, and then the gate and drain ohmic metals are short-circuited to form an anode, that is, a low conduction voltage diode is realized in the diode region. The current conduction through the ohmic contact can reduce the conduction voltage and switching loss of the low conduction voltage diode. In addition, the p-n depletion region formed by p-type gallium nitride and aluminum gallium nitride can close the channel, so it can further reduce the leakage current and increase the breakdown voltage of the device.

After explaining the concept of the present invention, the present invention is described in detail with an embodiment. First, please refer to FIG. 7. The semiconductor structure at the bottom of FIG. 7 is the single chip of the present invention that integrates the enhanced AlGaN/GaN high electron mobility transistor and the low on-voltage diode using the regrowth technology. The single chip includes a substrate 11, a buffer layer 12, a gallium nitride channel layer 13a, a first re-growth barrier layer 15d, a first re-growth p-type cladding layer 16f, a first source S1, a first drain D1, a gate electrode E2, a native barrier layer 14b, a second re-growth barrier layer 15c, a second re-growth p-type cladding layer 16e, a second source S2, a second drain D2, an anode electrode E1 and a plurality of passivation insulators M21-M27.

The buffer layer 12 is formed on the substrate 11, and the substrate 11 is a sapphire substrate, a silicon carbide substrate or a QST (Qromis Substrate Technology) substrate, and the present invention is not limited thereto. In some applications, the substrate 11 may be removed when leaving the factory, that is, the single chip may selectively not have the substrate 11. Before the gallium nitride channel layer 13a is grown, a layer of buffer layer 12 is first grown at a low temperature to reduce the adverse effects on crystallinity caused by the difference in lattice constant and thermal expansion coefficient between the substrate 11 and gallium nitride, thereby improving the electrical and optical properties of the gallium nitride channel layer 13a. The buffer layer 12 can be made of aluminum gallium nitride material, but the present invention is not limited thereto.

The gallium nitride channel layer 13a is formed on the buffer layer 12 and has a trench T01 to define a transistor region R1 and a diode region R2 on both sides of the trench T01. Through a re-growth process, a first re-growth barrier layer 15d made of aluminum-gallium nitride material is formed on the gallium nitride channel layer 13a and located in the transistor region R1. The first source S1, the first regrown p-type cap layer 16f and the first drain D1 are insulated from each other by the passivation insulators M22 and M23. The passivation insulators M22, M23, the first source S1, the first regrown p-type cap layer 16f and the first drain D1 are all located on the first regrown barrier layer 15d. The passivation insulator M21 is located between the gallium nitride channel layer 13a. A passivation insulator M21 is formed on one side of the first source S1, the first source S1 and the first drain D1 are formed on both sides of the first regenerated p-type cladding layer 16f, a passivation insulator M22 is provided between the first source S1 and the first regenerated p-type cladding layer 16f, and a passivation insulator M23 is provided between the first drain D1 and the first regenerated p-type cladding layer 16f. A gate electrode E2 is formed on the first regenerated p-type cladding layer 16f.

The native barrier layer 14 made of aluminum-gallium nitride material is natively formed on the gallium nitride channel layer 13a and located in the diode region R2. Through the regrowth process, a second regrowth barrier layer 15c made of aluminum-gallium nitride material is formed on the native barrier layer 14 and located in the diode region R2. The second drain D2, the second regrown p-type cap layer 16e and the second source S2 are insulated from each other by the passivation insulators M25 and M26. The passivation insulators M25, M26, the second drain D2, the second regrown p-type cap layer 16e and the second source S2 are all located on the second regrown barrier layer 15c. The passivation insulator M27 is located between the gallium nitride channel layer 13a. On, the passivation insulating member M27 is located on one side of the second source S1, the second drain D2 and the second source S2 are formed on both sides of the second regenerated p-type cladding layer 16e, respectively, there is a passivation insulating member M25 between the second drain D2 and the second regenerated p-type cladding layer 16e, and there is a passivation insulating member M26 between the second source S2 and the second regenerated p-type cladding layer 16e. The passivation insulating member M24 is located in the trench T01 and on the gallium nitride channel layer 13a, and the passivation insulating member M24 is between the first drain D1 and the second drain D2. The anode electrode E1 is formed on the first drain D1, the passivation insulator M24 in the trench T01, the second drain D2 and the second regrown p-type cladding layer 16e. Thus, a p-type enhanced AlGaN/GaN high electron mobility transistor can be formed in the transistor region R1.

The first regenerated growth barrier layer 15d, the native barrier layer 14, and the second regenerated growth barrier layer 15c use the same aluminum gallium nitride material, which is _{AlxGa1 -xN} , and x is any value from 0.13 to 0.25. The thickness of each of the first regenerated growth p-type cladding layer 16f and the second regenerated growth p-type cladding layer 16e is 10 to 100 nanometers, the thickness of each of the native barrier layer 14, the first regenerated growth barrier layer 15d and the second regenerated growth barrier layer 15c is 1 to 20 nanometers, and the thickness of the gallium nitride channel layer is 100 to 300 nanometers. The first regenerated growth p-type cladding layer 16f and the second regenerated growth p-type cladding layer 16f use the same material, and this material is doped with a concentration of 1 10 ¹⁷ to 1 10 ²¹ cm ^-3 of magnesium. In this way, a low on-voltage diode can be formed in the diode region R2. Preferably, the on-voltage of the low on-voltage diode is greater than 0 volt and less than or equal to 1 volt, and can even be less than or equal to 0.1 volt, but the present invention is not limited thereto.

Please refer to Figures 9 and 10. The enhanced AlGaN/GaN high electron mobility transistor is a normally closed switch. It must be applied with a V _GS voltage greater than 1.7 volts for the enhanced AlGaN/GaN high electron mobility transistor to be turned on. Furthermore, when the V _GS voltage is 0.8 volts and the V _DS voltage is 8 volts, the resistivity of the on-resistance is 14.6 ohm•cm, and when the V _GS voltage is 0, the enhanced AlGaN/GaN high electron mobility transistor must be applied with a V _DS voltage greater than 423 volts for it to be reversely turned on. 11 and 12 , when a forward voltage close to 0V (eg, 0.1V) is applied to the low conduction voltage diode, the low conduction voltage diode will conduct, and when a reverse voltage greater than 606V is applied to the low conduction voltage diode, the low conduction voltage diode will conduct in the reverse direction.

Please refer to FIG8 , which is a schematic circuit diagram of a DC-to-DC boost converter of an embodiment of the present invention. The above-mentioned single chip can be applied to the DC-to-DC boost converter, and the enhanced aluminum gallium nitride/gallium nitride high electron mobility transistor 21 and the low conduction voltage diode 22 are integrated in the above-mentioned single chip, and are electrically connected to the DC-to-DC boost converter through an external inductor L and an external capacitor C is electrically connected to the low conduction voltage diode 22, that is, the DC-to-DC boost converter of FIG8 can be realized.

After explaining the details and applications of the single chip of the embodiment of the present invention, please refer to Figures 1 to 7 to further introduce the manufacturing method of the single chip. In Figure 1, a semiconductor structure with an aluminum gallium nitride/gallium nitride high electron mobility transistor is provided, and the semiconductor structure is subjected to high-table etching, and a portion of the gallium nitride channel layer 13 of the semiconductor structure is etched to form a trench T01, wherein the transistor region R1 and the diode region R2 are defined on both sides of the trench T01.

Furthermore, the semiconductor structure provided is formed by stacking a substrate 11, a buffer layer 12, a gallium nitride channel layer 13, a barrier layer 14, an etch stop layer 15 and a p-type gallium nitride cap layer 16 from bottom to top. The p-type gallium nitride cap layer 16 is used to protect the surface material and has a thickness of 1 to 2 nanometers. The etch stop layer 15 is made of aluminum nitride material and has a thickness of 1 to 2 nanometers and is used as a high selectivity etch stop layer. The barrier layer 14 is made of aluminum gallium nitride material, which is Al _x Ga _1-x N, and x is any value from 0.13 to 0.25. The thickness of the barrier layer 14 is 1 to 20 nanometers, and the thickness of the buffer layer 12 is 1 to 10 micrometers.

After the gallium nitride channel layer 13 is etched on the mesa, a portion of the trench T01 penetrates into the gallium nitride channel layer 13 to form a gallium nitride channel layer 13a. After the trench T01 is formed, a barrier layer 14a, an etch stop layer 15a, and a p-type gallium nitride capping layer 16a are sequentially formed on the gallium nitride channel layer 13a in the transistor region R1; and a native barrier layer 14b, an etch stop layer 15b, and a p-type gallium nitride capping layer 16b are sequentially formed on the gallium nitride channel layer 13a in the diode region R2.

Next, as shown in FIG. 2 , a photoresist PR01 is disposed above the p-type gallium nitride capping layer 16b in the diode region R2, and dry etching is performed to etch the transistor region R1 of the semiconductor structure and etch to the gallium nitride channel layer 13a, that is, the barrier layer 14a, the etching stop layer 15a and the p-type gallium nitride capping layer 16a are removed by dry etching. After the dry etching is completed, the photoresist PR01 is removed.

Afterwards, as shown in FIG. 3 , a photoresist PR02 is placed on the gallium nitride channel layer 13a in the transistor region R1, and the diode region R2 of the semiconductor structure is etched by using an etch stop layer 15b of a high selectivity material and digital etching technology, and the etching is performed to the native barrier layer 14b of the semiconductor structure, that is, the etch stop layer 15b and the p-type gallium nitride cap layer 16b are removed by digital etching. After the digital etching is completed, the photoresist PR02 is removed. Please note that digital etching is not used to limit the present invention, and other etching purposes that can achieve the above purpose can also be used in the present invention.

Then, as shown in FIG. 4 , mask members M01 and M03 are disposed on both sides of the gallium nitride channel layer 13a, and a mask member M02 is disposed on the gallium nitride channel layer 13a in the trench T01, and a re-growth process is performed, for example, by using metal organic chemical vapor deposition (MOCVD) or molecular beam epitaxy (MBE) equipment, so as to sequentially form a first re-growth barrier layer 15d and a first re-growth p-type cap layer 16d on the gallium nitride channel layer 13a in the transistor region R1, and sequentially form a second re-growth barrier layer 15c and a second re-growth p-type cap layer 16c on the native barrier layer 14 in the diode region R2, and then remove the mask members M01 to M03.

The first regeneration barrier layer 15d, the native barrier layer 14, and the second regeneration barrier layer 15c use the same aluminum gallium nitride material, which is _{AlxGa1 -xN} , and x is any value from 0.13 to 0.25. The thickness of each of the first regeneration p-type cladding layer 16f and the second regeneration p-type cladding layer 16e is 10 to 100 nanometers, and the thickness of each of the first regeneration barrier layer 15d and the second regeneration barrier layer 15c is 1 to 20 nanometers. The first regeneration p-type cladding layer 16f and the second regeneration p-type cladding layer 16f use the same material, and this material is doped with a concentration of 1 10 ¹⁷ to 1 10 ²¹ cm ^-3 of magnesium.

Next, as shown in FIG. 5 , a hard mask M11 of silicon nitride material is disposed on the first regrown p-type cladding layer 16d of the transistor region R1 to define the gate region in the transistor region R1, and a hard mask M12 of silicon nitride material is disposed on the second regrown p-type cladding layer 16c of the diode region R2 to define the gate region in the transistor region R1, and etching is performed. After the first regrown p-type cladding layer 16d and the second regrown p-type cladding layer 16c are etched, the first regrown p-type cladding layer 16f and the second regrown p-type cladding layer 16e are formed to expose the first regrown barrier layer 15d on both sides of the first regrown p-type cladding layer 16f and the second regrown barrier layer 15c on both sides of the second regrown p-type cladding layer 16e. After etching, the hard mask members M11 and M12 are removed.

Afterwards, as shown in FIG6 , a passivation insulating layer M2 of silicon nitride material is formed to cover the first regenerated growth barrier layer 15d, the first regenerated growth p-type cap layer 16f, the gallium nitride channel layer 13a in the trench T01, the second regenerated growth barrier layer 15c and the second regenerated growth p-type cap layer 16e, and a portion of the passivation insulating layer M2 is etched to the first regenerated growth barrier layer 15d and the second regenerated growth barrier layer 15c to define the source region and the drain region of each of the transistor region R1 and the diode region R2. After the portion of the passivation insulating layer M2 is etched, a plurality of passivation insulating members M21 to M27 are formed.

Finally, as shown in FIG. 7 , a first source S1 and a first drain D1 are formed in the source region and the drain region of the transistor region R1, respectively, and a second source S2 and a second drain D2 are formed in the source region and the drain region of the diode region R2, respectively. Then, a gate electrode E2 is formed to cover the first regrown p-type cover layer 16f, and an anode electrode E1 is formed to cover the first drain D1, the passivation insulator M24 in the trench T01, the second drain D2 and the second regrown p-type cover layer 16e.

As can be seen from the above description, the embodiment of the present invention provides a single chip and a manufacturing method thereof that integrates an enhanced aluminum gallium nitride/gallium nitride high electron mobility transistor and a low on-voltage diode using a regrowth technique, wherein the single chip is particularly suitable for use in a DC-to-DC boost converter. Since the enhanced AlGaN/GaN high electron mobility transistor and the low on-voltage diode are integrated in a single chip, there is no need to connect the enhanced AlGaN/GaN high electron mobility transistor and the low on-voltage diode through a copper wire, so the conversion efficiency can be increased and the device size can be reduced. Furthermore, the diode has a low on-voltage and a high breakdown voltage, and the AlGaN/GaN high electron mobility transistor is an enhanced type, so the overall surface area is small and commercially competitive. Furthermore, integrating enhanced AlGaN/GaN high electron mobility transistors and low on-voltage diodes into a single chip can avoid packaging and mismatch issues between circuit integration.

The embodiments described above are only for illustrating the technical ideas and features of the present invention, and their purpose is to enable people familiar with this technology to understand the content of the present invention and implement it accordingly. They cannot be used to limit the patent scope of the present invention. In other words, all equivalent changes or modifications made according to the spirit disclosed by the present invention should still be included in the patent scope of the present invention.

11: Substrate 12: Buffer layer 13, 13a: GaN channel layer 14, 14a, 14b: Barrier layer 14b: Native barrier layer 15a, 15b: Etch stop layer 15d: First regrown barrier layer 15c: Second regrown barrier layer 16, 16a, 16b: P-type GaN cap layer 16d, 16f: First regrown p-type cap layer 16c, 16e: Second regrown p-type cap layer 21: Enhanced AlGaN/GaN high electron mobility transistor 22: Low on-voltage diode S1: First source S2: Second source D1: First drain D2: Second drain E1: Anode electrode E2: Gate electrode M21~M27: Passivated insulator T01: Trench R1: Transistor region R2: Diode region PR01, PR02: Photoresist M01~M03: Mask M11, M12: Hard mask M2: Passivated insulator L: Inductor C: Capacitor

The accompanying drawings are provided to enable a person with ordinary knowledge in the art to which the present invention belongs to further understand the present invention, and are incorporated into and constitute a part of the specification of the present invention. The accompanying drawings show exemplary embodiments of the present invention, and are used together with the specification of the present invention to explain the principles of the present invention.

FIG. 1 to FIG. 7 are schematic diagrams of multiple steps of a method for manufacturing a single chip integrating an enhanced AlGaN/GaN high electron mobility transistor and a low on-voltage diode using regrowth technology according to an embodiment of the present invention.

FIG8 is a schematic diagram of an embodiment of the present invention using a single chip integrating an enhanced AlGaN/GaN high electron mobility transistor and a low on-voltage diode using regrowth technology and applied to a DC-to-DC boost converter.

Figures 9 and 10 are respectively schematic diagrams of the V GS and V DS voltage-current curves of the enhanced AlGaN/GaN high electron mobility transistor in a single chip that integrates the enhanced AlGaN/GaN high electron mobility transistor and a low on-voltage _diode using the regrowth technology in an embodiment _of the present invention, and a schematic diagram of the V _DS voltage-current curve when V _GS is 0.

FIG. 11 and FIG. 12 are respectively schematic diagrams of the forward voltage-current curve and the reverse voltage-current curve of the low on-voltage diode in the single chip integrating the enhanced aluminum gallium nitride/gallium nitride high electron mobility transistor and the low on-voltage diode using the regrowth technology in an embodiment of the present invention.

11: Substrate 12: Buffer layer 13a: GaN channel layer 14b: Native barrier layer 15d: First regrown barrier layer 15c: Second regrown barrier layer 16f: First regrown p-type cladding layer 16e: Second regrown p-type cladding layer S1: First source S2: Second source D1: First drain D2: Second drain E1: Anode electrode E2: Gate electrode M21~M27: Passivated insulator T01: Trench R1: Transistor region R2: Diode region

Claims (10)

A single chip using regrowth technology to integrate an enhanced aluminum gallium nitride/gallium nitride high electron mobility transistor and a low on-voltage diode comprises: a buffer layer (12); a gallium nitride channel layer (13a) formed on the buffer layer (12) and having a trench (T01) to define a transistor region (R1) and a diode region (R2) on both sides of the trench (T01); a first regrowth barrier layer (15d) made of an aluminum gallium nitride material; The present invention is characterized in that the present invention is characterized in that the first regrown p-type cap layer (16f), a first source (S1) and a first drain (D1) are insulated from each other and are all located on the first regrown barrier layer (15d), wherein the first source (S1) and the first drain (D1) are respectively formed on two sides of the first regrown p-type cap layer (16f); a gate electrode (16f) is provided on the first regrown p-type cap layer (16f); and a gate electrode (16f) is provided on the first regrown p-type cap layer (16f). a first regrown p-type cap layer (16f); a native barrier layer (14b) formed of the aluminum-gallium nitride material, natively formed on the gallium nitride channel layer (13a) and located in the diode region (R2); a second regrown barrier layer (15c) formed of the aluminum-gallium nitride material, formed on the native barrier layer (14b) through the regrowing process and located in the diode region (R2); a second regrown p-type The capping layer (16e), a second source (S2) and a second drain (D2) are insulated from each other and are all located on the second regeneration barrier layer (15c), wherein the second source (S2) and the second drain (D2) are respectively formed on the two sides of the second regeneration p-type capping layer (16e); and an anode electrode (E2) is formed on the first drain (D1), the second drain (D2) and the second regeneration p-type capping layer (16e). The single chip of enhanced aluminum gallium nitride/gallium nitride high electron mobility transistor and low on-voltage diode integrated by using regrowth technology as described in claim 1 further comprises: a substrate (11), wherein the buffer layer (12) is formed on the substrate (12); a plurality of passivated insulators (M21-M26), wherein a portion of the passivated insulators (M21-M26) is formed on the gallium nitride channel layer (13a), and the passivated insulators (M21-M26) are formed on the gallium nitride channel layer (13a). Another part of the passivated insulating members (M21-M26) is formed on the first regeneration barrier layer (15d) to insulate the first regeneration p-type cap layer (16f), the first source (S1) and the first drain (D1) from each other, and another part of the passivated insulating members (M21-M26) is formed on the second regeneration barrier layer (15c) to insulate the second regeneration p-type cap layer (16e), the second source (S2) and the second drain (D2) from each other. A single chip integrating enhanced aluminum gallium nitride/gallium nitride high electron mobility transistors and low on-voltage diodes using regrowth technology as described in claim 2, wherein the aluminum gallium nitride material is Al _x Ga _1-x N, and x is any value from 0.13 to 0.25, and the substrate (11) is a sapphire substrate, a silicon carbide substrate or a QST (Qromis Substrate Technology) substrate. A single chip integrating an enhanced aluminum gallium nitride/gallium nitride high electron mobility transistor and a low on-voltage diode using a regrowth technique as described in claim 3, wherein the buffer layer (12) has a thickness of 1 to 10 microns, the first regrowth p-type cladding layer (16f) and the second regrowth p-type cladding layer (16e) each have a thickness of 10 to 100 nanometers, the native barrier layer (14b), the first regrowth barrier layer (15d) and the second regrowth barrier layer (15c) each have a thickness of 1 to 20 nanometers, and the gallium nitride channel layer (13a) has a thickness of 100 to 300 nanometers. A single chip integrating an enhanced aluminum gallium nitride/gallium nitride high electron mobility transistor and a low on-voltage diode using a regrowth technique as described in claim 4, wherein each of the first regrowth p-type cladding layer (16f) and the second regrowth p-type cladding layer (16e) is doped with magnesium at a concentration of 1×10 ¹⁷ to 1×10 ²¹ cm ^-3 . A single chip integrating an enhanced aluminum gallium nitride/gallium nitride high electron mobility transistor and a low on-voltage diode using regrowth technology as described in claim 5, wherein a low on-voltage diode formed in the diode region (R2) has a turn-on voltage greater than 0 volts and less than or equal to 1 volt. A method for manufacturing a single chip integrating an enhanced AlGaN/GaN high electron mobility transistor and a low on-voltage diode using a regrowth technique, comprising: providing a semiconductor structure having an AlGaN/GaN high electron mobility transistor, performing a mesa etching on the semiconductor structure, and etching to a GaN through-hole of the semiconductor structure; A portion of the channel layer (13) is formed to form a trench (T01), wherein a transistor region (R1) and a diode region (R2) are defined on both sides of the trench (T01); the transistor region (R1) of the semiconductor structure is etched and is etched to the gallium nitride channel layer (13a); the diode region (R2) of the semiconductor structure is etched Etching is performed to a native barrier layer (14b) of the semiconductor structure; a re-growth process is performed to sequentially form a first re-growth barrier layer (15d) and a first re-growth p-type cap layer (16d) on the gallium nitride channel layer (13) of the transistor region (R1), and a first re-growth p-type cap layer (16d) on the native barrier layer of the diode region (R2). (14b) sequentially forms a second regrowing barrier layer (15c) and a second regrowing p-type cap layer (16c); Etching the first regrowing p-type cap layer (16d) and the second regrowing p-type cap layer (16c) to expose the first regrowing barrier layer (15d) on both sides of the first regrowing p-type cap layer (16d) , and exposing the second regrown p-type cover layer (16c) on both sides of the second regrown growth barrier layer (15c); forming a passivation insulating layer (M2) covering the first regrown growth barrier layer (15d), the first regrown p-type cover layer (16d), the gallium nitride channel layer (13) in the trench (T01), the second regrown growth barrier layer (15c), and the second regrown growth barrier layer (15d). layer (15c) and the second regrown p-type cap layer (16c), and etching a portion of the passivated insulating layer (M2) to the first regrown barrier layer (15d) and the second regrown barrier layer (15c) to define a source region and a drain region of each of the transistor region (R1) and the diode region (R2); and The source region and the drain region of the transistor region (R1) form a first source (S1) and a first drain (D1) respectively, and the source region and the drain region of the diode region (R2) form a second source (S2) and a second drain (D2) respectively, forming a gate electrode (E2) covering the first regrown p-type cover layer (16d ) and forming an anode electrode (E2) covering the first drain (D1), the second drain (D2) and the second regenerated p-type capping layer (16e); wherein the native barrier layer (14b), the first regenerated barrier layer (15d) and the first regenerated p-type capping layer (16d) are composed of an aluminum gallium nitride material. A method for manufacturing a single chip integrating an enhanced aluminum gallium nitride/gallium nitride high electron mobility transistor and a low on-voltage diode using regrowth technology as described in claim 7, wherein the aluminum gallium nitride material is Al _x Ga _1-x N, and x is any value from 0.13 to 0.25, and a substrate (11) of the semiconductor structure is a sapphire substrate, a silicon carbide substrate or a QST (Qromis Substrate Technology) substrate. A method for manufacturing a single chip integrating an enhanced aluminum gallium nitride/gallium nitride high electron mobility transistor and a low on-voltage diode using a regrowth technique as described in claim 7, wherein a buffer layer (12) of the semiconductor structure has a thickness of 1 to 10 microns, a thickness of each of the first regrowth p-type cladding layer (16f) and the second regrowth p-type cladding layer (16e) is 10 to 100 nanometers, a thickness of each of the native barrier layer (14b), the first regrowth barrier layer (15d) and the second regrowth barrier layer (15c) is 1 to 20 nanometers, and a thickness of the gallium nitride channel layer (13a) is 100 to 300 nanometers. A method for manufacturing a single chip integrating an enhanced aluminum gallium nitride/gallium nitride high electron mobility transistor and a low on-voltage diode using a regrowth technique as described in claim 7, wherein each of the first regrowth p-type cladding layer (16f) and the second regrowth p-type cladding layer (16e) is doped with magnesium at a concentration of 1×10 ¹⁷ to 1×10 ²¹ cm ^-3 .