TWI850779B - Modulation device - Google Patents

Abstract

A modulation device including a substrate, a modulation unit, a data line, and a scan line is provided. The modulation unit is disposed on the substrate. The data line is disposed on the substrate and is electrically connected to the modulation unit. The scan line is disposed on the substrate, and has an overlapping region overlapping the data line and a non-overlapping region not overlapping the data line. The overlapping region has a first width along a first direction, and the non-overlapping region has a second width along the first direction, wherein the first width is smaller than the second width.

Description

Modulation device

The present invention relates to a modulation device.

The circuit layout in a large-scale modulation device is relatively complex. Therefore, the coupling between the lines used to transmit different signals will increase the resistance-capacitance loading (RC loading), which will affect the quality of signal transmission and reduce the reliability of the modulation device.

The present disclosure provides a modulation device that can reduce the impedance value and/or capacitance load of a line used to transmit different signals to reduce the resistance and capacitance load.

According to an embodiment of the present disclosure, a modulation device includes a substrate, a modulation unit, a data line, and a scanning line. The modulation unit is disposed on the substrate. The data line is disposed on the substrate and electrically connected to the modulation unit. The scanning line is disposed on the substrate and has an overlapping region overlapping with the data line and a non-overlapping region not overlapping with the data line. In a first direction, the scanning line has a first width in the overlapping region, and has a second width in the non-overlapping region, and the first width is smaller than the second width.

According to an embodiment of the present disclosure, a modulation device includes a substrate, a modulation unit, a data line, and a scan line. The modulation unit is disposed on the substrate. The data line is disposed on the substrate and electrically connected to the modulation unit. The scan line is disposed on the substrate and partially overlaps with the data line. The data line has an overlapping region overlapping with the scan line and a non-overlapping region not overlapping with the scan line. In the second direction, the data line has a third width in the overlapping region, and the data line has a fourth width in the non-overlapping region, and the third width is smaller than the fourth width.

According to an embodiment of the present disclosure, the modulation device includes a substrate, a plurality of modulation units, a data line, and a scanning line. The plurality of modulation units are disposed on the substrate. The data line is disposed on the substrate and electrically connected to at least one of the plurality of modulation units. The scanning line is disposed on the substrate and parallel to the data line.

In order to make the above features and advantages of the present disclosure more clearly understandable, the following is a detailed description of the embodiments with accompanying drawings.

10a, 10b, 10c, 10d, 10e, 10f, 10g, 10h: Modulation device

20: Photosensitive device

100: Modulation unit group

A1-A1’, A2-A2’, B-B’, C-C’, D1-D1’, D2-D2’, E-E’, F-F’: section line

Area1, Area2: Area

AU, MEMS, MEMS1, MEMS2, MEMS3: Modulation unit

BF: Buffer layer

BL: Bias line

C1: first electrode

C1_OP, C2_OP, CE_OP, SL_OP: opening

C1_SLIT, C2_SLIT: narrow slot

C2: Second electrode

CE: Common Electrode

CL, CL1, CL1’, CL2, CL2’: shared wires

CLa, DLa, SLa: Main electrode wires

CLb, DLb, SLb: Auxiliary electrode wires

CL_CS: Electrical connection line segment

CL_ES: Extend line segment

D: Drain

d1: first direction

d2: Second direction

DC: drive circuit

D _CS , D _ES : distance

DL, DL1, DL1’, DL2, DL2’, DL3, DL3’: data line

DL_NOA, SL_NOA: non-overlapping area

DL_OA, SL_OA: Overlapping area

DL_W1: Third width

DL_W2: Fourth width

E1, E2: Electrode

G, G1, G2: Gate

IC: chip

IL0, IL1, IL2, IL3, IL4: Insulation layer

IL1_T:Thickness

IL0_V1, IL0_V2, IL0_V3, IL1_V1, IL1_V3, IL2_V1, IL3_V, IL4_V, V1, V2, VC, VC1, VC2, VD, VD1, VD2, VD3, VS, VS1, VS2: Through hole

M: Conductive layer

ME: Modulation Electrode

n: Looking down

P: Pitch

PAD1, PAD2: pads

PD: Photodiode

PD1, PD3: semiconductor layer

PD2: Photosensitive layer

PS: Photoelectric unit

S: Source

SB: Substrate

SB_S1: First surface

SB_S2: Second surface

SE: semiconductor layer

SL, SL1, SL1’, SL2, SL2’: Scanning lines

SLa: Main electrode line

SLb: Auxiliary electrode wire

SL_W1: First width

SL_W2: Second width

TC: Heat dissipation structure

TFT, TFT’, TFT”: transistor

Figure 1A is a partial top view schematic diagram of the modulation device of the first embodiment of the present disclosure.

FIG1B is a schematic cross-sectional view of an embodiment cut along the section line A1-A1' of FIG1A.

FIG1C is a partial top view schematic diagram of the arrangement relationship between the scan lines and the data lines in the modulation device of an embodiment of the present disclosure.

FIG1D is a partial top view schematic diagram of the arrangement relationship between the scan lines and the data lines in the modulation device of another embodiment of the present disclosure.

FIG. 1E is a schematic cross-sectional view of an embodiment cut along the section line A2-A2' of FIG. 1A .

FIG1F is a schematic cross-sectional view of another embodiment cut along the section line A2-A2' of FIG1A.

FIG1G is a schematic cross-sectional view of another embodiment cut along the section line A2-A2' of FIG1A.

Figure 2A is a partial top view schematic diagram of the modulation device of the second embodiment of the present disclosure.

FIG2B is a schematic cross-sectional view of an embodiment cut along the section line B-B' of FIG2A.

FIG2C is a schematic cross-sectional view of another embodiment cut along the section line B-B' of FIG2A.

FIG3A is a partial top view schematic diagram of the modulation device of the third embodiment of the present disclosure.

FIG3B is a schematic cross-sectional view of an embodiment cut along the section line C-C' of FIG3A.

Figure 4 is a partial top view schematic diagram of the modulation device of the fourth embodiment of the present disclosure.

FIG5A is a partial top view schematic diagram of the modulation device of the fifth embodiment of the present disclosure.

FIG5B is a schematic cross-sectional view of an embodiment cut along the section line D1-D1' of FIG5A.

FIG5C is a schematic cross-sectional view of an embodiment cut along the section line D2-D2' of FIG5A.

FIG5D is a schematic cross-sectional view of another embodiment cut along the section line D2-D2' of FIG5A.

FIG6A is a partial top view schematic diagram of the modulation device of the sixth embodiment of the present disclosure.

FIG6B is a schematic cross-sectional view of an embodiment cut along the section line E-E' of FIG6A.

FIG. 7 is a partial top view schematic diagram of the arrangement relationship between the scanning lines and the common electric lines in the modulation device of an embodiment of the present disclosure.

FIG8A is a partial top view schematic diagram of the modulation device of the seventh embodiment of the present disclosure.

FIG8B is a partial top view schematic diagram of the driving circuit of the modulation device according to FIG8A.

FIG9A is a partial top view schematic diagram of a photosensitive device according to an embodiment of the present disclosure.

FIG9B is a schematic cross-sectional view of an embodiment cut along the section line F-F' of FIG9A.

Figure 10 is a partial top view schematic diagram of the modulation device of the eighth embodiment of the present disclosure.

The present disclosure can be understood by referring to the following detailed description and the accompanying drawings. It should be noted that in order to make it easier for readers to understand and the drawings are concise, the multiple drawings in the present disclosure only depict a portion of the electronic device, and the specific components in the drawings are not drawn according to the actual scale. In addition, the number and size of each component in the figure are only for illustration and are not used to limit the scope of the present disclosure.

Certain terms are used throughout this disclosure and in the patent applications that follow to refer to specific components. It should be understood by those skilled in the art that electronic device manufacturers may refer to the same component by different names. This document does not intend to distinguish between components that have the same function but different names. In the following description and patent applications, the words "include", "contain", "have" and the like are open-ended terms, and therefore should be interpreted as "including but not limited to..." Therefore, when the terms "include", "contain" and/or "have" are used in the description of this disclosure, they specify the existence of corresponding features, regions, steps, operations and/or components, but do not exclude the existence of one or more corresponding features, regions, steps, operations and/or components.

The directional terms mentioned herein, such as "up", "down", "front", "back", "left", "right", etc., are only used with reference to the directions of the accompanying drawings. Therefore, the directional terms used are used for illustration and not for limiting the present disclosure. In the accompanying drawings, each figure depicts the general characteristics of the methods, structures and/or materials used in a particular embodiment. However, these figures should not be interpreted as defining or limiting the scope or nature covered by these embodiments. For example, for the sake of clarity, the relative size, thickness and position of each film layer, region and/or structure may be reduced or enlarged.

When a corresponding component (such as a film layer or region) is referred to as "on another component", it can be directly on the other component, or there can be other components between the two. On the other hand, when a component is referred to as "directly on another component", there is no component between the two. In addition, when a component is referred to as "on another component", the two have a vertical relationship in the top view direction, and this component can be above or below the other component, and this vertical relationship depends on the orientation of the device.

The terms "approximately", "substantially" or "substantially" are generally interpreted as within 10% of a given value or range, or within 5%, 3%, 2%, 1% or 0.5% of a given value or range.

The ordinal numbers used in the specification and patent application, such as "first", "second", etc., are used to modify the components. They do not imply or represent any previous ordinal numbers of the component (or components), nor do they represent the order of one component and another component, or the order of the manufacturing method. The use of these ordinal numbers is only used to make a component with a certain name clearly distinguishable from another component with the same name. The patent application and the specification may not use the same words. Accordingly, the first component in the specification may be the second component in the patent application.

It should be noted that the following embodiments can replace, reorganize, and mix the features of several different embodiments to complete other embodiments without departing from the spirit of the present disclosure. The features of each embodiment can be mixed and matched as long as they do not violate the spirit of the invention or conflict with each other.

The electrical connection or coupling described in this disclosure may refer to direct connection or indirect connection. In the case of direct connection, the endpoints of the components on the two circuits are directly connected or connected to each other by a conductor segment, and in the case of indirect connection, there are switches, diodes, capacitors, inductors, other suitable components, or combinations of the above components between the endpoints of the components on the two circuits, but not limited to these.

In the present disclosure, the thickness, length and width can be measured by an optical microscope, and the thickness can be measured by a cross-sectional image in an electron microscope, but it is not limited to this. In addition, any two values or directions used for comparison may have a certain error. If the first value is equal to the second value, it implies that there may be an error of about 10% between the first value and the second value; if the first direction is perpendicular to the second direction, the angle between the first direction and the second direction may be between 80 degrees and 100 degrees; if the first direction is parallel to the second direction, the angle between the first direction and the second direction may be between 0 degrees and 10 degrees.

The electronic device disclosed herein may include a display device, an antenna device, a reconfigurable intelligent surface device, a signal feeding device, a waveguide device, a sensing device, a light emitting device, or a splicing device, but is not limited thereto. The electronic device may include a bendable or flexible electronic device. The electronic device may include an electronic element. The electronic device may include, for example, a liquid crystal layer or a light emitting diode (LED). The electronic element may include passive elements and active elements, such as capacitors, resistors, inductors, variable capacitors, filters, diodes, transistors, sensors, micro-electromechanical system elements (MEMS), liquid crystal chips, etc., but is not limited thereto. The diode may include a light emitting diode or a photodiode. The light emitting diode may include, for example, an organic light emitting diode (OLED), a sub-millimeter light emitting diode (mini LED), a micro LED, a quantum dot LED, fluorescence, phosphor or other suitable materials, or a combination thereof, but not limited thereto. The sensor may include, for example, a capacitive sensor, an optical sensor, an electromagnetic sensor, a fingerprint sensor (FPS), a touch sensor, an antenna, or a pen sensor, but not limited thereto. The following text will use a display device as an electronic device to illustrate the content of the present disclosure, but the present disclosure is not limited thereto.

The following are examples of exemplary embodiments of the present disclosure, and the same component symbols are used in the drawings and descriptions to represent the same or similar parts.

FIG. 1A is a partial top view schematic diagram of a modulation device of the first embodiment of the present disclosure, FIG. 1B is a cross-sectional schematic diagram of an embodiment cut along the section line A1-A1' of FIG. 1A, FIG. 1C is a partial top view schematic diagram of the arrangement relationship between the scan line and the data line in the modulation device of one embodiment of the present disclosure, and FIG. 1D is a partial top view schematic diagram of the arrangement relationship between the scan line and the data line in the modulation device of another embodiment of the present disclosure.

Please refer to FIG. 1A and FIG. 1B at the same time. The modulation device 10a of this embodiment includes a substrate SB, a modulation unit AU, a scanning line SL, and a data line DL. The modulation device 10a may be applicable to the communication field, the radar/lidar field, the reconfigurable intelligent surface (RIS) technology, or other suitable fields/technologies, but the present disclosure is not limited thereto.

The material of the substrate SB may be, for example, glass, plastic or a combination thereof. For example, the material of the substrate SB may include quartz, sapphire, silicon (Si), germanium (Ge), silicon carbide (SiC), gallium nitride (GaN), silicon germanium (SiGe), polymethyl methacrylate (PMMA), polycarbonate (PC), polyimide (PI), polyethylene terephthalate (PET) or other suitable materials or a combination of the above materials, and the present disclosure is not limited thereto.

The modulation unit AU is, for example, disposed on the substrate SB. In some embodiments, the modulation unit AU may include a varactor diode, a variable capacitor, a variable resistor, a phase shifter, an amplifier, an antenna, a biometric sensor, a graphene sensor, other suitable components or a combination thereof. For example, the modulation unit AU of the present embodiment includes a varactor diode, and the varactor diode can provide different capacitance values according to the signals provided by the driving circuit DC and the transistor TFT to be introduced later, that is, the capacitance value of the varactor diode can be changed by changing the voltage at both ends of the varactor diode. Therefore, by adjusting the capacitance value of the varactor diode, the modulation device 10a of the present embodiment can adjust the operating frequency band, but the present disclosure is not limited thereto. In some embodiments, the pitch P between adjacent modulation units AU in the same row is related to the wavelength of the electromagnetic wave to be adjusted. For example, the pitch P between adjacent modulation units AU is about half of the wavelength of the electromagnetic wave to be adjusted, but the present disclosure is not limited to this.

The scanning line SL and the data line DL are, for example, disposed on the substrate SB. The scanning line SL is, for example, electrically connected to the transistor TFT to be described later, and the data line DL is, for example, electrically connected to the modulation unit AU. In some embodiments, the scanning line SL extends in a first direction d1, and the data line DL extends in a second direction d2, wherein the first direction d1 is different from the second direction d2. In the present embodiment, the first direction d1 is perpendicular to the second direction d2, but the present disclosure is not limited thereto. The scanning line SL, for example, partially overlaps with the data line DL, wherein the data line DL partially covers the scanning line SL, but the present disclosure is not limited thereto. In the present embodiment, the scanning line SL and the data line DL have overlapping areas and non-overlapping areas. Specifically, the aforementioned overlapping area is defined as an area where the scanning line SL overlaps with the data line DL in the top-view direction n of the substrate SB, and the top-view direction n is, for example, perpendicular to the first direction d1 and the second direction d2, wherein the scanning line SL has an overlapping area SL_OA overlapping with the data line DL and a non-overlapping area SL_NOA not overlapping with the data line DL; or the data line DL has an overlapping area DL_OA overlapping with the scanning line SL and a non-overlapping area DL_NOA not overlapping with the scanning line SL.

In this embodiment, the scanning line SL and/or the data line DL may have the following design to reduce the capacitive load of the modulation device 10a, wherein the capacitive load generated by the scanning line SL and the data line DL may, for example, conform to the following relationship: C=(ε*A)/d, C is the capacitive load generated by the scanning line SL and the data line DL, ε is the dielectric constant of the medium between the scanning line SL and the data line DL, A is the overlapping area of the scanning line SL and the data line DL in the top view direction n of the substrate SB, and d is the distance between the scanning line SL and the data line DL in the top view direction n of the substrate SB.

In some embodiments, as shown in FIG1C , the overlap area SL_OA and the non-overlap area SL_NOA of the scan line SL may have different widths in the second direction d2. Specifically, the scan line SL has a first width SL_W1 in the overlap area SL_OA in the second direction d2, and the scan line SL has a second width SL_W2 in the non-overlap area SL_NOA in the second direction d2, and the first width SL_W1 is smaller than the second width SL_W2 (SL_W1<SL_W2). In other embodiments, as shown in FIG1D , the overlap area DL_OA and the non-overlap area DL_NOA of the data line DL may have different widths in the first direction d1. Specifically, the data line DL has a third width DL_W1 in the first direction d1 in the overlapping area DL_OA, and the data line DL has a fourth width DL_W2 in the first direction d1 in the non-overlapping area DL_NOA, and the third width DL_W1 is smaller than the fourth width DL_W2 (DL_W1<DL_W2).

Through the above-mentioned design, the overlapping area of the scanning line SL and the data line DL in the top view direction n of the substrate SB can be reduced, so that the capacitive load generated by the scanning line SL and the data line DL can be reduced, thereby improving the signal transmission quality of the modulation device 10a.

In some embodiments, the modulation device 10a further includes an insulating layer IL1, an insulating layer IL2, a first electrode C1, a second electrode C2, a transistor TFT, a common line CL, a driving circuit DC, a heat dissipation structure TC, and a conductive layer M.

The insulating layer IL1 is, for example, disposed on the substrate SB. In the present embodiment, the insulating layer IL1 is disposed between the data line DL and the scanning line SL, and covers the scanning line SL. The material of the insulating layer IL1 may be, for example, an inorganic material (e.g., silicon oxide, silicon nitride, silicon oxynitride, or a stacked layer of at least two of the above materials), an organic material (e.g., polytetrafluoroethylene, polyimide, polyparaxylene, benzocyclobutene, or other suitable materials), or a combination thereof, but the present disclosure is not limited thereto. The insulating layer IL1 (medium) disposed between the data line DL and the scanning line SL may have a relatively low capacitance due to the aforementioned material, so that the capacitance load generated by the scanning line SL and the data line DL can be reduced, thereby improving the signal transmission quality of the modulation device 10a. In some embodiments, the capacitance of the insulating layer IL1 may be less than 5. In other embodiments, the capacitance of the insulating layer IL1 may be less than 4. In still other embodiments, the capacitance of the insulating layer IL1 may be less than 3.

In some embodiments, the insulating layer IL1 may be a single-layer structure or a multi-layer structure, but the present disclosure is not limited thereto. In addition, in some embodiments, the thickness IL1_T of the insulating layer IL1 is 0.2 μm-10 μm. In other embodiments, the thickness IL1_T of the insulating layer IL1 is 1 μm-5 μm. Since the thickness IL1_T of the insulating layer IL1 is substantially the distance between the scanning line SL and the data line DL in the top view direction n of the substrate SB, when the thickness IL1_T of the insulating layer IL1 is within the aforementioned range, the distance between the data line DL in the top view direction n of the substrate SB can be relatively increased, so that the capacitive load generated by the scanning line SL and the data line DL can be reduced, thereby improving the signal transmission quality of the modulation device 10a.

The insulating layer IL2 is, for example, disposed on the substrate SB. In this embodiment, the insulating layer IL2 covers the data line DL. The material included in the insulating layer IL2 may be the same as or similar to the material included in the insulating layer IL1, and will not be described in detail here.

The first electrode C1 and the second electrode C2 are, for example, disposed on the substrate SB. In the present embodiment, the first electrode C1 and the second electrode C2 are disposed on the insulating layer IL2, and the first electrode C1 and the second electrode C2 may belong to the same metal layer or may belong to different metal layers. In some embodiments, the first electrode C1 and/or the second electrode C2 may be composed of a single metal layer or a combination of multiple metal layers, but the present disclosure is not limited thereto. The modulation unit AU is, for example, disposed on the first electrode C1 and the second electrode C2, and may be, for example, electrically connected to the first electrode C1 and the second electrode C2 via the pads PAD1 and PAD2, but the present disclosure is not limited thereto. The first electrode C1 may, for example, have an opening C1_OP and/or a slot C1_SLIT, and the second electrode C2 may, for example, also have an opening C2_OP and/or a slot C2_SLIT. By making the first electrode C1 and the second electrode C2 have the aforementioned design, the signal reflected by the first electrode C1 and/or the second electrode C2 may, for example, be reduced to obtain a controllable operating frequency range of the modulation unit AU. It is worth noting that this embodiment does not limit the number of openings and/or slots that the first electrode C1 and the second electrode C2 have to be one, nor does it limit the first electrode C1 and the second electrode C2 to having both openings and slots. The first electrode C1 and the second electrode C2 can be formed, for example, by a known patterning process. For example, the first electrode C1 and the second electrode C2 can be formed by laser direct structuring (LDS), but the present disclosure is not limited thereto.

The transistor TFT may be electrically connected to the modulation unit AU, for example, to drive the modulation unit AU. The transistor TFT may include, for example, a gate G, a source S, a drain D, and a semiconductor layer SE, but the present disclosure is not limited thereto. In the present embodiment, the gate G and the scanning line SL belong to the same metal layer, and the source S and the drain D and the data line DL belong to the same metal layer, wherein the gate G is covered by the insulating layer IL1, the source S is covered by the insulating layer IL2, and the drain D is partially covered by the insulating layer IL2, but the present disclosure is not limited thereto. The transistor TFT can be electrically connected to the modulation unit AU, for example, through a through hole V1 penetrating the insulating layer IL2. Specifically, the through hole V1 penetrates the insulating layer IL2 in the top view direction n of the substrate SB and exposes a portion of the drain D of the transistor TFT, wherein the first electrode C1 is electrically connected to the drain D of the transistor TFT through the through hole V1, so that the modulation unit AU disposed on the first electrode C1 can be electrically connected to the transistor TFT.

In some embodiments, the scan line SL can be electrically connected to the gate G of the transistor TFT, and the data line DL can be electrically connected to the source S of the transistor TFT, wherein the scan line SL and the data line DL can each be used to provide a scan signal and a data signal to the corresponding transistor TFT to operate the modulation unit AU, but the present disclosure is not limited thereto. In addition, in this embodiment, the data line DL can be electrically connected to the first electrode C1 through the transistor TFT.

In some embodiments, the material of the semiconductor layer SE includes low temperature polysilicon (LTPS), metal oxide or amorphous silicon (a-Si), or a combination thereof, but the present disclosure is not limited thereto. For example, the material of the semiconductor layer SE may include but is not limited to amorphous silicon, polycrystalline silicon, germanium, compound semiconductors (such as gallium nitride, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide and/or indium antimonide), alloy semiconductors (such as SiGe alloy, GaAsP alloy, AlInAs alloy, AlGaAs alloy, GaInAs alloy, GaInP alloy, GaInAsP alloy), or a combination thereof. The material of the semiconductor layer SE may also include but is not limited to metal oxides, such as indium gallium zinc oxide (IGZO), indium zinc oxide (IZO), indium gallium zinc oxide (IGZTO), or an organic semiconductor containing a polycyclic aromatic compound, or a combination thereof. The gate G at least partially overlaps with the semiconductor layer SE in the top view direction n of the substrate SB, for example. The source S and the drain D are, for example, separated from each other, and cover at least a portion of the semiconductor layer SE and are electrically connected to the semiconductor layer SE. Alternatively, the source S and the drain D may each be electrically connected to each other through a through hole (not shown) in an insulating layer (not shown) between the source S and the drain D and the semiconductor layer SE. It is worth noting that the transistor TFT is any bottom gate type thin film transistor known to those skilled in the art. However, although this embodiment takes the bottom gate type thin film transistor as an example, the present disclosure is not limited thereto.

The common line CL is, for example, disposed on the substrate SB. In some embodiments, the common line CL and the scanning line SL extend in the same direction, that is, the common line CL extends in the first direction d1, but the present disclosure is not limited thereto. In the present embodiment, the common line CL, the gate G, and the scanning line SL belong to the same metal layer, wherein the common line CL is partially covered by the insulating layer IL1, but the present disclosure is not limited thereto. The common line CL is, for example, electrically connected to the modulation unit AU to provide a common signal to the modulation unit AU. In the present embodiment, the common line CL can be electrically connected to the modulation unit AU through a through hole V2 penetrating the insulating layer IL1 and the insulating layer IL2. Specifically, the through hole V2 penetrates the insulating layer IL1 and the insulating layer IL2 in the top view direction n of the substrate SB and exposes a portion of the common line CL, wherein the second electrode C2 is electrically connected to the common line CL through the through hole V2, so that the modulation unit AU disposed on the second electrode C2 can be electrically connected to the common line CL.

The driving circuit DC is, for example, disposed on the substrate SB. In some embodiments, the driving circuit DC may be disposed on at least one side of the substrate SB. In detail, the driving circuit DC may be disposed in a peripheral area (not shown) of the substrate SB, but the present disclosure is not limited thereto. For example, as shown in FIG. 1A , the driving circuit DC is at least disposed in a peripheral area located on one side of the substrate SB, but the present disclosure is not limited thereto. In some embodiments, the driving circuit DC is disposed in a manner of directly disposing the driving circuit on the substrate SB; or the driving circuit DC is disposed in a manner of disposing a chip on the substrate SB, but the present disclosure is not limited thereto. The driving circuit DC may include, for example, a timing control circuit, a data driving circuit, a voltage supply circuit, a power driving circuit, other suitable circuits or a combination thereof, but the present disclosure is not limited thereto. In this embodiment, the driving circuit DC is electrically connected to the scanning line SL, the data line DL and the common line CL respectively (the driving circuit electrically connected to the data line DL is not shown in FIG. 1A ), wherein the driving circuit DC can provide corresponding scanning signals and data signals to the transistor TFT through the scanning line SL and the data line DL, and the driving circuit DC can also provide corresponding common signals to the modulation unit AU through the common line CL, so that the modulation unit AU can be operated according to the voltage levels provided by the transistor TFT and the common line CL respectively, thereby achieving the effect of multi-frequency operation and/or broadband operation.

The heat dissipation structure TC is, for example, disposed below the substrate SB. Specifically, the heat dissipation structure TC is disposed below the substrate SB in the top-view direction n of the substrate SB. The heat dissipation structure TC can be used, for example, to dissipate the heat generated by each electronic component (such as transistor TFT, modulation unit AU, scanning line SL, data line DL, etc.) disposed above the substrate SB to the outside, so as to achieve the effect of lowering the temperature of the modulation device 10a. In some embodiments, the heat dissipation structure TC may include a heat sink having a plurality of heat dissipation fins to quickly dissipate the aforementioned heat to the outside. In other embodiments, the heat dissipation structure TC may include a vapor chamber having a chamber including a microstructure, the chamber including a heat absorbing end and a heat releasing end, and the working fluid flows in the chamber. When the aforementioned heat is transferred to the heat absorbing end of the chamber, the working fluid absorbs the heat and vaporizes. The vaporized working fluid moves to the heat releasing end with lower pressure due to the increased pressure, and condenses back into liquid at the heat releasing end to release the heat, thereby dissipating the aforementioned heat to the outside. Afterwards, the liquid can return to the heat absorbing end through the capillary phenomenon of the microstructure.

In this embodiment, the heat dissipation structure TC can reduce the impedance of the scanning line SL and/or the data line DL during operation, wherein the scanning line SL and/or the data line DL can, for example, meet the following relationship: R=(ρ*L)/A’, ρ is the resistivity of the scanning line SL and/or the data line DL, L is the length of the scanning line SL in the first direction d1 and/or the length of the data line DL in the second direction d2, and A’ is the cross-sectional area of the scanning line SL in the second direction d2 and/or the cross-sectional area of the data line DL in the first direction d1.

In some embodiments, as shown in FIG. 1B , the heat dissipation structure TC is disposed below the substrate SB to dissipate the heat generated by each electronic component disposed above the substrate SB to the outside, so that the temperature of the scanning line SL and/or the data line DL can be reduced to reduce its resistivity, thereby reducing the impedance of the scanning line SL and/or the data line DL.

The conductive layer M is, for example, disposed between the heat dissipation structure TC and the substrate SB. Specifically, the conductive layer M is disposed between the heat dissipation structure TC and the substrate SB in the top-view direction n of the substrate SB. The material of the conductive layer M may, for example, include copper, molybdenum, graphite, other suitable conductors, or combinations thereof, and the conductive layer M may, for example, include a single-layer structure or a multi-layer structure, but the present disclosure is not limited thereto. The conductive layer M may, for example, be used to conduct heat generated by each electronic element (such as transistor TFT, modulation unit AU, scanning line SL, data line DL, etc.) disposed above the substrate SB to the heat dissipation structure TC to reduce the temperature of the modulation device 10a, but the present disclosure is not limited thereto. In other embodiments, the conductive layer M may be used for electrical conduction purposes. For example, the conductive layer M may include a ground plate, the material of which may include metal, which may be electrically connected to the modulation unit AU to ground the modulation unit AU. The conductive layer M may have a light-proof property, and may be formed completely below the substrate SB or may have an opening to shield electromagnetic waves that are not to be received, but the present disclosure is not limited thereto.

FIG. 1E is a schematic cross-sectional view of an embodiment according to the section line A2-A2' of FIG. 1A, FIG. 1F is a schematic cross-sectional view of another embodiment according to the section line A2-A2' of FIG. 1A, and FIG. 1G is a schematic cross-sectional view of yet another embodiment according to the section line A2-A2' of FIG. 1A.

Please refer to FIG. 1E , this embodiment may further include an insulating layer IL0. The insulating layer IL0 is, for example, disposed on the substrate SB and disposed between the substrate SB and the insulating layer IL1. The material included in the insulating layer IL0 may be the same as or similar to the material included in the insulating layer IL1, and will not be described in detail here. In addition, the scanning line SL and/or the data line DL of this embodiment may include an auxiliary electrode line. Specifically, as shown in FIG. 1E , the scanning line SL includes a main electrode line SLa and an auxiliary electrode line SLb, and the data line DL includes a main electrode line DLa and an auxiliary electrode line DLb, wherein the auxiliary electrode line SLb and the auxiliary electrode line DLb are partially covered by the insulating layer IL0, and the main electrode line SLa and the main electrode line DLa are disposed on the insulating layer IL0 and are electrically connected to the auxiliary electrode line SLb and the auxiliary electrode line DLb respectively through the through hole IL0_V1 and the through hole IL0_V2 penetrating the insulating layer IL0.

Through the above-mentioned design, the cross-sectional area of the scanning line SL in the second direction d2 and/or the cross-sectional area of the data line DL in the first direction d1 can be increased, thereby reducing the impedance value of the scanning line SL and/or the data line DL.

In addition, the common line CL may also include an auxiliary electrode line. Specifically, as shown in FIG. 1E , the common line CL includes a main electrode line CLa and an auxiliary electrode line CLb, wherein the auxiliary electrode line CLb is partially covered by the insulating layer IL0, and the main electrode line CLa is disposed on the insulating layer IL0 and is electrically connected to the auxiliary electrode line CLb through a through hole IL0_V3 penetrating the insulating layer IL0.

In some embodiments, the material of the auxiliary electrode line (e.g., auxiliary electrode line SLb, auxiliary electrode line DLb, or/and auxiliary electrode line CLb) may be different from the material of the main electrode line (e.g., main electrode line SLa, main electrode line DLa, or/and main electrode line CLa). In addition, the material resistivity of the auxiliary electrode line (e.g., auxiliary electrode line SLb, auxiliary electrode line DLb, or/and auxiliary electrode line CLb) may be lower than the material resistivity of the main electrode line (e.g., main electrode line SLa, main electrode line DLa, or/and main electrode line CLa), but the present disclosure is not limited thereto. In other embodiments, the thickness of the auxiliary electrode line (e.g., auxiliary electrode line SLb, auxiliary electrode line DLb, or/and auxiliary electrode line CLb) in the top view direction n may be greater than the thickness of the main electrode line (e.g., main electrode line SLa, main electrode line DLa, or/and main electrode line CLa), but the present disclosure is not limited thereto. In other embodiments, in a cross-sectional direction, the thickness of the auxiliary electrode line (e.g., auxiliary electrode line SLb, auxiliary electrode line DLb, or/and auxiliary electrode line CLb) may be greater than the thickness of the main electrode line (e.g., main electrode line SLa, main electrode line DLa, or/and main electrode line CLa), but the present disclosure is not limited thereto.

However, the pattern of the scanning line SL and/or the data line DL is not limited to the embodiment shown in FIG. 1E. FIG. 1F and FIG. 1G show other patterns of the scanning line SL and/or the data line DL.

Please refer to FIG. 1F, which also shows that the scanning line SL and/or data line DL of this embodiment includes an auxiliary electrode line. In detail, as shown in FIG. 1F, the scanning line SL includes a main electrode line SLa and an auxiliary electrode line SLb, and the data line DL includes a main electrode line DLa and an auxiliary electrode line DLb, wherein the auxiliary electrode line SLb and the auxiliary electrode line DLb are arranged below the substrate SB, and the main electrode line SLa and the main electrode line DLa are arranged above the substrate SB and are respectively electrically connected to the auxiliary electrode line SLb and the auxiliary electrode line DLb through the through hole VS and the through hole VD penetrating the substrate SB.

Through the above-mentioned design, the cross-sectional area of the scanning line SL in the second direction d2 and/or the cross-sectional area of the data line DL in the first direction d1 can be increased, thereby reducing the impedance value of the scanning line SL and/or the data line DL.

In addition, the common line CL may also include an auxiliary electrode line. Specifically, as shown in FIG. 1F , the common line CL includes a main electrode line CLa and an auxiliary electrode line CLb, wherein the auxiliary electrode line CLb is disposed below the substrate SB, and the main electrode line CLa is disposed above the substrate SB and is electrically connected to the auxiliary electrode line CLb through a through hole VC penetrating the substrate SB.

Please refer to FIG. 1G, which shows that the scanning line SL of this embodiment includes a main electrode line SLa and an auxiliary electrode line SLb, wherein the main electrode line SLa is disposed on the substrate SB, and the auxiliary electrode line SLb is disposed on the insulating layer IL2 and is electrically connected to the main electrode line SLa through a through hole IL2_V1 penetrating the insulating layer IL2 and a through hole IL1_V1 penetrating the insulating layer IL1, wherein the through hole IL2_V1 is connected to the through hole IL1_V1.

Through the above-mentioned design, the cross-sectional area of the scanning line SL in the second direction d2 can be increased, thereby reducing the impedance value of the scanning line SL.

However, it is explained again that the shape of the scanning line SL and/or the data line DL is not limited to the embodiments shown in Figures 1E to 1G. For example, the scanning line SL and/or the data line DL may have a thickness of more than 1 micron in the top view direction n of the substrate SB; or the scanning line SL and/or the data line DL may be composed of a multi-layer structure, so that the cross-sectional area of the scanning line SL in the second direction d2 and/or the cross-sectional area of the data line DL in the first direction d1 can be relatively increased, thereby reducing the impedance value of the scanning line SL and/or the data line DL.

FIG. 2A is a partial top view schematic diagram of the modulation device of the second embodiment of the present disclosure, FIG. 2B is a cross-sectional schematic diagram of an embodiment cut along the section line B-B' of FIG. 2A, and FIG. 2C is a cross-sectional schematic diagram of another embodiment cut along the section line B-B' of FIG. 2A. It should be noted that the embodiment of FIG. 2A can use the component numbers and part of the content of the embodiment of FIG. 1A, and the embodiments of FIG. 2B and FIG. 2C can use the component numbers and part of the content of the embodiments of FIG. 1E to FIG. 1G, wherein the same or similar numbers are used to represent the same or similar components, and the description of the same technical content is omitted.

Referring to FIG. 2A , the main difference between the modulation device 10b of the present embodiment and the modulation device 10a described above is that the scanning line SL included in the modulation device 10b is arranged in parallel with the data line DL, that is, the scanning line SL included in the modulation device 10b extends in the second direction d2. The maximum length of the modulation device 10b in the second direction d2 is less than the maximum length in the first direction d1, so compared with the arrangement in which the scanning line SL extends in the first direction d1, the scanning line SL included in the modulation device 10b has a shorter length.

Through the above-mentioned design, the scanning line SL can have a relatively short length in the second direction d2, thereby reducing the impedance value of the scanning line SL.

In addition, the common line CL of this embodiment can also extend in the second direction d2.

In FIG. 2B and FIG. 2C, other forms of the scanning line SL are shown.

Please refer to FIG. 2B and FIG. 2C, which show that the scanning line SL of this embodiment includes an auxiliary electrode line. In detail, as shown in FIG. 2B, the scanning line SL includes a main electrode line SLa and an auxiliary electrode line SLb, wherein the main electrode line SLa is disposed on the substrate SB and is partially covered by the insulating layer IL1, and the auxiliary electrode line SLb is disposed on the insulating layer IL1 and is electrically connected to the main electrode line SLa through a through hole IL1_V1 penetrating the insulating layer IL1. In addition, the auxiliary electrode line SLb of this embodiment and the data line DL belong to the same metal layer, but the present disclosure is not limited thereto. Please refer to FIG. 2B and FIG. 2C. In FIG. 2B, the auxiliary electrode line SLb of the scanning line SL does not overlap with the common line CL; whereas in FIG. 2C, the auxiliary electrode line SLb of the scanning line SL overlaps with the common line CL.

Through the above-mentioned design, the cross-sectional area of the scanning line SL in the second direction d2 can be increased, thereby reducing the impedance value of the scanning line SL.

In addition, in the embodiment shown in FIG. 2B , the common line CL may also include an auxiliary electrode line. Specifically, as shown in FIG. 2B , the common line CL includes a main electrode line CLa and an auxiliary electrode line CLb, wherein the main electrode line CLa is disposed on the substrate SB and is partially covered by the insulating layer IL1, and the auxiliary electrode line CLb is disposed on the insulating layer IL1 and is electrically connected to the main electrode line CLa through a through hole IL1_V3 penetrating the insulating layer IL1. In addition, the auxiliary electrode line CLb of this embodiment also belongs to the same metal layer as the data line DL, but the present disclosure is not limited thereto.

FIG3A is a partial top view schematic diagram of the modulation device of the third embodiment of the present disclosure, and FIG3B is a cross-sectional schematic diagram of an embodiment cut along the section line C-C' of FIG3A. It should be noted that the embodiment of FIG3A can use the component numbers and part of the content of the embodiment of FIG2A, wherein the same or similar numbers are used to represent the same or similar components, and the description of the same technical content is omitted.

Please refer to FIG. 3A and FIG. 3B at the same time. The main difference between the modulation device 10c of this embodiment and the modulation device 10b mentioned above is that the driving circuit DC of the modulation device 10c is arranged below the substrate SB, and the driving circuit DC is arranged roughly in the middle area of the substrate SB.

Specifically, the driving circuit DC is disposed under the substrate SB. The driving circuit DC of this embodiment is electrically connected to the scanning line SL, the data line DL, and the common line CL through the through hole VS, the through hole VD, and the through hole VC, wherein the through hole VS and the through hole VC penetrate the substrate SB, and the through hole VD penetrates the insulating layer IL1 and the substrate SB. In some embodiments, the conductive layer M may be disposed between the substrate SB and the driving circuit DC, and the driving circuit DC may be electrically connected to the scanning line SL, the data line DL, or/and the common line CL through multiple through holes penetrating the substrate SB and the conductive layer M, but the present disclosure is not limited thereto.

Based on this, in the modulation device 10c, the driving circuit DC is arranged below the substrate SB. Therefore, compared with the arrangement in which the driving circuit DC is arranged on at least one side of the substrate SB, the scanning line SL and/or the data line DL included in the modulation device 10c has a shorter length.

Through the above-mentioned design, the scanning line SL in the second direction d2 and/or the data line DL in the second direction d2 can have a relatively short length, thereby reducing the impedance value of the scanning line SL and/or the data line DL.

FIG4 is a partial top view schematic diagram of the modulation device of the fourth embodiment of the present disclosure. It should be noted that the embodiment of FIG4 can use the component numbers and part of the content of the embodiment of FIG1A, wherein the same or similar numbers are used to represent the same or similar components, and the description of the same technical content is omitted.

Please refer to FIG. 4 . The main difference between the modulation device 10d of this embodiment and the aforementioned modulation device 10a is that a modulation unit AU of the modulation device 10d is operated by two transistors and includes two data lines.

Specifically, the modulation device 10d includes a first transistor TFT1 and a second transistor TFT2 for operating a modulation unit AU, and the data line DL includes a main data line DL1 and an auxiliary data line DL1'. The main data line DL1 can be electrically connected to the first transistor TFT1, and the auxiliary data line DL1' can be electrically connected to the second transistor TFT2, so as to provide corresponding data signals respectively, so that the first transistor TFT1 and the second transistor TFT2 are used to operate the modulation unit AU, but the present disclosure is not limited thereto. In some embodiments, when the voltage or current borne by the main data line DL1 is too large, the auxiliary data line DL1' can be used to share the load, but the present disclosure is not limited thereto.

It is worth noting that the modulation device 10d of this embodiment (or the aforementioned modulation device 10a, modulation device 10b or modulation device 10c) may also include two scanning lines (not shown), which include a main scanning line and an auxiliary scanning line, wherein the main scanning line and the auxiliary scanning line are each electrically connected to a corresponding transistor, but the present disclosure is not limited thereto.

FIG. 5A is a partial top view schematic diagram of the modulation device of the fifth embodiment of the present disclosure, FIG. 5B is a cross-sectional schematic diagram of an embodiment cut out according to the section line D1-D1' of FIG. 5A, FIG. 5C is a cross-sectional schematic diagram of an embodiment cut out according to the section line D2-D2' of FIG. 5A, and FIG. 5D is a cross-sectional schematic diagram of another embodiment cut out according to the section line D2-D2' of FIG. 5A. It should be noted that the embodiment of FIG. 5A can use the component numbers and part of the content of the embodiment of FIG. 1A, the embodiment of FIG. 5B can use the component numbers and part of the content of the embodiment of FIG. 1B, and the embodiments of FIG. 5C and FIG. 5D can each use the component numbers and part of the content of the embodiments of FIG. 1E to FIG. 1G, wherein the same or similar numbers are used to represent the same or similar components, and the description of the same technical content is omitted.

Please refer to FIG. 5A and FIG. 5B at the same time. The main difference between the modulation device 10e of this embodiment and the modulation device 10a mentioned above is that the transistor TFT in the modulation device 10e is a top gate type thin film transistor, and the material included in the semiconductor layer SE in the transistor TFT is low-temperature polysilicon.

In this embodiment, the modulation device 10e also includes a buffer layer BF and an insulating layer IL0.

The buffer layer BF is, for example, disposed on the substrate SB, and the semiconductor layer SE is, for example, disposed on the buffer layer BF. In the present embodiment, the buffer layer BF is disposed between the substrate SB and the semiconductor layer SE, but the present disclosure is not limited thereto. The material of the buffer layer BF may be, for example, an inorganic material (e.g., silicon oxide, silicon nitride, silicon oxynitride, or a stacked layer of at least two of the above materials), but the present disclosure is not limited thereto. The buffer layer BF may be, for example, used to reduce the situation where impurities in the substrate SB enter the semiconductor layer SE, and may be, for example, used to enhance the adhesion between the substrate SB and the semiconductor layer SE, but the present disclosure is not limited thereto.

The insulating layer IL0 is, for example, disposed on the buffer layer BF and partially covers the semiconductor layer SE. The material included in the insulating layer IL0 may be the same as or similar to the material included in the insulating layer IL1, and will not be described in detail here.

In some embodiments, the semiconductor layer SE may include a source region, a drain region, and a channel region (not shown), the source region contacts the source S, the drain region contacts the drain D, and the channel region overlaps with the gate G in the top view direction n of the substrate SB. In addition, the modulation device 10e may further include a light shielding layer (not shown), which may be, for example, disposed between the substrate SB and the channel region of the semiconductor layer SE and covered by the buffer layer BF, and the light shielding layer at least partially overlaps with the channel region of the semiconductor layer SE in the top view direction n of the substrate SB, thereby reducing the degradation of the channel region due to exposure to external ambient light. In some embodiments, the material of the light shielding layer may include a material with a transmittance lower than 30%, but the present disclosure is not limited thereto.

Please refer to Figure 5C and Figure 5D, the scanning line SL of this embodiment may include an auxiliary electrode line.

In detail, in one embodiment, as shown in FIG. 5C , the scanning line SL includes a main electrode line SLa and an auxiliary electrode line SLb, wherein the auxiliary electrode line SLb is located on the main electrode line SLa. From another perspective, the modulation device 10e may include an area Area1 and an area Area2, and the area Area1 and the area Area2 are adjacent to each other in the first direction d1, wherein the area Area2 is defined as an area that does not overlap with the data line DL or the semiconductor layer SE in the top view direction n of the substrate SB, and the area Area1 is an area outside the area Area2. The main electrode line SLa is, for example, distributed in the area Area1 and the area Area2, and the auxiliary electrode line SLb is, for example, distributed in the area Area2. Based on this, through the aforementioned design, the cross-sectional area of the scanning line SL in the area Area2 in the second direction d2 can be increased, thereby reducing the impedance value of the scanning line SL.

In another embodiment, as shown in FIG. 5D , the main electrode line SLa included in the scanning line SL is located on the auxiliary electrode line SLb, wherein the main electrode line SLa is distributed in the area Area1 and the area Area2, and the auxiliary electrode line SLb is distributed in the area Area2. Based on this, through the above-mentioned design, the cross-sectional area of the scanning line SL located in the area Area2 in the second direction d2 can be increased, thereby reducing the impedance value of the scanning line SL.

FIG6A is a partial top view schematic diagram of the modulation device of the sixth embodiment of the present disclosure, and FIG6B is a cross-sectional schematic diagram of an embodiment cut along the section line E-E' of FIG6A. It should be noted that the embodiment of FIG6A can use the component numbers and part of the content of the embodiment of FIG5A, and the embodiment of FIG6B can use the component numbers and part of the content of the embodiment of FIG5B, wherein the same or similar numbers are used to represent the same or similar components, and the description of the same technical content is omitted.

Please refer to FIG. 6A and FIG. 6B at the same time. The main difference between the modulation device 10f of this embodiment and the aforementioned modulation device 10e is that the transistor TFT' in the modulation device 10f is a bipolar thin film transistor.

Specifically, in this embodiment, the scanning line SL has an opening SL_OP, wherein the opening SL_OP of the scanning line SL exposes a portion of the semiconductor layer SE in the top view direction n of the substrate SB, thereby forming a transistor TFT' having two gates (gate G1 and gate G2) separated from each other.

Although not shown in FIG. 6A , in some embodiments, the opening SL_OP of the scanning line SL may extend along the first direction d1 and partially overlap with the data line DL in the top-view direction n of the substrate SB, thereby reducing the overlapping area of the scanning line SL and the data line DL in the top-view direction n of the substrate SB.

Through the above-mentioned design, the overlapping area of the scanning line SL and the data line DL in the top view direction n of the substrate SB can be reduced, so that the capacitive load generated by the scanning line SL and the data line DL can be reduced, thereby improving the signal transmission quality of the modulation device 10f.

FIG7 is a partial top view schematic diagram of the arrangement relationship between the scanning lines and the common electric lines in the modulation device of an embodiment of the present disclosure.

In some embodiments, as shown in FIG. 7 , the common line CL has an electrical connection line segment CL_CS and an extension line segment CL_ES. The electrical connection line segment CL_CS of the common line CL is used, for example, to be electrically connected to the modulation unit AU. In addition, the extension line segment CL_ES of the common line CL, for example, extends in the extension direction of the common line CL (the first direction d1 in this embodiment), and its two ends are connected to adjacent electrical connection line segments CL_CS. In this embodiment, the electrical connection line segment CL_CS of the common line CL is relatively far away from the scanning line SL, that is, the distance D _CS between the electrical connection line segment CL_CS of the common line CL and the scanning line SL in the second direction d2 is greater than the distance D _ES between the extension line segment CL_ES of the common line CL and the scanning line SL in the second direction d2.

Through the above-mentioned design, the distance between the common line CL and the scanning line SL in the second direction d2 can be increased, so that the capacitive load generated by the common line CL and the scanning line SL can be reduced.

It is worth noting that in other embodiments, the extended line segment CL_ES of the common line CL can also be made relatively far away from the scanning line SL, that is, the distance D _CS between the electrical connection line segment CL_CS of the common line CL and the scanning line SL in the second direction d2 is smaller than the distance D _ES between the extended line segment CL_ES of the common line CL and the scanning line SL in the second direction d2, but the present disclosure is not limited to this.

In addition, in other embodiments, the distance between the common line CL used to drive a row and the scanning line SL used to drive an adjacent row in the second direction d2 may also be increased, but the present disclosure is not limited thereto.

FIG8A is a partial top view schematic diagram of the modulation device of the seventh embodiment of the present disclosure, and FIG8B is a partial top view schematic diagram of the driving circuit of the modulation device according to FIG8A It should be noted that the embodiment of FIG8A can use the component numbers and part of the content of the embodiment of FIG3A, and the embodiment of FIG8B can use the component numbers and part of the content of the embodiment of FIG3B, wherein the same or similar numbers are used to represent the same or similar components, and the description of the same technical content is omitted.

Please refer to FIG. 8A . The main difference between the modulation device 10g of this embodiment and the modulation device 10a described above is that the modulation device 10g includes a plurality of chip ICs disposed under the substrate SB, and the plurality of modulation units AU are driven by the plurality of chip ICs in a zoned manner.

In detail, the modulation device 10g of the present embodiment divides m*n modulation units AU into a group of modulation unit groups 100, wherein the m*n modulation units AU are arranged in an array, m modulation units AU are arranged in a first direction d1, and n modulation units AU are arranged in a second direction d2. Therefore, on the first surface SB_S1 of the substrate SB (the surface where the modulation units AU are arranged), a group of modulation unit groups 100 includes n scanning lines, m data lines, and n common lines, and a group of modulation unit groups 100 is driven by a chip IC. Taking FIG. 8A as an example, the modulation device 10g of the present embodiment divides 3*2 modulation units AU into a group of modulation unit groups 100 and arranges them in an array. On the first surface SB_S1 of the substrate SB (the surface where the modulation unit AU is disposed), a modulation unit group 100 includes 2 scanning lines (scanning line SL1 and scanning line SL2), 3 data lines (data line DL1, data line DL2 and data line DL3) and 2 common lines (common line CL1 and common line CL2), and a modulation unit group 100 is driven by a chip IC.

The chip IC may include, for example, a timing control circuit, a data drive circuit, a voltage supply circuit, a power drive circuit, other suitable circuits or combinations thereof, and the present disclosure is not limited thereto. In the present embodiment, the chip may be formed under the substrate SB by a panel level package (PLP) process, wherein the panel level package may include a redistribution structure first (RDL first) process or a chip first process. Therefore, the substrate SB of the present embodiment may have a panel-level size (that is, the area of the substrate SB may be greater than or equal to 50 cm x 50 cm), which may be used to achieve high throughput requirements.

In addition, in the present embodiment, the substrate SB has a plurality of through holes, wherein a plurality of chips ICs can be electrically connected to the modulation unit AU through the plurality of through holes of the substrate SB. Specifically, in a modulation unit assembly 100, two scanning lines (scanning line SL1’ and scanning line SL2’) electrically connected to a chip IC, three data lines (data line DL1’, data line DL2’ and data line DL3’) and two common lines (common line CL1’ and common line CL2’) are arranged on the second surface SB_S2 of the substrate SB (the surface on which the chip IC is arranged), wherein the scanning line SL1’ is electrically connected to the scanning line SL1 through the through hole VS1 of the substrate SB, and the scanning line SL2’ is electrically connected to the scanning line CL2 through the through hole VS1 of the substrate SB. The scanning line SL2 is electrically connected through the through hole VS2 of the substrate SB, the data line DL1' is electrically connected to the data line DL1 through the through hole VD1 of the substrate SB, the data line DL2' is electrically connected to the data line DL2 through the through hole VD2 of the substrate SB, the data line DL3' is electrically connected to the data line DL3 through the through hole VD3 of the substrate SB, the common line CL1' is electrically connected to the common line CL1 through the through hole VC1 of the substrate SB, and the common line CL2' is electrically connected to the common line CL2 through the through hole VC2 of the substrate SB.

Through the above-mentioned design, in the modulation device 10g, the length of the scanning line SL in the first direction d1 and/or the length of the data line DL in the first direction d1 can be reduced, thereby reducing the impedance value of the scanning line SL and/or the data line DL.

FIG. 9A is a partial top view schematic diagram of a photosensitive device of an embodiment of the present disclosure, and FIG. 9B is a cross-sectional schematic diagram of an embodiment cut along the section line F-F' of FIG. 9A. It should be noted that the embodiment of FIG. 9A can use the component numbers and part of the content of the embodiment of FIG. 1A, and the embodiment of FIG. 9B can use the component numbers and part of the content of the embodiment of FIG. 1B, wherein the same or similar numbers are used to represent the same or similar components, and the description of the same technical content is omitted.

Please refer to FIG. 9A , the main difference between the photosensitive device 20 of this embodiment and the aforementioned modulation device 10a is that the photosensitive device 20 includes a photoelectric unit PS but does not include a modulation unit AU.

Specifically, the photosensitive device 20 includes a photoelectric unit PS, wherein the photoelectric unit PS includes a photodiode PD, an electrode E1, and an electrode E2. The photodiode PD may include, for example, a semiconductor layer PD1, a photosensitive layer PD2, and a semiconductor layer PD3, and the semiconductor layer PD1, the photosensitive layer PD2, and the semiconductor layer PD3 are stacked in this order in a top-view direction n of the substrate SB. The electrode E1 and the electrode E2 are, for example, electrically connected to the semiconductor layer PD1 and the semiconductor layer PD3, respectively. The photodiode PD may include, for example, a single crystal material, a polycrystalline material, or an organic material. For example, the photodiode PD may include, for example, an organic photodiode (OPD), but the present disclosure is not limited thereto.

The photoelectric unit PS is, for example, electrically connected to the drain D of the transistor TFT” so that the transistor TFT” can be used to drive the photoelectric unit PS. Specifically, the photoelectric unit PS can convert received photons into carriers (e.g., electrons and/or holes), and when the transistor TFT” is not turned on, the carriers are stored in the photoelectric unit PS. After the transistor TFT” is turned on, the carriers stored in the photoelectric unit PS can be read, for example, via a read line (data line DL) coupled to the transistor TFT”, thereby realizing the role of light detection. The transistor TFT” of this embodiment is, for example, a dual-gate thin film transistor (including a gate G1 and a gate G2), and the material included is, for example, low-temperature polysilicon, but the present disclosure is not limited thereto.

In some embodiments, the photosensitive device 20 may further include a buffer layer BF, an insulating layer IL3, an insulating layer IL4, and a bias line BL.

The buffer layer BF is, for example, disposed between the substrate SB and the semiconductor layer SE of the "transistor TFT". The material of the buffer layer BF may be, for example, an inorganic material (e.g., silicon oxide, silicon nitride, silicon oxynitride, or a stacked layer of at least two of the above materials), but the present disclosure is not limited thereto. The buffer layer BF may, for example, be used to reduce the situation where impurities in the substrate SB enter the semiconductor layer SE, and may, for example, be used to enhance the adhesion between the substrate SB and the semiconductor layer SE, but the present disclosure is not limited thereto.

The insulating layer IL3 is, for example, disposed on the insulating layer IL2. In this embodiment, the insulating layer IL3 covers the transistor TFT" and partially covers the photoelectric unit PS, wherein the insulating layer IL3 has a through hole IL3_V exposing the electrode E2 of the photoelectric unit PS. The material included in the insulating layer IL3 may be the same as or similar to the material included in the insulating layer IL1, and will not be described in detail here.

The insulating layer IL4 is, for example, disposed on the insulating layer IL3. In the present embodiment, the insulating layer IL4 also covers the transistor TFT" and partially covers the photoelectric unit PS, wherein the insulating layer IL4 has a through hole IL4_V exposing the electrode E2 of the photoelectric unit PS, that is, the through hole IL4_V can be connected with the through hole IL3_V to expose part of the electrode E2 together. The material included in the insulating layer IL4 can be the same as or similar to the material included in the insulating layer IL1, which will not be repeated here. In some embodiments, the insulating layer IL4 can be used as a planar layer, but the present disclosure is not limited thereto.

The bias line BL is, for example, disposed on the insulating layer IL4 and electrically connected to the photoelectric unit PS, wherein the bias line BL can be, for example, electrically connected to the electrode E2 of the photoelectric unit PS through the connected through hole IL3_V and the through hole IL4_V. The bias line BL can, for example, be used to apply a voltage to the photoelectric unit PS to separate the hole-electron pairs in the photoelectric unit PS to generate carriers. In some embodiments, the bias line BL can extend in the second direction d2, but the present disclosure is not limited thereto.

In this embodiment, the design of the scanning line SL and/or the data line DL applied in the modulation device 10a to the modulation device 10g can also be applied to the photosensitive device 20 to improve the light detection quality of the photosensitive device 20. For example, the capacitance load generated by the scanning line SL and the data line DL can be reduced by reducing the overlapping area of the scanning line SL and the data line DL in the top view direction n of the substrate SB; or the cross-sectional area of the scanning line SL in the second direction d2 and/or the cross-sectional area of the data line DL in the first direction d1 can be increased by making the scanning line SL and/or the data line DL include a stack of main electrode lines and auxiliary electrode lines, thereby reducing the impedance value of the scanning line SL and/or the data line DL, but the present disclosure is not limited thereto.

FIG10 is a partial top view schematic diagram of the modulation device of the eighth embodiment of the present disclosure. It should be noted that the embodiment of FIG10 can use the component numbers and part of the content of the embodiment of FIG1A, wherein the same or similar numbers are used to represent the same or similar components, and the description of the same technical content is omitted.

Please refer to FIG. 10 . The main difference between the modulation device 10h of this embodiment and the modulation device 10a described above is that the modulation device 10h includes a modulation unit MEMS but does not include a modulation unit AU.

Specifically, the modulation unit MEMS in the modulation device 10h is, for example, a micro-electromechanical unit, which includes a common electrode CE and a modulation electrode ME. The common electrode CE is, for example, electrically connected to a common line CL to receive a signal provided by the common line CL, and the common electrode CE has, for example, an opening CE_OP, but the present disclosure is not limited thereto. The modulation electrode ME is, for example, electrically connected to a transistor TFT to move by a corresponding signal provided by the transistor TFT. In the present embodiment, the modulation electrode ME can receive a corresponding signal provided by the transistor TFT and rotate and move. For example, a group of modulation units MEMS1 in the first row of the modulation device 10h is in a state where the transistor TFT is not turned on, a group of modulation units MEMS2 in the second row of the modulation device 10h receives a first signal provided by the transistor TFT and rotates, and a group of modulation units MEMS3 in the third row of the modulation device 10h receives a second signal provided by the transistor TFT and rotates.

By rotating the modulation electrode ME, the capacitance between the common electrode CE and the modulation electrode ME can be changed, thereby adjusting the operating frequency band; or the effective length of the opening CE_OP of the common electrode CE can be changed, thereby adjusting the resonance frequency of the opening CE_OP, but the present disclosure is not limited to this.

In this embodiment, the design of the scanning line SL and/or the data line DL applied in the modulation device 10a to the modulation device 10g can also be applied to the modulation device 10h to improve the signal transmission quality of the modulation device 10h. For example, the capacitance load generated by the scanning line SL and the data line DL can be reduced by reducing the overlapping area of the scanning line SL and the data line DL in the top view direction n of the substrate SB; or the cross-sectional area of the scanning line SL in the second direction d2 and/or the cross-sectional area of the data line DL in the first direction d1 can be increased by making the scanning line SL and/or the data line DL include a stack of main electrode lines and auxiliary electrode lines, thereby reducing the impedance value of the scanning line SL and/or the data line DL, but the present disclosure is not limited thereto.

According to the above, some embodiments of the present disclosure can reduce the impedance value of the scanning line and/or data line by reducing the length of the scanning line and/or data line, increasing the cross-sectional area of the scanning line and/or data line, and/or providing a heat dissipation structure in the modulation device. Other embodiments of the present disclosure can reduce the capacitive load of the scanning line and/or data line by reducing the capacitance of the insulating layer provided between the scanning line and the data line, reducing the overlapping area of the scanning line and the data line, and/or increasing the distance between the scanning line and the data line in the modulation device. In addition, some other embodiments of the present disclosure can include a combination of the aforementioned designs of the modulation device, so that the impedance value and the capacitive load of the scanning line and/or data line can be reduced. Based on this, the modulation device provided by the disclosed embodiment can reduce the resistance and capacitance load, and its signal transmission quality and reliability can be improved.

Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present disclosure, rather than to limit them. Although the present disclosure is described in detail with reference to the above embodiments, ordinary technicians in this field should understand that they can still modify the technical solutions described in the above embodiments, or replace some or all of the technical features therein with equivalent ones. However, these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present disclosure. The features of the embodiments can be mixed and matched as they please as long as they do not violate the spirit of the invention or conflict with each other.

10a: Modulation device

A1-A1’, A2-A2’: section line

AU: Modulation Unit

C1: first electrode

C1_OP, C2_OP: Opening

C1_SLIT, C2_SLIT: narrow slot

C2: Second electrode

CL: shared cable

d1: first direction

d2: Second direction

DC: drive circuit

DL: Data Line

n: Looking down

P: Pitch

SB: Substrate

SL: Scan line

TFT: Transistor

Claims (20)

A modulation device comprises: a substrate; a modulation unit disposed on the substrate; a data line disposed on the substrate and electrically connected to the modulation unit; a scan line disposed on the substrate and having an overlapping region overlapping with the data line and a non-overlapping region not overlapping with the data line; a first insulating layer disposed between the data line and the scan line; and a second insulating layer disposed on the data line, wherein in a first direction, the scan line has a first width in the overlapping region, and the scan line has a second width in the non-overlapping region, and the first width is smaller than the second width, wherein the modulation unit is disposed on the data line, the first insulating layer and the second insulating layer. The modulation device as described in claim 1 further includes a first electrode and a second electrode, wherein the first electrode and the second electrode are disposed on the substrate, and the modulation unit is disposed on the first electrode and the second electrode. The modulation device as described in claim 2 further includes a common line, the common line is electrically connected to the second electrode, and the data line is electrically connected to the first electrode. The modulation device as described in claim 1 further includes a heat dissipation structure, and the heat dissipation structure is arranged under the substrate. The modulation device as described in claim 4 further includes a conductive layer, wherein the conductive layer is disposed between the heat dissipation structure and the substrate. A modulation device as described in claim 1, wherein the scanning line includes a main electrode line and an auxiliary electrode line, wherein the auxiliary electrode line is electrically connected to the main electrode line through a through hole penetrating the insulating layer. A modulation device as described in claim 1, wherein the thickness of the first insulating layer is 0.2μm-10μm. A modulation device comprises: a substrate; a modulation unit disposed on the substrate; a data line disposed on the substrate and electrically connected to the modulation unit; a scan line disposed on the substrate and partially overlapping with the data line; a first insulating layer disposed between the data line and the scan line; and a second insulating layer disposed on the data line, wherein the data line has a The overlapping area where the scan lines overlap and the non-overlapping area that does not overlap with the scan lines, wherein in the second direction, the data line has a third width in the overlapping area, the data line has a fourth width in the non-overlapping area, and the third width is smaller than the fourth width, wherein the modulation unit is disposed on the data line, the first insulating layer and the second insulating layer. The modulation device as described in claim 8 further includes a first electrode and a second electrode, wherein the first electrode and the second electrode are disposed on the substrate, and the modulation unit is disposed on the first electrode and the second electrode. The modulation device as described in claim 9 further includes a common line, the common line is electrically connected to the second electrode, and the data line is electrically connected to the first electrode. The modulation device as described in claim 8 further includes a heat dissipation structure, and the heat dissipation structure is arranged under the substrate. The modulation device as described in claim 11 further includes a conductive layer, wherein the conductive layer is disposed between the heat dissipation structure and the substrate. A modulation device as described in claim 8, wherein the data line includes a main electrode line and an auxiliary electrode line, wherein the auxiliary electrode line is electrically connected to the main electrode line through a through hole penetrating the insulating layer. A modulation device as described in claim 8, wherein the thickness of the first insulating layer is 0.2μm-10μm. A modulation device includes: a substrate; a plurality of modulation units disposed on the substrate; a data line disposed on the substrate and electrically connected to at least one of the plurality of modulation units; and a scanning line disposed on the substrate and parallel to the data line. The modulation device as described in claim 15 further includes a driving circuit, the driving circuit is arranged on the substrate, and the driving circuit is arranged in the peripheral area of the substrate. The modulation device as described in claim 15 further includes a driving circuit, the driving circuit is arranged on the substrate, and the driving circuit is arranged in the middle area of the substrate. The modulation device as described in claim 15 further includes a plurality of chips, the plurality of chips are disposed under the substrate, and the plurality of chips drive the plurality of modulation units in a zoned manner. A modulation device as described in claim 18, wherein the plurality of chips are formed under the substrate through a panel-level packaging process. A modulation device as described in claim 18, wherein the substrate has a plurality of through holes, and the plurality of chips are electrically connected to the plurality of modulation units through the plurality of through holes.

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