TWI850094B - Micro-electro-mechanical system package and fabrication method thereof - Google Patents
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本揭露係關於微機電(Micro Electro Mechanical System,MEMS)封裝,特別是關於微機電封裝包含具有不同壓力的MEMS元件及其製造方法。 The present disclosure relates to a micro-electromechanical system (MEMS) package, and in particular to a micro-electromechanical system package including MEMS components with different pressures and a manufacturing method thereof.
微機電(MEMS)元件是整合機械和電性組件的微型元件,以感測物理量和/或與周圍環境交互作用,MEMS元件例如加速度計(accelerometer)、陀螺儀(gyroscope)、壓力感測器和麥克風等已廣泛應用於許多現代電子產品中,舉例來說,由加速度計和/或陀螺儀組成的慣性測量單元(inertial measurement units,IMU)常見於平板電腦、汽車或智能手機中。對於某些應用而言,需要將各種MEMS元件整合到一個微機電封裝中。然而,針對需要不同壓力的MEMS元件,這些MEMS元件需要在不同的環境壓力下分開封裝,然後再整合到一個微機電封裝中,因此傳統的微機電封裝的封裝製程複雜,且傳統的微機電封裝也需要較大的佔位面積(footprint)。 Micro-electromechanical (MEMS) devices are miniature components that integrate mechanical and electrical components to sense physical quantities and/or interact with the surrounding environment. MEMS devices such as accelerometers, gyroscopes, pressure sensors, and microphones have been widely used in many modern electronic products. For example, inertial measurement units (IMUs) composed of accelerometers and/or gyroscopes are commonly found in tablets, cars, or smartphones. For some applications, it is necessary to integrate various MEMS components into a MEMS package. However, for MEMS components that require different pressures, these MEMS components need to be packaged separately under different environmental pressures and then integrated into a MEMS package. Therefore, the packaging process of traditional MEMS packaging is complicated, and traditional MEMS packaging also requires a larger footprint.
有鑑於此,本揭露的一些實施例提供微機電(MEMS)封裝及其製造方法,以克服傳統的微機電封裝的前述缺點。本揭露的微機電封裝包含位於鍵合 密封環中的孔洞,以在鍵合後達到MEMS元件的空腔之壓力調節。此外,在壓力調節的製程步驟期間,還可以在MEMS元件上形成抗黏附塗層。因此,相較於傳統的微機電封裝,本揭露包含具有不同空腔壓力的多個MEMS元件的微機電封裝之封裝製程可被簡化,且微機電封裝的佔位面積較小。 In view of this, some embodiments of the present disclosure provide a microelectromechanical (MEMS) package and a manufacturing method thereof to overcome the aforementioned shortcomings of conventional MEMS packages. The MEMS package disclosed herein includes a hole in a bonding seal ring to achieve pressure adjustment of the cavity of the MEMS element after bonding. In addition, an anti-adhesion coating can also be formed on the MEMS element during the pressure adjustment process step. Therefore, compared to conventional MEMS packages, the packaging process of the MEMS package disclosed herein including multiple MEMS elements with different cavity pressures can be simplified, and the MEMS package occupies a smaller area.
根據本揭露的一實施例,提供了一種微機電(MEMS)封裝,包括晶圓、互連層、第一元件基板、第二元件基板、第一鍵合密封環、第二鍵合密封環、第一支撐基板、第二支撐基板、孔洞以及介電膜。互連層設置在晶圓上,第一元件基板包括第一MEMS元件,且設置在晶圓上,第二元件基板包括第二MEMS元件,且設置在晶圓上,第二元件基板與第一元件基板側向隔開。第一鍵合密封環設置在第一元件基板下方且鍵合至互連層,第二鍵合密封環設置在第二元件基板下方且鍵合至互連層。第一支撐基板包括第一空腔且鍵合至第一元件基板,第二支撐基板包括第二空腔且鍵合至第二元件基板。孔洞設置在第二鍵合密封環中,介電膜設置於互連層上,且鄰近第一鍵合密封環和第二鍵合密封環。第一空腔具有第一壓力,第二空腔具有第二壓力,第二壓力不同於第一壓力。 According to an embodiment of the present disclosure, a microelectromechanical (MEMS) package is provided, including a wafer, an interconnection layer, a first component substrate, a second component substrate, a first bonding sealing ring, a second bonding sealing ring, a first supporting substrate, a second supporting substrate, holes, and a dielectric film. The interconnection layer is arranged on the wafer, the first component substrate includes a first MEMS element and is arranged on the wafer, the second component substrate includes a second MEMS element and is arranged on the wafer, and the second component substrate is laterally separated from the first component substrate. The first bonding sealing ring is arranged below the first component substrate and bonded to the interconnection layer, and the second bonding sealing ring is arranged below the second component substrate and bonded to the interconnection layer. The first supporting substrate includes a first cavity and is bonded to the first component substrate, and the second supporting substrate includes a second cavity and is bonded to the second component substrate. The hole is arranged in the second bonding sealing ring, the dielectric film is arranged on the interconnection layer, and is adjacent to the first bonding sealing ring and the second bonding sealing ring. The first cavity has a first pressure, and the second cavity has a second pressure, and the second pressure is different from the first pressure.
根據本揭露的一實施例,提供一種微機電封裝的製造方法,包括以下步驟:提供支撐晶圓,其包含第一空腔和第二空腔形成於其中;提供元件晶圓,其包含第一MEMS元件和第二MEMS元件形成於其中且彼此側向隔開;形成第一鍵合密封環和第二鍵合密封環,分別在第一MEMS元件和第二MEMS元件下方;在第二鍵合密封環中形成孔洞;在元件晶圓中形成兩條預切割線,且位於第一MEMS元件和第二MEMS元件之間;將支撐晶圓鍵合至元件晶圓,其中第一空腔位於第一MEMS元件正上方,第二空腔位於第二MEMS元件正上方;提供晶圓,並在晶圓上形成互連層;在第一壓力下將元件晶圓鍵合至晶圓上的互連層;移除在兩條預切割線之間的支撐晶圓的一部分和元件晶圓的一部分,讓第二鍵 合密封環中的孔洞暴露於環境壓力下;以及在互連層上形成介電膜。 According to an embodiment of the present disclosure, a method for manufacturing a micro-electromechanical system package is provided, comprising the following steps: providing a support wafer, wherein a first cavity and a second cavity are formed therein; providing a device wafer, wherein a first MEMS device and a second MEMS device are formed therein and are laterally spaced from each other; forming a first bonding seal ring and a second bonding seal ring, respectively, below the first MEMS device and the second MEMS device; forming a hole in the second bonding seal ring; forming two pre-cut lines in the device wafer, and the pre-cut lines are located between ... between a MEMS element and a second MEMS element; bonding a support wafer to a component wafer, wherein a first cavity is located directly above the first MEMS element and a second cavity is located directly above the second MEMS element; providing a wafer and forming an interconnect layer on the wafer; bonding the component wafer to the interconnect layer on the wafer under a first pressure; removing a portion of the support wafer and a portion of the component wafer between two pre-cut lines to expose a hole in a second bonding sealing ring to an ambient pressure; and forming a dielectric film on the interconnect layer.
為了讓本揭露之特徵明顯易懂,下文特舉出實施例,並配合所附圖式,作詳細說明如下。 In order to make the features of this disclosure clear and easy to understand, the following is a detailed description of the embodiments with the help of the attached drawings.
100:微機電封裝 100:Micro-electromechanical packaging
100A:第一MEMS區 100A: First MEMS area
100B:第二MEMS區 100B: Second MEMS area
SL:切割道 SL: Cutting Road
110:支撐晶圓 110: Support wafer
110A:第一支撐基板 110A: The first supporting substrate
110B:第二支撐基板 110B: Second supporting substrate
110F、110K、110T:表面 110F, 110K, 110T: Surface
112:第一空腔 112: First cavity
114:第二空腔 114: Second cavity
116:鍵合層 116: Bonding layer
116A:第一鍵合層 116A: First bonding layer
116B:第二鍵合層 116B: Second bonding layer
118、118A、118B:導電層 118, 118A, 118B: Conductive layer
120:元件晶圓 120: Component wafer
120A:第一元件基板 120A: First component substrate
120B:第二元件基板 120B: Second component substrate
120P:元件晶圓的一部分 120P: Part of the component wafer
121:支座凸塊 121: Support bump
122:第一MEMS元件 122: First MEMS element
123、127:溝槽 123, 127: Groove
124:第二MEMS元件 124: Second MEMS element
125A:第一鍵合密封環 125A: First key sealing ring
125B:第二鍵合密封環 125B: Second key sealing ring
126:鍵合材料 126: Bonding materials
130:晶圓 130: Wafer
132:互連層 132: Interconnection layer
134:保護層 134: Protective layer
140:通氣孔/孔洞 140: Ventilation holes/holes
142:孔洞 142: Hole
145:抗黏附塗層 145: Anti-adhesion coating
150:台階結構 150: Step structure
151、152、153:預切割線 151, 152, 153: Pre-cut lines
152P:突出部分 152P: protruding part
154:接合墊 154:Joint pad
160:介電膜 160: Dielectric film
161:介電材料層 161: Dielectric material layer
170:密封層 170: Sealing layer
S101、S103、S105、S107、S201、S202、S203、S205、S207:步驟 S101, S103, S105, S107, S201, S202, S203, S205, S207: Steps
為了使下文更容易被理解,在閱讀本揭露時可同時參考圖式及其詳細文字說明。透過本文中之具體實施例並參考相對應的圖式,俾以詳細解說本揭露之具體實施例,並用以闡述本揭露之具體實施例之作用原理。此外,為了清楚起見,圖式中的各特徵可能未按照實際的比例繪製,因此某些圖式中的部分特徵的尺寸可能被刻意放大或縮小。 In order to make the following easier to understand, the drawings and their detailed text descriptions can be referred to simultaneously when reading this disclosure. Through the specific embodiments in this article and reference to the corresponding drawings, the specific embodiments of this disclosure are explained in detail, and the working principles of the specific embodiments of this disclosure are explained. In addition, for the sake of clarity, the features in the drawings may not be drawn according to the actual scale, so the size of some features in some drawings may be deliberately enlarged or reduced.
第1圖是根據本揭露一實施例所繪示的微機電(MEMS)封裝的俯視示意圖。 Figure 1 is a schematic top view of a micro-electromechanical system (MEMS) package according to an embodiment of the present disclosure.
第2圖是根據本揭露一實施例所繪示的MEMS封裝的剖面示意圖。 Figure 2 is a cross-sectional schematic diagram of a MEMS package according to an embodiment of the present disclosure.
第3圖是根據本揭露另一實施例所繪示的MEMS封裝的俯視示意圖。 Figure 3 is a schematic top view of a MEMS package according to another embodiment of the present disclosure.
第4圖是根據本揭露另一實施例所繪示的MEMS封裝的剖面示意圖。 Figure 4 is a cross-sectional schematic diagram of a MEMS package according to another embodiment of the present disclosure.
第5圖、第6圖和第7圖是根據本揭露一實施例所繪示的MEMS封裝的製造方法之一些中間階段的剖面示意圖。 Figures 5, 6 and 7 are cross-sectional schematic diagrams of some intermediate stages of a method for manufacturing a MEMS package according to an embodiment of the present disclosure.
第8圖、第9圖和第10圖是根據本揭露另一實施例所繪示的MEMS封裝的製造方法之一些中間階段的剖面示意圖。 Figures 8, 9 and 10 are cross-sectional schematic diagrams of some intermediate stages of a method for manufacturing a MEMS package according to another embodiment of the present disclosure.
本揭露提供了數個不同的實施例,可用於實現本揭露的不同特徵。為簡化說明起見,本揭露也同時描述了特定構件與佈置的範例。提供這些實施例的目的僅在於示意,而非予以任何限制。舉例而言,下文中針對「第一特徵 形成在第二特徵上或上方」的敘述,其可以是指「第一特徵與第二特徵直接接觸」,也可以是指「第一特徵與第二特徵間另存在有其他特徵」,致使第一特徵與第二特徵並不直接接觸。此外,本揭露中的各種實施例可能使用重複的參考符號和/或文字註記。使用這些重複的參考符號與註記是為了使敘述更簡潔和明確,而非用以指示不同的實施例及/或配置之間的關聯性。 The present disclosure provides several different embodiments that can be used to implement different features of the present disclosure. For the purpose of simplifying the description, the present disclosure also describes examples of specific components and arrangements. The purpose of providing these embodiments is only for illustration and not for limitation. For example, the description below of "a first feature is formed on or above a second feature" may refer to "the first feature is in direct contact with the second feature" or "there are other features between the first feature and the second feature", so that the first feature and the second feature are not in direct contact. In addition, various embodiments in the present disclosure may use repeated reference symbols and/or text annotations. These repeated reference symbols and annotations are used to make the description more concise and clear, rather than to indicate the relationship between different embodiments and/or configurations.
另外,針對本揭露中所提及的空間相關的敘述詞彙,例如:「在...之下」,「低」,「下」,「上方」,「之上」,「上」,「頂」,「底」和類似詞彙時,為便於敘述,其用法均在於描述圖式中一個元件或特徵與另一個(或多個)元件或特徵的相對關係。除了圖式中所顯示的擺向外,這些空間相關詞彙也用來描述微機電封裝在使用中以及操作時的可能擺向。隨著微機電封裝的擺向的不同(旋轉90度或其它方位),用以描述其擺向的空間相關敘述亦應透過類似的方式予以解釋。 In addition, for the spatially related descriptive terms mentioned in this disclosure, such as "under", "low", "down", "above", "above", "up", "top", "bottom" and similar terms, for the convenience of description, their usage is to describe the relative relationship between one element or feature and another (or multiple) elements or features in the drawings. In addition to the orientation shown in the drawings, these spatially related terms are also used to describe the possible orientations of the MEMS package during use and operation. As the orientation of the MEMS package is different (rotated 90 degrees or other orientations), the spatially related descriptions used to describe its orientation should also be interpreted in a similar manner.
雖然本揭露使用第一、第二、第三等等用詞,以敘述種種元件、部件、區域、層、及/或區塊,但應了解此等元件、部件、區域、層、及/或區塊不應被此等用詞所限制。此等用詞僅是用以區分某一元件、部件、區域、層、及/或區塊與另一個元件、部件、區域、層、及/或區塊,其本身並不意含及代表該元件有任何之前的序數,也不代表某一元件與另一元件的排列順序、或是製造方法上的順序。因此,在不背離本揭露之具體實施例之範疇下,下列所討論之第一元件、部件、區域、層、或區塊亦可以第二元件、部件、區域、層、或區塊之詞稱之。 Although the present disclosure uses the terms first, second, third, etc. to describe various elements, components, regions, layers, and/or blocks, it should be understood that these elements, components, regions, layers, and/or blocks should not be limited by these terms. These terms are only used to distinguish a certain element, component, region, layer, and/or block from another element, component, region, layer, and/or block, and they do not imply or represent any previous sequence of the element, nor do they represent the arrangement order of a certain element and another element, or the order of the manufacturing method. Therefore, without departing from the scope of the specific embodiments of the present disclosure, the first element, component, region, layer, or block discussed below can also be referred to as the second element, component, region, layer, or block.
本揭露中所提及的「約」或「實質上」之用語通常表示在一給定值或範圍的20%之內,較佳是10%之內,且更佳是5%之內,或3%之內,或2%之內,或1%之內,或0.5%之內。應注意的是,說明書中所提供的數量為大約的數量,亦即在沒有特定說明「約」或「實質上」的情況下,仍可隱含「約」或「實質 上」之含義。 The terms "about" or "substantially" mentioned in this disclosure generally mean within 20% of a given value or range, preferably within 10%, and more preferably within 5%, or within 3%, or within 2%, or within 1%, or within 0.5%. It should be noted that the quantities provided in the specification are approximate quantities, that is, in the absence of specific description of "about" or "substantially", the meaning of "about" or "substantially" can still be implied.
本揭露中所提及的「耦接」、「耦合」、「電連接」一詞包含任何直接及間接的電氣連接手段。舉例而言,若文中描述第一部件耦接於第二部件,則代表第一部件可直接電氣連接於第二部件,或透過其他裝置或連接手段間接地電氣連接至該第二部件。 The terms "coupling", "coupling", and "electrical connection" mentioned in this disclosure include any direct and indirect electrical connection means. For example, if the text describes that a first component is coupled to a second component, it means that the first component can be directly electrically connected to the second component, or indirectly electrically connected to the second component through other devices or connection means.
雖然下文係藉由具體實施例以描述本揭露的發明,然而本揭露的發明原理亦可應用至其他的實施例。此外,為了不致使本發明之精神晦澀難懂,特定的細節會被予以省略,該些被省略的細節係屬於所屬技術領域中具有通常知識者的知識範圍。 Although the invention disclosed herein is described below by means of specific embodiments, the invention principles disclosed herein can also be applied to other embodiments. In addition, in order not to obscure the spirit of the invention, certain details will be omitted, and these omitted details belong to the knowledge scope of those with ordinary knowledge in the relevant technical field.
本揭露係關於微機電(MEMS)封裝及其製造方法,微機電封裝包含在第一壓力下封裝的第一MEMS元件,以及在第二壓力下封裝的第二MEMS元件,第二壓力不同於第一壓力。在一些實施例中,微機電封裝可包含慣性測量單元(IMU),其可包含加速度計和陀螺儀,以及需要不同壓力的其他MEMS元件。在一些實施例中,第一MEMS元件可以是需要高真空的第一壓力之陀螺儀,第二MEMS元件可以是需要低真空的第二壓力之加速度計。第一鍵合密封環和第二鍵合密封環分別對應第一MEMS元件和第二MEMS元件設置,並且在第二鍵合密封環中設置孔洞,以形成通氣孔(vent hole),藉此達成第二MEMS元件的第二空腔之鍵合後的壓力調節。此外,在鍵合後的壓力調節之製程步驟期間,還可以通過通氣孔在第二MEMS元件上形成抗黏附塗層(anti-stiction coating layer)。因此,簡化了包含不同空腔壓力的各種MEMS元件之微機電封裝的封裝製程,並且微機電封裝的佔位面積比傳統的微機電封裝的佔位面積更小。 The present disclosure relates to a microelectromechanical (MEMS) package and a method of making the same, wherein the MEMS package includes a first MEMS component packaged under a first pressure and a second MEMS component packaged under a second pressure, the second pressure being different from the first pressure. In some embodiments, the MEMS package may include an inertial measurement unit (IMU), which may include an accelerometer and a gyroscope, and other MEMS components that require different pressures. In some embodiments, the first MEMS component may be a gyroscope that requires a first pressure of high vacuum, and the second MEMS component may be an accelerometer that requires a second pressure of low vacuum. The first bonding sealing ring and the second bonding sealing ring are respectively arranged corresponding to the first MEMS element and the second MEMS element, and a hole is arranged in the second bonding sealing ring to form a vent hole, thereby achieving pressure adjustment of the second cavity of the second MEMS element after bonding. In addition, during the process step of pressure adjustment after bonding, an anti-stiction coating layer can also be formed on the second MEMS element through the vent hole. Therefore, the packaging process of the MEMS package containing various MEMS elements with different cavity pressures is simplified, and the footprint of the MEMS package is smaller than that of the traditional MEMS package.
第1圖是本揭露一實施例的微機電封裝100的俯視示意圖,微機電封裝100包含彼此分開的各種MEMS元件,例如,第一MEMS元件122位於第一MEMS區100A中,第二MEMS元件124位於第二MEMS區100B中,第一MEMS區100A和第 二MEMS區100B由切割道SL分開。在切割道SL中形成有兩條預切割線151和152,且位於第一MEMS元件122和第二MEMS元件124之間。此外,在切割道SL中設置有多個接合墊(bond pad)154,且位於兩條預切割線151和152之間,另一條預切割線153也形成在切割道SL中。第一MEMS元件122和第二MEMS元件124的操作需要不同的真空度,並且第一MEMS元件122和第二MEMS元件124的MEMS結構不同。第一MEMS元件122和第二MEMS元件124可以包含各種部件特徵,例如支座凸塊(standoff bump)121、溝槽127、檢測質量塊(proof mass)(未繪示)等部件特徵,並且第一MEMS元件122的支座凸塊121、溝槽127和其他部件特徵的佈局不同於第二MEMS元件124的那些部件特徵的佈局。在一些實施例中,第一MEMS元件122例如是需要高真空的陀螺儀,第二MEMS元件124例如是需要低真空或大氣壓的加速度計。此外,第二MEMS元件124可能需要抗黏附塗層,而第一MEMS元件122可能不需要抗黏附塗層,但不限於此。 FIG. 1 is a schematic top view of a micro-electromechanical system package 100 according to an embodiment of the present disclosure. The micro-electromechanical system package 100 includes various MEMS components separated from each other. For example, a first MEMS component 122 is located in a first MEMS region 100A, and a second MEMS component 124 is located in a second MEMS region 100B. The first MEMS region 100A and the second MEMS region 100B are separated by a scribe line SL. Two pre-cut lines 151 and 152 are formed in the scribe line SL and are located between the first MEMS component 122 and the second MEMS component 124. In addition, a plurality of bond pads 154 are provided in the scribe line SL and are located between the two pre-cut lines 151 and 152. Another pre-cut line 153 is also formed in the scribe line SL. The first MEMS element 122 and the second MEMS element 124 require different vacuum levels for operation, and the first MEMS element 122 and the second MEMS element 124 have different MEMS structures. The first MEMS element 122 and the second MEMS element 124 may include various component features, such as standoff bumps 121, grooves 127, and proof mass (not shown), and the layout of the standoff bumps 121, grooves 127, and other component features of the first MEMS element 122 is different from the layout of those component features of the second MEMS element 124. In some embodiments, the first MEMS element 122 is, for example, a gyroscope that requires high vacuum, and the second MEMS element 124 is, for example, an accelerometer that requires low vacuum or atmospheric pressure. In addition, the second MEMS element 124 may require an anti-adhesion coating, while the first MEMS element 122 may not require an anti-adhesion coating, but is not limited thereto.
另外,微機電封裝100包含位於第一MEMS元件122正上方的第一空腔112,以及位於第二MEMS元件124正上方的第二空腔114。第一空腔112具有第一壓力,第二空腔114具有第二壓力,由於第一MEMS元件122和第二MEMS元件124需要不同的空腔壓力,因此第二壓力不同於第一壓力。從俯視圖來看,第一MEMS元件122和第二MEMS元件124均可包含位於其空腔範圍之外或以內的溝槽123。此外,微機電封裝100包含對應第一MEMS元件122設置的第一鍵合密封環125A,以及對應第二MEMS元件124設置的第二鍵合密封環125B。於一些實施例中,孔洞140設置在第二鍵合密封環125B中,以形成通氣孔(vent hole),用於調節第二空腔114內的壓力。孔洞140側向穿過第二鍵合密封環125B(例如沿著Y軸方向)形成,並且連接到第二空腔114。於其他實施例中,在第二鍵合密封環125B中可以設置多個孔洞140,以形成多個通氣孔,用於調節第二空腔114中的壓力,每個孔洞140均側向地穿過第二鍵合密封環125B(例如沿X軸或Y軸方向)形成,且所有孔 洞140均連接到第二空腔114。在一些實施例中,每個孔洞140在X軸或Y軸方向上的寬度可以在約1微米(μm)到約100μm之間,每個孔洞140在Y軸或X軸方向上的長度大致上與第二鍵合密封環125B的寬度相同。 In addition, the micro-electromechanical package 100 includes a first cavity 112 located directly above the first MEMS element 122, and a second cavity 114 located directly above the second MEMS element 124. The first cavity 112 has a first pressure, and the second cavity 114 has a second pressure. Since the first MEMS element 122 and the second MEMS element 124 require different cavity pressures, the second pressure is different from the first pressure. From a top view, the first MEMS element 122 and the second MEMS element 124 may both include a groove 123 located outside or inside their cavity range. In addition, the micro-electromechanical package 100 includes a first bonding seal ring 125A disposed corresponding to the first MEMS element 122, and a second bonding seal ring 125B disposed corresponding to the second MEMS element 124. In some embodiments, a hole 140 is provided in the second keyed sealing ring 125B to form a vent hole for adjusting the pressure in the second cavity 114. The hole 140 is formed laterally through the second keyed sealing ring 125B (e.g., along the Y-axis direction) and is connected to the second cavity 114. In other embodiments, a plurality of holes 140 may be provided in the second keyed sealing ring 125B to form a plurality of vent holes for adjusting the pressure in the second cavity 114, each hole 140 is formed laterally through the second keyed sealing ring 125B (e.g., along the X-axis or Y-axis direction), and all holes 140 are connected to the second cavity 114. In some embodiments, the width of each hole 140 in the X-axis or Y-axis direction may be between about 1 micrometer (μm) and about 100 μm, and the length of each hole 140 in the Y-axis or X-axis direction is substantially the same as the width of the second keying seal ring 125B.
第2圖是本揭露一實施例的微機電封裝100的剖面示意圖,其係沿著第1圖中的剖面線A-A’繪製。為了讓圖式簡潔易懂,將第2圖中的第一MEMS元件122和第二MEMS元件124的剖面細部結構予以簡化,其中溝槽127的數量以及溝槽127之間的部件尺寸並未完全對應於第1圖,那些被簡化的細部結構係屬於所屬技術領域中具有通常知識者可以理解。微機電封裝100包含晶圓130,以及形成在晶圓130上的互連層132。晶圓130可包含多個互補式金屬氧化物半導體(CMOS)或其他元件形成在其中,互連層132包含多個金屬層、多個金屬間介電(inter-metal dielectric,IMD)層以及位於IMD層中用以連接兩個金屬層的多個導通孔(via)。接合墊(bond pad)154設置在互連層132的頂部金屬層上,保護層134也設置在互連層132的頂部金屬層上,且具有多個開口,以分別暴露出接合墊154。此外,微機電封裝100包含第一元件基板120A和第二元件基板120B,第一元件基板120A包含第一MEMS元件122且設置在晶圓130上,第二元件基板120B包含第二MEMS元件124且也設置在晶圓130上,第二元件基板120B和第一元件基板120A側向地隔開。為了讓圖式簡單且容易理解,在第2圖中簡化了第一MEMS元件122和第二MEMS元件124的MEMS結構。另外,第一鍵合密封環125A設置在第一元件基板120A下方,且經由鍵合材料126鍵合至互連層132。第二鍵合密封環125B設置在第二元件基板120B下方,且也經由鍵合材料126鍵合至互連層132。在一些實施例中,第一鍵合密封環125A和第一元件基板120A可以是一體成型結構,並具有相同的組成,例如矽。第二鍵合密封環125B和第二元件基板120B也可以是一體成型結構,並具有相同的組成,例如矽。鍵合材料126用於與互連層132的頂部金屬層產生共晶鍵合(eutectic bonding),例如是鍺(Ge)。 FIG. 2 is a cross-sectional schematic diagram of a MEMS package 100 according to an embodiment of the present disclosure, which is drawn along the section line A-A' in FIG. 1. In order to make the diagram concise and easy to understand, the cross-sectional details of the first MEMS element 122 and the second MEMS element 124 in FIG. 2 are simplified, wherein the number of trenches 127 and the component size between the trenches 127 do not completely correspond to FIG. 1, and those simplified details are understandable to those with ordinary knowledge in the relevant technical field. The MEMS package 100 includes a wafer 130 and an interconnect layer 132 formed on the wafer 130. The wafer 130 may include a plurality of complementary metal oxide semiconductors (CMOS) or other devices formed therein, and the interconnect layer 132 includes a plurality of metal layers, a plurality of inter-metal dielectric (IMD) layers, and a plurality of vias in the IMD layer for connecting two metal layers. A bond pad 154 is disposed on the top metal layer of the interconnect layer 132, and a protective layer 134 is also disposed on the top metal layer of the interconnect layer 132 and has a plurality of openings to expose the bond pads 154 respectively. In addition, the micro-electromechanical package 100 includes a first element substrate 120A and a second element substrate 120B. The first element substrate 120A includes a first MEMS element 122 and is disposed on a wafer 130. The second element substrate 120B includes a second MEMS element 124 and is also disposed on the wafer 130. The second element substrate 120B is laterally separated from the first element substrate 120A. In order to make the figure simple and easy to understand, the MEMS structure of the first MEMS element 122 and the second MEMS element 124 is simplified in FIG. 2. In addition, a first bonding sealing ring 125A is disposed below the first element substrate 120A and is bonded to the interconnection layer 132 via a bonding material 126. A second bonding sealing ring 125B is disposed below the second element substrate 120B and is also bonded to the interconnection layer 132 via a bonding material 126. In some embodiments, the first bonding seal ring 125A and the first element substrate 120A can be an integrally formed structure and have the same composition, such as silicon. The second bonding seal ring 125B and the second element substrate 120B can also be an integrally formed structure and have the same composition, such as silicon. The bonding material 126 is used to produce eutectic bonding with the top metal layer of the interconnect layer 132, such as germanium (Ge).
另外,微機電封裝100包含第一支撐基板110A,其經由第一鍵合層116A鍵合到第一元件基板120A,以及第二支撐基板110B,其經由第二鍵合層116B鍵合到第二元件基板120B。第一支撐基板110A包含第一空腔112形成在其中,且第一空腔112設置在第一MEMS元件122正上方。第二支撐基板110B包含第二空腔114形成在其中,且第二空腔114設置在第二MEMS元件124正上方。第一鍵合層116A設置在第一元件基板120A和第一支撐基板110A之間。於一些實施例中,第一鍵合層116A可以進一步延伸到第一空腔112內,以順向地(conformally)設置在第一空腔112的側壁和底面上。第二鍵合層116B設置在第二元件基板120B和第二支撐基板110B之間,第二鍵合層116B也可以延伸到第二空腔114內,以順向地設置在第二空腔114的側壁和底面上。另外,在第一支撐基板110A的頂面上可設置導電層118A,在第二支撐基板110B的頂面上可設置導電層118B,導電層118A可以是電耦接到第一MEMS元件122和/或互連層132的圖案化導電層,導電層118B可以是電耦接到第二MEMS元件124和/或互連層132的圖案化導電層。 In addition, the micro-electromechanical package 100 includes a first supporting substrate 110A, which is bonded to a first element substrate 120A via a first bonding layer 116A, and a second supporting substrate 110B, which is bonded to a second element substrate 120B via a second bonding layer 116B. The first supporting substrate 110A includes a first cavity 112 formed therein, and the first cavity 112 is disposed directly above a first MEMS element 122. The second supporting substrate 110B includes a second cavity 114 formed therein, and the second cavity 114 is disposed directly above a second MEMS element 124. The first bonding layer 116A is disposed between the first element substrate 120A and the first supporting substrate 110A. In some embodiments, the first bonding layer 116A may further extend into the first cavity 112 to be conformally disposed on the sidewalls and bottom surface of the first cavity 112. The second bonding layer 116B is disposed between the second element substrate 120B and the second supporting substrate 110B, and the second bonding layer 116B may also extend into the second cavity 114 to be conformally disposed on the sidewalls and bottom surface of the second cavity 114. In addition, a conductive layer 118A may be disposed on the top surface of the first supporting substrate 110A, and a conductive layer 118B may be disposed on the top surface of the second supporting substrate 110B. The conductive layer 118A may be a patterned conductive layer electrically coupled to the first MEMS element 122 and/or the interconnection layer 132, and the conductive layer 118B may be a patterned conductive layer electrically coupled to the second MEMS element 124 and/or the interconnection layer 132.
在一些實施例中,如第2圖所示,孔洞140沿X軸方向側向穿過第二鍵合密封環125B,並且經由第二MEMS元件124的溝槽連接到第二空腔114。因此,在第二元件基板120B鍵合至晶圓130上的互連層132之後,孔洞140可作為通氣孔,用於調節第二空腔114內的壓力,以達到第二MEMS元件124所需的壓力。於一些實施例中,在Z軸方向上,通氣孔/孔洞140的高度可相同於或稍微小於第二鍵合密封環125B的厚度,通氣孔/孔洞140的高度例如可以在約1μm至約2μm。 In some embodiments, as shown in FIG. 2 , the hole 140 passes through the second bonding seal ring 125B laterally along the X-axis direction and is connected to the second cavity 114 through the groove of the second MEMS element 124. Therefore, after the second element substrate 120B is bonded to the interconnect layer 132 on the wafer 130, the hole 140 can be used as a vent to adjust the pressure in the second cavity 114 to achieve the pressure required by the second MEMS element 124. In some embodiments, in the Z-axis direction, the height of the vent/hole 140 can be the same as or slightly less than the thickness of the second bonding seal ring 125B, and the height of the vent/hole 140 can be, for example, about 1μm to about 2μm.
在一些實施例中,第一空腔112具有第一壓力P1,而第二空腔114則可通過第二鍵合密封環125B中的通氣孔/孔洞140,來調節第二空腔114內的壓力,使得第二空腔114具有不同於第一壓力P1的第二壓力P2。在將第一元件基板120A鍵合到晶圓130上的互連層132之製程步驟期間,可以控制並決定第一空腔112內的第一壓力P1。在將第二元件基板120B鍵合到晶圓130上的互連層132之 後,則可以通過通氣孔/孔洞140將第二空腔114內的壓力調節到期望的真空度,以得到第二空腔114內的第二壓力P2。此外,在調節第二空腔114內的壓力之製程步驟期間,還可以通過通氣孔/孔140讓抗黏附塗層145順向地形成在第二元件基板120B上,以包裹第二MEMS元件124。在第二空腔114內的第二壓力P2調節到期望的真空度,並且在第二MEMS元件124上形成抗黏附塗層145之後,可以在互連層132上形成介電膜160,其中通氣孔/孔洞140的一部分被介電膜160填充,以重新密封通氣孔/孔洞140。在此實施例中,互連層132的頂面可提供用於沉積介電膜160的台階結構,以重新密封通氣孔/孔洞140。介電膜160可以形成在保護層134上,並且鄰近第一鍵合密封環125A和第二鍵合密封環125B。由於通氣孔/孔洞140的高度很小,例如約1μm至約2μm,因此藉由在互連層132上沉積介電膜160,可以很容易地重新密封通氣孔/孔洞140。另外,於此實施例中,在孔洞140的區域內,鍵合材料126的一部分可形成在第二元件基板120B的背面上,且介電膜160鄰近鍵合材料126的此部分。 In some embodiments, the first cavity 112 has a first pressure P1, and the second cavity 114 can adjust the pressure in the second cavity 114 through the vent hole/hole 140 in the second bonding seal ring 125B, so that the second cavity 114 has a second pressure P2 different from the first pressure P1. During the process step of bonding the first component substrate 120A to the interconnect layer 132 on the wafer 130, the first pressure P1 in the first cavity 112 can be controlled and determined. After the second component substrate 120B is bonded to the interconnect layer 132 on the wafer 130, the pressure in the second cavity 114 can be adjusted to a desired vacuum level through the vent hole/hole 140 to obtain the second pressure P2 in the second cavity 114. Furthermore, during the process step of adjusting the pressure in the second cavity 114, the anti-adhesion coating 145 may be formed sequentially on the second element substrate 120B through the vent/hole 140 to wrap the second MEMS element 124. After the second pressure P2 in the second cavity 114 is adjusted to a desired vacuum level and the anti-adhesion coating 145 is formed on the second MEMS element 124, a dielectric film 160 may be formed on the interconnect layer 132, wherein a portion of the vent/hole 140 is filled with the dielectric film 160 to reseal the vent/hole 140. In this embodiment, the top surface of the interconnect layer 132 may provide a step structure for depositing the dielectric film 160 to reseal the vent/hole 140. The dielectric film 160 may be formed on the protective layer 134 and adjacent to the first bonding seal ring 125A and the second bonding seal ring 125B. Since the height of the vent/hole 140 is very small, for example, about 1 μm to about 2 μm, the vent/hole 140 may be easily resealed by depositing the dielectric film 160 on the interconnect layer 132. In addition, in this embodiment, a portion of the bonding material 126 may be formed on the back side of the second element substrate 120B in the region of the hole 140, and the dielectric film 160 is adjacent to this portion of the bonding material 126.
第3圖是本揭露另一實施例的微機電封裝100的俯視示意圖,在第3圖的微機電封裝100中,孔洞142設置在第二鍵合密封環125B中,並且沿Z軸方向垂直地穿過第二鍵合密封環125B。從俯視圖來看,孔洞142被第二鍵合密封環125B圍繞,而且孔洞142沒有在Y軸或X軸方向上側向地穿過第二鍵合密封環125B。另外,在此實施例中,鄰近第二鍵合密封環125B的預切割線152具有對應於孔洞142位置的突出部分(平台結構)152P,突出部分152P遠離孔洞142向外突出,藉由突出部分152P可以在通過孔洞142所形成的通氣孔之外側提供台階結構。於一些實施例中,可以在第二鍵合密封環125B中形成多個孔洞142,並且預切割線152具有與這些孔洞142對應的多個突出部分152P。第3圖的微機電封裝100的其他部件特徵之細節可參考前述第1圖的微機電封裝100的相關說明,在此不再重複。 FIG. 3 is a schematic top view of a MEMS package 100 according to another embodiment of the present disclosure. In the MEMS package 100 of FIG. 3 , a hole 142 is disposed in the second keying seal ring 125B and vertically passes through the second keying seal ring 125B along the Z-axis direction. From the top view, the hole 142 is surrounded by the second keying seal ring 125B, and the hole 142 does not pass through the second keying seal ring 125B laterally in the Y-axis or X-axis direction. In addition, in this embodiment, the pre-cut line 152 adjacent to the second bonding sealing ring 125B has a protrusion (platform structure) 152P corresponding to the position of the hole 142, and the protrusion 152P protrudes outward away from the hole 142. The protrusion 152P can provide a step structure on the outside of the vent formed by the hole 142. In some embodiments, multiple holes 142 can be formed in the second bonding sealing ring 125B, and the pre-cut line 152 has multiple protrusions 152P corresponding to these holes 142. The details of other component features of the MEMS package 100 in FIG. 3 can refer to the relevant description of the MEMS package 100 in FIG. 1, which will not be repeated here.
第4圖是本揭露另一實施例的微機電封裝100的剖面示意圖,其係沿 著第3圖中的剖面線B-B’繪製。為了讓圖式簡潔易懂,將第4圖中的第一MEMS元件122和第二MEMS元件124的剖面細部結構予以簡化,其中溝槽127的數量以及溝槽127之間的部件尺寸並未完全對應於第3圖,那些被簡化的細部結構係屬於所屬技術領域中具有通常知識者可以理解。微機電封裝100包含設置在第二鍵合密封環125B中的孔洞142,孔洞142在Z軸方向上垂直地穿過第二鍵合密封環125B,並且進一步延伸以穿過第二元件基板120B。在此實施例中,通過孔洞142藉由蝕刻製程可去除位於第二元件基板120B和第二支撐基板110B之間的第二鍵合層116B的一部分,以在第二鍵合層116B中形成通氣孔140。如第4圖所示,於一些實施例中,通氣孔140在第二元件基板120B和第二支撐基板110B之間沿X軸方向側向延伸。此外,通氣孔140連接至第二空腔114和孔洞142,通過通氣孔140可將第二空腔114內的第二壓力P2調節至所需的真空度,使得第二空腔114內的第二壓力P2與第一空腔112內的第一壓力P1不同。 FIG. 4 is a cross-sectional schematic diagram of a MEMS package 100 according to another embodiment of the present disclosure, which is drawn along the cross-sectional line B-B' in FIG. 3. In order to make the diagram concise and easy to understand, the cross-sectional details of the first MEMS element 122 and the second MEMS element 124 in FIG. 4 are simplified, wherein the number of grooves 127 and the component size between the grooves 127 do not completely correspond to FIG. 3, and those simplified details are understandable to those with ordinary knowledge in the relevant technical field. The MEMS package 100 includes a hole 142 disposed in the second keying seal ring 125B, and the hole 142 vertically passes through the second keying seal ring 125B in the Z-axis direction, and further extends to pass through the second element substrate 120B. In this embodiment, a portion of the second bonding layer 116B between the second element substrate 120B and the second supporting substrate 110B can be removed by etching through the hole 142 to form a vent hole 140 in the second bonding layer 116B. As shown in FIG. 4, in some embodiments, the vent hole 140 extends laterally along the X-axis direction between the second element substrate 120B and the second supporting substrate 110B. In addition, the vent hole 140 is connected to the second cavity 114 and the hole 142, and the second pressure P2 in the second cavity 114 can be adjusted to the desired vacuum degree through the vent hole 140, so that the second pressure P2 in the second cavity 114 is different from the first pressure P1 in the first cavity 112.
另外,在此實施例中,如第3圖所示,鄰近第二鍵合密封環125B的預切割線152具有突出部分152P。在切割道SL上進行切割製程之後,如第4圖所示,第二元件基板120B和第二支撐基板110B構成鄰近孔洞142的台階結構150,並且經由孔洞142所形成的通氣孔140位於台階結構150中。此外,在調節第二空腔114內的壓力之製程步驟期間,通過通氣孔140可以讓抗黏附塗層145順向性地設置在第二元件基板120B上,以包裹第二MEMS元件124。當第二空腔114內的第二壓力P2調節至期望的真空度,並且通過通氣孔140在第二MEMS元件124上形成抗黏附塗層145之後,在台階結構150的平台上沉積密封層170,使得通氣孔140的一部分被密封層170填充,以重新密封通氣孔140。此外,在互連層132的保護層134上可形成介電膜160,且介電膜160的位置鄰近第一鍵合密封環125A和第二鍵合密封環125B。於一些實施例中,密封層170和介電膜160可以藉由相同的沉積製程形成,並且具有相同的組成,例如氧化矽。 In addition, in this embodiment, as shown in FIG. 3 , the pre-cut line 152 adjacent to the second bonding seal ring 125B has a protruding portion 152P. After the cutting process is performed on the cutting line SL, as shown in FIG. 4 , the second element substrate 120B and the second supporting substrate 110B form a step structure 150 adjacent to the hole 142, and the vent hole 140 formed through the hole 142 is located in the step structure 150. In addition, during the process step of adjusting the pressure in the second cavity 114, the anti-adhesion coating 145 can be disposed on the second element substrate 120B in a directional manner through the vent hole 140 to wrap the second MEMS element 124. When the second pressure P2 in the second cavity 114 is adjusted to the desired vacuum degree, and after the anti-adhesion coating 145 is formed on the second MEMS element 124 through the vent 140, the sealing layer 170 is deposited on the platform of the step structure 150 so that a portion of the vent 140 is filled with the sealing layer 170 to reseal the vent 140. In addition, a dielectric film 160 may be formed on the protective layer 134 of the interconnect layer 132, and the dielectric film 160 is located adjacent to the first bonding sealing ring 125A and the second bonding sealing ring 125B. In some embodiments, the sealing layer 170 and the dielectric film 160 may be formed by the same deposition process and have the same composition, such as silicon oxide.
於一些實施例中,如第4圖所示,第一鍵合層116A設置在第一元件基板120A和第一支撐基板110A之間,並且沒有延伸到第一空腔112的側壁和底面上。第二鍵合層116B設置在第二元件基板120B和第二支撐基板110B之間,並且沒有延伸到第二空腔114的側壁和底面上,第二鍵合層116B對應於孔洞142的部分可被去除,以形成通氣孔140。於一些實施例中,在Z軸方向上,通氣孔140的高度可以相同於或稍微小於第二鍵合層116B的厚度,例如,通氣孔140的高度可以為約1000埃(Å)至約2000Å。於一些實施例中,通氣孔140在Y軸方向上的寬度可以在約1μm至約100μm的範圍內,通氣孔140在X軸方向上的長度可以與第二鍵合層116B的寬度相同。第4圖的微機電封裝100的其他部件特徵的細節可參考前述第2圖的微機電封裝100的相關說明,在此不再重複。 In some embodiments, as shown in FIG. 4 , the first bonding layer 116A is disposed between the first element substrate 120A and the first supporting substrate 110A, and does not extend to the sidewalls and the bottom surface of the first cavity 112. The second bonding layer 116B is disposed between the second element substrate 120B and the second supporting substrate 110B, and does not extend to the sidewalls and the bottom surface of the second cavity 114, and a portion of the second bonding layer 116B corresponding to the hole 142 may be removed to form the vent 140. In some embodiments, in the Z-axis direction, the height of the vent 140 may be the same as or slightly less than the thickness of the second bonding layer 116B, for example, the height of the vent 140 may be about 1000 angstroms (Å) to about 2000 Å. In some embodiments, the width of the vent hole 140 in the Y-axis direction may be in the range of about 1 μm to about 100 μm, and the length of the vent hole 140 in the X-axis direction may be the same as the width of the second bonding layer 116B. The details of other component features of the MEMS package 100 in FIG. 4 can refer to the relevant description of the MEMS package 100 in FIG. 2 above, which will not be repeated here.
第5圖、第6圖和第7圖是根據本揭露一實施例所繪示的微機電封裝的製造方法之一些中間階段的剖面示意圖,參閱第5圖,於步驟S101,首先提供支撐晶圓(handle wafer)110,例如矽晶圓,並且在支撐晶圓110的表面110F上進行蝕刻製程,以形成第一空腔112和第二空腔114。然後,在支撐晶圓110上以及第一空腔112和第二空腔114內,順向地沉積鍵合層116,以包裹支撐晶圓110。鍵合層116的組成例如是二氧化矽,可以藉由熱氧化或沉積製程來形成鍵合層116。另外,提供元件晶圓(device wafer)120,例如矽晶圓,並將元件晶圓120鍵合至支撐晶圓110的表面110F上,以覆蓋第一空腔112和第二空腔114。之後,藉由光微影和蝕刻製程將元件晶圓120圖案化,以形成彼此側向隔開的第一MEMS元件122和第二MEMS元件124。如第5圖所示,元件晶圓120包含具有第一MEMS元件122的第一元件基板120A,具有第二MEMS元件124的第二元件基板120B,以及位於第一元件基板120A和第二元件基板120B之間的元件晶圓120的一部分120P。預切割線151形成在元件晶圓120中,且位於第一元件基板120A和元件晶圓120的一部分120P之間,另一預切割線152形成在元件晶圓120中,且位於第二元件基板120B 和元件晶圓120的一部分120P之間,並且這兩條預切割線151和152形成在第一MEMS元件122和第二MEMS元件124之間。可以藉由相同的蝕刻製程,例如深反應離子蝕刻(deep reactive-ion etching,DRIE)製程,同時形成預切割線151和152,以及第一MEMS元件122和第二MEMS元件124兩者的溝槽。 FIG. 5, FIG. 6 and FIG. 7 are cross-sectional schematic diagrams of some intermediate stages of a method for manufacturing a micro-electromechanical system package according to an embodiment of the present disclosure. Referring to FIG. 5, in step S101, a handle wafer 110, such as a silicon wafer, is first provided, and an etching process is performed on a surface 110F of the handle wafer 110 to form a first cavity 112 and a second cavity 114. Then, a bonding layer 116 is sequentially deposited on the handle wafer 110 and in the first cavity 112 and the second cavity 114 to wrap the handle wafer 110. The bonding layer 116 is composed of, for example, silicon dioxide, and the bonding layer 116 can be formed by thermal oxidation or a deposition process. In addition, a device wafer 120, such as a silicon wafer, is provided and bonded to the surface 110F of the support wafer 110 to cover the first cavity 112 and the second cavity 114. Thereafter, the device wafer 120 is patterned by photolithography and etching processes to form a first MEMS element 122 and a second MEMS element 124 that are laterally separated from each other. As shown in FIG. 5 , the device wafer 120 includes a first device substrate 120A having a first MEMS element 122, a second device substrate 120B having a second MEMS element 124, and a portion 120P of the device wafer 120 located between the first device substrate 120A and the second device substrate 120B. A pre-cut line 151 is formed in the device wafer 120 and is located between the first device substrate 120A and a portion 120P of the device wafer 120. Another pre-cut line 152 is formed in the device wafer 120 and is located between the second device substrate 120B and a portion 120P of the device wafer 120. The two pre-cut lines 151 and 152 are formed between the first MEMS device 122 and the second MEMS device 124. The pre-cut lines 151 and 152 and the grooves of the first MEMS device 122 and the second MEMS device 124 can be formed simultaneously by the same etching process, such as a deep reactive-ion etching (DRIE) process.
此外,形成第一鍵合密封環125A和第二鍵合密封環125B,分別對應於第一MEMS元件122和第二MEMS元件124,其中,第一鍵合密封環125A和第一元件基板120A可以是由元件晶圓120形成的一體成型結構,第二鍵合密封環125B和第二元件基板120B也可以是由元件晶圓120形成的一體成型結構。藉由將元件晶圓120圖案化,可以形成第一鍵合密封環125A和第二鍵合密封環125B。於此實施例中,可藉由蝕刻製程在第二鍵合密封環125B中形成如第1圖所示的孔洞140,孔洞140側向地穿過第二鍵合密封環125B。之後,在第一鍵合密封環125A和第二鍵合密封環125B上形成鍵合材料126,例如鍺(Ge),其中在孔洞140的區域內,鍵合材料126係形成在第二元件基板120B上。 In addition, a first bonding sealing ring 125A and a second bonding sealing ring 125B are formed, corresponding to the first MEMS element 122 and the second MEMS element 124, respectively, wherein the first bonding sealing ring 125A and the first element substrate 120A can be an integrally formed structure formed by the element wafer 120, and the second bonding sealing ring 125B and the second element substrate 120B can also be an integrally formed structure formed by the element wafer 120. The first bonding sealing ring 125A and the second bonding sealing ring 125B can be formed by patterning the element wafer 120. In this embodiment, a hole 140 as shown in FIG. 1 can be formed in the second bonding sealing ring 125B by an etching process, and the hole 140 laterally passes through the second bonding sealing ring 125B. Afterwards, a bonding material 126, such as germanium (Ge), is formed on the first bonding sealing ring 125A and the second bonding sealing ring 125B, wherein the bonding material 126 is formed on the second component substrate 120B in the region of the hole 140.
仍參閱第5圖,於步驟S103,將鍵合後的支撐晶圓110和元件晶圓120上下顛倒,其中第一空腔112位於第一MEMS元件122正上方,第二空腔114位於第二MEMS元件124正上方。之後,提供晶圓130,例如為其上形成有互連層132的CMOS晶圓。然後,在第一壓力P1下,通過鍵合材料126將元件晶圓120鍵合至晶圓130上的互連層132。於步驟S103,第一空腔112和第二空腔114均具有第一壓力P1。此外,在支撐晶圓110的另一表面110K上進行研磨或蝕刻製程,以減薄支撐晶圓110。然後,在減薄的支撐晶圓110之頂面110T上沉積導電層118,例如鋁(A1)層。 Still referring to FIG. 5 , in step S103, the bonded support wafer 110 and the device wafer 120 are turned upside down, wherein the first cavity 112 is located directly above the first MEMS element 122, and the second cavity 114 is located directly above the second MEMS element 124. Afterwards, a wafer 130 is provided, such as a CMOS wafer having an interconnection layer 132 formed thereon. Then, under a first pressure P1, the device wafer 120 is bonded to the interconnection layer 132 on the wafer 130 through a bonding material 126. In step S103, both the first cavity 112 and the second cavity 114 have the first pressure P1. In addition, a grinding or etching process is performed on the other surface 110K of the support wafer 110 to thin the support wafer 110. Then, a conductive layer 118, such as an aluminum (Al) layer, is deposited on the top surface 110T of the thinned support wafer 110.
接著,參閱第6圖,於步驟S105,經由切割製程去除在切割道SL上,位於兩條預切割線151和152之間的支撐晶圓110的一部分和元件晶圓120的一部分120P,使得孔洞140暴露於環境壓力下,並且在切割道SL上的接合墊154也可藉 由切割製程暴露出來。於步驟S105,在第一MEMS元件122正上方的第一空腔112仍保持步驟S103的第一壓力P1。另外,在第二鍵合密封環125B中的孔洞140則暴露出來並作為通氣孔,以調節第二空腔114內的壓力,使得第二空腔114內的壓力可以被調節成不同於第一壓力P1的第二壓力P2。此外,於一些實施例中,在調節第二空腔114內的壓力之製程步驟期間,可以通過通氣孔/孔洞140,讓抗黏附塗層145順向地沉積在第二元件基板120B上,以包裹第二MEMS元件124。於一些實施例中,抗黏附塗層145可以是經由氣相沉積製程形成的自組裝單層(self-assembled monolayer,SAM)塗層。抗黏附塗層145的組成可以是有機材料,例如1H,1H,2H,2H-全氟癸基三氯矽烷(perfluorodecyltrichlorosilane,FDTS)、十八烷基三氯矽烷(octadecyltrichlorosilane,OTS)或二氯二甲基矽烷(dichlorodimethylsilane,DDMS),但不限於此。 Next, referring to FIG. 6 , in step S105, a portion of the support wafer 110 and a portion 120P of the device wafer 120 located between the two pre-cut lines 151 and 152 on the scribe line SL are removed by a dicing process, so that the hole 140 is exposed to the ambient pressure, and the bonding pad 154 on the scribe line SL is also exposed by the dicing process. In step S105, the first cavity 112 directly above the first MEMS element 122 still maintains the first pressure P1 of step S103. In addition, the hole 140 in the second bonding seal ring 125B is exposed and used as a vent to adjust the pressure in the second cavity 114, so that the pressure in the second cavity 114 can be adjusted to a second pressure P2 different from the first pressure P1. Furthermore, in some embodiments, during the process step of adjusting the pressure in the second cavity 114, the anti-adhesion coating 145 can be sequentially deposited on the second device substrate 120B through the vent/hole 140 to wrap the second MEMS device 124. In some embodiments, the anti-adhesion coating 145 can be a self-assembled monolayer (SAM) coating formed by a vapor deposition process. The composition of the anti-adhesion coating 145 can be an organic material, such as 1H,1H,2H,2H-perfluorodecyltrichlorosilane (FDTS), octadecyltrichlorosilane (OTS) or dichlorodimethylsilane (DDMS), but is not limited thereto.
之後,參閱第7圖,於步驟S107,通過毯覆式沉積製程,例如化學氣相沉積(chemical vapor deposition,CVD)、物理氣相沉積(physical vapor deposition,PVD)或原子層沉積(atomic layer deposition,ALD)製程,在互連層132上沉積介電材料層161,以在第二壓力P2下重新密封通氣孔/孔洞140。此外,介電材料層161也會沉積在導電層118A和118B上,介電材料層161的組成例如是氧化矽。之後,經由蝕刻製程去除位於導電層118A和118B上的介電材料層161的那些部分,以暴露出導電層118A和118B。另外,在互連層132上的介電材料層161的另一部分也可經由此蝕刻製程被去除,以形成介電膜160,並且暴露出位於切割道SL的接合墊154。此外,通氣孔/孔洞140的一部分可被介電膜160填充,以完成第2圖的微機電封裝100。 Thereafter, referring to FIG. 7 , in step S107 , a dielectric material layer 161 is deposited on the interconnect layer 132 by a blanket deposition process, such as a chemical vapor deposition (CVD), a physical vapor deposition (PVD) or an atomic layer deposition (ALD) process, to reseal the vent/hole 140 under a second pressure P2. In addition, the dielectric material layer 161 is also deposited on the conductive layers 118A and 118B, and the composition of the dielectric material layer 161 is, for example, silicon oxide. Afterwards, the portions of the dielectric material layer 161 located on the conductive layers 118A and 118B are removed by an etching process to expose the conductive layers 118A and 118B. In addition, another portion of the dielectric material layer 161 on the interconnect layer 132 may also be removed by this etching process to form a dielectric film 160 and expose the bonding pad 154 located on the scribe line SL. In addition, a portion of the vent/hole 140 may be filled with the dielectric film 160 to complete the MEMS package 100 of FIG. 2.
第8圖、第9圖和第10圖是根據本揭露另一實施例所繪示的微機電封裝100的製造方法之一些中間階段的剖面示意圖。參閱第8圖,於步驟S201,首先提供支撐晶圓110,並且在支撐晶圓110中形成第一空腔112和第二空腔114。然 後,在支撐晶圓110上以及第一空腔112和第二空腔114內順向地沉積鍵合層116,以包裹支撐晶圓110。之後,提供元件晶圓120,並且將元件晶圓120鍵合至支撐晶圓110,以覆蓋第一空腔112和第二空腔114。如第8圖所示,元件晶圓120包含具有第一MEMS元件122的第一元件基板120A,具有第二MEMS元件122的第二元件基板120B,對應於第一MEMS元件122的第一鍵合密封環125A,對應於第二MEMS元件124的第二鍵合密封環125B,以及位於兩條預切割線151和152之間的元件晶圓120的一部分120P。另外,在第一鍵合密封環125A和第二鍵合密封環125B上形成鍵合材料126。 FIG. 8, FIG. 9 and FIG. 10 are cross-sectional schematic diagrams of some intermediate stages of a manufacturing method of a micro-electromechanical system package 100 according to another embodiment of the present disclosure. Referring to FIG. 8, in step S201, a support wafer 110 is first provided, and a first cavity 112 and a second cavity 114 are formed in the support wafer 110. Then, a bonding layer 116 is sequentially deposited on the support wafer 110 and in the first cavity 112 and the second cavity 114 to wrap the support wafer 110. Thereafter, a device wafer 120 is provided, and the device wafer 120 is bonded to the support wafer 110 to cover the first cavity 112 and the second cavity 114. As shown in FIG. 8 , the device wafer 120 includes a first device substrate 120A having a first MEMS device 122, a second device substrate 120B having a second MEMS device 122, a first bonding sealing ring 125A corresponding to the first MEMS device 122, a second bonding sealing ring 125B corresponding to the second MEMS device 124, and a portion 120P of the device wafer 120 located between two pre-cut lines 151 and 152. In addition, a bonding material 126 is formed on the first bonding sealing ring 125A and the second bonding sealing ring 125B.
在此實施例中,於步驟S201,形成如第3圖所示的孔洞142,其垂直地穿過鍵合材料126和第二鍵合密封環125B,並且進一步延伸以垂直地穿過第二元件基板120B,藉此暴露出鍵合層116的一部分。另外,可以藉由相同的蝕刻製程,例如深反應離子蝕刻(DRIE)製程,以同時形成預切割線151和152、第一MEMS元件122和第二MEMS元件124兩者的溝槽以及孔洞142。步驟S201的其他細節可參考前述第5圖中步驟S101的說明,在此不再重複。 In this embodiment, in step S201, a hole 142 as shown in FIG. 3 is formed, which vertically passes through the bonding material 126 and the second bonding sealing ring 125B, and further extends to vertically pass through the second element substrate 120B, thereby exposing a portion of the bonding layer 116. In addition, the pre-cut lines 151 and 152, the trenches of the first MEMS element 122 and the second MEMS element 124, and the hole 142 can be formed simultaneously by the same etching process, such as a deep reactive ion etching (DRIE) process. For other details of step S201, please refer to the description of step S101 in FIG. 5 above, which will not be repeated here.
仍參閱第8圖,於步驟S202,藉由使用蒸氣氫氟酸(vapor hydrofluoric acid,VHF)的蝕刻製程,經由第一MEMS元件122和第二MEMS元件124兩者的溝槽以及預切割線151和152,以去除在第一空腔112和第二空腔114內以及位於元件晶圓120和支撐晶圓110之間的鍵合層116的一些部分。此外,位於第二元件基板120B和支撐晶圓110之間的鍵合層116的一部分也可藉由使用VHF的此蝕刻製程,經由孔洞142被去除,以形成通氣孔140,通氣孔140連接到第二空腔114和孔洞142。 Still referring to FIG. 8, in step S202, by using a vapor hydrofluoric acid (VHF) etching process, through the trenches of the first MEMS element 122 and the second MEMS element 124 and the pre-cut lines 151 and 152, some portions of the bonding layer 116 in the first cavity 112 and the second cavity 114 and between the element wafer 120 and the support wafer 110 are removed. In addition, a portion of the bonding layer 116 between the second element substrate 120B and the support wafer 110 can also be removed through the hole 142 by using this VHF etching process to form a vent 140, which is connected to the second cavity 114 and the hole 142.
接著,參閱第9圖,於步驟S203,將鍵合後的支撐晶圓110和元件晶圓120上下翻轉,其中第一空腔112位於第一MEMS元件122正上方,第二空腔114位於第二MEMS元件124正上方。然後,提供晶圓130,其上形成有互連層132, 在第一壓力P1下,通過鍵合材料126將元件晶圓120鍵合至晶圓130上的互連層132。之後,在第二鍵合層116B中形成通氣孔140,於後續製程中,通氣孔140可用來調節第二空腔114內的壓力。步驟S203的其他細節可參考前述第5圖中步驟S103的說明,在此不再重複。 Next, referring to FIG. 9, in step S203, the bonded support wafer 110 and the component wafer 120 are turned upside down, wherein the first cavity 112 is located directly above the first MEMS component 122, and the second cavity 114 is located directly above the second MEMS component 124. Then, a wafer 130 is provided, on which an interconnection layer 132 is formed, and the component wafer 120 is bonded to the interconnection layer 132 on the wafer 130 through the bonding material 126 under a first pressure P1. Thereafter, a vent hole 140 is formed in the second bonding layer 116B, and the vent hole 140 can be used to adjust the pressure in the second cavity 114 in the subsequent process. For other details of step S203, please refer to the description of step S103 in Figure 5 above, which will not be repeated here.
然後,參閱第10圖,於步驟S205,經由切割製程去除在切割道SL上位於兩條預切割線151和152之間的支撐晶圓110的一部分和元件晶圓120的一部分120P,讓通氣孔140暴露於環境壓力下,並且在第二鍵合密封環125B和第二元件基板120B兩者中的孔洞142以及第二空腔114也暴露在環境壓力下。此外,於步驟S205,在第一MEMS元件122正上方的第一空腔112仍維持在步驟S203的第一壓力P1。於此實施例中,通氣孔140可用於調整第二空腔114內的壓力至所需的真空度,使得第二空腔114具有第二壓力P2,其不同於第一空腔112內的第一壓力P1。另外,在一些實施例中,於步驟S205進行期間,通過通氣孔140可讓抗黏附塗層145順向地沉積在第二元件基板120B上,以包裹第二MEMS元件124。步驟S205的其他細節可參考前述第6圖中的步驟S105的說明,在此不再重複。 Then, referring to FIG. 10, in step S205, a portion of the support wafer 110 and a portion 120P of the device wafer 120 located between the two pre-cut lines 151 and 152 on the scribe line SL are removed by a dicing process, so that the vent hole 140 is exposed to the ambient pressure, and the hole 142 in both the second bonding seal ring 125B and the second device substrate 120B and the second cavity 114 are also exposed to the ambient pressure. In addition, in step S205, the first cavity 112 directly above the first MEMS device 122 is still maintained at the first pressure P1 of step S203. In this embodiment, the vent hole 140 can be used to adjust the pressure in the second cavity 114 to the required vacuum level, so that the second cavity 114 has a second pressure P2, which is different from the first pressure P1 in the first cavity 112. In addition, in some embodiments, during step S205, the anti-adhesion coating 145 can be deposited on the second element substrate 120B through the vent hole 140 to wrap the second MEMS element 124. For other details of step S205, please refer to the description of step S105 in Figure 6 above, which will not be repeated here.
另外,於此實施例中,如第3圖所示,由於預切線152具有對應於孔洞142位置的突出部分152P,在步驟S205的切割製程之後,第二支撐基板110B和第二元件基板120B可構成如第10圖之剖面示意圖所示的台階結構150,並且通氣孔140位於台階結構150中。 In addition, in this embodiment, as shown in FIG. 3, since the pre-cut line 152 has a protruding portion 152P corresponding to the position of the hole 142, after the cutting process in step S205, the second supporting substrate 110B and the second element substrate 120B can form a step structure 150 as shown in the cross-sectional schematic diagram of FIG. 10, and the vent hole 140 is located in the step structure 150.
接著,仍參考第10圖,於步驟S207,在台階結構150的平台上沉積介電材料層161,以在第二壓力P2下重新密封通氣孔140。此外,介電材料層161也可沉積在互連層132上,且位於第一鍵合密封環125A和第二鍵合密封環125B周圍,同時,介電材料層161還可沉積在導電層118A和118B上。於一些實施例中,可以經由毯覆式沉積製程,例如CVD、PVD或ALD製程形成介電材料層161,介電材料層161的組成例如為氧化矽。然後,可以經由蝕刻製程去除位於導電層 118A和118B上的介電材料層161的一部分,以暴露出導電層118A和118B。此外,在互連層132上的介電材料層161的另一部分也可通過此蝕刻製程被去除,以形成介電膜160,並且暴露出在切割道SL的接合墊154。另外,還可通過此蝕刻製程去除在台階結構150的平台上的介電材料層161的一部分,以形成密封層170,且密封層170填充通氣孔140,以完成第4圖的微機電封裝100。 Next, still referring to FIG. 10 , in step S207 , a dielectric material layer 161 is deposited on the platform of the terrace structure 150 to reseal the vent hole 140 under the second pressure P2. In addition, the dielectric material layer 161 may also be deposited on the interconnect layer 132 and around the first bonding seal ring 125A and the second bonding seal ring 125B. At the same time, the dielectric material layer 161 may also be deposited on the conductive layers 118A and 118B. In some embodiments, the dielectric material layer 161 may be formed by a blanket deposition process, such as a CVD, PVD, or ALD process, and the composition of the dielectric material layer 161 may be, for example, silicon oxide. Then, a portion of the dielectric material layer 161 on the conductive layers 118A and 118B may be removed by an etching process to expose the conductive layers 118A and 118B. In addition, another portion of the dielectric material layer 161 on the interconnect layer 132 may also be removed by this etching process to form a dielectric film 160 and expose the bonding pad 154 on the dicing line SL. In addition, a portion of the dielectric material layer 161 on the platform of the step structure 150 may also be removed by this etching process to form a sealing layer 170, and the sealing layer 170 fills the vent hole 140 to complete the MEMS package 100 of FIG. 4.
根據本揭露的實施例,微機電封裝包含在不同壓力下封裝的各種MEMS元件。於一些實施例中,MEMS封裝可包含慣性測量單元(IMU),且慣性測量單元可包含例如為陀螺儀的第一MEMS元件,以及例如為加速度計的第二MEMS元件,第一MEMS元件和第二MEMS元件需要不同的真空度和不同的抗黏附要求,並且整合在同一個晶片上。於一實施例中,可設置一個或多個通氣孔側向穿過第二鍵合密封環,並且通氣孔連接到第二空腔,以調節第二空腔內的壓力,這些通氣孔的高度大致上相同於第二鍵合密封環的厚度。於另一實施例中,可以在第二元件基板和第二支撐基板之間的第二鍵合層中形成一個或多個通氣孔,並且通氣孔連接到第二空腔體,以調節第二空腔內的壓力,這些通氣孔的高度大致上相同於第二鍵合層的厚度。根據本揭露的實施例,在元件晶圓鍵合至支撐晶圓和CMOS晶圓之後,可以通過通氣孔調節第二空腔內的第二壓力,使得第二壓力不同於第一空腔內的第一壓力。 According to an embodiment of the present disclosure, a microelectromechanical package includes various MEMS components packaged under different pressures. In some embodiments, the MEMS package may include an inertial measurement unit (IMU), and the inertial measurement unit may include a first MEMS component such as a gyroscope, and a second MEMS component such as an accelerometer, the first MEMS component and the second MEMS component requiring different vacuum levels and different anti-adhesion requirements, and integrated on the same chip. In one embodiment, one or more vents may be provided laterally through the second keyed sealing ring, and the vents are connected to the second cavity to adjust the pressure in the second cavity, and the height of these vents is substantially the same as the thickness of the second keyed sealing ring. In another embodiment, one or more vents may be formed in the second bonding layer between the second component substrate and the second supporting substrate, and the vents are connected to the second cavity to adjust the pressure in the second cavity, and the height of these vents is substantially the same as the thickness of the second bonding layer. According to the embodiment disclosed herein, after the component wafer is bonded to the supporting wafer and the CMOS wafer, the second pressure in the second cavity may be adjusted through the vents so that the second pressure is different from the first pressure in the first cavity.
另外,在調節第二空腔內的壓力之製程步驟期間,還可以通過通氣孔在第二MEMS元件上形成抗黏附塗層。此外,微機電封裝在通氣孔外側還可包含平台結構,藉由在平台結構上沉積介電膜,可以很容易地重新密封高度較小的通氣孔,進而改善密封通氣孔的可靠度。因此,本揭露的微機電封裝能夠在鍵合後調節不同空腔內的壓力,並且在鍵合後於不同MEMS元件上形成抗黏附塗層,使得包含不同空腔壓力的各種MEMS元件之微機電封裝的封裝製程簡化,並且還可以縮減微機電封裝的佔位面積。 In addition, during the process step of adjusting the pressure in the second cavity, an anti-adhesion coating can be formed on the second MEMS element through the vent. In addition, the MEMS package can also include a platform structure outside the vent. By depositing a dielectric film on the platform structure, the vent with a smaller height can be easily re-sealed, thereby improving the reliability of sealing the vent. Therefore, the MEMS package disclosed in the present invention can adjust the pressure in different cavities after bonding, and form an anti-adhesion coating on different MEMS elements after bonding, so that the packaging process of the MEMS package containing various MEMS elements with different cavity pressures is simplified, and the footprint of the MEMS package can also be reduced.
以上所述僅為本發明之較佳實施例,凡依本發明申請專利範圍所做之均等變化與修飾,皆應屬本發明之涵蓋範圍。 The above is only the preferred embodiment of the present invention. All equivalent changes and modifications made according to the scope of the patent application of the present invention shall fall within the scope of the present invention.
100:微機電封裝 100:Micro-electromechanical packaging
100A:第一MEMS區 100A: First MEMS area
100B:第二MEMS區 100B: Second MEMS area
SL:切割道 SL: Cutting Road
110A:第一支撐基板 110A: The first supporting substrate
110B:第二支撐基板 110B: Second supporting substrate
112:第一空腔 112: First cavity
114:第二空腔 114: Second cavity
116A:第一鍵合層 116A: First bonding layer
116B:第二鍵合層 116B: Second bonding layer
118A、118B:導電層 118A, 118B: Conductive layer
120A:第一元件基板 120A: First component substrate
120B:第二元件基板 120B: Second component substrate
122:第一MEMS元件 122: First MEMS element
124:第二MEMS元件 124: Second MEMS element
125A:第一鍵合密封環 125A: First key sealing ring
125B:第二鍵合密封環 125B: Second key sealing ring
126:鍵合材料 126: Bonding materials
127:溝槽 127: Groove
130:晶圓 130: Wafer
132:互連層 132: Interconnection layer
134:保護層 134: Protective layer
140:通氣孔/孔洞 140: Ventilation holes/holes
145:抗黏附塗層 145: Anti-adhesion coating
154:接合墊 154:Joint pad
160:介電膜 160: Dielectric film
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| TW (1) | TWI850094B (en) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW201131710A (en) * | 2010-02-26 | 2011-09-16 | Xintec Inc | Chip package and fabrication method thereof |
| US20190245515A1 (en) * | 2018-02-05 | 2019-08-08 | Zhuhai Crystal Resonance Technologies Co., Ltd. | Single crystal piezoelectric rf resonators and filters with improved cavity definition |
| TW202314964A (en) * | 2021-09-09 | 2023-04-01 | 美商英特爾股份有限公司 | Microelectronic assemblies having backside die-to-package interconnects |
-
2023
- 2023-09-01 TW TW112133199A patent/TWI850094B/en active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW201131710A (en) * | 2010-02-26 | 2011-09-16 | Xintec Inc | Chip package and fabrication method thereof |
| US20190245515A1 (en) * | 2018-02-05 | 2019-08-08 | Zhuhai Crystal Resonance Technologies Co., Ltd. | Single crystal piezoelectric rf resonators and filters with improved cavity definition |
| TW202314964A (en) * | 2021-09-09 | 2023-04-01 | 美商英特爾股份有限公司 | Microelectronic assemblies having backside die-to-package interconnects |
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| TW202512408A (en) | 2025-03-16 |
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