TWI849716B - Hybrid ims cam cell, memory device and data search method - Google Patents

Abstract

A hybrid in-memory search (IMS) content addressable memory (CAM) cell includes: a first IMS CAM cell; and a second IMS CAM cell, coupled to the first IMS CAM cell. The first IMS CAM cell and the second IMS CAM cell are of different types. When the hybrid IMS CAM cell stores a storage data, the first IMS CAM cell stores a first part of the storage data and the second IMS CAM cell stores the storage data or a second part of the storage data.

Description

Hybrid in-memory search (IMS) content-addressable memory (CAM) unit, memory device, and data search method

The present invention relates to a hybrid in-memory search (IMS) content-addressable memory (CAM) unit, a memory device and a data search method.

With the rise of big data and artificial intelligence (AI) hardware accelerators, data search and data comparison are important functions. Existing ternary content addressable memory (TCAM) can be used to achieve highly parallel searching. Traditional TCAM is usually composed of static random access memory (SRAM), so the memory density is low and the access power is high. In order to save power consumption through dense memory density, a non-volatile memory array based on TCAM has been proposed recently.

Existing NAND-type in-memory search (IMS) can perform exact-matching operations. However, exact-matching operations limit match flexibility. Therefore, in-memory approximate search (IMAS) is proposed to provide approximate search to achieve fuzzy comparison function to improve match flexibility.

Therefore, a new IMS CAM approach is needed that can provide a high accuracy, high content density and stable search system.

According to one aspect of the present invention, a hybrid in-memory search (IMS) content addressable memory (CAM) unit is provided, comprising: a first IMS CAM unit cell; and a second IMS CAM unit cell coupled to the first IMS CAM unit cell, wherein the first IMS CAM unit cell and the second IMS CAM unit cell are of different types, and when the hybrid IMS CAM unit stores a storage data, the first IMS CAM unit cell stores a first part of the storage data, and the second IMS CAM unit cell stores the storage data or a second part of the storage data.

According to another aspect of the present invention, a hybrid in-memory search (IMS) content-addressable memory (CAM) memory device is provided, comprising: a hybrid IMS CAM memory array, comprising a plurality of hybrid IMS CAM cells, a plurality of word lines, and a plurality of bit lines, wherein the hybrid IMS CAM cells are coupled to the word lines and the bit lines; a word line driving circuit coupled to the word lines for applying a plurality of search voltages to the hybrid IMS CAM cells according to a plurality of search data to search the hybrid IMS CAM cells; a bit line driving circuit coupled to the bit lines for applying a plurality of bit line driving voltages to the bit lines; and a sense amplifier coupled to the hybrid IMS The CAM unit is used to receive a plurality of induced currents transmitted by the hybrid IMS CAM units to determine whether the search data matches a plurality of stored data in the hybrid IMS CAM units. The hybrid IMS CAM unit includes: a first IMS CAM unit cell; and a second IMS CAM unit cell coupled to the first IMS CAM unit cell. The first IMS CAM unit cell and the second IMS CAM unit cell are of different types. When the hybrid IMS CAM unit stores a stored data, the first IMS CAM unit cell stores a first part of the stored data, and the second IMS CAM unit cell stores the stored data or a second part of the stored data. During data search, a first part of the search data is decoded into a first search voltage and a second search voltage to search for the first part of the stored data stored in the first IMS CAM cell, and the search data or a second part of the search data is decoded into a third search voltage and a fourth search voltage to search for the stored data or the second part of the stored data stored in the second IMS CAM cell.

According to another aspect of the present invention, a hybrid in-memory search (IMS) content-addressable memory (CAM) data search method is provided, comprising: storing a storage data in a hybrid IMS CAM unit, the hybrid IMS CAM unit comprising: a first IMS CAM unit cell, and a second IMS CAM unit cell coupled to the first IMS CAM unit cell, wherein the first IMS CAM unit cell and the second IMS CAM unit cell are of different types, and when the hybrid IMS CAM unit stores the storage data, the first IMS CAM unit cell stores a first part of the storage data, and the second IMS CAM unit cell stores the storage data or a second part of the storage data; searching the storage data for the hybrid IMS The CAM unit performs a data search, wherein during the data search, a first part of the search data is decoded into a first search voltage and a second search voltage to search for the first part of the stored data stored in the first IMS CAM cell, and the search data or a second part of the search data is decoded into a third search voltage and a fourth search voltage to search for the stored data or the second part of the stored data stored in the second IMS CAM cell; a sensing current generated by the hybrid IMS CAM unit is sensed to generate a sensing result; and whether the search data matches the stored data is determined based on the sensing result.

In order to better understand the above and other aspects of the present invention, the following is a specific example and a detailed description with the attached drawings as follows:

100: Search CAM unit in hybrid memory

110: Approximate search for CAM cells in unit cell memory

120: Analog IMS CAM cell

T1-T4: Flash memory cell

SL_1, SL_2, VA, VB: Search voltage

I1~I6: current

S: Search data

S_1: The first part of the search data

S_2: The second part of searching data

Fn: Features

Fn_1: The first part of the characteristics

Fn_2: The second part of the characteristics

1100: Searching for CAM memory device in hybrid memory

1110: Searching for CAM memory array in hybrid memory

1120: word line driver circuit

1130: Bit line driver circuit

1140: Inductive amplifier

WL1~WLn: character line

BL1~BLm: bit line

1200A-1200D: Hybrid in-memory search CAM unit

1210A-1210D: First IMS CAM cell

1220A-1220D: Second IMS CAM cell

1310, 1320: SLC IMS CAM cell

1410, 1420, 1430, 1440: MLC IMS CAM cell

1500:MLC IMAS CAM cell

M1, M2: transistors

d1, d2: drain

s1, s2: source

g1, g2: gate

BL1: bit line

WL1(1), WL1(2): character line

1610-1640: Steps

Figure 1 shows a hybrid in-memory search (Hybrid IMS) content addressable memory (CAM) unit in an embodiment of the present invention.

Figure 2A shows the relationship between the number of cells and the critical voltage in an embodiment of the present invention.

Figure 2B shows the relationship between the search voltage (SL_1, SL_2) and the cell current according to an embodiment of the present invention.

Figure 3A shows the voltage-current curve of an analog IMS CAM cell according to an embodiment of the present invention.

FIG. 3B shows another voltage-current curve diagram of an analog IMS CAM cell according to an embodiment of the present invention.

Figure 4 shows a schematic diagram of the match range according to an embodiment of the present invention.

Figures 5A to 5C show schematic diagrams of the matching range of an analog IMS CAM cell according to an embodiment of the present invention.

Figures 6A and 6B show schematic diagrams of matching current of an analog IMS CAM cell according to an embodiment of the present invention.

Figure 7 shows a schematic diagram of the matching range of an analog IMS CAM cell according to an embodiment of the present invention.

Figure 8 shows a schematic diagram of extracting features from an image.

Figures 9A and 9B show the first data storage and search method according to an embodiment of the present invention.

Figures 10A and 10B show the second data storage and search method according to an embodiment of the present invention.

FIG. 11 shows a circuit diagram of a hybrid memory search CAM memory device according to an embodiment of the present invention.

Figures 12A to 12D show examples of hybrid memory intra-memory search CAM units according to other embodiments of the present invention.

Figures 13A and 13B show schematic diagrams of an SLC IMS CAM cell according to an embodiment of the present invention.

Figures 14A to 14D show schematic diagrams of an MLC IMS CAM cell and its operation according to an embodiment of the present invention.

Figures 15A to 15G show the MLC IMAS CAM cell and its operation schematic diagram according to an embodiment of the present invention.

FIG. 16 shows a hybrid in-memory search (IMS) content-addressable memory (CAM) data search method according to an embodiment of the present invention.

The technical terms in this specification refer to the customary terms in this technical field. If this specification explains or defines some terms, the interpretation of these terms shall be based on the explanation or definition in this specification. Each embodiment disclosed in this disclosure has one or more technical features. Under the premise of possible implementation, a person with ordinary knowledge in this technical field can selectively implement part or all of the technical features in any embodiment, or selectively combine part or all of the technical features in these embodiments.

Please refer to FIG. 1, which illustrates a hybrid IMS content addressable memory (CAM) unit in an embodiment of the present invention. As shown in FIG. 1, the hybrid IMS CAM unit 100 includes: a single level cell (SLC) intra-memory proximity search (IMAS) CAM cell 110 and an analog IMS CAM cell 120.

In an embodiment of the present case, the hybrid intra-memory search CAM unit can provide high array density, high accuracy and acceptable stability. Taking FIG. 1 as an example, the hybrid intra-memory search CAM unit 100 includes, for example but not limited to, a unit cell intra-memory approximate search CAM unit 110 and an analog IMS CAM unit 120. The unit cell intra-memory approximate search CAM unit 110 has high system stability and can be used for coarse-matching. The analog IMS CAM unit 120 can be used for analog value comparison to improve accuracy and can be used for fine-matching.

The single-bit cell memory intra-scan proximity search CAM cell 110 includes serially connected flash memory cells T1 and T2, and the analog IMS CAM cell 120 includes serially connected flash memory cells T3 and T4. The flash memory cells T1~T4 are, for example but not limited to, floating gate memory cells, Silicon-Oxide-Nitride-Oxide-Silicon (SONOS) memory cells, floating dot memory cells, Ferroelectric FET (FeFET) memory cells, Resistive Random Access Memory (RRAM), Phase-change memory, Conductive-bridging RAM (CBRAM), etc.

The gate of the flash memory cell T1 receives the first search voltage SL_1, the gate of the flash memory cell T2 receives the second search voltage SL_2, and the source of the flash memory cell T1 is electrically connected to the source of the flash memory cell T2. The drain of the flash memory cell T1 is electrically connected to other signal lines (not shown). The drain of the flash memory cell T2 is electrically connected to the drain of the flash memory cell T3 of the analog IMS CAM cell 120.

The gate of the flash memory cell T3 receives the third search voltage VA, the gate of the flash memory cell T4 receives the fourth search voltage VB, and the source of the flash memory cell T3 is electrically connected to the source of the flash memory cell T4. The drain of the flash memory cell T3 is electrically connected to the drain of the flash memory cell T2. The drain of the flash memory cell T4 is electrically connected to other signal lines (not shown).

The details of the approximate search CAM cell 110 and the analog IMS CAM cell 120 in the unit-bit cell memory of an embodiment of the present invention will now be described.

The storage data of the approximate search CAM cell 110 in the unit cell memory is determined by the combination of multiple critical voltages of the (first) flash memory cell T1 and the (second) flash memory cell T2.

Please refer to Figure 2A and Figure 2B. Figure 2A shows the relationship between the number of cells and the critical voltage in an embodiment of the present invention. Figure 2B shows the relationship between the search voltage (SL_1, SL_2) and the cell current according to an embodiment of the present invention.

As shown in FIG. 2A, in an embodiment of the present invention, the high reference critical voltage (HVT) is, for example but not limited to, 3-4V, and the low reference critical voltage (LVT) is, for example but not limited to, less than 0V. In addition, the reference search voltages VH1 and VH2 represent possible values of the first search voltage SL_1 and/or the second search voltage SL_2. For example, but not limited to, the reference search voltages VH1 and VH2 can be 5V and 8V respectively, that is, VH1 is less than VH2.

In an embodiment of the present case, the critical voltage of the flash memory cell T1 (also referred to as the first critical voltage), the critical voltage of the flash memory cell T2 (also referred to as the second critical voltage), the first search voltage SL_1 and the second search voltage SL_2 may be set as shown in the following table, wherein when performing data comparison, the search data is decoded into the first search voltage SL_1 and the second search voltage SL_2:

In an embodiment of the present case, when the stored data is the first predetermined stored data (1), the first critical voltage is the high reference critical voltage (HVT), and the second critical voltage is the low reference critical voltage (LVT); when the stored data is the second predetermined stored data (0), the first critical voltage is the low reference critical voltage (LVT), and the second critical voltage is the high reference critical voltage (HVT); when the stored data is the third predetermined stored data (X(don’t care), the first critical voltage and the second critical voltage are both high reference critical voltage (HVT); when the stored data is the fourth predetermined stored data (i.e. invalid data), the first critical voltage and the second critical voltage are both low reference critical voltage (LVT). That is, in one embodiment of the present case, the stored data of the SLC IMAS CAM cell 110 is determined by the combination of the first critical voltage of the flash memory cell T1 and the second critical voltage of the flash memory cell T2.

In an embodiment of the present case, when the search data is the first predetermined search data (1), the first search voltage SL_1 is the first reference search voltage (VH1), and the second search voltage SL_2 is the second reference search voltage (VH2); when the search data is the second predetermined search data (0), the first search voltage SL_1 is the second reference search voltage (VH2), and the second search voltage SL_2 is the first reference search voltage (VH1); When the search data is the third predetermined search data (WC), the first search voltage SL_1 and the second search voltage SL_2 are both the second reference search voltage (VH2); and when the search data is the fourth predetermined search data (invalid search), the first search voltage SL_1 and the second search voltage SL_2 are both the first reference search voltage (VH1), wherein the first reference search voltage (VH1) is lower than the second reference search voltage (VH2).

As shown in FIG. 2B , in one embodiment of the present invention, the voltage difference between the search voltage and the critical voltage is referred to as a gate overdrive voltage (GO). In a matched state, the gate overdrive voltage exceeds a threshold value, and the flash memory cell T1/T2 provides a high cell current; conversely, in a mismatched state, the gate overdrive voltage is lower than the threshold value, and the flash memory cell T1/T2 provides a low cell current. Taking FIG. 2B as an example, the reference search voltages VH1 and VH2 may be 5V and 8V respectively, the high reference critical voltage may be, for example but not limited to, 3~4V, and the low reference critical voltage may be, for example but not limited to, less than 0V. The gate overdrive voltage between the reference search voltage VH2 (8V) and the high reference critical voltage (3~4V) is approximately 4~5V, which can be regarded as a high gate overdrive voltage; the gate overdrive voltage between the reference search voltage VH2 (8V) and the low reference critical voltage (less than 0V) is approximately greater than 8V, which can be regarded as a high gate overdrive voltage; The gate overdrive voltage between the reference search voltage VH1 (5V) and the high reference critical voltage (3~4V) is about 1~2V, which can be regarded as a low gate overdrive voltage; the gate overdrive voltage between the reference search voltage VH1 (5V) and the low reference critical voltage (less than 0V) is about greater than 5V, which can be regarded as a high gate overdrive voltage.

In detail, when the search voltage is the second reference search voltage (VH2), regardless of whether the critical voltage of the flash memory cell T1/T2 is the low reference critical voltage (LVT) or the high reference critical voltage (HVT), the gate overdrive voltage of the flash memory cell T1/T2 exceeds the threshold value, so the cell current of the flash memory cell T1/T2 is the high reference cell current (I1). When the search voltage is the first reference search voltage (VH1), (1) if the critical voltage of the flash memory cell T1/T2 is the low reference critical voltage (LVT), the gate overdrive voltage of the flash memory cell T1/T2 exceeds the threshold value, so the cell current of the flash memory cell T1/T2 is approximately the high reference critical voltage (LVT). cell current (I1); and, (2) if the critical voltage of the flash memory cell T1/T2 is the high reference critical voltage (HVT), the gate overdrive voltage of the flash memory cell T1/T2 is lower than the threshold value, so the cell current of the flash memory cell T1/T2 is approximately the low reference cell current (I2).

In one example, when the high reference critical voltage (HVT) is 3~4V, the low reference critical voltage (LVT) is less than 0V, and the reference search voltages VH1 and VH2 are 5V and 8V respectively, the high reference cell current (I1) and the low reference cell current (I2) are, for example but not limited to, 100~500nA and 1~99nA respectively.

In an embodiment of the present case, the matching relationship between the search data and the storage data of the SLC IMAS CAM cell 110 is shown in the following table:

X：不導通(或低閘極過驅動電壓)O：導通(或高閘極過驅動電壓)

X: No conduction (or low gate overdrive voltage) O: Conduction (or high gate overdrive voltage)

Therefore, when the search data is 1 and the storage data is 0, the flash memory cell T1 is not turned on and the flash memory cell T2 is turned on, so the cell current of the SLC IMAS CAM cell 110 is the low reference cell current (I2), that is, the search result is not matched. Similarly, when the search data is 0 and the storage data is 0, the flash memory cell T1 is turned on and the flash memory cell T2 is turned on, so the cell current of the SLC IMAS CAM cell 110 is the high reference cell current (I1), that is, the search result is matched. The rest can be deduced in this way.

When searching the SLC IMAS CAM cell 110, when the search data matches the stored data, the cell current of the SLC IMAS CAM cell 110 is a high reference cell current (I1), indicating that the search result is a match; when the search data does not match the stored data, the cell current of the SLC IMAS CAM cell 110 is a low reference cell current (I2), indicating that the search result is a mismatch.

When the search data is a wildcard (WC), regardless of the value of the stored data, the cell current of the SLC IMAS CAM cell 110 is a high reference cell current (I1), indicating that the search result is a match; when the search data is an invalid search, regardless of whether the stored data is 1 or 0 or invalid data, the cell current of the SLC IMAS CAM cell 110 is a low reference cell current (I2), indicating that the search result is a mismatch.

When the stored data is X (don’t care, not important), regardless of the search data value, the cell current of the SLC IMAS CAM cell 110 is the high reference cell current (I1), indicating that the search result is a match. When the stored data is invalid data, regardless of the search data is 1 or 0 or invalid search, the cell current of the SLC IMAS CAM cell 110 is the low reference cell current (I2), indicating that the search result is a mismatch.

The details of the analog IMS CAM cell 120 according to an embodiment of the present invention will now be described. The analog storage data stored in the analog IMS CAM cell 120 is searched by analog search data. By adjusting the critical voltages of the flash memory cells T3 and T4 of the analog IMS CAM cell 120, different matching ranges can be established. The third search voltage (which is the analog search voltage) VA and the fourth search voltage (which is the analog search voltage) VB are input to the flash memory cells T3 and T4 respectively through different word lines.

FIG. 3A shows a voltage-current curve of an analog IMS CAM cell 120 according to an embodiment of the present invention. In FIG. 3A, the critical voltage of the flash memory cell T3 is represented as VT_A (or the third critical voltage), and the critical voltage of the flash memory cell T4 is represented as VT_B (or the fourth critical voltage). The critical voltages VT_A and VT_B can be independently programmed to any critical voltage value as needed.

Channel current IA represents the channel current flowing through flash memory cell T3. Channel current IB represents the channel current flowing through flash memory cell T4.

In an embodiment of the present case, the relationship between the third search voltage VA and the fourth search voltage VB is, for example but not limited to: VB=Vmax+Vmin-VA, where Vmax and Vmin represent the maximum value of the analog search voltage and the minimum value of the analog search voltage, respectively, and are both constants. For example but not limited to, Vmax=9V and Vmin=0V.

In an embodiment of the present case, when the minimum reference voltage value Vmin is greater than or equal to 0V, the third search voltage VA and the fourth search voltage VB are both positive values; when the maximum reference voltage value Vmax is less than or equal to 0V, the third search voltage VA and the fourth search voltage VB are both negative values; and, when the maximum reference voltage value Vmax is greater than 0V and the minimum reference voltage value Vmin is less than 0V, one of the third search voltage VA and the fourth search voltage VB is positive and the other is negative.

As shown in Figure 3A, when VA=0.7V and VB=8.3V, flash memory cell T3 has no current and flash memory cell T4 has current. Or, when VA=4.05V and VB=4.95V, both flash memory cell T3 and flash memory cell T4 have no current. Or, when VA=8.52V and VB=0.48V, flash memory cell T3 has current, but flash memory cell T4 has no current.

FIG. 3B shows another voltage-current curve of the analog IMS CAM cell 120 according to an embodiment of the present invention. The critical voltages VT_A and VT_B in FIG. 3B are both smaller than the critical voltages VT_A and VT_B in FIG. 3A.

As shown in Figure 3B, when VA=0.7V and VB=8.3V, both flash memory cell T3 and flash memory cell T4 have no current. Alternatively, when VA=4.05V and VB=4.95V, both flash memory cell T3 and flash memory cell T4 have current. Alternatively, when VA=8.52V and VB=0.48V, flash memory cell T3 has current, but flash memory cell T4 has no current.

FIG. 4 is a schematic diagram of a match range according to an embodiment of the present invention. In an embodiment of the present invention, the match range can be determined by the voltage-current relationship (i.e., voltage-current relationship curve) of the flash memory cell T3 and the voltage-current relationship (i.e., voltage-current relationship curve) of the flash memory cell T4. In an embodiment of the present invention, the match range is related to the analog storage data of the analog IMS CAM cell 120. For example, but not limited to, the analog storage data of the analog IMS CAM cell 120 is converted into the match range. The matching range is determined by the third critical voltage of the flash memory cell T3 and the fourth critical voltage of the flash memory cell T4 of the analog IMS CAM cell 120.

The analog storage data D has an analog storage data range between the analog storage data minimum value Dmin and the analog storage data maximum value Dmax. For example, but not limited to, in an embodiment of the present case, the analog storage data D of the analog IMS CAM cell 120 may be between 0.00 (Dmin) and 1.00 (Dmax). In an embodiment of the present case, the analog storage data minimum value Dmin and the analog storage data maximum value Dmax can be encoded into the critical voltage minimum value VTmin and the critical voltage maximum value VTmax of the third critical voltage or the fourth critical voltage respectively through the coding principle, that is, the critical voltage minimum value VTmin and the critical voltage maximum value VTmax are determined respectively according to the analog storage data minimum value Dmin and the analog storage data maximum value Dmax. The critical voltage of the flash memory cells T3 and T4 is between the critical voltage minimum value VTmin and the critical voltage maximum value VTmax.

In addition, the analog search data S has an analog search data range between the analog search data minimum value Smin and the analog search data maximum value Smax. For example, but not limited to, in an embodiment of the present case, the analog search data S that can be used to search the analog IMS CAM cell 120 can be between 0.00 (Smin) and 1.00 (Smax). In an embodiment of the present case, through the coding principle, the analog search data minimum value Smin and the analog search data maximum value Smax can be encoded into the third search voltage VA and the fourth search voltage minimum value Vmin and the analog search voltage maximum value Vmax, respectively. After encoding, the analog search data S is converted into the third search voltage VA and the fourth search voltage VB. Among them, the third search voltage VA and the fourth search voltage VB are both continuous values, the third search voltage VA is between the analog search voltage minimum value Vmin and the analog search voltage maximum value Vmax, and VB=Vmax+Vmin-VA.

In FIG. 4, the voltage-current curves are respectively related to critical voltages VT1_A~VTn_A, and critical voltages VT1_B~VTn_B. VT1_A~VTn_A respectively represent n different critical voltages (n is a positive integer) of the flash memory cell T3; and VT1_B~VTn_B respectively represent n different critical voltages of the flash memory cell T4. Among them, VT1_A<VT2_A<...<VTn_A, and VT1_B<VT2_B<...<VTn_B.

The matching range can be determined by the voltage-current relationship of the flash memory cell T3 (i.e., the voltage-current relationship curve) and the voltage-current relationship of the flash memory cell T4 (i.e., the voltage-current relationship curve). For example, but not limited to, when the critical voltages of the flash memory cells T3 and T4 are VT1_A and VT1_B, respectively, one matching range can be determined, and when the critical voltages of the flash memory cells T3 and T4 are VT2_A and VT1_B, respectively, another matching range can be determined.

Figures 5A to 5C show schematic diagrams of the matching range of the analog IMS CAM cell 120 according to an embodiment of the present invention. In an embodiment of the present invention, for example but not limited to, the matching range is between 1.5V and 2.5V, then the range width of the matching range is 2.5V-1.5V=1V, and the maximum and minimum values of the matching range are 2.5V and 1.5V. The maximum and minimum values of the matching range can also be referred to as the position of the matching range.

As shown in FIG. 5A, by changing the critical voltages VT_A and VT_B of the flash memory cells T3 and T4, the range width of the matching range MR can be changed. The definition of the matching range MR will be explained separately below.

As shown in Figure 5B, by changing the critical voltages VT_A and VT_B of the flash memory cells T3 and T4, the maximum and minimum values (positions) of the matching range MR can be changed.

As shown in FIG. 5C, by changing the critical voltages VT_A and VT_B of the flash memory cells T3 and T4, the range width and the maximum and minimum values (positions) of the matching range MR can be changed.

That is, in one embodiment of the present case, by changing the critical voltages VT_A and VT_B of the flash memory cells T3 and T4, the range width and/or position of the matching range MR can be changed.

FIG. 6A and FIG. 6B show matching current schematic diagrams of the analog IMS CAM cell 120 according to an embodiment of the present invention. In an embodiment of the present invention, the matching current value can be changed by changing the critical voltage of the flash memory cell T3 and/or the critical voltage of the flash memory cell T4. Here, the matching current refers to the current output by the flash memory cell T3 or T4 when the analog search data matches the matching range.

As shown in Figure 6A, when the critical voltage of the flash memory cell T4 is VT1_B~VT6_B (VT1_B<VT2_B<...<VT6_B), the matching current values are MC11~MC16, where MC11>MC12...>MC16.

As shown in Figure 6B, when the critical voltage of the flash memory cell T3 is VT1_A~VT6_A (VT1_A<VT2_A<...<VT6_A), the matching current values are MC21~MC26, where MC21>MC22...>MC26.

That is to say, in one embodiment of the present case, by adjusting the critical voltage of the flash memory cell T3 and/or TB, the matching current value can be adjusted.

FIG. 7 shows a schematic diagram of the matching range of the analog IMS CAM cell 120 according to an embodiment of the present invention. As shown in FIG. 7, it is assumed that the maximum value and the minimum value of the third search voltage VA are 4V and 0V respectively, and the fourth search voltage VB (VB=Vmax+Vmin-VA) is between 0V and 4V. The following example is given for illustration, but it should be noted that the present invention is not limited thereto. For example, but not limited to, when the third search voltage VA and the fourth search voltage VB are 1.6V and 2.4V respectively, according to the voltage-current curve of FIG. 7, both the flash memory cells T3 and T4 have current, and this situation is considered to be matched. Therefore, the matching range is defined as when both the flash memory cells T3 and T4 have current.

When the third search voltage VA and the fourth search voltage VB are 3.7V and 0.3V respectively, from the voltage-current curve of Figure 7, the flash memory cell T3 has current but the flash memory cell T4 has no current, and this situation is considered as mismatch. Alternatively, when the third search voltage VA and the fourth search voltage VB are 0.3V and 3.7V respectively, from the voltage-current curve of Figure 7, the flash memory cell T3 has no current but the flash memory cell T4 has current, and this situation is considered as mismatch. Therefore, when one of the flash memory cell T3 and the flash memory cell T4 has current but the other has no current, it is considered as mismatch.

That is, in the analog IMS CAM cell 120 of the first embodiment of the present case, when the third search voltage VA falls within the matching range, both the flash memory cell T3 and the flash memory cell T4 have current, and the analog IMS CAM cell 120 outputs a matching current. When the third search voltage VA falls outside the matching range, one of the flash memory cell T3 and the flash memory cell T4 has current and the other has no current, and the analog IMS CAM cell 120 does not output a matching current.

As described above, in one embodiment of the present case, the analog IMS CAM cell 120 is detected to determine whether it is matched or not by outputting a matching current.

The data search of the hybrid memory search CAM unit 100 according to an embodiment of the present invention will now be described.

FIG. 8 is a schematic diagram showing how to extract features from an image. As shown in FIG. 8 , the feature extractor extracts multiple features from an image. Here, 512 features F1 to F512 are extracted and each feature F1 to F512 has an 8-bit resolution. However, it should be noted that the present invention is not limited thereto. The features F1 to F512 can be stored in the 512 hybrid memory search CAM units 100.

When performing data search and matching, there are two ways to store the feature Fn (n=1-512) in the search CAM unit 100 in the hybrid memory, which will be explained below.

Figures 9A and 9B show the first data storage and search method according to an embodiment of the present invention. Figures 10A and 10B show the second data storage and search method according to an embodiment of the present invention.

In the first data storage and search method according to an embodiment of the present invention shown in FIG. 9A and FIG. 9B , when storing a feature Fn in a hybrid memory search CAM unit 100, a first portion Fn_1 of the feature Fn is stored in an SLC IMAS CAM cell 110; and the feature Fn is stored in an analog IMS CAM cell 120, wherein, for example but not limited to, the first portion Fn_1 of the feature Fn is the most significant bit (MSB) of the feature Fn. During data search, the first portion S_1 of the search data S is used to search for the first portion Fn_1 of the feature Fn stored in the SLC IMAS CAM cell 110; and the search data S is used to search for the feature Fn stored in the analog IMS CAM cell 120. That is, in decimal, for an 8-bit feature value, the feature Fn in the analog IMS CAM cell 120 is 0-255. Specifically, during data search, the first part S_1 of the search data S is decoded into the first search voltage SL_1 and the second search voltage SL_2 to search for the first part Fn_1 of the feature Fn stored in the SLC IMAS CAM cell 110; the search data S is decoded into the third search voltage VA and the fourth search voltage VB to search for the feature Fn stored in the analog IMS CAM cell 120.

In the second data storage and search method according to an embodiment of the present invention shown in Figures 10A and 10B, when the feature Fn is stored in the hybrid memory search CAM unit 100, the first part Fn_1 of the feature Fn is stored in the SLC IMAS CAM cell 110, and the second part Fn_2 of the feature Fn is stored in the analog IMS CAM cell 120, wherein, for example but not limited to, the first part Fn_1 of the feature Fn is the most significant bit (MSB) of the feature Fn, and the second part Fn_2 of the feature Fn is the remaining bits (7 bits) of the feature Fn, that is, the second most significant bit to the least significant bit (LSB) of the feature Fn. During data search, the first part S_1 of the search data S is used to search for the first part Fn_1 of the feature Fn stored in the SLC IMAS CAM cell 110; the second part S_2 of the search data S is used to search for the second part Fn_2 of the feature Fn stored in the analog IMS CAM cell 120. That is, in decimal, for an 8-bit feature value, the first part Fn_1 of the feature Fn in the SLC IMAS CAM cell 110 is 128-255, and the second part Fn_2 of the feature Fn in the analog IMS CAM cell 120 is 0-127. Specifically, During data search, the first part S_1 of the search data S is decoded into the first search voltage SL_1 and the second search voltage SL_2 to search for the first part Fn_1 of the feature Fn stored in the SLC IMAS CAM cell 110; the second part S_2 of the search data S is decoded into the third search voltage VA and the fourth search voltage VB to search for the second part Fn_2 of the feature Fn stored in the analog IMS CAM cell 120.

Please refer to Figure 9A and Figure 9B. Here, the search data S is 10011011 as an example for explanation, but it should be noted that the present case is not limited to this. When the search data S (10011011) is converted to decimal (DEC), the search data S is 155 (DEC). The first part S_1 of the search data S is logical 1 (MSB).

In FIG. 9B , when the storage data (analog storage value) of 155 is stored in the hybrid memory search CAM unit 100 , the first part Fn_1 of the feature Fn stored in the SLC IMAS CAM cell 110 is logic 1 (MSB), and the feature Fn stored in the analog IMS CAM cell 120 is 155 (DEC). During data search and comparison, the first part S_1 (logic 1 (MSB)) of the search data S searches for the first part Fn_1 (logic 1 (MSB)) of the feature Fn stored in the SLC IMAS CAM cell 110, and the search result is a match (the SLC IMAS CAM cell 110 generates a high current); and the search data S (155 (DEC) searches for the feature Fn (155 (DEC)) stored in the analog IMS CAM cell 120, and the analog IMS CAM cell 120 generates a first current I1.

In FIG. 9B , when the storage data (analog storage value) of 162 is stored in the hybrid memory search CAM unit 100 , the first part Fn_1 of the feature Fn stored in the SLC IMAS CAM cell 110 is logical 1 (MSB), and the feature Fn stored in the analog IMS CAM cell 120 is 162 (DEC). During data search and comparison, the first part S_1 (logic 1 (MSB)) of the search data S searches for the first part Fn_1 (logic 1 (MSB)) of the feature Fn stored in the SLC IMAS CAM cell 110, and the search result is a match (the SLC IMAS CAM cell 110 generates a high current); and the search data S (155 (DEC) searches for the feature Fn (162 (DEC)) stored in the analog IMS CAM cell 120, and the analog IMS CAM cell 120 generates a second current I2.

In FIG. 9B , when the storage data (analog storage value) of 110 is stored in the hybrid memory search CAM unit 100 , the first part Fn_1 of the feature Fn stored in the SLC IMAS CAM cell 110 is logical 0 (MSB), and the feature Fn stored in the analog IMS CAM cell 120 is 110 (DEC). During data search and comparison, the first part S_1 (logic 1 (MSB)) of the search data S searches for the first part Fn_1 (logic 0 (MSB)) of the feature Fn stored in the SLC IMAS CAM cell 110, and the search result is mismatch (the SLC IMAS CAM cell 110 generates a low current); and the search data S (155 (DEC) searches for the feature Fn (110 (DEC)) stored in the analog IMS CAM cell 120, and the analog IMS CAM cell 120 generates a third current I3. Among them, I1>I2>I3, that is, when the search data S is closer to the search feature Fn stored in the analog IMS CAM cell 120, the analog IMS The CAM cell 120 generates a higher current. Conversely, the analog IMS CAM cell 120 generates a lower current as the search data S is farther from the search feature Fn stored in the analog IMS CAM cell 120.

Please refer to Figure 10A and Figure 10B. Here, the search data S is 10011011 as an example for explanation, but it should be noted that the present case is not limited to this. When the search data S (10011011) is converted to decimal (DEC), the search data S is 155 (DEC). The first part S_1 of the search data S is logical 1 (MSB), and the second part S_2 of the search data S is 0011011, which is 27 (DEC) when converted to decimal.

In FIG. 10B , when the storage data (analog storage value) of 156 is stored in the hybrid memory search CAM unit 100 , the first part Fn_1 of the feature Fn stored in the SLC IMAS CAM cell 110 is logic 1 (MSB), and the second part Fn_2 of the feature Fn stored in the analog IMS CAM cell 120 is 28 (DEC). During data search and comparison, the first part S_1 (logic 1 (MSB)) of the search data S searches for the first part Fn_1 (logic 1 (MSB)) of the feature Fn stored in the SLC IMAS CAM cell 110, and the search result is a match (the SLC IMAS CAM cell 110 generates a high current); and the second part S_2 (27 (DEC)) of the search data S searches for the second part Fn_2 (28 (DEC)) of the feature Fn stored in the analog IMS CAM cell 120, and the analog IMS CAM cell 120 generates a fourth current I4.

In FIG. 10B , when the storage data (analog storage value) of 160 is stored in the hybrid memory search CAM unit 100 , the first part Fn_1 of the feature Fn stored in the SLC IMAS CAM cell 110 is logic 1 (MSB), and the second part Fn_2 of the feature Fn stored in the analog IMS CAM cell 120 is 32 (DEC). During data search and comparison, the first part S_1 (logic 1 (MSB)) of the search data S searches for the first part Fn_1 (logic 1 (MSB)) of the feature Fn stored in the SLC IMAS CAM cell 110, and the search result is a match (the SLC IMAS CAM cell 110 generates a high current); and the second part S_2 (27 (DEC)) of the search data S searches for the second part Fn_2 (32 (DEC)) of the feature Fn stored in the analog IMS CAM cell 120, and the analog IMS CAM cell 120 generates a fifth current I5.

In FIG. 10B , when the storage data (analog storage value) of 140 is stored in the hybrid memory search CAM unit 100 , the first part Fn_1 of the feature Fn stored in the SLC IMAS CAM cell 110 is logical 1 (MSB), and the second part Fn_2 of the feature Fn stored in the analog IMS CAM cell 120 is 12 (DEC). During data search and comparison, the first part S_1 (logic 1 (MSB)) of the search data S searches for the first part Fn_1 (logic 1 (MSB)) of the feature Fn stored in the SLC IMAS CAM cell 110, and the search result is a match (the SLC IMAS CAM cell 110 generates a high current); and the second part S_2 (27 (DEC)) of the search data S searches for the second part Fn_2 (12 (DEC)) of the feature Fn stored in the analog IMS CAM cell 120, and the analog IMS CAM cell 120 generates a sixth current I6. Among them, I4>I5>I6, that is, when the second part S_2 of the search data S is closer to the second part Fn_2 of the search feature Fn stored in the analog IMS CAM cell 120, the analog IMS CAM cell 120 generates a higher current. On the contrary, when the second part S_2 of the search data S is closer to the second part Fn_2 of the search feature Fn stored in the analog IMS CAM cell 120, the analog IMS CAM cell 120 generates a lower current.

FIG. 11 shows a circuit diagram of a hybrid memory search CAM memory device according to an embodiment of the present invention. As shown in FIG. 11 , the hybrid memory search CAM memory device 1100 includes: a hybrid memory search CAM memory array 1110, a word line driver circuit 1120, a bit line driver circuit 1130, and a sense amplifier (SA) 1140.

The hybrid memory in-body search CAM memory array 1110 includes a plurality of hybrid memory in-body search CAM units 100, a plurality of word lines WL1~WLn (n is a positive integer), and a plurality of bit lines BL1~BLm (m is a positive integer). The hybrid memory in-body search CAM units 100 are coupled to the word lines WL1~WLn and the bit lines BL1~BLm.

The word line driving circuit 1120 is coupled to the word lines WL1~WLn, and is used to apply search voltages SL_1, SL_2, VA and VB to the search CAM units 100 in the hybrid memory according to the search data S, so as to search the search CAM units 100 in the hybrid memory.

The bit line driving circuit 1130 is coupled to the bit lines BL1~BLm to apply a bit line driving voltage to the bit lines BL1~BLm.

The sense amplifier (SA) 1140 is coupled to the hybrid memory search CAM units 100 to receive the sense current transmitted from the hybrid memory search CAM units 100 to determine whether the search data S matches the storage data in the hybrid memory search CAM units 100.

Figures 12A to 12D show examples of hybrid memory search CAM units according to other embodiments of the present invention.

In FIG. 12A , the hybrid memory intra-search CAM unit 1200A includes: a first IMS CAM cell 1210A and a second IMS CAM cell 1220A, wherein the first IMS CAM cell 1210A is, for example but not limited to, a single-level cell (SLC) IMS CAM cell, and the second IMS CAM cell 1220A is, for example but not limited to, a SLC IMAS CAM cell or a multi-level cell (MLC) IMS CAM cell or an MLC IMAS CAM cell or an analog IMS CAM cell.

In FIG. 12B , the hybrid in-memory search CAM unit 1200B includes: a first IMS CAM cell 1210B and a second IMS CAM cell 1220B, wherein the first IMS CAM cell 1210B is, for example but not limited to, an SLC IMAS CAM cell, and the second IMS CAM cell 1220B is, for example but not limited to, an MLC IMS CAM cell or an MLC IMAS CAM cell or an analog IMS CAM cell.

In FIG. 12C , the hybrid in-memory search CAM unit 1200C includes: a first IMS CAM cell 1210C and a second IMS CAM cell 1220C, wherein the first IMS CAM cell 1210C is, for example but not limited to, an MLC IMS CAM cell, and the second IMS CAM cell 1220C is, for example but not limited to, an MLC IMAS CAM cell or an analog IMS CAM cell.

In FIG. 12D , the hybrid in-memory search CAM unit 1200D includes: a first IMS CAM cell 1210D and a second IMS CAM cell 1220D, wherein the first IMS CAM cell 1210D is, for example but not limited to, an MLC IMAS CAM cell, and the second IMS CAM cell 1220D is, for example but not limited to, an analog IMS CAM cell.

In summary, in one embodiment of the present case, the hybrid memory intra-search CAM unit includes: a first IMS CAM cell and a second IMS CAM cell, wherein the first IMS CAM cell and the second IMS CAM cell are of different types. The definition of "different types" is as described below.

In an embodiment of the present case, when the first IMS CAM cell and the second IMS CAM cell have different numbers of storage bits, the first IMS CAM cell and the second IMS CAM cell are of different types. For example, but not limited to, when the first IMS CAM cell is a single-bit cell (SLC) and the second IMS CAM cell is a multi-bit cell (MLC, multi-level cell) (2 bits, 3 bits, 4 bits... etc.), the first IMS CAM cell and the second IMS CAM cell are of different types.

Alternatively, in an embodiment of the present case, when the stored data of one of the first IMS CAM unit cell and the second IMS CAM unit cell is a digital value and the stored data of the other of the first IMS CAM unit cell and the second IMS CAM unit cell is an analog value, the first IMS CAM unit cell and the second IMS CAM unit cell are of different types. For example, but not limited to, when one of the first IMS CAM unit cell and the second IMS CAM unit cell is an analog IMS CAM unit cell (the stored data is an analog value) and one of the first IMS CAM unit cell and the second IMS CAM unit cell is a digital IMS CAM unit cell (the stored data is a digital value) or a digital IMS CAM unit cell (the stored data is a digital value), the first IMS CAM unit cell and the second IMS CAM unit cell are of different types. The digital IMS CAM cell is, for example, an SLC IMS CAM cell or an MLC IMS CAM cell, and the digital IMAS CAM cell is, for example, an SLC IMAS CAM cell or an MLC IMAS CAM cell.

Alternatively, in an embodiment of the present case, when one of the first IMS CAM unit cell and the second IMS CAM unit cell is an IMS CAM unit cell and the other of the first IMS CAM unit cell and the second IMS CAM unit cell is an IMAS CAM unit cell, the first IMS CAM unit cell and the second IMS CAM unit cell are of different types. For example, but not limited to, when one of the first IMS CAM unit cell and the second IMS CAM unit cell is an SLC IMS CAM unit cell or an MLC IMS CAM unit cell and the other of the first IMS CAM unit cell and the second IMS CAM unit cell is an SLC IMAS CAM unit cell or an MLC IMAS CAM unit cell, the first IMS CAM unit cell and the second IMS CAM unit cell are of different types.

That is, in an embodiment of the present case, the first IMS CAM cell and the second IMS CAM cell can be selected from the following: SLC IMAS CAM cell, analog IMS CAM cell, SLC IMS CAM cell, MLC IMS CAM cell, MLC IMAS CAM cell.

Figures 13A and 13B show schematic diagrams of an SLC IMS CAM cell according to an embodiment of the present invention.

Please refer to FIG. 13A, which shows an SLC IMS CAM cell 1310 according to an embodiment of the present invention. The SLC IMS CAM cell 1310 includes flash memory cells T1 and T2 connected in parallel. The flash memory cell T1 includes: a first end (e.g., a gate) receiving a search voltage SL_1; a second end (e.g., a source) coupled to a second end (e.g., a source) of the flash memory cell T2; and a third end (e.g., a drain) coupled to a third end (e.g., a drain) of the flash memory cell T2. The flash memory cell T2 includes: a first end (e.g., a gate) receiving a search voltage SL_2; a second end (e.g., a source) coupled to a second end (e.g., a source) of the flash memory cell T1; and a third end (e.g., a drain) coupled to a third end (e.g., a drain) of the flash memory cell T1.

The operation of the SLC IMS CAM cell 1310 may include an erase operation, a program operation, and a search operation, as described below.

During the erase operation, an erase voltage is applied as the search voltages SL_1 and SL_2. Generally, the erase voltage can be a negative bias to release the charges stored in the flash memory cells T1 and T2.

During the programming operation, by applying appropriate programming voltages to the search voltages SL_1 and SL_2, the critical voltages of the flash memory cells T1 and T2 are programmed respectively. When the critical voltage of the flash memory cell T1 is programmed as a low critical voltage and the critical voltage of the flash memory cell T2 is programmed as a high critical voltage, the data stored in the SLC IMS CAM cell 1310 is defined as a first value (e.g., 0); when the critical voltage of the flash memory cell T1 is programmed as a high critical voltage and the critical voltage of the flash memory cell T2 is programmed as a low critical voltage, the data stored in the SLC IMS CAM cell 1310 is defined as a second value (e.g., 1). In addition to the first value or the second value, the data stored in the SLC IMS CAM cell 1310 can also selectively support the storage of "don't care". When the critical voltage of the flash memory cell T1 is programmed as a low critical voltage and the critical voltage of the flash memory cell T2 is programmed as a low critical voltage, the data stored in the SLC IMS CAM cell 1310 is defined as "don't care".

During the search operation, when searching for the first value, a first reference search voltage is applied to the search voltage SL_1, and a second reference search voltage is applied to the search voltage SL_2; when searching for the second value, a second reference search voltage is applied to the search voltage SL_1, and a first reference search voltage is applied to the search voltage SL_2. The second reference search voltage is greater than the upper critical voltage, the upper critical voltage is greater than the first reference search voltage, and the first reference search voltage is greater than the lower critical voltage. In addition to searching for the first value and the second value, searching for "wild cards" can also be optionally supported. The so-called wildcard search here means that the data to be searched can be the first value or the second value, that is, when searching for a wildcard, whether the first value or the second value stored in the SLC IMS CAM cell 1310 is considered a match. When searching for a wildcard, the search voltage SL_1 will be applied with the second reference search voltage, and the search voltage SL_2 will be applied with the second reference search voltage.

Please refer to FIG. 13B for a diagram of an SLC IMS CAM cell 1320 according to another embodiment of the present invention. The SLC IMS CAM cell 1320 includes a flash memory cell T1 and a flash memory cell T2 connected in series. The flash memory cell T1 includes: a first end (e.g., a gate) receiving a search voltage SL_1; a second end (e.g., a source) coupled to a signal line; and a third end (e.g., a drain) coupled to a second end (e.g., a source) of the flash memory cell T2. The flash memory cell T2 includes: a first end (e.g., a gate) receiving a search voltage SL_2; a second end (e.g., a source) coupled to a third end (e.g., a drain) of the flash memory cell T1; and a third end (e.g., a drain) coupled to a signal line.

The operation of the SLC IMS CAM cell 1320 in the embodiment of FIG. 13B may include an erase operation, a program operation, and a search operation, as described in detail below.

During the erase operation, an erase voltage is applied to the search voltage SL_1 and the search voltage SL_2. Generally speaking, the erase voltage can be a negative bias to release the charge stored in the flash memory cell T1 and the flash memory cell T2.

During the programming operation, by applying appropriate programming voltages to the search voltage SL_1 and the search voltage SL_2, the critical voltages of the flash memory cell T1 and the flash memory cell T2 are programmed respectively. When the critical voltage of the flash memory cell T1 is programmed as a low critical voltage and the critical voltage of the flash memory cell T2 is programmed as a high critical voltage, the data stored in the SLC IMS CAM cell 1320 is defined as a first value (e.g., 0); when the critical voltage of the flash memory cell T1 is programmed as a high critical voltage and the critical voltage of the flash memory cell T2 is programmed as a low critical voltage, the data stored in the SLC IMS CAM cell 1320 is defined as a second value (e.g., 1). In addition to the first value or the second value, the data stored in the SLC IMS CAM cell 1320 can also selectively support the storage of "don't care". When the critical voltage of the flash memory cell T1 is programmed to a low critical voltage and the critical voltage of the flash memory cell T2 is programmed to a low critical voltage, the data stored in the SLC IMS CAM cell 1310 is defined as "don't care".

During the search operation, when searching for the first value, a first reference search voltage is applied to the search voltage SL_1, and a second reference search voltage is applied to the search voltage SL_2; when searching for the second value, a second reference search voltage is applied to the search voltage SL_1, and a first reference search voltage is applied to the search voltage SL_2. The second reference search voltage is greater than the upper critical voltage, the upper critical voltage is greater than the first reference search voltage, and the first reference search voltage is greater than the lower critical voltage. In addition to searching for the first value and the second value, searching for wildcards can also be optionally supported. The so-called wildcard search here means that the data to be searched can be the first value or the second value, that is, when searching for a wildcard, whether the first value or the second value stored in the SLC IMS CAM cell 1320 is considered a match. When searching for a wildcard, the search voltage SL_1 will be applied with the second reference search voltage, and the search voltage SL_2 will be applied with the second reference search voltage.

Figures 14A to 14D show schematic diagrams of an MLC IMS CAM cell and its operation according to an embodiment of the present invention.

FIG. 14A shows an MLC IMS CAM cell 1410 and its operation schematic diagram according to an embodiment of the present invention. As shown in FIG. 14A, the MLC IMS CAM cell 1410 of an embodiment of the present invention can be, for example but not limited to, a multi-level CAM (MLC) that can store two bits.

The MLC IMS CAM cell 1410 includes: two flash memory cells T1 and T2 connected in series, wherein the flash memory cells are, for example but not limited to, floating gate memory cells, Silicon-Oxide-Nitride-Oxide-Silicon (SONOS) memory cells, floating dot memory cells, Ferroelectric FET (FeFET) memory cells, etc.

The gate G1 of the flash memory cell T1 is used to receive the first search voltage SL_1, the gate G2 of the flash memory cell T2 is used to receive the second search voltage SL_2, and the source S1 of the flash memory cell T1 is electrically connected to the source S2 of the flash memory cell T2.

In addition, in an embodiment of the present invention, the critical voltage of the flash memory cell T1 (also referred to as the first critical voltage), the critical voltage of the flash memory cell T2 (also referred to as the second critical voltage), the first search voltage SL_1, and the second search voltage SL_2 can be set in a variety of ways. In FIG. 14A, the settings of the first critical voltage, the second critical voltage, the first search voltage SL_1, and the second search voltage SL_2 can be as shown in the following table, the details of which are omitted here:

In an embodiment of the present case, when the stored data is the first predetermined stored data (00), the first critical voltage is VT1 (also referred to as the minimum critical voltage value), and the second critical voltage is VT4 (also referred to as the maximum critical voltage value); when the stored data is the second predetermined stored data (11), the first critical voltage is a maximum critical voltage value, and the second critical voltage is a minimum critical voltage value; when the stored data is the third predetermined stored data (XX (don’t care), the first critical voltage and the second critical voltage are both a minimum critical voltage value; when the stored data is the fourth predetermined stored data (i.e., invalid data), the first critical voltage and the second critical voltage are equal to or greater than a maximum critical voltage value. That is, in an embodiment of the present case, the stored data of the MLC IMS CAM cell 1410 is determined by the combination of the first critical voltage and the second critical voltage.

In an embodiment of the present case, when the search data is the first predetermined search data (00), the first search voltage SL_1 is VS1 (also called the minimum search voltage value), and the second search voltage SL_2 is VS4 (also called the maximum search voltage value), wherein the search data represents the data to be searched; when the search data is the second predetermined search data (11), the first search voltage SL_1 is a maximum search voltage value, and the second search voltage SL_2 is a minimum search voltage value; when the search data is the third predetermined search data (WC), the first search voltage SL_1 and the second search voltage SL_2 are both maximum search voltage values.

Therefore, when searching, when the search data matches the stored data, both the flash memory cell T1 and the flash memory cell T2 generate matching currents, indicating that the search result is a match; when the search data does not match the stored data, at least one of the flash memory cell T1 and the flash memory cell T2 is not conducting and does not generate matching currents, indicating that the search result is a mismatch; when the search data is a wildcard (WC), regardless of the value of the stored data, both the flash memory cell T1 and the flash memory cell T2 generate matching currents, indicating that the search result is a match; when the stored data is XX (don’t care, don't care), no matter what the search data is, flash memory cell T1 and flash memory cell T2 both generate matching current, indicating that the search result is a match. For example, when the search data (00) matches the stored data (00), flash memory cell T1 and flash memory cell T2 both generate matching current, indicating that the search result is a match; when the search data (00) does not match the stored data (01), flash memory cell T1 is turned off and flash memory cell T2 is turned on, and no matching current is generated, indicating that the search result is a mismatch.

Please refer to FIG. 14B, which shows an MLC IMS CAM cell 1420 and its operation schematic diagram according to an embodiment of the present invention. The MLC IMS CAM cell 1420 is, for example but not limited to, a triple-level CAM (TLC) that can store three bits.

In the present embodiment, the first critical voltage, the second critical voltage, the first search voltage SL_1 and the second search voltage SL_2 may also have different settings. In FIG. 14B , the settings of the first critical voltage, the second critical voltage, the first search voltage SL_1 and the second search voltage SL_2 may be as shown in the following table, the details of which are omitted here:

In an embodiment of the present case, when the stored data is the first predetermined stored data (000), the first critical voltage is VT1 (also referred to as the minimum critical voltage value), and the second critical voltage is VT8 (also referred to as the maximum critical voltage value); when the stored data is the second predetermined stored data (111), the first critical voltage is a maximum critical voltage value, and the second critical voltage is a minimum critical voltage value; when the stored data is the third predetermined stored data (XXX (don’t care), the first critical voltage and the second critical voltage are both a minimum critical voltage value; when the stored data is the fourth predetermined stored data (i.e., invalid data), the first critical voltage and the second critical voltage are equal to or greater than a maximum critical voltage value. That is, in an embodiment of the present case, the stored data of the MLC IMS CAM cell 1420 is determined by the combination of the first critical voltage and the second critical voltage.

In an embodiment of the present case, when the search data is the first predetermined search data (000), the first search voltage SL_1 is VS1 (also called the minimum search voltage value), and the second search voltage SL_2 is VS8 (also called the maximum search voltage value); when the search data is the second predetermined search data (111), the first search voltage SL_1 is a maximum search voltage value, and the second search voltage SL_2 is a minimum search voltage value; when the search data is the third predetermined search data (WC), the first search voltage SL_1 and the second search voltage SL_2 are both maximum search voltage values.

Therefore, when searching, when the search data matches the stored data, both the flash memory cell T1 and the flash memory cell T2 generate matching currents, indicating that the search result is a match; when the search data does not match the stored data, at least one of the flash memory cell T1 and the flash memory cell T2 is not conducting and does not generate matching currents, indicating that the search result is a mismatch; when the search data is a wildcard (WC), regardless of the value of the stored data, both the flash memory cell T1 and the flash memory cell T2 generate matching currents, indicating that the search result is a match; when the stored data is XX (don’t care, don't care), no matter what the search data value is, flash memory cell T1 and flash memory cell T2 both generate matching current, indicating that the search result is a match. For example, when the search data (000) matches the stored data (000), flash memory cell T1 and flash memory cell T2 both generate matching current, indicating that the search result is a match; when the search data (000) does not match the stored data (001), flash memory cell T1 is turned off and flash memory cell T2 is turned on, and no matching current is generated, indicating that the search result is a mismatch.

Please refer to FIG. 14C, which shows an MLC IMS CAM cell 1430 and its operation schematic diagram according to an embodiment of the present invention. The MLC IMS CAM cell 1430 is, for example but not limited to, a quad-level CAM (QLC) that can store four bits.

In an embodiment of the present invention, the first critical voltage, the second critical voltage, the first search voltage SL_1 and the second search voltage SL_2 may also have different settings. In FIG. 14C , the settings of the first critical voltage, the second critical voltage, the first search voltage SL_1 and the second search voltage SL_2 may be as shown in the following table, the details of which are omitted here:

In the present embodiment, when the stored data is the first predetermined stored data (0000), the first critical voltage is VT1 (also referred to as the minimum critical voltage value), and the second critical voltage is VT16 (also referred to as the maximum critical voltage value); when the stored data is the second predetermined stored data (1111), the first critical voltage is a maximum critical voltage value, and the second critical voltage is a minimum critical voltage value; when the stored data is the third predetermined stored data (XXXX (don’t care), the first critical voltage and the second critical voltage are both a minimum critical voltage value; when the stored data is the fourth predetermined stored data (i.e., invalid data), the first critical voltage and the second critical voltage are equal to or greater than a maximum critical voltage value. That is, in the present embodiment, the stored data of the MLC IMS CAM cell 1430 is determined by the combination of the first critical voltage and the second critical voltage.

In the present embodiment, when the search data is the first predetermined search data (0000), the first search voltage SL_1 is VS1 (also called the minimum search voltage value), and the second search voltage SL_2 is VS16 (also called the maximum search voltage value); when the search data is the second predetermined search data (1111), the first search voltage SL_1 is a maximum search voltage value, and the second search voltage SL_2 is a minimum search voltage value; when the search data is the third predetermined search data (WC), the first search voltage SL_1 and the second search voltage SL_2 are both maximum search voltage values.

In the present embodiment, when the search data matches the stored data, both the flash memory cell T1 and the flash memory cell T2 generate matching currents, indicating that the search result is a match; when the search data does not match the stored data, at least one of the flash memory cell T1 and the flash memory cell T2 is not turned on and does not generate matching currents, indicating that the search result is a mismatch.

Please refer to FIG. 14D, which shows an MLC IMS CAM cell 1440 and its operation schematic diagram according to an embodiment of the present invention. The MLC IMS CAM cell 1440 can be, for example but not limited to, a five-bit penta-level CAM (PLC).

In the present embodiment, the first critical voltage, the second critical voltage, the first search voltage SL_1 and the second search voltage SL_2 may also have different settings. In FIG. 14D , the settings of the first critical voltage, the second critical voltage, the first search voltage SL_1 and the second search voltage SL_2 may be as shown in the following table, the details of which are omitted here:

In the present embodiment, when the stored data is the first predetermined stored data (00000), the first critical voltage is VT1 (also referred to as the minimum critical voltage value), and the second critical voltage is VT32 (also referred to as the maximum critical voltage value); when the stored data is the second predetermined stored data (11111), the first critical voltage is a maximum critical voltage value, and the second critical voltage is a minimum critical voltage value; when the stored data is the third predetermined stored data (XXXXX (don’t care), the first critical voltage and the second critical voltage are both a minimum critical voltage value; when the stored data is the fourth predetermined stored data (i.e., invalid data), the first critical voltage and the second critical voltage are equal to or greater than a maximum critical voltage value. That is, in the embodiment of the present case, the stored data of the MLC IMS CAM cell 1440 is determined by the combination of the first critical voltage and the second critical voltage.

In the present embodiment, when the search data is the first predetermined search data (00000), the first search voltage SL_1 is VS1 (also called the minimum search voltage value), and the second search voltage SL_2 is VS32 (also called the maximum search voltage value); when the search data is the second predetermined search data (11111), the first search voltage SL_1 is a maximum search voltage value, and the second search voltage SL_2 is a minimum search voltage value; when the search data is the third predetermined search data (WC), the first search voltage SL_1 and the second search voltage SL_2 are both maximum search voltage values.

In the present embodiment, when the search data matches the stored data, both the flash memory cell T1 and the flash memory cell T2 generate matching currents, indicating that the search result is a match; when the search data does not match the stored data, at least one of the flash memory cell T1 and the flash memory cell T2 is not conducting and does not generate matching currents, indicating that the search result is a mismatch.

Figures 15A to 15G show the MLC IMAS CAM unit cell and its operation schematic diagram according to an embodiment of the present invention.

FIG. 15A is a schematic diagram of an MLC IMAS CAM cell 1500 of an embodiment of the present invention. The MLC IMAS CAM cell 1500 is a unit of a memory device, and the memory device is used to perform an in-memory search. Referring to FIG. 15A, the MLC IMAS CAM cell 1500 includes two transistors M1 and M2 connected in series. Transistor M1 can be referred to as a "first transistor" and transistor M2 can be referred to as a "second transistor". Transistor M1 includes a first drain d1, a first source s1, and a first gate g1. Transistor M2 includes a second drain d2, a second source s2, and a second gate g2. The first drain d1 of the transistor M1 is connected to one of the bit lines of the memory device (for example, the first bit line BL1). The first source s1 of the transistor M1 is connected to the second drain d2 of the transistor M2. The first gate g1 of the transistor M1 and the second gate g2 of the transistor M2 are connected to one of the word lines of the memory device. For example, the first word line WL1 of the memory device includes the first word line WL1(1) and the second word line WL1(2), the first gate g1 of the transistor M1 is connected to the first word line WL1(1), and the second gate g2 of the transistor M2 is connected to the second word line WL1(2).

The transistor M1 has a first critical voltage Vth1, and the transistor M2 has a second critical voltage Vth2. The transistors M1 and M2 have floating gates, and a programming voltage can be applied to change the first critical voltage Vth1 and the second critical voltage Vth2. In one example, the transistors M1 and M2 are both multi-level cells (MLC). The first critical voltage Vth1 of the transistor M1 and the second critical voltage Vth2 of the transistor M2 can be adjusted to a first number of voltage distributions, and the first number is "4". The four voltage distributions are in order of voltage magnitude: the fourth voltage distribution VT4, the third voltage distribution VT3, the second voltage distribution VT2, and the first voltage distribution VT1. In another example, transistors M1 and M2 are both triple-level cells (TLC), and the first critical voltage Vth1 and the second critical voltage Vth2 can be adjusted to a second number of voltage distributions, and the second number is "8". In another example, transistors M1 and M2 are both quad-level cells (QLC), and the first critical voltage Vth1 and the second critical voltage Vth2 can be adjusted to a third number of voltage distributions, and the third number is "16".

The MLC IMAS CAM cell 1500 can store a storage data DAT, wherein the storage data DAT includes a first bit D1 and a second bit D2. The storage data DAT is encoded according to the first critical voltage Vth1 and the second critical voltage Vth2. That is, the storage data DAT is encoded according to the first to fourth voltage distributions VT1 to VT4 of the first critical voltage Vth1 and the first to fourth voltage distributions VT1 to VT4 of the second critical voltage Vth2, as shown in the following table:

In the example in the above table, when the first critical voltage Vth1 and the second critical voltage Vth2 are the first voltage distribution VT1 and the fourth voltage distribution VT4 respectively, the first bit D1 and the second bit D2 of the encoded storage data DAT are "0" and "0". When the first critical voltage Vth1 and the second critical voltage Vth2 are both the fourth voltage distribution VT4, the encoded storage data DAT is invalid data. When the first critical voltage Vth1 and the second critical voltage Vth2 are both the first voltage distribution VT1, the encoded storage data DAT is unimportant.

Furthermore, when the first critical voltage Vth1 and the second critical voltage Vth2 are the first voltage distribution VT1 and the third voltage distribution VT3 respectively, the first bit D1 and the second bit D2 of the encoded storage data DAT are "0" and "X", which can represent that the storage data DAT is [0 0] or [0 1]. When the first critical voltage Vth1 and the second critical voltage Vth2 are the first voltage distribution VT1 and the second voltage distribution VT2 respectively, the first bit D1 and the second bit D2 of the encoded storage data DAT are "X" and "0", which can represent that the storage data DAT is [1 0] or [0 0].

Similarly, when the first critical voltage Vth1 and the second critical voltage Vth2 are the third voltage distribution VT3 and the first voltage distribution VT1 respectively, the encoded storage data DAT is [1 X], that is, the storage data DAT is [1 0] or [1 1]. When the first critical voltage Vth1 and the second critical voltage Vth2 are the second voltage distribution VT2 and the first voltage distribution VT1 respectively, the encoded storage data DAT is [X 1], that is, the storage data DAT is [0 1] or [1 1].

When searching in memory, transistor M1 receives a first gate bias Vg1 via the first word line WL1(1), and transistor M2 receives a second gate bias Vg2 via the second word line WL1(2). In operation, the first gate bias Vg1 and the second gate bias Vg2 can be adjusted to a first number of bias values (i.e., 4 bias values), respectively, and are arranged in order of voltage value: fourth bias value VH4, third bias value VH3, second bias value VH2, and first bias value VH1. Furthermore, the voltage value of each of the first to fourth bias values VH1~VH4 is greater than the first to fourth voltage distributions VT1~VT4. The magnitude relationship is: the fourth bias value VH4> the third bias value VH3> the second bias value VH2> the first bias value VH1> the fourth voltage distribution VT4> the third voltage distribution VT3> the second voltage distribution VT2> the first voltage distribution VT1. That is, the first bias value VH1 with the lowest voltage value is still greater than the fourth voltage distribution VT4 with the highest voltage value. The voltage magnitude relationship between the first to fourth bias values VH1~VH4 and the first to fourth voltage distributions VT1~VT4 can be seen in Figure 15B.

The MLC IMAS CAM cell 1500 may receive search data SW, wherein the search data SW includes a first bit S1 and a second bit S2. The search data SW may be encoded according to the first gate bias Vg1 and the second gate bias Vg2. That is, the search data SW is encoded according to the first to fourth bias values VH1-VH4 of the first gate bias Vg1 and the first to fourth bias values VH1-VH4 of the second gate bias Vg2, as shown in the following table:

In the example in the above table, when the first gate bias Vg1 and the second gate bias Vg2 are the first bias value VH1 and the fourth bias value VH4 respectively, the first bit S1 and the second bit S2 of the encoded search data SW are "0" and "0" respectively. When the first gate bias Vg1 and the second gate bias Vg2 are both the fourth bias value VH4, the encoded search data SW is a wildcard.

In operation, there is a first voltage difference between the first gate bias Vg1 received by transistor M1 and the first critical voltage Vth1 of transistor M1, and transistor M1 generates current I1 according to the first voltage difference. Similarly, there is a second voltage difference between the second gate bias Vg2 received by transistor M2 and the second critical voltage Vth2 of transistor M2, and transistor M2 generates current I2 according to the second voltage difference. Since transistor M1 is connected in series with transistor M2, the current value of output current Is1 generated by MLC IMAS CAM cell 1500 on bit line BL1 is substantially equal to the smaller of current values of current I1 and current I2. The output current Is1 is generated from the second source s2 of the transistor M2.

FIG. 15C shows examples of voltage values of the first to fourth bias values VH1~VH4, the first to fourth voltage distributions VT1~VT4, the first voltage difference, and the second voltage difference. In the example of FIG. 15C, the first to fourth bias values VH1~VH4 are 5.5V, 7V, 8.5V, and 10V, respectively. In addition, the minimum voltage value of the first voltage distribution VT1 is 0V, the maximum voltage value is 1V, and the peak voltage value is 0.5V. The minimum voltage value of the second voltage distribution VT2 is 1.5V, the maximum voltage value is 2.5V, and the peak voltage value is 2V. The minimum voltage value of the third voltage distribution VT3 is 3V, the maximum voltage value is 4V, and the peak voltage value is 3.5V. The lowest voltage value of the fourth voltage distribution VT4 is 4.5V, the highest voltage value is 5.5V, and the peak voltage value is 5V.

In operation, different search data SW can be provided to search for the storage data DAT stored in the MLC IMAS CAM cell 1500. Figures 15D to 15GD are schematic diagrams of searching for storage data DAT of different contents when the search data SW is [0 0]. Please refer to Figure 15D first. When the search data SW is [0 0], the first gate bias Vg1 received by the transistor M1 is the first bias value VH1, and the second gate bias Vg2 received by the transistor M2 is the fourth bias value VH4. When the storage data DAT is [0 0], the first critical voltage Vth1 is the first voltage distribution VT1, and the second critical voltage Vth2 is the fourth voltage distribution VT4.

The first voltage difference between the first gate bias Vg1 and the first critical voltage Vth1 of the transistor M1 is the "gate overdrive voltage difference". When the search data SW is [0 0] and the storage data DAT is [0 0], the first gate bias Vg1 is the first bias value VH1, and the first critical voltage Vth1 is the first voltage distribution VT1. The voltage difference between the first bias value VH1 (5.5V) and the highest voltage value (1V) of the first voltage distribution VT1 is 4.5V. That is, the first voltage difference between the first gate bias Vg1 and the first critical voltage Vth1 of the transistor M1 is 4.5V.

The voltage difference between two adjacent bias values among the first to fourth bias values VH1~VH4 is defined as a predetermined level, which can be called "1-level", (1-level, (1L)). Similarly, for the first to fourth voltage distributions VT1~VT4, the voltage difference between the maximum voltage values of two adjacent voltage distributions is also equal to 1-level (1L). In the embodiment of Figure 15C, the voltage difference between two adjacent bias values is 1.5V, and 1.5V is used as the predetermined level (i.e., one-level (1L)). Accordingly, the first voltage difference 4.5V of the transistor M1 is 3-level (3L).

On the other hand. When the search data SW is [0 0] and the storage data DAT is [0 0], the voltage difference between the fourth bias value VH4 (10V) of the transistor M2 and the highest voltage value (5.5V) of the fourth voltage distribution VT4 is 4.5V. That is, the second voltage difference between the second gate bias Vg2 of the transistor M2 and the second critical voltage Vth2 is 4.5V, which is 3 times the level (3L).

The current value of the current I1 generated by the transistor M1 corresponds to the first voltage difference of the transistor M1 (3 times the step (3L)), and the current value of the current I2 generated by the transistor M2 corresponds to the second voltage difference of the transistor M2 (3 times the step (3L)). The current I1 is equal to the current I2, so the current value of the output current Is1 generated by the MLC IMAS CAM cell 1500 is equal to the current I1 and the current I2. The gate overdrive voltage difference corresponding to the current value of the output current Is1 is 3 times the step (3L).

The storage data DAT and the search data SW are both [0 0], and the mismatch distance between the storage data DAT and the search data SW is "0" (i.e., perfect match). When the storage data DAT and the search data SW are perfectly matched, the gate overdrive voltage difference corresponding to the current value of the output current Is1 is 3 times the level (3L).

Next, please refer to Figure 15E. When the search data SW is [0 0] and the storage data DAT is [0 1], the mismatch distance between the storage data DAT and the search data SW is "1". The first voltage difference between the first bias value VH1 (5.5V) of the transistor M1 and the highest voltage value (2.5V) of the second voltage distribution VT2 is 3V (i.e., 2 times the level (2L)). The second voltage difference between the fourth bias value VH4 (10V) of the transistor M2 and the highest voltage value (4V) of the third voltage distribution VT3 is 6V (i.e., 4 times the level (4L)).

Accordingly, the current value of current I1 corresponds to the first voltage difference of transistor M1 (2 times the step (2L)), and the current value of current I2 corresponds to the second voltage difference of transistor M2 (4 times the step (4L)). Current I1 is less than current I2, and the output current Is1 generated by MLC IMAS CAM cell 1500 is the smaller of current I1 and current I2, and the current value of output current Is1 is equal to current I1. The gate overdrive voltage difference corresponding to the current value of output current Is1 is 2 times the step (2L).

Next, please refer to FIG. 15F. When the search data SW is [0 0] and the stored data DAT is [1 0], the mismatch distance between the stored data DAT and the search data SW is "2". The first voltage difference between the first bias value VH1 (5.5V) of the transistor M1 and the highest voltage value (4V) of the third voltage distribution VT3 is 1.5V (i.e., 1 times the step (1L)). The second voltage difference between the fourth bias value VH4 (10V) of the transistor M2 and the highest voltage value (2.5V) of the second voltage distribution VT2 is 7.5V (i.e., 5 times the step (5L)). Current I1 is less than current I2, the current value of output current Is1 is equal to current I1, and the gate overdrive voltage difference corresponding to the current value of output current Is1 is 1 times the level (1L).

Next, please refer to Figure 15G. When the search data SW is [0 0] and the storage data DAT is [1 1], the mismatch distance between the storage data DAT and the search data SW is "3". The first voltage difference between the first bias value VH1 (5.5V) of the transistor M1 and the highest voltage value (5.5V) of the fourth voltage distribution VT4 is 0V (i.e., 0 times the step (0L)). The first voltage difference between the fourth bias value VH4 (10V) of the transistor M2 and the highest voltage value (1V) of the first voltage distribution VT1 is 9V (i.e., 6 times the step (6L)). Accordingly, the gate overdrive voltage difference corresponding to the current value of the output current Is1 is 0 times the step (0L).

From the above, when the mismatch distance between the search data SW and the storage data DAT is "0", "1", "2", "3", the level of the gate overdrive voltage difference corresponding to the current value of the output current Is1 is "3L", "2L", "1L", "0L". When the mismatch degree between the search data SW and the storage data DAT is higher, the mismatch distance is larger, and the current value of the generated output current Is1 is smaller. Based on this, the mismatch distance and mismatch degree between the search data SW and the storage data DAT can be judged according to the current value of the output current Is1 of the MLC IMAS CAM cell 1500.

That is, in the MLC IMAS CAM cell of an embodiment of the present invention shown in FIGS. 15A to 15G, the storage data is encoded according to the first critical voltage and the second critical voltage, the search data is encoded according to the first gate bias and the second gate bias, there is a mismatch distance between the storage data and the search data, and an output current generated by the MLC IMAS CAM cell is related to the mismatch distance.

FIG. 16 shows a hybrid in-memory search (IMS) content-addressable memory (CAM) data search method according to an embodiment of the present invention, comprising: (1610) storing a storage data in a hybrid IMS CAM unit, the hybrid IMS CAM unit comprising: a first IMS CAM unit cell, and a second IMS CAM unit cell coupled to the first IMS CAM unit cell, wherein the first IMS CAM unit cell and the second IMS CAM unit cell are of different types, and when the hybrid IMS CAM unit stores the storage data, the first IMS CAM unit cell stores a first part of the storage data, and the second IMS CAM unit cell stores the storage data or a second part of the storage data; (1620) searching the hybrid IMS CAM unit cell with a search data; The CAM unit performs a data search, wherein during the data search, a first part of the search data is decoded into a first search voltage and a second search voltage to search for the first part of the stored data stored in the first IMS CAM cell, and the search data or a second part of the search data is decoded into a third search voltage and a fourth search voltage to search for the stored data or the second part of the stored data stored in the second IMS CAM cell; (1630) a sensed current generated by the hybrid IMS CAM unit is sensed to generate a sensed result; and (1640) whether the search data matches the stored data is determined based on the sensed result.

The SLC IMAS CAM cell can provide high system stability, while the analog IMS CAM cell can improve accuracy. Therefore, the hybrid in-memory search CAM unit of the present embodiment can have high accuracy, high content density and search stability.

The hybrid in-memory search CAM unit and the hybrid in-memory search CAM memory device of an embodiment of the present invention can be applied to a two-dimensional architecture or a three-dimensional architecture.

The hybrid in-memory search CAM unit and the hybrid in-memory search CAM memory device of an embodiment of the present case can have good performance and can be applied to various fields, such as but not limited to, big-data searching, AI hardware accelerator/classifier, approximate computing, associative memory, few-shot learning, single source data (SSD) data management, deoxyribonucleic acid (DNA) matching, data filter, etc.

In summary, although the present invention has been disclosed as above by the embodiments, it is not intended to limit the present invention. Those with common knowledge in the technical field to which the present invention belongs can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be subject to the scope defined in the attached patent application.

1610-1640: Steps

Claims (24)

A hybrid in-memory search (IMS) content addressable memory (CAM) unit includes: a first IMS CAM unit cell; and a second IMS CAM unit cell coupled to the first IMS CAM unit cell, wherein the first IMS CAM unit cell and the second IMS CAM unit cell are of different types, and when the hybrid IMS CAM unit stores a storage data, the first IMS CAM unit cell stores a first part of the storage data, and the second IMS CAM unit cell stores the storage data or a second part of the storage data, wherein the first part of the storage data is the most significant bit of the storage data, and the second part of the storage data is the remaining bits of the storage data. A hybrid in-memory search (IMS) content-addressable memory (CAM) unit as described in claim 1, wherein when a storage bit number of the first IMS CAM unit cell and the second IMS CAM unit cell is different, the first IMS CAM unit cell and the second IMS CAM unit cell are of different types; or when the storage data of one of the first IMS CAM unit cell and the second IMS CAM unit cell is a digital value and the storage data of the other of the first IMS CAM unit cell and the second IMS CAM unit cell is an analog value, the first IMS CAM unit cell and the second IMS CAM unit cell are of different types; or When one of the first IMS CAM unit cell and the second IMS CAM unit cell is an IMS unit cell and the other of the first IMS CAM unit cell and the second IMS CAM unit cell is an in-memory approximate search (in-memory approximate search search, IMS) cell, the first IMS CAM cell and the second IMS CAM cell are of different types. A hybrid in-memory search (IMS) content addressable memory (CAM) unit as described in claim 1, wherein the first IMS CAM cell and the second IMS CAM cell are selected from the following: single-level cell (SLC) IMS CAM cell, analog IMS CAM cell, SLC IMS CAM cell, multi-level cell (MLC) IMS CAM cell, MLC IMAS CAM cell. A hybrid in-memory search (IMS) content addressable memory (CAM) unit as described in claim 3, wherein the single-bit cell (SLC) IMS CAM cell comprises: a first memory cell and a second memory cell connected in series, when a first predetermined storage data is stored in the single-bit cell (SLC) IMS CAM cell, a first critical voltage of the first memory cell is a first reference critical voltage, and a second critical voltage of the second memory cell is a second reference critical voltage; when a second predetermined storage data is stored in the single-bit cell (SLC) IMS CAM cell, the first critical voltage is the second reference critical voltage, and the second critical voltage is the first reference critical voltage; When a third predetermined storage data is stored in the unit cell (SLC) IMAS CAM cell, the first critical voltage and the second critical voltage are both the first reference critical voltage; and when a fourth predetermined storage data is stored in the unit cell (SLC) IMAS When the CAM cell is used, the first critical voltage and the second critical voltage are both the second reference critical voltage; when the search data is a first predetermined search data, a first search voltage applied to the first memory cell is a first reference search voltage, and a second search voltage applied to the second memory cell is a second reference search voltage; when the search data is a second predetermined search data, the first search voltage is the second reference search voltage. When the search data is a third predetermined search data, the first search voltage and the second search voltage are both the second reference search voltage; and when the search data is a fourth predetermined search data, the first search voltage and the second search voltage are both the first reference search voltage, wherein the first reference search voltage is lower than the second reference search voltage. A hybrid in-memory search (IMS) content-addressable memory (CAM) unit as described in claim 4, wherein the analog IMS CAM cell comprises: a third and a fourth memory cell connected in series, the third and the fourth memory cell respectively having a third critical voltage and a fourth critical voltage, When performing a data search, an analog search data is converted into a third analog search voltage and a fourth analog search voltage, the third and the fourth memory cell receive the third analog search voltage and the fourth analog search voltage, and when the third analog search voltage and the fourth analog search voltage match within a matching range, the analog IMS The CAM cell provides a memory cell current; and when the third analog search voltage and the fourth analog search voltage do not match within the matching range, the analog IMS CAM cell does not provide the memory cell current. A hybrid intra-memory search (IMS) content addressable memory (CAM) unit as described in claim 3, wherein the SLC IMS CAM cell includes: a first and a second memory cell connected in parallel, or a first and a second memory cell connected in series, the first memory cell receiving a first search voltage, the second memory cell receiving a second search voltage, during an erase operation, an erase voltage is applied to the first and the second search voltages, the erase voltage is a negative bias, during a programming operation, a programming voltage is applied to the first and the second search voltages respectively to respectively program a first and a second critical voltage of the first and the second memory cells to define the SLC IMS A storage data of a CAM cell, and in a search operation, the first search voltage is applied with a first reference search voltage or a second reference search voltage, the second search voltage is applied with the first reference search voltage or the second reference search voltage, the second reference search voltage is greater than a first reference critical voltage, the first reference critical voltage is greater than the first reference search voltage, and the first reference search voltage is greater than a second reference critical voltage. A hybrid in-memory search (IMS) content-addressable memory (CAM) unit as described in claim 3, wherein the multi-bit cell (MLC) IMS CAM cell comprises: a first and a second memory cell connected in series, the first memory cell receiving a first search voltage, the second memory cell receiving a second search voltage, the multi-bit cell (MLC) IMS The storage data of the CAM cell is determined by the combination of the plurality of critical voltages of the first memory cell and the second memory cell. When the storage data is a first predetermined storage data, a first critical voltage of the first memory cell is a minimum critical voltage value, and a second critical voltage of the second memory cell is a maximum critical voltage value; when the storage data is a second predetermined storage data , the first critical voltage is the maximum critical voltage value, and the second critical voltage is the minimum critical voltage value; when the stored data is a third predetermined stored data, the first critical voltage and the second critical voltage are both the minimum critical voltage value; and when the stored data is a fourth predetermined stored data, the first critical voltage and the second critical voltage are equal to or greater than the maximum critical voltage value. A hybrid in-memory search (IMS) content-addressable memory (CAM) unit as described in claim 3, wherein the MLC IMAS CAM cell stores a storage data and receives a search data, the MLC IMAS The CAM cell includes: a first transistor having a first critical voltage and receiving a first gate bias; and a second transistor connected to the first transistor, the second transistor having a second critical voltage and receiving a second gate bias; wherein the storage data is encoded according to the first critical voltage and the second critical voltage, the search data is encoded according to the first gate bias and the second gate bias, there is a mismatch distance between the storage data and the search data, and an output current generated by the MLC IMAS CAM cell is related to the mismatch distance. A hybrid in-memory search (IMS) content-addressable memory (CAM) memory device includes: a hybrid IMS CAM memory array including a plurality of hybrid IMS CAM cells, a plurality of word lines, and a plurality of bit lines, wherein the hybrid IMS CAM cells are coupled to the word lines and the bit lines; a word line driving circuit coupled to the word lines for applying a plurality of search voltages to the hybrid IMS CAM cells according to a plurality of search data to search the hybrid IMS CAM cells; a bit line driving circuit coupled to the bit lines for applying a plurality of bit line driving voltages to the bit lines; and a sense amplifier coupled to the hybrid IMS The CAM unit is used to receive a plurality of induced currents transmitted by the hybrid IMS CAM units to determine whether the search data matches a plurality of stored data in the hybrid IMS CAM units. The hybrid IMS CAM unit includes: a first IMS CAM unit cell; and a second IMS CAM unit cell coupled to the first IMS CAM unit cell. The first IMS CAM unit cell and the second IMS CAM unit cell are of different types. When the hybrid IMS CAM unit stores a stored data, the first IMS CAM unit cell stores a first part of the stored data, and the second IMS The CAM cell stores the stored data or a second part of the stored data, and during data search, decodes a first part of a search data into a first search voltage and a second search voltage to search for the first part of the stored data stored in the first IMS CAM cell, and decodes the search data or a second part of the search data into a third search voltage and a fourth search voltage to search for the stored data or the second part of the stored data stored in the second IMS CAM cell, wherein the first part of the stored data is the most significant bit of the stored data, and the second part of the stored data is the remaining bits of the stored data. A hybrid in-memory search (IMS) content-addressable memory (CAM) memory device as described in claim 9, wherein when a storage bit number of the first IMS CAM cell and the second IMS CAM cell is different, the first IMS CAM cell and the second IMS CAM cell are of different types; or When the storage data of one of the first IMS CAM cell and the second IMS CAM cell is a digital value and the storage data of the other of the first IMS CAM cell and the second IMS CAM cell is an analog value, the first IMS CAM cell and the second IMS CAM cell are of different types; or when one of the first IMS CAM cell and the second IMS CAM cell is an IMS cell and the other of the first IMS CAM cell and the second IMS CAM cell is an in-memory proximity search (in-memory proximity search) approximate search, IMS) cell, the first IMS CAM cell and the second IMS CAM cell are of different types. A hybrid in-memory search (IMS) content addressable memory (CAM) memory device as described in claim 9, wherein the first IMS CAM cell and the second IMS CAM cell are selected from the following: single-level cell (SLC) IMS CAM cell, analog IMS CAM cell, SLC IMS CAM cell, multi-level cell (MLC) IMS CAM cell, MLC IMAS CAM cell. A hybrid in-memory search (IMS) content addressable memory (CAM) memory device as described in claim 11, wherein the single-bit cell (SLC) IMS CAM cell comprises: a first memory cell and a second memory cell connected in series, when a first predetermined storage data is stored in the single-bit cell (SLC) IMS CAM cell, a first critical voltage of the first memory cell is a first reference critical voltage, and a second critical voltage of the second memory cell is a second reference critical voltage; when a second predetermined storage data is stored in the single-bit cell (SLC) IMS CAM cell, the first critical voltage is the second reference critical voltage, and the second critical voltage is the first reference critical voltage; when a third predetermined storage data is stored in the unit cell (SLC) IMAS CAM cell, the first critical voltage and the second critical voltage are both the first reference critical voltage; and when a fourth predetermined storage data is stored in the unit cell (SLC) IMAS When the search data is a first predetermined search data, a first search voltage applied to the first memory cell is a first reference search voltage, and a second search voltage applied to the second memory cell is a second reference search voltage; when the search data is a second predetermined search data, the first search voltage is the second reference search voltage. When the search data is a third predetermined search data, the first search voltage and the second search voltage are both the second reference search voltage; and when the search data is a fourth predetermined search data, the first search voltage and the second search voltage are both the first reference search voltage, wherein the first reference search voltage is lower than the second reference search voltage. A hybrid in-memory search (IMS) content-addressable memory (CAM) memory device as described in claim 12, wherein the analog IMS CAM cell comprises: a third and a fourth memory cell connected in series, the third and the fourth memory cell respectively having a third critical voltage and a fourth critical voltage, and when performing a data search, an analog search data is converted into a third analog search voltage and a fourth analog search voltage, the third and the fourth memory cell receive the third analog search voltage and the fourth analog search voltage, and when the third analog search voltage and the fourth analog search voltage match in a matching range, the analog IMS The CAM cell provides a memory cell current; and when the third analog search voltage and the fourth analog search voltage do not match within the matching range, the analog IMS CAM cell does not provide the memory cell current. A hybrid intra-memory search (IMS) content-addressable memory (CAM) memory device as described in claim 11, wherein the SLC IMS CAM cell comprises: a first and a second memory cell connected in parallel, or a first and a second memory cell connected in series, the first memory cell receiving a first search voltage, the second memory cell receiving a second search voltage, during an erase operation, an erase voltage is applied to the first and the second search voltages, the erase voltage being a negative bias, and during a programming operation, a programming voltage is applied to the first and the second search voltages respectively to respectively program a first and a second critical voltage of the first and the second memory cells to define the SLC IMS A storage data of a CAM cell, and in a search operation, the first search voltage is applied with a first reference search voltage or a second reference search voltage, the second search voltage is applied with the first reference search voltage or the second reference search voltage, the second reference search voltage is greater than a first reference critical voltage, the first reference critical voltage is greater than the first reference search voltage, and the first reference search voltage is greater than a second reference critical voltage. A hybrid in-memory search (IMS) content-addressable memory (CAM) memory device as described in claim 11, wherein the multi-bit cell (MLC) IMS CAM cell comprises: a first and a second memory cell connected in series, the first memory cell receiving a first search voltage, the second memory cell receiving a second search voltage, the multi-bit cell (MLC) IMS The storage data of the CAM cell is determined by the combination of the plurality of critical voltages of the first memory cell and the second memory cell. When the storage data is a first predetermined storage data, a first critical voltage of the first memory cell is a minimum critical voltage value, and a second critical voltage of the second memory cell is a maximum critical voltage value; when the storage data is a second predetermined storage data , the first critical voltage is the maximum critical voltage value, and the second critical voltage is the minimum critical voltage value; when the stored data is a third predetermined stored data, the first critical voltage and the second critical voltage are both the minimum critical voltage value; and when the stored data is a fourth predetermined stored data, the first critical voltage and the second critical voltage are equal to or greater than the maximum critical voltage value. The hybrid in-memory search (IMS) content-addressable memory (CAM) memory device of claim 11, wherein the MLC IMS CAM cell stores a storage data and receives a search data, the MLC IMS The CAM cell includes: a first transistor having a first critical voltage and receiving a first gate bias; and a second transistor connected to the first transistor, the second transistor having a second critical voltage and receiving a second gate bias; wherein the storage data is encoded according to the first critical voltage and the second critical voltage, the search data is encoded according to the first gate bias and the second gate bias, there is a mismatch distance between the storage data and the search data, and an output current generated by the MLC IMAS CAM cell is related to the mismatch distance. A hybrid in-memory search (IMS) content-addressable memory (CAM) data search method includes: storing a storage data in a hybrid IMS CAM unit, the hybrid IMS CAM unit includes: a first IMS CAM unit cell, and a second IMS CAM unit cell coupled to the first IMS CAM unit cell, wherein the first IMS CAM unit cell and the second IMS CAM unit cell are of different types, and when the hybrid IMS CAM unit stores the storage data, the first IMS CAM unit cell stores a first part of the storage data, and the second IMS CAM unit cell stores the storage data or a second part of the storage data; searching the storage data for the hybrid IMS The CAM unit performs a data search, wherein during the data search, a first portion of the search data is decoded into a first search voltage and a second search voltage to search for the first portion of the stored data stored in the first IMS CAM cell, and the search data or a second portion of the search data is decoded into a third search voltage and a fourth search voltage to search for the stored data or the second portion of the stored data stored in the second IMS CAM cell; sensing the hybrid IMS The CAM unit generates a sensing current to generate a sensing result; and determines whether the search data matches the stored data based on the sensing result, wherein the first part of the stored data is the most significant bit of the stored data, and the second part of the stored data is the remaining bits of the stored data. A hybrid in-memory search (IMS) content-addressable memory (CAM) data search method as described in claim 17, wherein when a storage bit number of the first IMS CAM unit cell and the second IMS CAM unit cell is different, the first IMS CAM unit cell and the second IMS CAM unit cell are of different types; or when the storage data of one of the first IMS CAM unit cell and the second IMS CAM unit cell is a digital value and the storage data of the other of the first IMS CAM unit cell and the second IMS CAM unit cell is an analog value, the first IMS CAM unit cell and the second IMS CAM unit cell are of different types; or when one of the first IMS CAM unit cell and the second IMS CAM unit cell is an IMS unit cell and the other of the first IMS CAM unit cell and the second IMS CAM unit cell is an in-memory approximate search (in-memory approximate search) search, IMS) cell, the first IMS CAM cell and the second IMS CAM cell are of different types. A hybrid in-memory search (IMS) content-addressable memory (CAM) data search method as described in claim 17, wherein the first IMS CAM cell and the second IMS CAM cell are selected from the following: single-level cell (SLC) IMS CAM cell, analog IMS CAM cell, SLC IMS CAM cell, multi-level cell (MLC) IMS CAM cell, MLC IMAS CAM cell. A hybrid in-memory search (IMS) content-addressable memory (CAM) data search method as described in claim 19, wherein the single-bit cell (SLC) IMS CAM cell comprises: a first memory cell and a second memory cell connected in series, when a first predetermined storage data is stored in the single-bit cell (SLC) IMS CAM cell, a first critical voltage of the first memory cell is a first reference critical voltage, and a second critical voltage of the second memory cell is a second reference critical voltage; When a second predetermined storage data is stored in the single-bit cell (SLC) IMS CAM cell, the first critical voltage is the second reference critical voltage, and the second critical voltage is the first reference critical voltage; when a third predetermined storage data is stored in the unit cell (SLC) IMAS CAM cell, the first critical voltage and the second critical voltage are both the first reference critical voltage; and when a fourth predetermined storage data is stored in the unit cell (SLC) IMAS When the search data is a first predetermined search data, a first search voltage applied to the first memory cell is a first reference search voltage, and a second search voltage applied to the second memory cell is a second reference search voltage; when the search data is a second predetermined search data, the first search voltage is the second reference search voltage. When the search data is a third predetermined search data, the first search voltage and the second search voltage are both the second reference search voltage; and when the search data is a fourth predetermined search data, the first search voltage and the second search voltage are both the first reference search voltage, wherein the first reference search voltage is lower than the second reference search voltage. A hybrid in-memory search (IMS) content-addressable memory (CAM) data search method as described in claim 20, wherein the analog IMS CAM cell comprises: a third and a fourth memory cell connected in series, the third and the fourth memory cell respectively having a third critical voltage and a fourth critical voltage, when performing a data search, an analog search data is converted into a third analog search voltage and a fourth analog search voltage, the third and the fourth memory cell receive the third analog search voltage and the fourth analog search voltage, when the third analog search voltage and the fourth analog search voltage match in a matching range, the analog IMS The CAM cell provides a memory cell current; and when the third analog search voltage and the fourth analog search voltage do not match within the matching range, the analog IMS CAM cell does not provide the memory cell current. A hybrid intra-memory search (IMS) content-addressable memory (CAM) data search method as described in claim 19, wherein the SLC IMS CAM cell comprises: a first and a second memory cell connected in parallel, or a first and a second memory cell connected in series, the first memory cell receiving a first search voltage, the second memory cell receiving a second search voltage, during an erase operation, an erase voltage is applied to the first and the second search voltages, the erase voltage being a negative bias, during a programming operation, by applying a programming voltage to the first and the second search voltages, respectively, to respectively program a first and a second critical voltage of the first and the second memory cell to define the SLC IMS A storage data of a CAM cell, and in a search operation, the first search voltage is applied with a first reference search voltage or a second reference search voltage, the second search voltage is applied with the first reference search voltage or the second reference search voltage, the second reference search voltage is greater than a first reference critical voltage, the first reference critical voltage is greater than the first reference search voltage, and the first reference search voltage is greater than a second reference critical voltage. A hybrid in-memory search (IMS) content-addressable memory (CAM) data search method as described in claim 19, wherein the multi-bit cell (MLC) IMS CAM cell comprises: a first and a second memory cell connected in series, the first memory cell receiving a first search voltage, the second memory cell receiving a second search voltage, the multi-bit cell (MLC) IMS The storage data of the CAM cell is determined by the combination of the plurality of critical voltages of the first memory cell and the second memory cell. When the storage data is a first predetermined storage data, a first critical voltage of the first memory cell is a minimum critical voltage value, and a second critical voltage of the second memory cell is a maximum critical voltage value; when the storage data is a second predetermined storage data , the first critical voltage is the maximum critical voltage value, and the second critical voltage is the minimum critical voltage value; when the stored data is a third predetermined stored data, the first critical voltage and the second critical voltage are both the minimum critical voltage value; and when the stored data is a fourth predetermined stored data, the first critical voltage and the second critical voltage are equal to or greater than the maximum critical voltage value. The hybrid in-memory search (IMS) content-addressable memory (CAM) data search method as described in claim 19, wherein the MLC IMAS CAM cell stores a storage data and receives a search data, the MLC IMAS The CAM cell includes: a first transistor having a first critical voltage and receiving a first gate bias; and a second transistor connected to the first transistor, the second transistor having a second critical voltage and receiving a second gate bias; wherein the storage data is encoded according to the first critical voltage and the second critical voltage, the search data is encoded according to the first gate bias and the second gate bias, there is a mismatch distance between the storage data and the search data, and an output current generated by the MLC IMAS CAM cell is related to the mismatch distance.

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