TWI849715B - Semiconductor structure for 3d memory and manufacturing method thereof - Google Patents

Abstract

Provided are a semiconductor structure for a three-dimensional (3D) memory and a manufacturing method thereof. The semiconductor structure may be used in a 3D AND flash memory. The semiconductor structure includes a dielectric layer disposed on a substrate, a ground layer, a ground via, a dielectric stacked structure, and a through via. The ground layer is disposed on the dielectric layer. The ground via is disposed in the ground layer and the dielectric layer and electrically connected to the substrate. The dielectric stacked structure is disposed on the ground layer. The through via is disposed in the dielectric stacked structure and connected to the ground layer. The dielectric stacked structure has a vertical channel hole.

Description

Semiconductor structure for three-dimensional memory and method for manufacturing the same

The present invention relates to a semiconductor device and a manufacturing method thereof, and in particular to a semiconductor structure used for three-dimensional (3D) memory and a manufacturing method thereof.

Non-volatile memory (such as flash memory) has the advantage that the stored data will not disappear even after power failure. Therefore, it has become a type of memory widely used in personal computers and other electronic devices.

In current 3D flash memory, in the memory array region, a vertical channel (VC) is disposed in a stacked structure consisting of a dielectric layer and a conductive layer serving as a gate. Generally speaking, in the process of forming a vertical channel, a patterned hard mask layer having a considerable thickness is first formed on the stacked structure consisting of an oxide layer and a nitride layer, and then a patterning process is performed to form a vertical channel opening (hole) in the stacked structure, and then the vertical channel opening is filled with a channel material.

However, the patterned hard mask layer often needs to have a large thickness, which results in reduced thickness uniformity. In particular, since the edge of the substrate usually has a sloping profile, the stacked structure described above will have a sloping sidewall at the edge of the substrate. As a result, when the patterned hard mask layer extends to the sidewall of the stacked structure, the patterned hard mask layer on the sidewall of the stacked structure will have a thinner thickness. In the subsequent deep-etching process for forming the vertical channel, charges will gradually accumulate around the vertical channel opening and the thinner portion of the patterned hard mask layer. When the accumulated charge is too much, arcing occurs, causing damage to the substrate and/or components mounted on the substrate.

The present invention provides a semiconductor structure for three-dimensional memory, which has a through via disposed in a dielectric stack structure and connected to a ground layer to release charges generated in a manufacturing process.

The present invention provides a method for manufacturing a semiconductor structure for a three-dimensional memory, wherein a through via is formed in a dielectric stack structure and connected to a ground layer.

The semiconductor structure for three-dimensional memory of the present invention includes a dielectric layer, a ground layer, a ground via, a dielectric stack structure and a through via. The dielectric layer is arranged on a substrate. The ground layer is arranged on the dielectric layer. The ground via is arranged in the ground layer and the dielectric layer and is electrically connected to the substrate. The dielectric stack structure is arranged on the ground layer. The through via is arranged in the dielectric stack structure and is connected to the ground layer. The dielectric stack structure has a vertical channel opening.

In one embodiment of the semiconductor structure for three-dimensional memory of the present invention, the material of the through via includes polysilicon or metal.

In one embodiment of the semiconductor structure for three-dimensional memory of the present invention, the diameter of the through via is the same as the diameter of the vertical channel opening.

In one embodiment of the semiconductor structure for three-dimensional memory of the present invention, the shortest distance between the through via and the vertical channel opening is more than 10% of the aperture of the vertical channel opening.

In one embodiment of the semiconductor structure for three-dimensional memory of the present invention, the shortest distance between the through via and the ground via is more than 10% of the aperture of the ground via.

In one embodiment of the semiconductor structure for three-dimensional memory of the present invention, the bottom surface of the through via is located on the top surface of the ground layer.

In one embodiment of the semiconductor structure for three-dimensional memory of the present invention, the bottom surface of the through via is located in the ground layer.

In one embodiment of the semiconductor structure for three-dimensional memory of the present invention, the bottom surface of the through via is located on the top surface of the dielectric layer.

In one embodiment of the semiconductor structure for three-dimensional memory of the present invention, the bottom surface of the through via and the bottom surface of the vertical channel opening are located at the same level.

In one embodiment of the semiconductor structure for three-dimensional memory of the present invention, a device structure layer is further included. The device structure layer is disposed between the substrate and the dielectric layer, wherein the grounding via is electrically connected to the substrate through the device structure layer.

In one embodiment of the semiconductor structure for three-dimensional memory of the present invention, it also includes a device structure layer, wherein the substrate includes a memory area, a peripheral area, an edge area and a peripheral device area, the peripheral area is located between the memory area and the edge area, the peripheral device area is adjacent to the memory area, and the device structure layer is arranged on the substrate in the peripheral device area.

In one embodiment of the semiconductor structure for three-dimensional memory of the present invention, the substrate includes a memory region, a peripheral region and an edge region, the peripheral region is located between the memory region and the edge region, and the through-via is located in the peripheral region.

In one embodiment of the semiconductor structure for three-dimensional memory of the present invention, the substrate includes a memory region, a peripheral region and an edge region, the peripheral region is located between the memory region and the edge region, and the through-via is located in the memory region.

The manufacturing method of the semiconductor structure for three-dimensional memory of the present invention includes the following steps. A dielectric layer is formed on a substrate. A grounding layer is formed on the dielectric layer. A grounding via is formed in the grounding layer and the dielectric layer and is electrically connected to the substrate. A dielectric stack structure is formed on the grounding layer. A through-via connected to the grounding layer is formed in the dielectric stack structure. A patterned hard mask layer is formed on the dielectric stack structure, wherein the patterned hard mask layer extends to the side wall of the dielectric stack structure. A vertical channel opening is formed in the dielectric stack structure using the patterned hard mask layer as a mask.

In one embodiment of the method for manufacturing a semiconductor structure for a three-dimensional memory of the present invention, the bottom surface of the through via is located on the top surface of the ground layer.

In one embodiment of the method for manufacturing a semiconductor structure for a three-dimensional memory of the present invention, the bottom surface of the through via is located in the ground layer.

In one embodiment of the method for manufacturing a semiconductor structure for a three-dimensional memory of the present invention, the bottom surface of the through via is located on the top surface of the dielectric layer.

In an embodiment of the method for manufacturing a semiconductor structure for three-dimensional memory of the present invention, before forming the dielectric layer, the method further includes forming a device structure layer on the substrate.

In one embodiment of the manufacturing method of the semiconductor structure for three-dimensional memory of the present invention, the substrate includes a memory area, a peripheral area, an edge area and a peripheral component area, the peripheral area is located between the memory area and the edge area, the peripheral component area is adjacent to the memory area, and the component structure layer is formed on the substrate in the peripheral component area.

In one embodiment of the method for manufacturing a semiconductor structure for three-dimensional memory of the present invention, the thickness of the patterned hard mask layer on the top surface of the dielectric stack structure is greater than the thickness of the patterned hard mask layer on the sidewall of the dielectric stack structure.

Based on the above, in the semiconductor structure for three-dimensional memory of the present invention, the through via is arranged in the dielectric stack structure and connected to the ground layer, and the ground layer is electrically connected to the substrate through the ground via. Therefore, a conductive path composed of the through via, the ground layer and the ground via can be formed to conduct the charge generated in the process to the substrate through the conductive path. In this way, arc discharge caused by charge accumulation can be effectively prevented, thereby preventing the substrate and/or components arranged on the substrate from being damaged by arc discharge.

The following examples are listed and illustrated in detail, but the examples provided are not intended to limit the scope of the present invention. In addition, the drawings are for illustration purposes only and are not drawn in their original size. For ease of understanding, the same components will be indicated by the same symbols in the following description.

The terms "include", "including", "have", etc. used in this document are open terms, which means "including but not limited to".

Directional terms used herein, such as "above", "below", etc., are only used to refer to the directions of the drawings and are not used to limit the present invention. Therefore, it should be understood that "above" can be used interchangeably with "below", and when an element such as a layer or film is placed "on" another element, the element can be placed directly on the other element, or there can be an intermediate element. On the other hand, when an element is said to be placed "directly" on another element, there is no intermediate element between the two.

In addition, in this article, the range expressed by "a numerical value to another numerical value" is a summary expression method to avoid listing all numerical values in the range one by one in the specification. Therefore, the description of a specific numerical range covers any numerical value in the numerical range, and covers a smaller numerical range defined by any numerical value in the numerical range.

The semiconductor structure of the present invention can be applied to three-dimensional memory, and in particular to three-dimensional flash memory, to prevent arc discharge during the manufacturing process, thereby preventing the substrate and/or components disposed on the substrate from being damaged. The semiconductor structure of the present invention will be described in detail below.

1A to 1E are schematic cross-sectional views of a manufacturing process of a semiconductor structure for a three-dimensional memory according to a first embodiment of the present invention.

First, referring to FIG. 1A , a substrate 100 is provided. The substrate 100 includes a memory region 100a, a peripheral region 100b, and an edge region 100c. Generally speaking, after forming a three-dimensional memory, a staircase structure is formed in the peripheral region 100b, so the peripheral region 100b can also be referred to as a staircase region. In this embodiment, the substrate 100 is, for example, a silicon wafer. Then, a device structure layer 102 is formed on the substrate 100. The device structure layer 102 is electrically connected to the substrate 100. In order to make the figure clear and easy to describe, the detailed structure of the device structure layer 102 is not shown in FIG. 1A . The device structure layer 102 may include various semiconductor devices that are generally known. For example, in this embodiment, the device structure layer 102 may include a metal oxide semiconductor (MOS) transistor formed on the surface of the substrate 100, an interconnect structure electrically connected to the MOS transistor, and a dielectric layer covering the MOS transistor and the interconnect structure, but the present invention is not limited thereto. In other embodiments, the device structure layer 102 may also include other semiconductor devices known to those skilled in the art. In addition, the method for forming the device structure layer 102 is well known to those skilled in the art and will not be described separately herein.

Generally speaking, the edge of the substrate usually has an inclined profile, so that the film layer formed at the edge of the substrate will have an inclined sidewall. Therefore, in this embodiment, the device structure layer 102 formed near the edge of the substrate 100 has an inclined sidewall S1.

Then, a dielectric layer 104 is formed on the device structure layer 102. The dielectric layer 104 can be used as an insulating layer between the conductive layer formed subsequently and the device structure layer 102. In this embodiment, the dielectric layer 104 is a silicon oxide layer, but the present invention is not limited thereto. The method for forming the dielectric layer 104 is well known to those skilled in the art and will not be described further herein. Similarly, the dielectric layer 104 formed near the edge of the substrate 100 has an inclined sidewall S2.

Next, referring to FIG. 1B , a grounding layer 106 is formed on the dielectric layer 104. The grounding layer 106 can be used to conduct the charges generated in the subsequent process to the substrate 100. In the present embodiment, the grounding layer 106 is a polysilicon layer, but the present invention is not limited thereto. In other embodiments, the grounding layer 106 can be other conductive layers, such as a metal layer. Similarly, the grounding layer 106 formed near the edge of the substrate 100 has an inclined sidewall S3.

Afterwards, a grounding via 108 is formed in the grounding layer 106 and the dielectric layer 104. The method for forming the grounding via 108 is, for example, to first form a hole in the grounding layer 106 and the dielectric layer 104 to expose the conductive pad of the device structure layer 102, and then fill the hole with a conductive material. In the present embodiment, the material of the grounding via 108 may be tungsten. In this way, the grounding via 108 can connect the grounding layer 106 and the conductive pad in the device structure layer 102, so that the grounding layer 106 can be electrically connected to the device structure layer 102. In FIG. 1C, only one grounding via 108 is shown, and the grounding via 108 is adjacent to the edge of the substrate 100, but the present invention is not limited to this. In other embodiments, a plurality of ground vias 108 may be formed in the ground layer 106 and the dielectric layer 104 according to actual conditions, and the ground vias 108 may be located at any appropriate position. In this embodiment, the ground vias 108 are formed in the peripheral region 100b.

Then, referring to FIG. 1C , a dielectric stack structure 110 is formed on the ground layer 106. The dielectric stack structure 110 is formed by alternately stacking different dielectric layers. The dielectric stack structure 110 is well known to those skilled in the art as the initial structure for the three-dimensional memory to be formed subsequently, and will not be described separately here. In the present embodiment, the dielectric stack structure 110 includes a plurality of oxide layers 110a and a plurality of nitride layers 110b alternately formed on the ground layer 106. The nitride layer 110b can be used as a sacrificial layer for subsequently forming a gate of the memory. The method for forming the dielectric stack structure 110 is well known to those skilled in the art, and will not be described separately here. In addition, in this embodiment, a portion of the dielectric stack structure 110 is located on the substrate 100. That is, the dielectric stack structure 110 covers the device structure layer 102, the dielectric layer 104, and the ground layer 106. Similarly, the dielectric stack structure 110 formed near the edge of the substrate 100 has an inclined sidewall S4.

Next, referring to FIG. 1D , a through via 112 connected to the ground layer 106 is formed in the dielectric stack structure 110. The method for forming the through via 112 is, for example, to first form a hole in the dielectric stack structure 110 and the ground layer 106 to expose the ground layer 106, and then fill the hole with a conductive material. In this embodiment, the material of the through via 112 can be polysilicon or metal. In this embodiment, the bottom surface of the through via 112 can be located on the top surface of the ground layer 106. That is, in the process of forming the through via 112, the ground layer 106 is used as an etching stop layer. Alternatively, in other embodiments, the bottom surface of the through via 112 may be located in the ground layer 106, as long as the through via 112 can contact the ground layer 106 to achieve the purpose of electrical connection. Alternatively, in other embodiments, the through via 112 may penetrate the ground layer 106 so that the bottom surface of the through via 112 is located on the top surface of the dielectric layer 104.

In FIG. 1D , only one through via 112 is shown, and the through via 112 is adjacent to the ground via 108. The shortest distance between the through via 112 and the ground via 108 is, for example, more than 10% of the diameter of the ground via 108. In other embodiments, a plurality of through vias 112 may be formed, and the through vias 112 may be formed at other locations in the dielectric stack structure 110 according to layout requirements, and the present invention is not limited thereto.

In this embodiment, the through via 112 is located in the peripheral area 100b and between the ground via 108 and the memory area 100a, but the present invention is not limited thereto. In other embodiments, as shown in FIG. 3 , the through via 112 may be located in the peripheral area 100b and between the ground via 108 and the edge area 100c.

1E , a patterned hard mask layer 114 is formed on the dielectric stack structure 110. The patterned hard mask layer 114 has openings that expose the region where the vertical channel openings of the three-dimensional memory are to be formed. In addition, since the dielectric stack structure 110 near the edge of the substrate 100 has an inclined sidewall S4, the patterned hard mask layer 114 formed on the dielectric stack structure 110 extends to the sidewall S4 of the dielectric stack structure 110 and has an inclined sidewall S5. As a result, the thickness of the patterned mask layer 114 on the top surface of the dielectric stack structure 110 is greater than the thickness of the patterned hard mask layer 114 on the sidewall S4 of the dielectric stack structure 110 .

Afterwards, a dry etching process is performed using the patterned hard mask layer 114 as an etching mask to remove a portion of the dielectric stack structure 110, so as to form a vertical channel opening 116 exposing the ground layer 106 in the dielectric stack structure 110. In this embodiment, the depth of the vertical channel opening 116 is the same as the depth of the through-via 112, that is, the bottom surface of the through-via 112 and the bottom surface of the vertical channel opening 116 are located at the same horizontal height, but the present invention is not limited thereto.

The diameter of the through-via 112 may be the same as the diameter of the vertical channel opening 116, but the present invention is not limited thereto. In addition, the shortest distance between the through-via 112 and the vertical channel opening 116 is, for example, more than 10% of the diameter of the vertical channel opening 116 to avoid the through-via 112 and the vertical channel opening 116 being too close to each other and affecting the channel region of the memory formed subsequently.

In this way, the manufacturing of the semiconductor structure 10 of this embodiment is completed. Subsequently, the semiconductor structure 10 may be subjected to a commonly known three-dimensional memory process to form a three-dimensional memory.

In the semiconductor structure 10, a through via 112 is disposed in the dielectric stack structure 110 and connected to the ground layer 106, and the ground layer 106 is electrically connected to the device structure layer 102 disposed on the substrate 100 through the ground via 108. Therefore, a conductive path consisting of the through via 112, the ground layer 106, the ground via 108, and the conductive element in the device structure layer 102 is formed in the semiconductor structure 10. Therefore, even if the thickness of the patterned hard mask layer 114 on the sidewall of the dielectric stack structure 110 is relatively thin, the charges generated during the process of forming the vertical channel opening 116 by the dry etching process can be conducted to the substrate 100 via the above-mentioned conductive path, and will not be accumulated around the vertical channel opening 116 and at the thinner portion of the patterned hard mask layer 114. Therefore, arc discharge can be effectively prevented from being generated, so as to prevent the substrate and/or the components disposed on the substrate from being damaged by arc discharge during the manufacturing process.

2A to 2B are schematic cross-sectional views of a manufacturing process of a semiconductor structure for a three-dimensional memory according to a second embodiment of the present invention. In this embodiment, the same elements as those in the first embodiment are denoted by the same reference numerals and will not be described again.

First, referring to FIG. 2A , in this embodiment, the substrate 100 includes a memory region 100a, a peripheral region 100b, an edge region 100c, and a peripheral device region 100d. The peripheral device region 100d is adjacent to the memory region 100a. A device structure layer 102 is formed on the substrate 100 in the peripheral device region 100d. Then, a dielectric layer 104 and a grounding layer 106 are formed on the substrate 100 in the memory region 100a, the peripheral region 100b, and the edge region 100c. Then, a grounding via 108 connected to the substrate 100 is formed in the dielectric layer 104 and the grounding layer 106. That is, in this embodiment, the device structure layer 102 including the metal oxide semiconductor transistor, the interconnect structure and the dielectric layer covering the metal oxide semiconductor transistor and the interconnect structure is not formed under the three-dimensional memory formed subsequently, but is formed outside the memory region 100a.

Then, referring to FIG. 2B , the steps described in FIG. 1C to FIG. 1E are performed to form the semiconductor structure 20. In the semiconductor structure 20, the through via 112 is disposed in the dielectric stack structure 110 and connected to the ground layer 106, and the ground via 108 passes through the dielectric layer 104 and is connected to the substrate 100. Therefore, a conductive path consisting of the through via 112, the ground layer 106, and the ground via 108 is formed in the semiconductor structure 20. Therefore, even if the thickness of the patterned hard mask layer 114 on the sidewall of the dielectric stack structure 110 is relatively thin, the charges generated during the process of forming the vertical channel opening 116 by the dry etching process can be conducted to the substrate via the above-mentioned conductive path, and will not be accumulated around the vertical channel opening 116 and at the thinner portion of the patterned hard mask layer. Therefore, arc discharge can be effectively prevented from being generated, so as to prevent the substrate and/or the components disposed on the substrate from being damaged by arc discharge during the manufacturing process.

Although the present invention has been disclosed as above by the embodiments, they are not intended to limit the present invention. Any person with ordinary knowledge in the relevant technical field can make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be defined by the scope of the attached patent application.

10, 20: semiconductor structure 100: substrate 100a: memory area 100b: peripheral area 100c: edge area 100d: peripheral device area 102: device structure layer 104: dielectric layer 106: ground layer 108: ground via 110: dielectric stack structure 110a: oxide layer 110b: nitride layer 112: through via 114: patterned hard mask layer 116: vertical channel opening S1, S2, S3, S4, S5: sidewalls

Figures 1A to 1E are schematic cross-sectional views of the manufacturing process of a semiconductor structure for a three-dimensional memory according to the first embodiment of the present invention. Figures 2A to 2B are schematic cross-sectional views of the manufacturing process of a semiconductor structure for a three-dimensional memory according to the second embodiment of the present invention. Figure 3 is a schematic cross-sectional view of the position of a through-hole according to another embodiment of the present invention.

20:Semiconductor structure

100: Base

100a: memory area

100b: Peripheral area

100c:Fringe Area

102: Component structure layer

104: Dielectric layer

106: Ground layer

108: Grounding via

110: Dielectric stack structure

110a: oxide layer

110b: Nitride layer

112: Through-hole

114: Patterned hard cover layer

116: Vertical channel opening

Claims (20)

A semiconductor structure for three-dimensional memory, comprising: a dielectric layer disposed on a substrate; a ground layer disposed on the dielectric layer; a ground via disposed in the ground layer and the dielectric layer and electrically connected to the substrate; a dielectric stack structure disposed on the ground layer; and a through via disposed in the dielectric stack structure and connected to the ground layer, wherein the dielectric stack structure has a vertical channel opening. A semiconductor structure for three-dimensional memory as described in claim 1, wherein the material of the through via comprises polysilicon or metal. A semiconductor structure for three-dimensional memory as described in claim 1, wherein the aperture of the through via is the same as the aperture of the vertical channel opening. A semiconductor structure for three-dimensional memory as described in claim 1, wherein the shortest distance between the through via and the vertical channel opening is more than 10% of the aperture of the vertical channel opening. A semiconductor structure for three-dimensional memory as described in claim 1, wherein the minimum distance between the through via and the ground via is more than 10% of the hole diameter of the ground via. A semiconductor structure for three-dimensional memory as described in claim 1, wherein the bottom surface of the through via is located on the top surface of the ground layer. A semiconductor structure for three-dimensional memory as described in claim 1, wherein the bottom surface of the through via is located in the ground layer. A semiconductor structure for three-dimensional memory as described in claim 1, wherein the bottom surface of the through via is located on the top surface of the dielectric layer. A semiconductor structure for three-dimensional memory as described in claim 1, wherein the bottom surface of the through via and the bottom surface of the vertical channel opening are located at the same horizontal height. The semiconductor structure for three-dimensional memory as described in claim 1 further includes a device structure layer disposed between the substrate and the dielectric layer, wherein the ground via is electrically connected to the substrate through the device structure layer. The semiconductor structure for three-dimensional memory as described in claim 1 further includes a device structure layer, wherein the substrate includes a memory region, a peripheral region, an edge region and a peripheral device region, the peripheral region is located between the memory region and the edge region, the peripheral device region is adjacent to the memory region, and the device structure layer is arranged on the substrate in the peripheral device region. A semiconductor structure for three-dimensional memory as described in claim 1, wherein the substrate includes a memory region, a peripheral region and an edge region, the peripheral region is located between the memory region and the edge region, and the through-via is located in the peripheral region. A semiconductor structure for three-dimensional memory as described in claim 1, wherein the substrate includes a memory region, a peripheral region and an edge region, the peripheral region is located between the memory region and the edge region, and the through-via is located in the memory region. A method for manufacturing a semiconductor structure for a three-dimensional memory, comprising: forming a dielectric layer on a substrate; forming a grounding layer on the dielectric layer; forming a grounding via electrically connected to the substrate in the grounding layer and the dielectric layer; forming a dielectric stacking structure on the grounding layer; forming a through-via connected to the grounding layer in the dielectric stacking structure; forming a patterned hard mask layer on the dielectric stacking structure, wherein the patterned hard mask layer extends to the side wall of the dielectric stacking structure; and using the patterned hard mask layer as a mask, forming a vertical channel opening in the dielectric stacking structure. A method for manufacturing a semiconductor structure for a three-dimensional memory as described in claim 14, wherein the bottom surface of the through via is located on the top surface of the ground layer. A method for manufacturing a semiconductor structure for a three-dimensional memory as described in claim 14, wherein the bottom surface of the through via is located in the ground layer. A method for manufacturing a semiconductor structure for a three-dimensional memory as described in claim 14, wherein the bottom surface of the through via is located on the top surface of the dielectric layer. The method for manufacturing a semiconductor structure for three-dimensional memory as described in claim 14 further includes forming a device structure layer on the substrate before forming the dielectric layer. A method for manufacturing a semiconductor structure for a three-dimensional memory as described in claim 18, wherein the substrate includes a memory region, a peripheral region, an edge region and a peripheral component region, the peripheral region is located between the memory region and the edge region, the peripheral component region is adjacent to the memory region, and the component structure layer is formed on the substrate in the peripheral component region. A method for manufacturing a semiconductor structure for a three-dimensional memory as described in claim 14, wherein the thickness of the patterned hard mask layer on the top surface of the dielectric stack structure is greater than the thickness of the patterned hard mask layer on the side wall of the dielectric stack structure.

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