TWI849505B - GaN POWER DEVICE - Google Patents

Abstract

A GaN power device includes a substrate. A transition layer, a buffer layer, a channel layer, a barrier layer, and a gate stack are sequentially formed on the substrate. The substrate includes silicon substrate and a 3C-SiC layer formed on the silicon substrate.　The transition layer includes doped GaN. The channel layer includes GaN. A 2DEG channel is formed between the channel layer and the barrier layer. The gate stack includes a p-type GaN layer on the barrier layer, a cap layer on the p-type GaN layer, and a gate electrode on the cap layer. The cap layer includes Al _xGa _1-xN, in which x is from 0.18 to 0.24.

Description

Gallium Nitride Power Devices

The present invention relates to a gallium nitride power device.

Group III nitride materials, such as gallium nitride (GaN), are wide bandgap materials that have attracted attention for use in manufacturing power transistors. Power devices made using GaN will achieve faster switching speeds, less energy loss, and greater blocking voltages compared to silicon-based power devices.

However, the bonding of III-nitride materials to silicon substrates is not without challenges. There are considerable differences in the thermal expansion coefficient values and lattice spacing between III-nitride materials and silicon substrates. The mismatch in these parameters will result in higher mechanical stress values in the III-nitride layer on the silicon substrate. If the stress is too high, the substrate will bend significantly and cracks will appear in the deposited film, affecting the yield of the finished product.

One embodiment of the present invention provides a gallium nitride power element, comprising a dielectric substrate, a transition layer disposed on the dielectric substrate, a buffer layer disposed on the transition layer, a channel layer disposed on the buffer layer, a barrier layer disposed on the channel layer, and a gate stack disposed on the barrier layer. The dielectric substrate comprises a silicon substrate and a 3C-SiC layer formed on the silicon substrate. The buffer layer comprises a doped gallium nitride material, and the channel layer comprises a gallium nitride material. A two-dimensional electron (2DEG) channel is formed between the channel layer and the barrier layer. The gate stack includes a p-type gallium nitride layer disposed on the barrier layer, a cap layer disposed on the p-type gallium nitride layer, and a gate electrode disposed on the cap layer. The cap layer includes _{AlxGa1 -xN} , wherein x is between 0.18 and 0.24.

In some embodiments, the barrier layer comprises _{AlyGa1 -yN} , wherein the value of y is less than 0.3.

In some embodiments, the gate stack further includes an etch stop layer disposed between the barrier layer and the p-type gallium nitride layer.

In some embodiments, the width of the gate electrode is smaller than the width of the capping layer.

In some embodiments, the gallium nitride power device further includes a drain electrode and a source electrode respectively disposed on two sides of the gate stack, wherein the distance between the drain electrode and the gate stack is greater than the distance between the source electrode and the gate stack.

In some embodiments, the gallium nitride power device further includes a drain electrode and a source electrode respectively disposed on two sides of the gate stack, wherein the drain electrode and the source electrode respectively include an n-type heavily doped metal.

In some embodiments, the gallium nitride power device further includes a reinforcement layer disposed between the barrier layer and the 2DEG channel, wherein the reinforcement layer includes aluminum nitride.

In some embodiments, the buffer layer contains carbon or iron impurities.

In some embodiments, the doping concentration of the p-type gallium nitride layer is between 10 ¹⁹ cm ^-3 and 10 ²⁰ cm ^-3 , and the activation rate of the p-type gallium nitride layer is between 1% and 3%.

In some embodiments, the thickness of the p-type gallium nitride layer is 70 nm to 100 nm, and the thickness of the cap layer is 5 nm to 15 nm.

The gallium nitride power element of the present invention uses a silicon carbide layer formed on a silicon substrate as a dielectric substrate, which can reduce the lattice mismatch problem between the gallium nitride material and the dielectric substrate in the subsequent epitaxial growth and has the advantages of low cost and low resistance. In addition, the gallium nitride power element of the present invention uses _{AlxGa1 -xN} as the material of the cap layer, where x is between 0.18 and 0.24. The material of the cap layer has a wide energy gap, which can effectively suppress hole injection, help enhance the electron injection of the channel layer, and achieve the purpose of improving the gate reliability.

The following will clearly illustrate the spirit of the present invention with drawings and detailed descriptions. After understanding the preferred embodiments of the present invention, any person having ordinary knowledge in the relevant technical field can make changes and modifications based on the techniques taught by the present invention without departing from the spirit and scope of the present invention.

Traditional GaN power devices fabricated directly on silicon substrates are prone to various problems due to large differences in thermal expansion coefficients or lattice mismatch. If GaN power devices are fabricated directly on other types of substrates, the cost will increase because these substrates are difficult to obtain.

The gallium nitride power element provided by one embodiment of the present invention can improve the operating temperature and thermal conduction by prefabricating a silicon carbide layer on a silicon substrate. More importantly, it can improve the working efficiency of the gallium nitride power element by lattice matching with the gallium nitride material layer, and can be integrated into the existing process without excessively increasing the production cost.

Referring to FIG. 1 to FIG. 10, they are schematic diagrams of a gallium nitride power device according to an embodiment of the present invention at different manufacturing stages. First, as shown in FIG. 1, a dielectric substrate 100 is manufactured, including forming a silicon carbide layer 120 on a silicon substrate 110. In some embodiments, the silicon carbide layer 120 can be formed on the silicon substrate 110 by a suitable deposition process, such as metal-organic chemical vapor deposition (MOCVD). Preferably, the silicon carbide layer 120 is a crystalline form having a cubic phase zirconite structure (hereinafter referred to as 3C-SiC). Compared with other crystalline forms of silicon carbide, 3C-SiC has the advantage of a relatively low manufacturing cost. Since the dielectric substrate 100 is the carrier of the subsequent epitaxial layer of the device, it has a greater impact on the working performance. After comprehensively considering factors such as cost, lattice matching with the epitaxial layer, thermal conductivity and the difficulty of obtaining large-size wafers, the dielectric substrate 100 obtained by forming a silicon carbide layer 120 on a silicon substrate 110 has great advantages.

Next, referring to FIG. 2 , at least one transition layer 130 is sequentially fabricated on the dielectric substrate 100. The transition layer 130 is also referred to as a nucleation layer in some embodiments. Since there is still some lattice mismatch between the dielectric substrate 100 and the subsequently epitaxially grown III-nitride layer, such as the lattice mismatch rate between silicon carbide and gallium nitride is 3.5%, a transition layer 130 of a certain thickness needs to be introduced to reduce the interface tension caused by the mismatch.

The transition layer 130 plays an important role in reducing the current collapse caused by interface mismatch, defects or trap effects, reducing static current leakage and RF conduction, and improving RF performance. Generally speaking, the material of the transition layer 130 can be AlGaN or AlN, and the thickness of the transition layer 130 is about 10 nm to 100 nm.

After the transition layer 130 is fabricated, a buffer layer 140 is then epitaxially grown on the transition layer 130. The buffer layer 140 changes the thermal expansion coefficient and lattice constant from a value close to the dielectric substrate 100 to a value close to the desired top crystalline film through an appropriate combination of layers and compositions, so as to obtain a final structure with low mechanical stress and good crystal quality. The buffer layer 140 can be a thin film with high resistance to reduce the background carrier concentration to reduce the drain current collapse caused by the trap effect of the buffer layer 140. In some embodiments, the buffer layer 140 may be an unintentionally doped semi-insulating material, such as a gallium nitride material layer containing carbon (C) or iron (Fe) impurities. The thickness of the buffer layer 140 may be 1µm-6µm.

After the buffer layer 140 is fabricated, a channel layer 150, a spike layer 160, and a barrier layer 170 are sequentially epitaxially grown on the buffer layer 140. A two-dimensional electron gas (2DEG) channel 152 is formed slightly below the interface between the barrier layer 170 and the buffer layer 140. The 2DEG channel 152 is a very thin volume region below the barrier layer 170 and parallel to the dielectric substrate 100, where electron current will flow when a voltage is applied. The channel layer 150 can be deposited on the buffer layer 140 before the barrier layer 170 is formed. The channel layer 150 can be optimized to positively influence the characteristics of the 2DEG channel 152 .

The channel layer 150 is used to separate the heterojunction between the doped barrier layer 170 and the buffer layer 140, and reduce the influence of the ion scattering of the doped barrier layer 170 on the mobility and concentration of the 2DEG channel 152 in the channel. The thicker the channel layer 150 is, the more obvious the effect of reducing scattering is, but at the same time it will also limit the electrons into the channel, reducing the electron concentration. In some embodiments, the material of the channel layer 150 is gallium nitride, and the thickness of the channel layer 150 is about 50 nm-300 nm. In some embodiments, the resistance of the buffer layer 140 is greater than the resistance of the channel layer 150.

The barrier layer 170 provides a certain barrier height for the gate Schottky contact. Considering the lattice matching between the barrier layer 170 and the channel layer 150, the material of the barrier layer 170 can be aluminum-doped gallium nitride, i.e., _{AlyGa1 -yN} , where the value of y is less than 0.3, so as to reduce the impact on epitaxial stress and avoid the generation of undesirable defects such as DX centers.

Although the electric field strength of a thinner barrier layer 170 is greater, the current collapse will be more serious and the saturated output power will be lower, while a thicker barrier layer 170 will increase parasitic effects and reduce small signal gain characteristics. Therefore, it is necessary to compromise the effect of the thickness of the barrier layer 170 on the device characteristics, and the thickness of the fault barrier layer 170 does not exceed 30nm.

The reinforcing layer 160 is disposed between the channel layer 150 and the barrier layer 170 to increase the electron concentration of the channel and improve the DC/high frequency characteristics. In some embodiments, the reinforcing layer 160 may be made of aluminum nitride, and the thickness of the reinforcing layer 160 is about 1 nm to 3 nm.

Next, as shown in FIG. 3 , an etch stop layer 180, a p-type gallium nitride material layer 190, and a cap material layer 200 are formed on the barrier layer 170. Since it is difficult to control the etching depth of the p-type gallium nitride material layer 190 in a power device using a p-type gallium nitride material, the etch stop layer 180 is further disposed between the p-type gallium nitride material layer 190 and the barrier layer 170 to enhance the etching selectivity between the p-type gallium nitride material layer 190 and the barrier layer 170. In some embodiments, the material of the etch stop layer 180 may be aluminum nitride, and the thickness of the etch stop layer 180 is about 1 nm to 2 nm.

A pn depletion region is formed between the p-type gallium nitride material layer 190 and the 2DEG channel 152 to close the channel and form a normally-off device. Since the pn depletion region is used as a device switch, the p-type gallium nitride material layer 190 preferably has a low on-resistance. In some embodiments, the doping concentration of the p-type gallium nitride material layer 190 during epitaxy is approximately between 10 ¹⁹ cm ^-3 and 10 ²⁰ cm ^-3 , the activation rate of the p-type gallium nitride material layer 190 is approximately between 1% and 3%, and the thickness of the p-type gallium nitride material layer 190 is approximately between 70 nm and 100 nm.

The cap material layer 200 is a material with a wide bandgap, which can effectively suppress hole injection and achieve the purpose of improving gate reliability. In some embodiments, the cap material layer 200 can be aluminum-doped gallium nitride, i.e., _{AlxGa1 -xN} , where the value of x is set between 0.18 and 0.24, and the thickness of the cap material layer 200 is about 5nm~15nm. As the aluminum concentration of the cap material layer 200 decreases, the threshold voltage ( _VTH ) of the device will shift to the positive direction, accompanied by a lower device current.

Next, referring to FIG. 4 , the capping material layer 200 is etched to obtain a capping layer 200 ′ and define a gate region. In some embodiments, the capping material layer 200 may be etched by dry etching. For example, the capping material layer 200 may be etched by inductively coupled plasma (ICP) etching, and the etching gas used may include Cl ₂ /BCl ₃ .

Next, referring to FIG. 5 , the p-type gallium nitride material layer 190 is continuously etched to the etch stop layer 180 using the cap layer 200 ′ as a mask to remove the p-type gallium nitride material layer 190 outside the gate region and release the 2DEG channel 152 again, while the p-type gallium nitride layer 190 ′ and the etch stop layer 180 ′ covered by the cap layer 200 ′ are retained. In some embodiments, the p-type gallium nitride material layer 190 may be etched by inductively coupled plasma etching, and the etching gas used may include Cl ₂ /BCl ₃ /SF ₆ . In some embodiments, the etch stop layer 180 outside the gate region is also completely removed.

Next, referring to FIG. 6 , an isolation region 210 is formed in the channel layer 150, the reinforcement layer 160, and the barrier layer 170 to cut off the flow of the 2DEG channel 152 between the devices and to serve as isolation between the devices. In some embodiments, the isolation region 210 can be formed by ion implantation using plasma containing passivation gas ions (such as argon ions) in the channel layer 150, the reinforcement layer 160, and the barrier layer 170.

Next, as shown in FIG. 7 , a source electrode 220 and a drain electrode 230 are formed at predetermined positions on both sides of the cap layer 200 ′, the residual p-type gallium nitride layer 190 ′, and the residual etch stop layer 180 ′, wherein the source electrode 220 and the drain electrode 230 are located between two adjacent isolation regions 210. The source electrode 220 and the drain electrode 230 can be formed by heating the material by electron beam irradiation, such as an electron beam evaporator, until the material evaporates and the material is attached to the surface of the substrate. In some embodiments, when depositing materials on the substrate surface by electron beam evaporation, a mask may be used to allow the materials to be deposited only at predetermined locations of the source electrode 220 and the drain electrode 230 .

In some embodiments, after the material is deposited at the predetermined positions of the source electrode 220 and the drain electrode 230, a rapid thermal annealing (RTA) may be performed to activate the doping elements in the semiconductor material so that the source electrode 220 and the drain electrode 230 form an ohmic contact with the underlying barrier layer 170. In some embodiments, the rapid thermal annealing process is performed at a temperature of about 875 degrees Celsius for about 30 seconds.

Next, as shown in FIG. 8 , the gate electrode 240 is deposited on the cap layer 200 ′ by electron beam evaporation. When depositing the material by electron beam evaporation, a mask can be used to allow the material to be deposited only at a predetermined position on the cap layer 200 ′. A Schottky barrier is formed between the gate electrode 240 and the cap layer 200 ′. In some embodiments, the width w1 of the gate electrode 240 is smaller than the width w2 of the cap layer 200 ′.

In some embodiments, the gate electrode 240 is used as a Schottky contact, which is usually a metal material stack of nickel/gold (Ni/Au) or platinum/gold (Pt/Au). These metal materials have a high work function and can suppress gate leakage current. In some other embodiments, the gate electrode 240 can also be a concave or T-shaped structure to reduce parasitic effects and reduce the aspect ratio of the component in the vertical direction, thereby reducing the short channel effect and improving the RF characteristics of the component. In some embodiments, the gate electrode 240, the cap layer 200', the p-type gallium nitride layer 190' and the etch stop layer 180' can be collectively referred to as a gate stack.

The source electrode 220 and the drain electrode 230 are used as ohmic contacts, which are usually stacked with multiple layers of metal materials such as titanium/aluminum (Ti/Al) or titanium/aluminum/titanium/gold (Ti/Al/Ti/Au). In addition, in some embodiments, the source electrode 220 and the drain electrode 230 can be further n-type heavily doped to reduce the resistance of the ohmic contact. In some embodiments, in order to improve the breakdown characteristics, the distance d1 between the gate electrode 240 and the drain electrode 230 can be farther than the distance d2 between the gate electrode 240 and the source electrode 220.

Referring to FIG. 9 , a passivation treatment is performed on the structure completed in FIG. 8 to form a passivation layer 250 thereon. The passivation layer 250 can be formed by depositing an insulating material on the structure shown in FIG. 8 . For example, the passivation layer 250 can be formed by plasma enhanced chemical vapor deposition (PECVD), and the material of the passivation layer 250 can be silicon dioxide and/or silicon nitride.

The passivation layer 250 is provided to protect the device from damage by water and oxygen in the environment, and the passivation layer 250 can reduce the drain current collapse and maintain the polarization characteristics of the 2DEG channel 152. The passivation layer 250 can also reduce the gate leakage current, enhance the source/drain ohmic contact and breakdown voltage. After the passivation treatment, the electron concentration of the 2DEG channel 152 is increased by about 20%.

Finally, as shown in FIG. 10 , an opening 252 is formed on the passivation layer 250 to partially expose the gate electrode 240, the drain electrode 230, and the source electrode 220. The exposed portions of the gate electrode 240, the drain electrode 230, and the source electrode 220 can be used as a probe contact area when measuring device characteristics. In some embodiments, the step of forming the opening 252 on the passivation layer 250 can be formed by reactive-ion etching (RIE), and the reactive gas used includes CF ₄ /O ₂ /Ar.

At this point, the gallium nitride power element 300 is obtained, and the passivation layer 250 covers the side walls of the cap layer 200', the residual p-type gallium nitride layer 190' and the residual etch stop layer 180'. The passivation layer 250 covers the side walls and a portion of the upper surface of the gate electrode 240, the drain electrode 230 and the source electrode 220. The passivation layer 250 further covers the upper surface of the isolation region 210 and the upper surface of the barrier layer 170 that is not blocked by the gate electrode 240, the drain electrode 230 and the source electrode 220.

The gallium nitride power element 300 of the present invention uses a silicon carbide layer 120 formed on a silicon substrate 110 as a dielectric substrate 100, wherein the silicon carbide layer 120 is a single crystal 3C-SiC structure without a deflection angle, for example, the angle between the normal direction of the silicon carbide layer 120 and the [0001] crystal direction is less than plus or minus 0.2 degrees. Compared with the use of a silicon substrate alone, the problem of lattice mismatch between the gallium nitride material grown in subsequent epitaxial growth and the dielectric substrate 100 can be reduced; compared with the use of a silicon carbide substrate alone, it has the advantages of lower cost and lower resistance.

In addition, the gallium nitride power device 300 of the present invention uses _{AlxGa1 -xN} as the material of the cap layer 200', where x is between 0.18 and 0.24. The material of the cap layer 200' has a wide bandgap, which can effectively suppress hole injection, help enhance electron injection of the channel layer, and achieve the purpose of improving gate reliability.

Please refer to FIG. 10 and FIG. 11 to FIG. 13 , where FIG. 11 to FIG. 13 respectively show energy band diagrams of different embodiments of the gate region in the gallium nitride power device of the present invention. When the gate voltage exceeds the threshold voltage (V _TH ), the metal allows holes to flow laterally between the cap layer 200 ′ and the channel layer 150 . When the V _GSQ applied to the gallium nitride power device is between 1V and 5V, as shown in FIG. 11 , holes are accumulated at the AlGaN/p-GaN interface between the cap layer 200' and the p-type gallium nitride layer 190', or are trapped at the p-GaN/AlGaN interface between the p-type gallium nitride layer 190' and the barrier layer 170. This phenomenon is beneficial to temporarily increase the density of the 2DEG channel 152 and cause a negative shift in the threshold voltage.

When the V _GSQ applied to the GaN power device is between 5V and 15V, the threshold voltage will shift positively as shown in FIG. 12 . This phenomenon may be caused by the injected electrons being trapped by the p-GaN/AlGaN electron trap interface between the p-type GaN layer 190 ′ and the barrier layer 170 .

When the V _GSQ applied to the gallium nitride power device is greater than 15V, as shown in FIG. 13 , hole injection is turned on, and holes are injected into the p-GaN/AlGaN interface between the p-type gallium nitride layer 190 ′ and the barrier layer 170 and recombine with the trapped electrons, causing the threshold voltage shift to reverse again.

The gallium nitride power element of the present invention uses a silicon carbide layer formed on a silicon substrate as a dielectric substrate, which can reduce the lattice mismatch problem between the gallium nitride material and the dielectric substrate in the subsequent epitaxial growth and has the advantages of low cost and low resistance. In addition, the gallium nitride power element of the present invention uses _{AlxGa1 -xN} as the material of the cap layer, where x is between 0.18 and 0.24. The material of the cap layer has a wide energy gap, which can effectively suppress hole injection, help enhance the electron injection of the channel layer, and achieve the purpose of improving the gate reliability.

Although the present invention has been disclosed as above by way of embodiments, it is not intended to limit the present invention. Anyone skilled in the art may make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined in the attached patent application.

100: dielectric substrate 110: silicon substrate 120: silicon carbide layer 130: transition layer 140: buffer layer 150: channel layer 152: 2DEG channel 160: reinforcement layer 170: barrier layer 180: etch stop layer 180’: etch stop layer 190: p-type gallium nitride material layer 190’: p-type gallium nitride layer 200: cap material layer 200’: cap layer 210: isolation region 220: source electrode 230: drain electrode 240: Gate electrode 250: Passivation layer 252: Opening 300: GaN power element w1, w2: Width d1, d2: Spacing

In order to make the purpose, features, advantages and embodiments of the present invention more clearly understandable, the detailed description of the attached figures is as follows: Figures 1 to 10 are schematic diagrams of a gallium nitride power device in one embodiment of the present invention at different manufacturing stages. Figures 11 to 13 are schematic diagrams of energy bands of different embodiments of the gate region in the gallium nitride power device of the present invention.

100: Dielectric substrate

110: Silicon substrate

120: Silicon carbide layer

130: Transition layer

140: Buffer layer

150: Channel layer

152:2DEG

160: Reinforcement layer

170: Barrier layer

180’: Etch stop layer

190’: p-type gallium nitride layer

200’: Cap layer

210: Isolation area

220: Source electrode

230: Drain electrode

240: Gate electrode

250: Passivation layer

252: Open mouth

300: Gallium nitride power element

Claims (9)

A gallium nitride power device comprises: a dielectric substrate, comprising: a silicon substrate; and a cubic silicon carbide (3C-SiC) layer formed on the silicon substrate; a transition layer disposed on the dielectric substrate; a buffer layer disposed on the transition layer, the buffer layer comprising a doped gallium nitride material; a channel layer disposed on the buffer layer, the channel layer comprising a gallium nitride material; a barrier layer disposed A two-dimensional electron (2DEG) channel is formed on the channel layer between the channel layer and the barrier layer; a gate stack is disposed on the barrier layer, the gate stack includes: a p-type gallium nitride layer, disposed on the barrier layer; a cap layer, disposed on the p-type gallium nitride layer, wherein the cap layer includes Al _{xGa1 -xN} , wherein x is between 0.18 and 0.24; and a gate electrode disposed on the cap layer; and a drain electrode and a source electrode disposed on both sides of the gate stack, respectively, wherein the drain electrode and the source electrode respectively comprise n-type heavily doped metal. A gallium nitride power device as described in claim 1, wherein the barrier layer comprises _{AlyGa1 -yN} , wherein the value of y is less than 0.3. A gallium nitride power device as described in claim 1, wherein the gate stack further comprises an etch stop layer disposed between the barrier layer and the p-type gallium nitride layer. A gallium nitride power device as described in claim 1, wherein the width of the gate electrode is smaller than the width of the cap layer. A gallium nitride power device as described in claim 1, wherein the distance between the drain electrode and the gate stack is greater than the distance between the source electrode and the gate stack. The gallium nitride power device as described in claim 1 further comprises a reinforcement layer disposed between the barrier layer and the 2DEG channel, wherein the reinforcement layer comprises aluminum nitride. A gallium nitride power device as described in claim 1, wherein the buffer layer contains carbon or iron impurities. The gallium nitride power device as described in claim 1, wherein the doping concentration of the p-type gallium nitride layer is between 10 ¹⁹ cm ^-3 and 10 ²⁰ cm ^-3 , and the activation rate of the p-type gallium nitride layer is between 1% and 3%. The gallium nitride power device as described in claim 1, wherein the thickness of the p-type gallium nitride layer is 70nm~100nm, and the thickness of the cap layer is 5nm~15nm.

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