TWI848381B - Memory system - Google Patents

Abstract

The memory device of the present invention includes: a memory cell array that stores data; a control circuit that controls the memory cell array in response to instructions; and a receiver that becomes activated based on the first signal, the second signal, or the result of the operation of the address and the instruction, and can receive instructions or data.

Description

Memory system

An embodiment relates to a memory device.

As a memory device, NAND (Not-AND) type flash memory is known.

The memory device of the embodiment includes: a memory cell array that stores data; a control circuit that controls the memory cell array in response to a command; and a receiver that becomes activated based on the first signal, the second signal, or the result of the operation of the address and the command, and can receive the command or data.

01h: Write command

05h: Read out instructions

1: Memory system

10: NAND flash memory

11a: PMOS transistor

11b: NMOS transistor

11c~11f: PMOS transistor

11g~11i: NMOS transistor

20:Memory controller

30: Host machine

80h: Write instruction

100:LUN

101: Input and output interface

101a: AND operation circuit

101b: OR operation circuit

101c: NAND operation circuit

101d: Inverter

101g: NAND operation circuit

101g1:NAND operation circuit

101h: NAND operation circuit

101i: NAND operation circuit

101j:OR operation circuit

101k: NAND operation circuit

101l: NAND operation circuit

101m: NAND operation circuit

101n: Inverter

101o: AND operation circuit

101p:OR operation circuit

101q: Switching circuit

101r: Switching circuit

101s: OR operation circuit

101t:Switching circuit

101u: Switching circuit

101v: Receiver No. 1

101w: Receiver No. 2

102: Control signal input interface

103: Control circuit

104: Instruction register

104a: Memory

105: Address register

105a: Memory

106: Status register

110: Memory cell array

111: Sense amplifier

112: Data register

113: Line decoder

114: Line buffer

115: Column address decoder

116: Column address buffer decoder

120: Receiver

130: Transmitter

210: Host interface (Host I/F)

220: Built-in memory (RAM)

230: Processor (CPU)

240: Buffer memory

250:NAND interface (NAND I/F)

ADD: address

ALE: Address latch enable signal

BCE: Chip Enable Signal

BDQS: Data selection signal

BRE: Read Enable Signal

BWE: Write enable signal

BWP: Write protection signal

C1: row address

C2: row address

CLE: Command latch enable signal

CMD: Command

D0~Dn: write data

DQ: input and output signal

DQ0~DQ7: input and output signals

DQS: Data selection signal

E0h: Instructions

EFh: instruction

ENBn:Signal

EN:Signal

FFh: Initialization instruction

GP0: memory group

GP1: Memory Group

IREFN: reference voltage

MS:Signal

N1~N7: Node

NP:Signal

R1~R3: column address

RE: Read enable signal

RY/BBY: Ready. Busy signal

T0~T29: Time

t _CALS : Period

VDD: power supply voltage

VREF: reference voltage

W-B0~W-B3: Information

XXh: Instructions

YYh: Instructions

^~ ALE: Invert signal

^~ BCE: reverse signal

^~ BWE: reverse signal

^~ BWP: reverse signal

^~ CLE: reverse signal

FIG1 is a block diagram of the memory system of the first embodiment.

FIG2 is a block diagram of the LUN of the memory system of the first implementation form.

Figure 3 is a circuit diagram of the input and output interface of the memory system of the first embodiment.

FIG4 is a schematic diagram of the operation of the memory system of the first embodiment.

FIG5 is a timing diagram showing an example of a write operation of the memory system of the first embodiment.

FIG6 is a timing diagram showing an example of a read operation of the memory system of the first embodiment.

FIG7 is a circuit diagram of the input-output interface of the memory system of the second embodiment.

FIG8 is a timing diagram showing an example of a write operation of the memory system of the second embodiment.

FIG9 is a timing diagram showing an example of a write operation of the memory system of the second embodiment.

FIG10 is a timing diagram showing an example of a write operation of the memory system of the second embodiment.

FIG11 is a timing diagram showing an example of a read operation of the memory system of the second embodiment.

FIG12 is a timing diagram showing an example of a read operation of the memory system of the second embodiment.

FIG13 is a timing diagram showing an example of a read operation of the memory system of the second embodiment.

FIG14 is a timing diagram showing an example of a read operation of the memory system of the second embodiment.

FIG15 is a timing diagram showing an example of a write operation of a memory system in Variation 1 of the second embodiment.

FIG16 is a timing diagram showing an example of a read operation of the memory system in the first variation of the second embodiment.

FIG17 is a circuit diagram of the input/output interface of the memory system of variation 2 of the second embodiment.

FIG18 is a circuit diagram of the input-output interface of the memory system of the third embodiment.

FIG19 is a timing diagram showing an example of a write operation of the memory system of the third embodiment.

FIG20 is a timing diagram showing an example of a write operation of the memory system of the third embodiment.

FIG21 is a timing diagram showing an example of a write operation of the memory system of the third embodiment.

FIG22 is a timing diagram showing an example of a read operation of the memory system of the third embodiment.

FIG23 is a timing diagram showing an example of a read operation of the memory system of the third embodiment.

FIG24 is a timing diagram showing an example of a read operation of the memory system of the third embodiment.

FIG25 is a timing diagram showing an example of a read operation of the memory system of the third embodiment.

FIG26 is a timing diagram showing an example of a write operation of the memory system of the third embodiment.

FIG27 is a timing diagram showing an example of a read operation of the memory system of the third embodiment.

FIG28 is a circuit diagram of the input/output interface of the memory system of a variation of the third embodiment.

FIG29 is a circuit diagram of the input/output interface of the memory system of the fourth embodiment.

FIG30 is a diagram showing the mode selection operation of the memory system of the fourth embodiment.

Figure 31 is a circuit diagram of the input/output interface of the memory system in variation 1 of the fourth embodiment.

Figure 32 is a circuit diagram of the input-output interface of the memory system of variation 2 of the fourth embodiment.

Figure 33 is a circuit diagram of the input-output interface of the memory system of variation 3 of the fourth embodiment.

FIG34 is a circuit diagram of the input-output interface of the memory system of the fifth embodiment.

FIG35 is a timing diagram showing an example of a write operation of the memory system of the fifth embodiment.

FIG36 is a timing diagram showing an example of a write operation of the memory system of the fifth embodiment.

FIG37 is a timing diagram showing an example of a write operation of the memory system of the fifth embodiment.

FIG38 is a timing diagram showing an example of a read operation of the memory system of the fifth embodiment.

FIG39 is a timing diagram showing an example of a read operation of the memory system of the fifth embodiment.

FIG40 is a timing diagram showing an example of a read operation of the memory system of the fifth embodiment.

FIG41 is a timing diagram showing an example of a read operation of the memory system of the fifth embodiment.

FIG42 is a timing diagram showing an example of a write operation of a memory system in a variation of the fifth embodiment.

FIG43 is a timing diagram showing an example of a write operation of a memory system in a variation of the fifth embodiment.

FIG44 is a timing diagram showing an example of a write operation of a memory system in a variation of the fifth embodiment.

FIG45 is a timing diagram showing an example of a read operation of a memory system in a variation of the fifth embodiment.

FIG. 46 is a timing diagram showing an example of a read operation of a memory system in a variation of the fifth embodiment.

FIG47 is a timing diagram showing an example of a read operation of a memory system in a variation of the fifth embodiment.

FIG48 is a timing diagram showing an example of a read operation of a memory system in a variation of the fifth embodiment.

FIG49 is a circuit diagram of the input-output interface of the memory system of the sixth embodiment.

FIG. 50 is a circuit diagram showing a receiver of a memory system of the seventh embodiment.

FIG. 51 is a circuit diagram showing the first receiver of the memory system of the seventh embodiment.

FIG. 52 is a circuit diagram showing the second receiver of the memory system of the seventh embodiment.

Figure 53 is a diagram showing the operating conditions of the memory system in the first to fifth implementation forms.

The following is a description of the implementation form with reference to the drawings. In the above description, common reference symbols are used throughout all the drawings to mark common parts.

<1>The first implementation form

A semiconductor memory device of the first embodiment is described. In the following, a NAND flash memory is taken as an example of a semiconductor memory device for description.

<1-1> Composition

<1-1-1> Overall structure of the memory system

First, the general overall structure of the memory system including the semiconductor memory device of the present embodiment is described using FIG1. FIG1 is a block diagram of the memory system of the present embodiment.

As shown in FIG1 , the memory system 1 has a NAND flash memory 10 and a memory controller 20. The NAND flash memory 10 and the memory controller 20 can be combined to form a semiconductor device, for example, a memory card such as an SD card (Secure Digital Card) or an SSD (solid state drive).

The NAND flash memory 10 has a plurality of memory cell transistors and stores data non-volatilely. The memory controller 20 is connected to the NAND flash memory 10 via a NAND bus and is connected to a host machine 30 via a host bus. Furthermore, the memory controller 20 controls the NAND flash memory 10 and accesses the NAND flash memory 10 in response to commands received from the host machine 30. The host machine 30 is, for example, a digital camera or a personal computer, and the host bus is, for example, a bus that complies with the SDTM (Study Data Tabulation Model) interface.

The NAND bus sends and receives signals in accordance with the NAND interface. Specific examples of the above signals are the chip enable signal BCE, the command latch enable signal CLE, the address latch enable signal ALE, the write enable signal BWE, the read enable signal RE, BRE, the write protection signal BWP, the data selection signal DQS, BDQS, the input and output signal DQ, and the ready and busy signal RY/BBY. When there is no need to distinguish the above signals, they can also be recorded as signals.

The chip enable signal BCE is a signal for selecting the LUN (Logical unit number) 100 included in the NAND type flash memory 10. The chip enable signal BCE is asserted (“Low” level) when the LUN 100 is selected.

The command latch enable signal CLE is a signal used to notify the NAND flash memory 10 that the input/output signal DQ of the NAND flash memory 10 is a command. The command latch enable signal CLE is asserted (“High” level (Low<High)) when the command is captured to the NAND flash memory 10.

The address latch enable signal ALE is a signal used to notify the NAND flash memory 10 that the input/output signal DQ of the NAND flash memory 10 is an address. The address latch enable signal ALE is asserted (“high” level) when the address is captured to the NAND flash memory 10.

The write enable signal BWE is a signal for capturing the input-output signal DQ to the NAND type flash memory 10. The write enable signal BWE is asserted (“low” level) when the input-output signal DQ is captured to the NAND type flash memory 10.

The read enable signal RE is a signal used to read the input/output signal DQ from the NAND flash memory 10. The read enable signal BRE is a complementary signal of RE. The read enable signals RE and BRE are established when the input/output signal DQ is read from the NAND flash memory 10 (RE = "high" level, BRE = "low" level).

The write protection signal BWP is used to protect data from accidental erasure or writing when the input signal of the NAND flash memory 10 is uncertain, such as when the power is turned on or off. The write protection signal BWP is asserted ("low" level) when protecting data.

The input/output signal DQ is, for example, an 8-bit signal. Moreover, the input/output signal DQ is a command, address, write data, and read data sent and received between the NAND flash memory 10 and the memory controller 20.

The data selection signal DQS is a signal used to transmit and receive the input/output signal DQ (data) between the memory controller 20 and the NAND flash memory 10. The data selection signal BDQS is a complementary signal of DQS. The NAND flash memory 10 receives the input/output signal DQ (data) in accordance with the timing of the data selection signals DQS and BDQS supplied from the memory controller 20. The memory controller 20 receives the input/output signal DQ (data) in accordance with the timing of the data selection signals DQS and BDQS supplied from the NAND flash memory 10. The data selection signals DQS and BDQS are established when transmitting and receiving the input/output signal DQ (DQS = "low" level, BDQS = "high" level).

Ready. Busy signal RY/BBY is a signal indicating whether LUN100 is in a ready state (a state in which commands from the memory controller 20 can be received) or in a busy state (a state in which commands from the memory controller 20 cannot be received). Ready. Busy signal RY/BBY is set to a "low" level in the case of a busy state.

<1-1-2> Composition of memory controller

Using Figure 1, the details of the structure of the memory controller 20 are described. As shown in Figure 1, the memory controller 20 has a host interface (Host I/F) 210, a built-in memory (RAM: Random access memory) 220, a processor (CPU: Central processing unit) 230, a buffer memory 240, and a NAND interface (NAND I/F) 250.

The host interface 210 is connected to the host machine 30 via the host bus, and transmits the commands and data received from the host machine 30 to the processor 230 and the buffer memory 240 respectively. The host interface 210 responds to the commands of the processor 230 and transmits the data in the buffer memory 240 to the host machine 30.

The processor 230 controls the overall operation of the memory controller 20. For example, when the processor 230 receives a write command from the host machine 30, it responds by issuing a write command to the NAND interface 250. The same is true for reading and erasing. The processor 230 performs various processes such as wear leveling for managing the NAND flash memory 10.

The NAND interface 250 is connected to the NAND flash memory 10 via the NAND bus and is responsible for communicating with the NAND flash memory 10. Furthermore, based on the command received from the processor 230, the chip enable signal BCE, the command latch enable signal CLE, the address latch enable signal ALE, the write enable signal BWE, the read enable signals RE, BRE, the write protection signal BWP, and the data selection signals DQS, BDQS are output to the NAND flash memory 10. When writing, the write command issued by the processor 230 and the write data in the buffer memory 240 are transmitted to the NAND flash memory 10 as the input-output signal DQ. Furthermore, when reading, the read command issued by the processor 230 is transmitted to the NAND flash memory 10 as the input-output signal DQ, and the data read from the NAND flash memory 10 is received as the input-output signal DQ and transmitted to the buffer memory 240.

The buffer memory 240 temporarily holds the written data or read data.

The built-in memory 220 is a semiconductor memory such as DRAM (Dynamic random access memory) and is used as a working area of the processor 230. In addition, the built-in memory 220 maintains firmware for managing the NAND flash memory 10, or various management tables, etc.

<1-1-3>NAND flash memory

<1-1-3-1> Composition of NAND flash memory

Next, the structure of the NAND flash memory 10 is described.

As shown in FIG. 1 , the NAND flash memory 10 has a plurality of memory groups (in the example of FIG. 1 , GP0 and GP1 are used as an example).

Each memory group GP has a plurality of LUNs 100 (four in the example of FIG. 1). When a plurality of LUNs 100 are distinguished, they are indicated by LUNs (m: m is an arbitrary integer). Specifically, memory group GP0 has LUNs (0) to (3), and memory group GP1 has LUNs (4) to (7). LUNs 100 are the smallest units that can be controlled independently. LUNs 100 only need to have at least one memory chip, or may have more than two memory chips. In this embodiment, the case where LUNs 100 have one memory chip is described.

In this embodiment, an independent chip enable signal BCE is input to each memory group GP. In other words, the same chip enable signal BCE is input to LUN100 in the same memory group GP.

In a certain memory group GP, the number of active LUN100 can be one or more.

<1-1-3-2> Composition of LUN100

Next, the structure of LUN100 is explained using Figure 2.

The memory controller 20 and LUN 100 are connected via an input/output interface 101 and a control signal input interface 102.

The input/output interface 101 has a receiver 120 and a transmitter 130. The receiver 120 inputs input/output signals (DQ0~DQ7) via the data input/output line (the wiring for receiving and transmitting input/output signals DQ in the NAND bus). The transmitter 130 outputs input/output signals (DQ0~DQ7) via the data input/output line.

When the input/output interface 101 outputs the input/output signal (DQ0~DQ7) from the data input/output line, it outputs the data selection signals DQS and BDQS to the memory controller 20.

The control signal input interface 102 receives the chip enable signal BCE, the command latch enable signal CLE, the address latch enable signal ALE, the write enable signal BWE, the read enable signals RE, BRE, the write protection signal BWP, and the data selection signals DQS, BDQS from the memory controller 20.

Although not shown in Figure 2, LUN100 is also provided with Vcc/Vss/Vccq/Vssq terminals for power supply.

The control circuit 103 outputs the data read from the memory cell array 110 to the memory controller 20 via the input/output interface 101. The control circuit 103 receives various instructions, addresses, and write data such as write, read, erase, and status read via the control signal input interface 102.

The control circuit 103 controls the command register 104, the address register 105, the status register 106, the sense amplifier 111, the data register 112, the column decoder 113, and the row address decoder 115.

The control circuit 103 supplies the required voltage to the memory cell array 110, the sense amplifier 111, and the row decoder 115 when programming, verifying, reading, and erasing data.

The instruction register 104 stores the instructions input from the control circuit 103.

The address register 105 stores, for example, an address supplied from the memory controller 20. Furthermore, the address register 105 converts the stored address into an internal physical address (row address and column address). Then, the address register 105 supplies the row address to the column buffer 114 and supplies the column address to the row address buffer decoder 116.

The status register 106 is used to notify the outside of various states within the LUN 100. The status register 106 has a ready/busy register (not shown) that holds data indicating whether the LUN 100 is in a ready/busy state, and a write status register (not shown) that holds data indicating whether the write is passed/failed.

The memory cell array 110 includes a plurality of bit lines BL, a plurality of word lines WL, and a source line SL. The memory cell array 110 is composed of a plurality of blocks BLK in which electrically rewritable memory cell transistors (also referred to as memory cells) MC are arranged in a matrix. The memory cell transistor MC has, for example, a multilayer gate including a control gate electrode and a charge storage layer (e.g., a floating gate electrode), and stores binary or multi-value data according to a change in the threshold of the transistor determined by the amount of charge injected into the floating gate electrode. Furthermore, the memory cell transistor MC may also have a MONOS (Metal-Oxide-Nitride-Oxide-Silicon) structure that traps electrons in a nitride film.

Furthermore, the configuration of the memory cell array 110 may be another configuration. That is, the configuration of the memory cell array 110 is described, for example, in U.S. Patent Application No. 12/407,403 filed on March 19, 2009, entitled "Three-dimensional layered non-volatile semiconductor memory". In addition, it is described in U.S. Patent Application No. 12/406,524 filed on March 18, 2009, entitled "Three-dimensional layered non-volatile semiconductor memory", U.S. Patent Application No. 12/679,991 filed on March 25, 2010, entitled "Non-volatile semiconductor memory device and method of manufacturing the same", and U.S. Patent Application No. 12/532,030 filed on March 23, 2009, entitled "Semiconductor memory and method of manufacturing the same". The above patent applications are incorporated by reference in their entirety into the description of this application.

During the data reading operation, the sense amplifier 111 senses the data read from the memory cell transistor MC to the bit line.

The data register 112 is composed of SRAM (Static Random Access Memory). The data register 112 stores data supplied from the memory controller 20 or verification results detected by the sense amplifier 111.

The row decoder 113 decodes the row address signal stored in the row buffer 114, and outputs a selection signal for selecting any one of the bit lines BL to the sense amplifier 111.

The row buffer 114 temporarily stores the row address signal input from the address register 105.

The column address decoder 115 decodes the column address signal inputted through the column address buffer decoder 116. In addition, the column address decoder 115 selects the word line WL driving the memory cell array 110 and selects the gate lines SGD and SGS.

The column address buffer decoder 116 temporarily stores the column address signal input from the address register 105.

<1-1-3-3> Input and output interface structure

Next, the structure of the input/output interface 101 is specifically described using FIG3.

As shown in FIG3 , the input/output interface 101 inputs and outputs the input/output signal DQ based on the instruction latch enable signal CLE, the address latch enable signal ALE, and the signal from the instruction register 104 or the address register 105.

Specifically, the command register 104 outputs the command CMD stored in the memory unit 104a to the AND operation circuit 101a of the input-output interface 101 based on the write enable signal BWE. When the command register 104 outputs the command CMD, it maintains a "high" level state before inputting the next command. The address register 105 outputs the address ADD stored in the memory unit 105a to the AND operation circuit 101a of the input-output interface 101 based on the write enable signal BWE. When the address register 105 selects its own LUN 100, it maintains a "high" level state.

The AND operation circuit 101a outputs the operation result to the OR operation circuit 101b based on the instruction CMD and the address ADD. The AND operation circuit 101a outputs a "high" level signal only when the instruction CMD and the address ADD are both "high" levels.

The OR operation circuit 101b generates the signal EN based on the operation result of the AND operation circuit 101a, the instruction latch enable signal CLE, or the address latch enable signal ALE. The OR operation circuit 101b outputs the signal EN of the "low" level only when the operation result of the AND operation circuit 101a, the instruction latch enable signal CLE, and the address latch enable signal ALE are all at the "low" level. In other words, the OR operation circuit 101b outputs the signal EN of the "high" level when at least one of the operation result of the AND operation circuit 101a, the instruction latch enable signal CLE, and the address latch enable signal ALE is at the "high" level. In the following, sometimes, the setting of the signal EN from the "low" level to the "high" level is described as "rising", and the setting of the signal EN from the "high" level to the "low" level is described as "falling".

The receiver 120 receives the input/output signal DQ inside the LUN 100 based on the signal EN and the input/output signal DQ. Specifically, the NAND operation circuit 101c generates a signal based on the signal EN supplied from the OR operation circuit 101b and the input/output signal DQ supplied from the memory controller 20. The NAND operation circuit 101c generates a "low" level signal only when the signal EN and the input/output signal DQ are both "high". In addition, the inverter 101d inverts and outputs the operation result of the NAND operation circuit 101c. That is, the receiver 120 receives the input/output signal DQ inside the LUN 100 only when the signal EN and the input/output signal DQ are both "high".

In the following, the state of inputting a "high" level signal EN to the receiver 120 is sometimes described as "startup state", and the state of inputting a "low" level signal EN is sometimes described as "standby state". When the receiver 120 is in the startup state, it is in a state capable of receiving input/output data DQ. Furthermore, when the receiver 120 is in the standby state, it is in a state unable to receive input/output data DQ.

<1-2>Action

<1-2-1> Overview of the memory system's operation

Using Figure 4, the operation of the memory system of this embodiment is briefly described.

FIG4 focuses on the operation of memory group GP0 and explains the overview of the operation when access (write operation, read operation, etc.) is changed from LUN(0) to LUN(1). As shown in FIG4, during access to LUN(0), the signal EN in LUN(0) becomes "high" and the signal EN in LUN(1) to LUN(3) becomes "low". That is, during access to LUN(0), the receiver 120 of LUN(0) is set to the start state and the receiver 120 of LUN(1) to LUN(3) is set to the standby state.

Furthermore, at time T0, the memory system 1 performs a LUN switching operation. At this time, at least the signal EN in all LUNs (LUN(0)~LUN(3)) in the memory group GP0 becomes a "high" level. That is, during the LUN switching operation, at least the receiver 120 in all LUNs (LUN(0)~LUN(3)) in the memory group GP0 is set to the start state.

At time T1, if the address of LUN(1) is determined as the selected LUN address, access to LUN(1) begins. During access to LUN(1), the signal EN in LUN(1) becomes "high", and the signal EN in LUN(0), LUN(2), and LUN(3) becomes "low". That is, during access to LUN(1), the receiver 120 of LUN(1) is set to the start state, and the receivers 120 of LUN(0), LUN(2), and LUN(3) are set to the standby state.

<1-2-2>Write action example 1

Using Figure 5, the write operation example 1 of the memory system 1 of this embodiment is described. Here, the instruction sequence of the memory group GP0 is described.

At time T2, the memory controller 20 asserts ("high" level) the command latch enable signal CLE. At time T2, the chip enable signal BCE asserts ("low" level). If the command latch enable signal CLE is asserted, the signal EN becomes "high" as shown in FIG3.

LUN 100 must wait for a period t _CALS as a period required for the setup of the command input from the assertion of the command latch enable signal CLE.

At time T3 after a period _tCALS has passed since time T2, the memory controller 20 issues commands "01h" and "80h".

The instruction "01h" is issued when the memory cell transistor MC can hold 3 bits of data. More specifically, the instruction "01h" is an instruction for specifying the first page. Although the instruction "01h" is recorded here as an example, it is not limited to this. If the memory controller 20 specifies other pages, other instructions can also be input. The instruction "80h" is used to specify the write action.

The memory controller 20 asserts (at a "low" level) the write enable signal BWE whenever it issues signals such as commands, addresses, and data. Furthermore, whenever the write enable signal BWE is triggered, the signal is captured to LUN100.

Next, the memory controller 20 issues addresses (C1, C2: row addresses, R1~R3: column addresses) for example across 5 cycles, and asserts (“high” level) the address latch enable signal ALE.

When issuing the address, the command latch enable signal CLE is negated ("low" level), but the address latch enable signal ALE is asserted. If the address latch enable signal ALE is asserted, the signal EN becomes "high" level as shown in Figure 3. That is, when receiving the address, LUN100 maintains the signal EN at a "high" level.

However, by including the selected LUN address in the column address R3, for example, and supplying the column address R3 to LUN100, the selection of LUN100 is confirmed. If the selection of LUN100 is confirmed, the address latch circuit 105 outputs a "high" level signal in the selected LUN100 as shown in FIG. 3. As a result, the signal EN in the selected LUN100 is maintained at a "high" level. On the other hand, in the non-selected LUN100, the address latch circuit 105 outputs a "low" level signal. As a result, the signal EN in the selected LUN100 becomes a "low" level. In other words, the receiver 120 of the selected LUN100 is maintained in an activated state, and the receiver 120 of the non-selected LUN100 becomes a standby state.

Next, the memory controller 20 outputs write data (D0~Dn) across multiple cycles. During the above period, the signals ALE and CLE are negated ("L" level). The write data received by LUN100 is maintained in the page buffer in the sense amplifier 111.

Although not shown in FIG. 5 , the memory controller 20 issues a write command "10H" and asserts the command latch enable signal CLE. If the command "10h" is received, the control circuit 103 starts the write operation and LUN 100 becomes busy (RY/BBY = "low" level).

<1-2-3>Reading action example 1

Using Figure 6, the read operation example 1 of the memory system 1 of this embodiment is described. Here, the instruction sequence of the memory group GP0 is described.

At time T5, the memory controller 20 asserts the command latch enable signal CLE. At time T5, the chip enable signal BCE is asserted. If the command latch enable signal CLE is asserted, the signal EN becomes a "high" level.

At time T6 after a period _tCALS has passed since time T5, the memory controller 20 issues a read command "05h".

Next, the memory controller 20 issues addresses (C1, C2: row addresses, R1~R3: column addresses) for example across 5 cycles, and asserts (“high” level) the address latch enable signal ALE.

The memory controller 20 issues the command "E0h". If LUN100 receives the command "E0h", it starts the read operation.

The instruction register 104 recognizes that the action requested from the memory controller 20 is a read action. Then, the instruction register 104 supplies a "low" level signal to the AND operation circuit 101a (refer to FIG. 3). Thereby, the signal EN becomes a "low" level.

That is, the receiver 120 becomes a standby state.

<1-3>Effects

According to the above implementation form, the address ADD, command CMD, command latch enable signal CLE, address latch enable signal ALE, etc. are used to properly control the electrical connection between LUN100 and the data input and output lines.

For example, during a write operation, if the non-selected LUN 100 receives the write data, useless current flows in the LUN 100. However, by adopting the above-mentioned implementation form, the operation current of the non-selected LUN 100 can be suppressed.

Furthermore, during the read operation, LUN100 does not need to receive data. By adopting the above-mentioned implementation form, the operation current of LUN100 can be suppressed.

<2> Second implementation form

The second embodiment is described. In the second embodiment, another structure of the input/output interface is described. Furthermore, the basic structure and basic operation of the memory device of the second embodiment are the same as those of the memory device of the first embodiment described above. Therefore, the description of the matters described in the first embodiment described above and the matters that can be inferred from the first embodiment described above are omitted.

<2-1> Input and output interface structure

Next, using FIG. 7, the structure of the input/output interface 101 of the memory system of the second embodiment is specifically described.

As shown in FIG7 , the input/output interface 101 inputs and outputs the input/output signal DQ based on the instruction latch enable signal CLE, the address latch enable signal ALE, and the signal from the instruction register 104 or the address register 105.

Specifically, the NAND operation circuit 101g outputs the operation result to the NAND operation circuit 101h based on the instruction latch enable signal CLE and the address latch enable signal ALE. The NAND operation circuit 101g generates a "low" level signal only when the instruction latch enable signal CLE and the address latch enable signal ALE are both "high" levels.

NAND operation circuit 101h and NAND operation circuit 101i form an RS flip-flop circuit. Specifically, NAND operation circuit 101h outputs the operation result based on the operation results of NAND operation circuit 101g and NAND operation circuit 101i. NAND operation circuit 101i outputs the operation result based on the operation result of NAND operation circuit 101h and the signal from instruction register 104 (such as instruction CMD).

The operation of this RS flip-flop circuit is briefly explained. When the signal from the NAND operation circuit 101g is at a "high" level and the signal from the instruction register 104 is at a "low" level, the NAND operation circuit 101h outputs a "low" level signal. Furthermore, when the signal from the NAND operation circuit 101g is at a "low" level and the signal from the instruction register 104 is at a "high" level, the NAND operation circuit 101h outputs a "high" level signal. In addition, when the output signal of the NAND operation circuit 101h is determined, even if the signal from the NAND operation circuit 101g or the signal from the instruction register 104 changes, the output signal of the NAND operation circuit 101h is maintained.

The OR operation circuit 101j generates the signal EN based on the operation result of the NAND operation circuit 101h and the signal from the address register 105. The OR operation circuit 101j outputs the signal EN of "low" level only when the operation result of the NAND operation circuit 101h and the signal from the address register 105 are both "low" level. In other words, the OR operation circuit 101j outputs the signal EN of "high" level when at least one of the operation result of the NAND operation circuit 101h and the signal from the address register 105 is "high" level.

The receiver 120 receives the input/output signal DQ inside the LUN 100 only when the signal EN and the input/output signal DQ are both at a "high" level.

<2-2>Action

The difference between the action described in the first implementation form and the action described in the second implementation form lies in the rising method of the signal EN in LUN100.

In the memory system 1 of the first embodiment, the signal EN is raised based on the assertion of the instruction latch enable signal CLE. In the memory system 1 of the second embodiment, the signal EN is raised by simultaneously asserting the instruction latch enable signal CLE and the address latch enable signal ALE. The action of simultaneously asserting the instruction latch enable signal CLE and the address latch enable signal ALE becomes the action for raising the signal EN.

<2-2-1>Write action example 2

Using Figure 8, Example 2 of the write operation of the memory system 1 of this embodiment is described. Here, the instruction sequence of the memory group GP0 is described.

At time T8, the memory controller 20 establishes the instruction latch enable signal CLE and the address latch enable signal ALE. As a result, the signal EN becomes "high" as described using FIG. 7. Then, the memory controller 20 negates the instruction latch enable signal CLE and the address latch enable signal ALE. Therefore, since the input signal of the NAND operation circuit 101h changes, the input signal of the NAND operation circuit 101i does not change, so the output signal of the NAND operation circuit 101h is maintained at a "high" level. As a result, the signal EN is maintained at a "high" level.

At time T9 after a period _tCALS has passed since time T8, the memory controller 20 issues write commands "01h" and "80h".

At time T10, if the selection of LUN100 is confirmed, the address latch circuit 105 outputs a "high" level signal in the selected LUN100 as shown in FIG7. As a result, the signal EN in LUN100 maintains a "high" level. On the other hand, in the non-selected LUN100, the address latch circuit 105 outputs a "low" level signal. As a result, the signal EN in the selected LUN100 becomes a "low" level. In other words, the receiver 120 of the selected LUN100 maintains the activation state, and the non-selected LUN100 is set to the standby state.

The memory controller 20 issues addresses (C1, C2: row addresses, R1~R3: column addresses) across 5 cycles, for example, and asserts (“high” level) the address latch enable signal ALE.

Secondly, the memory controller 20 outputs write data (D0~Dn) across multiple cycles. During the above period, the signals ALE and CLE are negated. The write data received by LUN100 is maintained in the page buffer in the sense amplifier 111.

<2-2-2>Write action example 3

Using Figures 9 and 10, Example 3 of the write operation of the memory system 1 of this embodiment is described. Here, the instruction sequence of the memory group GP0 is described.

The rising method of the signal EN in write action example 3 is the same as that in write action example 2, so the description is omitted. Here, the falling timing of the signal EN of the non-selected LUN100 is described.

For example, the selected LUN address is included in the column address R3. By supplying the column address R3 to LUN100, the selection of LUN100 is determined. If the selection of LUN100 is determined, the signal EN in the selected LUN100 is maintained at a "high" level, and the signal EN in the non-selected LUN100 becomes a "low" level. In other words, the receiver 120 of the selected LUN100 is maintained in an activated state, and the non-selected LUN100 is set to a standby state.

As shown in FIG9, after receiving the row address R3, the signal EN in the non-selected LUN 100 may immediately become a "low" level. As shown in FIG10, the signal EN in the non-selected LUN 100 may also become a "low" level according to the timing before and after the input and output of the data.

<2-2-3>Reading action example 2

Using Figure 11, the read operation example 2 of the memory system 1 of this embodiment is described. Here, the instruction sequence of the memory group GP0 is described.

The rising method of signal EN in read action example 2 is the same as that in write action example 2.

At time T13, the memory controller 20 asserts the command latch enable signal CLE and the address latch enable signal ALE. As a result, the signal EN becomes a "high" level as described using FIG. 7 .

At time T14 after a period _tCALS has passed since time T13, a read command "05h" is issued.

If the instruction register 104 receives "05h", it recognizes that the action requested from the memory controller 20 is a read action. Then, the instruction register 104 supplies a "low" level signal to the AND operation circuit 101a (refer to Figure 3). As a result, the signal EN becomes a "low" level.

That is, the receiver 120 becomes a standby state.

<2-2-4> Reading action example 3

Using Figures 12 to 14, the read operation example 3 of the memory system 1 of this embodiment is described. Here, the instruction sequence of the memory group GP0 is described.

The rising method of signal EN in read action example 3 is the same as that in read action example 2, so the description is omitted. Here, the falling timing of signal EN of LUN100 is described.

The instruction register 104 recognizes that the action requested from the memory controller 20 is a read action. Then, the instruction register 104 supplies a "low" level signal to the AND operation circuit 101a (refer to FIG. 3). As a result, the signal EN becomes a "low" level.

That is, the receiver 120 becomes a standby state.

As shown in FIG12, the signal EN in LUN100 may become a "low" level immediately after receiving the column address R3. Also, as shown in FIG13, the signal EN in LUN100 may become a "low" level immediately after receiving the command "E0h". Also, as shown in FIG14, the signal EN in LUN100 may become a "low" level according to the timing before and after the input and output of the data.

<2-3>Effects

According to the above-mentioned implementation form, by simultaneously establishing the command latch enable signal CLE and the address latch enable signal ALE, the receivers 120 of the plurality of LUNs 100 become activated.

With the increase in the speed of data input and output, the instruction address input cycle must be increased in speed. For example, in the case of the first implementation form, if the data input and output is increased in speed, the period required for setting the instruction input from the time the instruction latch enable signal CLE is established becomes insufficient, and there is a possibility that the setting is too late. In other words, before the instruction is input, LUN100 is not electrically connected to the data input and output line through the receiver 120, and there is a possibility that LUN100 cannot properly receive the instruction.

Therefore, in this embodiment, the receiver 120 is set to an activation state before the command latch enable signal CLE is asserted for inputting a command. Thus, the substantial period t _CALS can be relaxed compared to the first embodiment. Therefore, a memory system can be provided that can appropriately perform the transmission and reception of the input/output signal DQ along with the high speed of data input/output.

<2-4> Example 1 of variation of the second implementation form

<2-4-1>Write action example 4

Using FIG. 15, the write operation example 4 of the memory system 1 of this embodiment is described. Here, the instruction sequence of the memory group GP0 is described.

The rising method of the signal EN in write action example 4 is the same as that in write action example 2 of the second implementation form, so the description is omitted. Here, the falling timing of the signal EN of the non-selected LUN100 is described.

For example, the selected LUN address is included in the column address R3. By supplying the column address R3 to LUN100, the selection of LUN100 is determined. As shown in FIG7 , if the selection of LUN100 is determined and the command "XXh" is input, the output signal of the command register 104 becomes a "low" level. On the other hand, in the selected LUN100, the address register 105 maintains a "high" level signal, and in the non-selected LUN100, the address register 105 outputs a "low" level signal. Therefore, the signal EN in the selected LUN100 maintains a "high" level, and the signal EN in the non-selected LUN100 becomes a "low" level. In other words, the receiver 120 of the selected LUN 100 remains activated, and the receiver 120 of the non-selected LUN 100 is set to standby.

<2-4-2> Reading action example 4

Using Figure 16, the read operation example 4 of the memory system 1 of this embodiment is described. Here, the instruction sequence of the memory group GP0 is described.

The rising method of signal EN in read action example 4 is the same as that in read action example 2 of the second implementation form, so the description is omitted. Here, the falling timing of signal EN of LUN100 is described.

If the instruction register 104 receives "XXh", it recognizes that the action requested from the memory controller 20 is a read action. Then, the instruction register 104 supplies a "low" level signal to the AND operation circuit 101a (refer to Figure 3). Thereby, the signal EN becomes a "low" level. That is, the receiver 120 becomes a standby state.

<2-5> Example 2 of variation of the second implementation form

Using Figure 17, the structure of the input/output interface 101 of the memory system of the variation 2 of the second implementation form is specifically described.

The input/output interface 101 shown in FIG. 17 has a circuit for controlling the receiver 120 in a manner that is not electrically connected to the LUN 100 and the data input/output line when outputting data.

Specifically, as shown in FIG. 17 , the input/output interface 101 includes a NAND operation circuit 101k. Furthermore, the NAND operation circuit 101k outputs the operation result to the NAND operation circuit 1011 based on the inverted signal ^~ CLE of the command latch enable signal CLE, the inverted signal ^~ ALE of the address latch enable signal ALE, the inverted signal ^~ BCE of the chip enable signal BCE, and the write enable signal BWE. The NAND operation circuit 101k generates a "low" level signal only when the signals ^~ CLE, ^~ ALE, ^~ BCE, and BWE are all at a "high" level.

NAND operation circuit 101l and NAND operation circuit 101m constitute an RS flip-flop circuit. Specifically, NAND operation circuit 101l outputs the operation result based on the operation results of NAND operation circuit 101k and NAND operation circuit 101m. NAND operation circuit 101m outputs the operation result based on the operation result of NAND operation circuit 101l and read enable signal BRE.

The operation of this RS flip-flop circuit is briefly described. When the signal from the NAND operation circuit 101k is at a "high" level and the read enable signal BRE is at a "low" level, the NAND operation circuit 101l outputs a "low" level signal. Furthermore, when the signal from the NAND operation circuit 101k is at a "low" level and the read enable signal BRE is at a "high" level, the NAND operation circuit 101l outputs a "high" level signal. In addition, when the output signal of the NAND operation circuit 101l is determined, even if the signal from the NAND operation circuit 101k or the read enable signal BRE changes, the output signal of the NAND operation circuit 101l is maintained.

Furthermore, the inverter 101n inverts the output signal of the NAND operation circuit 101l and supplies it to the AND operation circuit 101o.

The AND operation circuit 101o outputs the operation result to the OR operation circuit 101p based on the output signal of the inverter 101n and the signal from the address register 105. The AND operation circuit 101a outputs a "high" level signal only when the output signal of the inverter 101n and the signal from the address register 105 are both "high" levels.

The OR operation circuit 101p generates the signal EN based on the operation results of the AND operation circuit 101o and the NAND operation circuit 101h. The OR operation circuit 101p outputs the signal EN of "low" level only when the operation results of the AND operation circuit 101o and the NAND operation circuit 101h are both "low" level. In other words, the OR operation circuit 101p outputs the signal EN of "high" level when at least one of the operation results of the AND operation circuit 101o and the NAND operation circuit 101h is "high" level.

During the data output period, the signals ^~ CLE, ^~ ALE, ^~ BCE, BWE, and BREA all become "high" level. As a result, the output signal of the NAND operation circuit 1011 is a signal with a "high" level. As a result, during the data output period, the signal EN becomes a "low" level.

In this way, the input/output interface 101 of the memory system of the variation 2 of the second embodiment can be controlled in a manner that the receiver 120 is not electrically connected to the LUN 100 and the data input/output line when outputting data.

<3>The third implementation form

The third embodiment is described. In the third embodiment, another structure of the input/output interface is described. Furthermore, the basic structure and basic operation of the memory device of the third embodiment are the same as those of the memory devices of the first and second embodiments described above. Therefore, the description of the matters described in the first and second embodiments described above and the matters that can be inferred from the first and second embodiments described above are omitted.

<3-1> Input and output interface structure

Next, the configuration of the input/output interface 101 of the memory system of the third embodiment will be specifically described using FIG18. Compared with the input/output interface 101 of the memory system of the second embodiment, the input/output interface 101 of the memory system of the third embodiment further inputs and outputs the input/output signal DQ based on the inverted signal ^~ BWE of the write enable signal BWE.

Specifically, the NAND operation circuit 101g1 outputs the operation result to the NAND operation circuit 101h based on the signals CLE, ALE, and ^~ BWE. The NAND operation circuit 101g1 generates a "low" level signal only when the signals CLE, ALE, and ^~ BWE are all at a "high" level.

<3-2>Action

The difference between the action described in the second implementation form and the action described in the third implementation form lies in the rising method of the signal EN in LUN100.

In the memory system 1 of the second embodiment, the signal EN is raised by simultaneously asserting the instruction latch enable signal CLE and the address latch enable signal ALE. On the other hand, in the memory system 1 of the third embodiment, the signal EN is raised by simultaneously asserting the instruction latch enable signal CLE, the address latch enable signal ALE, and the write enable signal BWE. That is, the action of simultaneously asserting the signals CLE, ALE, and BWE becomes the action for raising the signal EN.

<3-2-1>Write action example 5

Using Figure 19, the write operation example 5 of the memory system 1 of this embodiment is described. Here, the instruction sequence of the memory group GP0 is described.

At time T8, the memory controller 20 establishes the command latch enable signal CLE, the address latch enable signal ALE, and the write enable signal BWE. As a result, the signal EN becomes "high" as described using FIG. 18. Then, the memory controller 20 negates the command latch enable signal CLE, the address latch enable signal ALE, and the write enable signal BWE. Therefore, since the input signal of the NAND operation circuit 101h changes, the input signal of the NAND operation circuit 101i does not change, so the output signal of the NAND operation circuit 101h is maintained at a "high" level. As a result, the signal EN is maintained at a "high" level.

The actions after time T9 are the same as those described in Figure 8.

<3-2-2>Other access actions

As shown in Figure 20, the rising method of the signal EN in write action example 5 can also be applied to write action example 3 described in Figure 9.

Similarly, as shown in FIG21, the rising method of the signal EN in the write action example 5 can also be applied to the write action example 3 illustrated in FIG10.

As shown in Figure 22, the rising method of the signal EN in write action example 5 can also be applied to write action example 2 described in Figure 11.

Similarly, as shown in FIG23, the rising method of the signal EN in the write action example 5 can also be applied to the write action example 3 described in FIG12.

Similarly, as shown in FIG24, the rising method of the signal EN in the write action example 5 can also be applied to the write action example 3 described in FIG13.

Similarly, as shown in FIG25, the rising method of the signal EN in the write action example 5 can also be applied to the write action example 3 described in FIG14.

Similarly, as shown in FIG26, the rising method of the signal EN in the write action example 5 can also be applied to the write action example 4 described in FIG15.

Similarly, as shown in FIG27, the rising method of the signal EN in the write action example 5 can also be applied to the write action example 4 described in FIG16.

<3-3>Effects

According to the above implementation form, the same effect as the second implementation form can be achieved.

<3-4> Example of changes to the third implementation form

Next, the configuration of the input/output interface 101 of the memory system of the variation of the third embodiment will be specifically described using FIG28. Compared with the input/output interface 101 of the memory system of the variation of the second embodiment, the input/output interface 101 of the memory system of the variation of the third embodiment further inputs and outputs the input/output signal DQ based on the inverted signal ^~ BWE of the write enable signal BWE.

Specifically, the NAND operation circuit 101g1 outputs the operation result to the NAND operation circuit 101h based on the signals CLE, ALE, and ^~ BWE. The NAND operation circuit 101g1 generates a "low" level signal only when the signals CLE, ALE, and ^~ BWE are all at a "high" level.

<4>The fourth implementation form

The fourth embodiment is described. In the fourth embodiment, another structure of the input-output interface is described. Furthermore, the basic structure and basic operation of the memory device of the fourth embodiment are the same as those of the memory devices of the first to third embodiments described above. Therefore, the description of the matters described in the first to third embodiments described above and the matters that can be inferred from the first to third embodiments described above are omitted.

<4-1> Input and output interface structure

As shown in FIG. 29, the input/output interface 101 of the memory system 1 of the first embodiment and the input/output interface 101 of the memory system 1 of the second embodiment can be combined.

Moreover, as shown in FIG. 29 , the switch circuit 101q can be used to select which signal EN to use, the input/output interface 101 of the memory system 1 of the first embodiment or the input/output interface 101 of the memory system 1 of the second embodiment. For example, the output signal can be selected by generating a signal MS by using a “Set Feature” action and inputting it to the switch circuit 101q. The “Set Feature” action is, for example, an action to change the action mode of LUN 100.

<4-2>Action

Here, Figure 30 is used to explain the mode selection operation of the memory system of this embodiment.

As shown in FIG30 , when the memory system 1 is powered on, LUN 100 is set to the first operation mode. Furthermore, the memory controller 20 issues an initialization command "FFh". Then, the memory controller 20 performs a "setting feature" operation.

Specifically, the memory controller 20 issues the "set feature" action commands "EFh" and "YYh" to LUN100 in sequence, and then issues information about the change of the action mode (W-B0~W-B3).

If LUN100 receives the command "EFh" and "YYh" and the information (W-B0~W-B3), the operation mode is changed. For example, in this embodiment, it is changed to the second operation mode.

Here, the operation of the switch circuit 101q when the first operation mode is changed to the second operation mode is briefly described. As shown in FIG. 29, for example, in the first operation mode, the switch circuit 101q is sometimes controlled by selecting the output signal of the OR circuit 101b to be output as the signal EN. However, by switching to the second operation mode, the switch circuit 101q is controlled by selecting the output signal of the OR circuit 101j to be output as the signal EN.

Then, by performing the "Set Features" action, LUN100 will operate in the second action mode unless the action mode is changed.

If you want to make LUN100 operate in the first operation mode, you must change the operation mode again through the "Set Features" action.

<4-3>Effects

By using the switch circuit 101q as described above, the first and second embodiments can be appropriately combined to operate appropriately.

<4-4> Example 1 of variation of the fourth implementation form

As shown in FIG. 31 , the input/output interface 101 of the memory system 1 of the first embodiment and the input/output interface 101 of the memory system 1 of variation 2 of the second embodiment can be combined.

Moreover, as shown in FIG31, the switch circuit 101r can be used to select which signal to use, the input/output interface 101 of the memory system 1 of the first embodiment or the input/output interface 101 of the memory system 1 of the second embodiment of the variation 2. For example, the output signal can be selected by generating a signal MS by using a "set feature" action, etc., and inputting it to the switch circuit 101r. The "set feature" action is the same as the action described using FIG30.

<4-5> Example 2 of variation of the fourth implementation form

As shown in FIG. 32 , the input/output interface 101 of the memory system 1 of the first embodiment and the input/output interface 101 of the memory system 1 of the third embodiment can be combined.

Moreover, as shown in FIG32, the switch circuit 101q can be used to select which signal to use, the input/output interface 101 of the memory system 1 of the first embodiment or the input/output interface 101 of the memory system 1 of the third embodiment. For example, the output signal can be selected by generating a signal MS by using a "set feature" action, etc., and inputting it to the switch circuit 101q. The "set feature" action is the same as the action described using FIG30.

<4-6> Example 3 of variation of the fourth implementation form

As shown in FIG. 33 , the input/output interface 101 of the memory system 1 of the first embodiment and the input/output interface 101 of the memory system 1 of the variation of the third embodiment can be combined.

Moreover, as shown in FIG33, the switch circuit 101r can be used to select which signal to use, the input/output interface 101 of the memory system 1 of the first embodiment or the input/output interface 101 of the memory system 1 of the third embodiment. For example, the output signal can be selected by generating a signal MS by using a "setting feature" action and inputting it to the switch circuit 101r. The "setting feature" action is the same as the action described using FIG30.

<5> Fifth implementation form

The fifth embodiment is described. In the fifth embodiment, another structure of the input/output interface is described. Furthermore, the basic structure and basic operation of the memory device of the fifth embodiment are the same as those of the memory devices of the first and second embodiments described above. Therefore, the description of the matters described in the first and second embodiments described above and the matters that can be inferred from the first and second embodiments described above are omitted.

<5-1> Input and output interface structure

Next, the structure of the input/output interface 101 is specifically described using FIG. 34.

As shown in FIG. 34 , the input/output interface 101 inputs and outputs the input/output signal DQ based on the inverted signal ^~ BWP of the write protection signal BWP or the signal from the address register 105.

The OR operation circuit 101s generates the signal EN based on the signal ^~ BWP and the signal from the address register 105. The OR operation circuit 101s outputs the signal EN of "low" level only when the signal ^~ BWP and the signal from the address register 105 are both at "low" level. In other words, the OR operation circuit 101s outputs the signal EN of "high" level when at least one of the signal ^~ BWP and the signal from the address register 105 is at "high" level.

The receiver 120 receives the input/output signal DQ inside the LUN 100 based on the signal EN and the input/output signal DQ. The receiver 120 receives the input/output signal DQ inside the LUN 100 only when the signal EN and the input/output signal DQ are both at a "high" level.

<5-2>Action

<5-2-1>Write action example 6

Using Figure 35, the write operation example 6 of the memory system 1 of this embodiment is described. Here, the instruction sequence of the memory group GP0 is described.

At time T20, the memory controller 20 asserts (at a "low" level) the write protection signal BWP. During the assertion of the write protection signal BWP, the signal EN is maintained at a "high" level.

At time T21 after a period _tCALS has passed since time T20, the memory controller 20 issues write commands "01h" and "80h".

After determining the address of LUN100, at time T22, the memory controller 20 negates ("high" level) the write protection signal BWP. If the write protection signal BWP is negated, the signal EN in the non-selected LUN100 becomes "low" level. On the other hand, in the selected LUN100, since the signal of the address register 105 is maintained at a "high" level, the signal EN is maintained at a "high" level.

The other actions are the same as those described in Figure 8.

As described above, in this embodiment, the write protection signal BWP is used to control the signal EN. On the other hand, when implementing this action, the write protection action cannot be performed. However, if an action such as "setting features" is used, the mode of operating this embodiment and the mode of using the write protection action can be appropriately switched.

<5-2-2>Write action example 7

Using Figures 36 and 37, the write operation example 7 of the memory system 1 of this embodiment is described. Here, the instruction sequence of the memory group GP0 is described.

The rising method of the signal EN in write action example 7 is the same as that in write action example 6, so the description is omitted. Here, the falling timing of the signal EN of the non-selected LUN100 is described.

For example, the selected LUN address is included in the column address R3. After determining the address of LUN100, at time T23, the memory controller 20 negates ("high" level) the write protection signal BWP. If the write protection signal BWP is negated, the signal EN in the non-selected LUN100 becomes "low" level. On the other hand, in the selected LUN100, since the signal of the address register 105 is maintained at a "high" level, the signal EN is maintained at a "high" level.

As shown in FIG36, after receiving the row address R3, the signal EN in the non-selected LUN100 may immediately become a "low" level. As shown in FIG37, the signal EN in the non-selected LUN100 may also become a "low" level according to the timing before and after the input and output of the data.

<5-2-3> Reading action example 5

Using Figure 38, the read operation example 5 of the memory system 1 of this embodiment is explained. Here, the instruction sequence of the memory group GP0 is explained.

At time T25, the memory controller 20 asserts the write protection signal BWP. During the assertion of the write protection signal BWP, the signal EN is maintained at a "high" level.

At time T26 after a period _tCALS has passed since time T25, a read command "05h" is issued.

After determining that it is a read action, at time T27, the memory controller 20 negates ("high" level) the write protection signal BWP. If the write protection signal BWP is negated, the signal EN in the selected LUN100 becomes a "low" level.

<5-2-4> Reading action example 6

Using Figures 39 to 41, the read operation example 6 of the memory system 1 of this embodiment is explained. Here, the instruction sequence of the memory group GP0 is explained.

The rising method of signal EN in read action example 6 is the same as that in read action example 5, so the description is omitted. Here, the falling timing of signal EN of LUN100 is described.

After determining that the read operation is in progress, at time T28, the memory controller 20 negates (“high” level) the write protection signal BWP. If the write protection signal BWP is negated, the signal EN in the selected LUN100 becomes “low” level.

As shown in FIG39, the signal EN in LUN100 may become a "low" level immediately after receiving the column address R3. Also, as shown in FIG40, the signal EN in LUN100 may become a "low" level immediately after receiving the command "E0h". Also, as shown in FIG41, the signal EN in LUN100 may become a "low" level according to the timing before and after the input and output of the data.

<5-3>Effects

According to the above implementation form, the same effect as the second implementation form can be achieved.

<5-4> Example of changes to the fifth implementation form

In the fifth embodiment, the write protection signal BWP is used to control the signal EN. However, a signal NP dedicated to the control of the signal EN may also be used. In the above case, as shown in FIG. 34, the signal NP is input to the OR operation circuit 101s instead of the signal ^~ BWP. The above signal NP is set to be input from the memory controller 20 to the NAND type flash memory 10.

<5-4-1>Write action example 8

Using Figure 42, the write operation example 8 of the memory system 1 of this embodiment is described. Here, the instruction sequence of the memory group GP0 is described.

At time T20, the memory controller 20 asserts (“high” level) the signal NP. During the assertion of the signal NP, the signal EN is maintained at a “high” level.

At time T21 after a period _tCALS has passed since time T20, the memory controller 20 issues write commands "01h" and "80h".

After determining the address of LUN100, at time T22, the memory controller 20 negates ("low" level) the signal NP. If the signal NP is negated, the signal EN in the non-selected LUN100 becomes "low" level. On the other hand, in the selected LUN100, since the signal of the address register 105 is maintained at a "high" level, the signal EN is maintained at a "high" level.

The other actions are the same as those described in Figure 8.

As described above, in this embodiment, the signal NP is used to control the signal EN.

<5-4-2>Write action example 9

Using Figures 43 and 44, the write operation example 9 of the memory system 1 of this embodiment is described. Here, the instruction sequence of the memory group GP0 is described.

The rising method of the signal EN in write action example 9 is the same as that in write action example 8, so the description is omitted. Here, the falling timing of the signal EN of the non-selected LUN100 is described.

For example, the selected LUN address is included in the column address R3. After determining the address of LUN100, at time T23, the memory controller 20 negates the signal NP. If the signal NP is negated, the signal EN in the non-selected LUN100 becomes a "low" level. On the other hand, in the selected LUN100, since the signal of the address register 105 is maintained at a "high" level, the signal EN is maintained at a "high" level.

As shown in FIG43, after receiving the row address R3, the signal EN in the non-selected LUN100 may immediately become a "low" level. As shown in FIG44, the signal EN in the non-selected LUN100 may also become a "low" level according to the timing before and after the input and output of the data.

<5-4-3> Reading action example 7

Using Figure 45, the read operation example 7 of the memory system 1 of this embodiment is explained. Here, the instruction sequence of the memory group GP0 is explained.

At time T25, the memory controller 20 asserts the signal NP. During the assertion of the signal NP, the signal EN is maintained at a "high" level.

At time T26 after a period _tCALS has passed since time T25, a read command "05h" is issued.

After determining that the read action is a read operation, at time T27, the memory controller 20 negates the signal NP. If the signal NP is negated, the signal EN in the selected LUN100 becomes a "low" level.

<5-4-4> Reading action example 8

Using Figures 46 to 48, the read operation example 8 of the memory system 1 of this embodiment is described. Here, the instruction sequence of the memory group GP0 is described.

The rising method of signal EN in read action example 8 is the same as that in read action example 7, so the description is omitted. Here, the falling timing of signal EN of LUN100 is described.

After determining that the read action is a read operation, at time T28, the memory controller 20 negates the signal NP. If the signal NP is negated, the signal EN in the selected LUN100 becomes a "low" level.

As shown in FIG46, the signal EN in LUN100 may become a "low" level immediately after receiving the column address R3. Also, as shown in FIG47, the signal EN in LUN100 may become a "low" level immediately after receiving the command "E0h". Also, as shown in FIG48, the signal EN in LUN100 may become a "low" level according to the timing before and after the input and output of the data.

<6> The sixth implementation form

The sixth embodiment is described. In the sixth embodiment, another structure of the input/output interface is described. Furthermore, the basic structure and basic operation of the memory device of the sixth embodiment are the same as those of the memory devices of the first and fifth embodiments described above. Therefore, the description of the matters described in the first and fifth embodiments described above and the matters that can be inferred from the first and fifth embodiments described above are omitted.

<6-1> Input and output interface structure

As shown in FIG. 49, the input/output interface 101 of the memory system 1 of the first embodiment and the input/output interface 101 of the memory system 1 of the fifth embodiment can be combined.

Moreover, as shown in FIG. 49, the switch circuit 101t can be used to select which signal EN is used, the input/output interface 101 of the memory system 1 of the first embodiment or the input/output interface 101 of the memory system 1 of the fifth embodiment. For example, the output signal can be selected by generating the signal MS by using the "setting feature" action, etc., and inputting it to the switch circuit 101t. The "setting feature" action is the same as the action described using FIG. 30.

<7> Implementation form 7

The seventh embodiment is described. In the seventh embodiment, another structure of the receiver is described. Furthermore, the basic structure and basic operation of the memory device of the seventh embodiment are the same as those of the memory devices of the first to sixth embodiments described above. Therefore, the description of the matters described in the first to sixth embodiments described above and the matters that can be analogized from the first to sixth embodiments described above are omitted. The receiver described below can be applied to each of the above embodiments.

<7-1> Receiver composition

Using FIG. 50, another example of the receiver 120 is described.

For example, in standby mode (when no data is being sent or received), it is better to suppress the current consumption in terms of reducing power consumption. Therefore, in this embodiment, the receiver 120 has a first receiver 101v that cannot operate at high speed but consumes low current, a second receiver 101w that can operate at high speed but consumes high current, and a switch circuit 101u that selects the connection between the first receiver 101v and the second receiver 101w.

The switch circuit 101u connects the data input/output line to the first receiver 101v when the signal EN is at a "low" level, and connects the data input/output line to the second receiver 101w when the signal EN is at a "high" level.

<7-2> Composition of the first receiver

Using Figure 51, the circuit example of the first receiver 101v is explained.

As shown in FIG. 51 , the first receiver 101v has an inverter including a PMOS (Positive-channel Metal Oxide Aemiconductor) transistor 11a and an NMOS (Negative-channel Metal Mxide Memiconductor) transistor 11b.

The power supply voltage VDD is applied to the source of the PMOS transistor 11a, the drain is connected to the output terminal (node N2), and the gate is connected to the input terminal (node N1). The drain of the NMOS transistor 11b is connected to the output terminal (node N2), the source is connected to the ground potential, and the gate is connected to the input terminal (node N1).

That is, the first receiver 101v outputs a "high" level signal from the output terminal when the input signal is at a "low" level, and outputs a "low" level signal from the output terminal when the input signal is at a "high" level.

<7-3> Construction of the second receiver

Using Figure 52, the circuit example of the second receiver 101w is explained.

As shown in FIG. 52 , the second receiver 101w has a mirror circuit including PMOS transistors 11c, 11d, 11e, 11f and NMOS transistors 11g, 11h, 11i.

A power voltage VDD is applied to the source of the PMOS transistor 11c, and a signal ENBn (the inversion signal of the signal EN) is input to the gate. The PMOS transistor 11c flows current when the signal ENBn is at a "low" level.

The source of PMOS transistor 11e is connected to the drain of PMOS transistor 11c, and the drain is connected to the gate.

A power voltage VDD is applied to the source of the PMOS transistor 11d, and a signal ENBn is input to the gate. The PMOS transistor 11d flows current when the signal ENBn is at a "low" level.

The source of PMOS transistor 11f is connected to the drain of PMOS transistor 11d, and the drain is connected to the output terminal (node N6), and the gate is connected to node N5. PMOS transistor 11f flows the same current as PMOS transistor 11e.

The drain of the NMOS transistor 11g is connected to the node N5, the source is connected to the node N7, and a reference voltage VREF is applied to the gate. The reference current flows through the NMOS transistor 11g.

The NMOS transistor 11h has a drain connected to the output terminal (node N6), a source connected to the node N7, and a gate connected to the input terminal.

The drain of the NMOS transistor 11i is connected to the node N7, the source is connected to the ground potential, and a reference voltage IREFN is applied to the gate. The above-mentioned NMOS transistor 11i functions as a constant current source.

That is, the second receiver 101w outputs a "high" level signal from the output terminal when the signal ENBn is at a "low" level and the input signal is at a "low" level, and outputs a "low" level signal from the output terminal when the signal ENBn is at a "low" level and the input signal is at a "high" level.

<8>Supplementary instructions

Furthermore, FIG. 53 shows the conditions for the rise of the signal EN (to set all LUNs 100 to be activated) in each of the above-mentioned implementation forms.

Furthermore, in each of the above-mentioned embodiments, although various descriptions are given of the falling timing of the signal EN, it is not limited to the above-mentioned timing and can be appropriately changed. Specifically, the signal EN can be dropped according to the timing before and after the input and output of the start data. In this way, the consumption of useless current for non-selected LUNs or LUNs during the reading operation can be suppressed.

Furthermore, in each embodiment of the present invention:

(1) In the read operation, the voltage applied to the selected word line for the A-level read operation is, for example, between 0V and 0.55V. This is not limited to this, and may also be set to any one of 0.1V to 0.24V, 0.21V to 0.31V, 0.31V to 0.4V, 0.4V to 0.5V, and 0.5V to 0.55V.

The voltage applied to the selected word line for the B-level read operation is, for example, between 1.5V and 2.3V. This is not limited to this, and can also be set to any one of 1.65V to 1.8V, 1.8V to 1.95V, 1.95V to 2.1V, and 2.1V to 2.3V.

The voltage applied to the selected word line for the C-level read operation is, for example, between 3.0V and 4.0V. It is not limited thereto and can also be set to any one of 3.0V to 3.2V, 3.2V to 3.4V, 3.4V to 3.5V, 3.5V to 3.6V, and 3.6V to 4.0V.

The readout action time (tR) can also be set, for example, between 25μs~38μs, 38μs~70μs, and 70μs~80μs.

(2) The writing operation includes the programming operation and the verification operation as described above. In the writing operation, the voltage initially applied to the selected word line during the programming operation is, for example, between 13.7V and 14.3V. This is not limited to this, and may also be set to, for example, between 13.7V and 14.0V or 14.0V and 14.6V.

It is also possible to change the voltage initially applied to the selected word line when writing to the odd-numbered word line and the voltage initially applied to the selected word line when writing to the even-numbered word line.

When the programming action is set to ISPP mode (Incremental Step Pulse Program), the voltage used for boosting is, for example, about 0.5V.

The voltage applied to the non-selected word line may be, for example, between 6.0V and 7.3V. It is not limited thereto and may be, for example, between 7.3V and 8.4V or below 6.0V.

The applied path voltage can also be changed according to whether the non-selected word line is an odd-numbered word line or an even-numbered word line.

The writing operation time (tProg) can also be set to, for example, 1700μs~1800μs, 1800μs~1900μs, or 1900μs~2000μs.

(3) During the erase operation, the voltage initially applied to the wafer formed on the upper part of the semiconductor substrate and having the memory cell disposed thereon is, for example, between 12V and 13.6V. This is not limited to the above situation, and may also be set to, for example, between 13.6V and 14.8V, 14.8V and 19.0V, 19.0 and 19.08V, or 19.8V and 21V.

The erase operation time (tErase) can also be set to, for example, 3000μs~4000μs, 4000μs~5000μs, or 4000μs~9000μs.

(4) The structure of the memory cell has a charge storage layer configured on a semiconductor substrate (silicon substrate) through a tunnel insulating film with a dielectric film thickness of 4 to 10 nm. The charge storage layer can be a multilayer structure of an insulating film such as SiN or SiON with a film thickness of 2 to 3 nm and polycrystalline silicon with a film thickness of 3 to 8 nm. In addition, metals such as Ru can also be added to polycrystalline silicon. An insulating film is provided on the charge storage layer. The insulating film has, for example, a lower layer High-k (high dielectric constant) film with a film thickness of 3 to 10 nm and a silicon oxide film with a film thickness of 4 to 10 nm sandwiched by an upper layer High-k film with a film thickness of 3 to 10 nm. Examples of High-k films include HfO, etc. In addition, the thickness of the silicon oxide film can be set to be thicker than the thickness of the High-k film. On the insulating film, a control electrode with a film thickness of 30nm~70nm is formed by a material with a dielectric film thickness of 3~10nm. Here, the material used for work function adjustment is, for example, a metal oxide film such as TaO, a metal nitride film such as TaN. The control electrode can use W, etc.

In addition, air gaps can form between memory cells.

Although the embodiments of the present invention have been described above, the present invention is not limited to the embodiments described above and can be implemented with various modifications within the scope of the main purpose. Furthermore, the embodiments described above include inventions at various stages, and various inventions can be extracted by appropriately combining the disclosed constituent elements. For example, if a specific effect can still be obtained by removing some constituent elements from the disclosed constituent elements, it can also be extracted as an invention.

101: Input and output interface

101c: NAND operation circuit

101d: Inverter

101g: NAND operation circuit

101h: NAND operation circuit

101i: NAND operation circuit

101j:OR operation circuit

104: Instruction register

105: Address register

105a: Memory

120: Receiver

ADD: address

ALE: Address latch enable signal

BWE: Write enable signal

CLE: Command latch enable signal

DQ: input and output signal

EN:Signal

Claims (20)

A memory system includes: a memory device; and a memory controller, wherein the memory device includes: a memory cell array configured to store data; a data input/output interface configured to receive instructions, addresses, and data to be written to the memory cell array from the memory controller, and output data read from the memory cell array to the memory controller; a transmitter connected to the data input/output interface and configured to be driven by an enable signal; and a control circuit configured to respond to a first control signal by the memory cell array to control the memory device. The memory controller asserts the reception of the read instruction and the second control signal, and the memory cell array performs a read operation as the read address is received after the read instruction; wherein the memory controller asserts the first control signal and the second control signal simultaneously before sending the read instruction, so that the control circuit of the memory device makes the enable signal become the first level, and maintains it at the first level at least after receiving the read instruction. A memory system as claimed in claim 1, wherein the memory device further comprises: a command register configured to store a command sent from the memory controller; and an address register configured to store an address sent from the memory controller, wherein the first control signal comprises a signal for causing the command register to store the command, and the second control signal comprises a signal for causing the address register to store the address. A memory system as claimed in claim 2, wherein in the memory device, the enable signal is set to the first level based on a first logical operation result, the first logical operation is a logical operation between an instruction and a second logical operation result, and the second logical operation result is a logical operation between the first control signal and the second control signal. A memory system as claimed in claim 3, wherein the logic operation of the first logic operation result is a RS flip flop (Reset and Set flip flop), and the logic operation of the second logic operation result is a NAND gate (NAND gate). A memory system as claimed in claim 1, wherein the transmitter outputs the data read from the memory cell array to the memory controller via the data input/output interface. A memory system as claimed in claim 5, wherein the data read from the memory cell array is sent to the memory controller together with a data selection signal via the data input/output interface. A memory system as claimed in claim 6, wherein the memory controller switches the third control signal when concurrently asserting the first control signal and the second control signal, so that the control circuit of the memory device causes the enable signal to be at the first level. A memory system as claimed in claim 7, wherein the memory device further comprises: a command register configured to store commands sent from the memory controller; and an address register configured to store addresses sent from the memory controller; wherein the first control signal comprises a signal for causing the command register to store commands, the second control signal comprises a signal for causing the address register to store addresses, and the third control signal comprises a signal for causing the memory device to accept (take) commands or data. A memory system as claimed in claim 1, wherein the first level is different from the level of the enable signal after receiving the read command. A memory system as claimed in claim 9, wherein the control circuit executes the read operation in response to the read instruction and the subsequent reception of the read address and a falling edge or a rising edge of the third instruction signal. A memory system includes: a memory device; and a memory controller, wherein the memory device includes: a memory cell array configured to store data; a data input/output interface configured to receive instructions, addresses, and data to be written to the memory cell array from the memory controller, and output data read from the memory cell array to the memory controller; a receiver connected to the data input/output interface and configured to be driven by an enable signal; and a control circuit configured to receive a write instruction, a second control signal, and a second control signal when a first control signal is asserted by the memory controller. The memory cell array performs a write operation when the write address is received after the write command and the data to be written to the memory cell array is received after the write address when the first control signal and the second control signal are not established by the memory controller; and the memory controller simultaneously establishes the first control signal and the second control signal before sending the write command, so that the control circuit of the memory device makes the enable signal become the first level, and maintains it at the first level at least after receiving the write command. A memory system as claimed in claim 11, wherein the memory device further comprises: a command register configured to store a command sent from the memory controller; and an address register configured to store an address sent from the memory controller; wherein the first control signal comprises a signal for causing the command register to store the command, and the second control signal comprises a signal for causing the address register to store the address. A memory system as claimed in claim 12, wherein in the memory device, the enable signal is set to the first level based on a first logical operation result, the first logical operation is a logical operation between an instruction and a second logical operation result, and the second logical operation result is a logical operation between the first control signal and the second control signal. A memory system as claimed in claim 13, wherein the logic operation of the first logic operation result is an RS flip-flop, and the logic operation of the second logic operation result is a NAND gate. A memory system as claimed in claim 11, wherein the receiver receives the data to be written to the memory cell array from the memory controller via the data input/output interface. A memory system as claimed in claim 15, wherein the data to be written to the memory cell array is received from the memory controller together with a data strobe signal via the data input/output interface. A memory system as claimed in claim 16, wherein the memory controller switches the third control signal when the first control signal and the second control signal are simultaneously established, so that the control circuit of the memory device causes the enable signal to become the first level. A memory system as claimed in claim 17, wherein the memory device further comprises: an instruction register configured to store instructions sent from the memory controller; and an address register configured to store addresses sent from the memory controller; wherein the first control signal comprises a signal for causing the instruction register to store instructions, the second control signal comprises a signal for causing the address register to store addresses, and the third control signal comprises a signal for causing the memory device to receive instructions or data. A memory system as claimed in claim 11, wherein the first level is different from the level of the enable signal after receiving the write command. A memory system as claimed in claim 19, wherein the control circuit performs the write operation in response to the write instruction and the write address following the read instruction and the falling edge or rising edge of the third instruction signal.

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