TWI685849B - Semiconductor memory device and operating method thereof - Google Patents

Abstract

In an embodiment, a method of operating a semiconductor memory device may include performing a read operation on a selected memory block, and, during the read operation, enabling local select lines to float so that potential levels of local word lines coupled to unselected memory blocks is increased.

Description

Semiconductor memory device and its operating method

Various embodiments of the present disclosure generally relate to semiconductor memory devices and operating methods thereof, and more particularly, to a semiconductor memory device having multiple memory blocks and an operating method thereof.

Cross-reference for related applications

This application is based on the priority of Korean Patent Application No. 10-2016-0006584 filed on January 19, 2016 at the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference.

Semiconductor memory devices can be classified into volatile memory devices and non-volatile memory devices.

Although the non-volatile memory device has a slow programming/reading operation speed, it can retain its data even in the absence of power. Therefore, the non-volatile memory device can be used for secondary storage (secondary storage) tasks, which does not lose data when the device is powered off. Examples of non-volatile memory devices may include read-only memory (ROM), mask ROM (MROM), programmable ROM (PROM), erasable programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), flash memory, random phase change Access memory (PRAM), magnetic RAM (MRAM), resistive RAM (RRAM), ferroelectric RAM (FRAM), etc. Flash memory is classified into NOR type memory and NAND type memory.

Like random access memory (RAM), flash memory can be written and erased multiple times, and like ROM, flash memory can retain its data even when power is interrupted. Recently, flash memory is widely used as a storage medium for portable electronic devices such as digital cameras, smart phones, personal digital assistants (PDAs), and MP3s.

In an embodiment of the present disclosure, a method of operating a semiconductor memory device may include the steps of: performing a read operation of a selected memory block; and, during the read operation, enabling a local selection line to float, The potential level of the local word line coupled to the unselected memory block is increased.

In an embodiment of the present disclosure, a method of operating a semiconductor memory device may include the steps of: performing a read operation of a selected memory block; and during the read operation, coupling to an unselected memory The local selection line of the block is pulled to ground.

In an embodiment of the present disclosure, a semiconductor memory device may include a plurality of memory blocks, a local selection line and a local word line coupled to the corresponding memory block, a voltage generating circuit, a selection line passing circuit, a word line Through circuits, block decoders and control logic. The voltage generating circuit can output various levels of operating voltages to the global selection line and the global word line. The selection line passing circuit can selectively couple or decouple the global selection line and the local selection line. The word line passing circuit may commonly couple or decouple the global word line and the local word line. The block decoder can control the shared The word line passes through the circuit. The control logic may control the voltage generation circuit, the selection line passing circuit, and the block decoder in response to a command.

According to an embodiment of the present disclosure, during a read operation of the semiconductor memory device, the potential levels of the word line and the selection line of the unselected memory block are controlled to prevent the unselected memory block from Hot carriers (eg, holes) are captured in the channel. As a result, the reliability of the read operation of unselected memory blocks can be improved.

100‧‧‧Semiconductor memory device

110‧‧‧ voltage generating circuit

120‧‧‧Switch circuit

121‧‧‧ First switch circuit

122‧‧‧ Second switch circuit

130‧‧‧Through the circuit group

131‧‧‧ First pass circuit

132‧‧‧ Second pass circuit

140‧‧‧Memory unit

141‧‧‧ First memory block

142‧‧‧Second memory block

150‧‧‧Control logic

160‧‧‧block decoder

200‧‧‧Semiconductor memory device

210‧‧‧ voltage generation circuit

220‧‧‧Switch circuit

221‧‧‧ First switch circuit

222‧‧‧ Second switch circuit

230‧‧‧Through the circuit group

231‧‧‧ First pass circuit

232‧‧‧ Second pass circuit

240‧‧‧Memory unit

241‧‧‧ First memory block

242‧‧‧Second memory block

250‧‧‧Control logic

260‧‧‧block decoder

270‧‧‧Select line control circuit

271‧‧‧ First source selection line controller

272‧‧‧The first drain selection line controller

273‧‧‧Second source selection line controller

274‧‧‧Second drain selection line controller

300‧‧‧Semiconductor memory device

310‧‧‧ voltage generation circuit

320‧‧‧Through the circuit group

321‧‧‧ First pass circuit

322‧‧‧Second pass circuit

330‧‧‧Select line switch circuit

331‧‧‧ First drain select line switch circuit

332‧‧‧ First source selection line switch circuit

333‧‧‧Second drain select line switch circuit

334‧‧‧Second source selection line switch circuit

340‧‧‧Memory unit

341‧‧‧ First memory block

342‧‧‧Second memory block

350‧‧‧Control logic

360‧‧‧block decoder

400‧‧‧Semiconductor memory device

410‧‧‧ voltage generation circuit

420‧‧‧Through the circuit

421‧‧‧ First drain select line pass circuit

422‧‧‧The first word line through circuit

423‧‧‧The first source selection line through circuit

424‧‧‧Second drain select line passing circuit

425‧‧‧The second word line through circuit

426‧‧‧Second source selection line passing circuit

430‧‧‧Memory unit

431‧‧‧ First memory block

432‧‧‧Second memory block

440‧‧‧Control logic

450‧‧‧block decoder

1000‧‧‧Memory system

1100‧‧‧Controller

1110‧‧‧RAM

1120‧‧‧ processing circuit

1130‧‧‧Host interface

1140‧‧‧Memory interface

1150‧‧‧Error correction block

2000‧‧‧Memory system

2100‧‧‧Semiconductor memory device

2200‧‧‧Controller

3000‧‧‧computing system

3100‧‧‧Central Processing Circuit

3200‧‧‧RAM

3300‧‧‧User interface

3400‧‧‧Power

3500‧‧‧ system bus

FIG. 1 is a diagram illustrating a semiconductor memory device according to an embodiment of the present disclosure.

FIG. 2 is a flowchart illustrating operation according to the embodiment of the semiconductor memory device illustrated in FIG. 1.

FIG. 3 is a flowchart illustrating operations according to the embodiment of the semiconductor memory device illustrated in FIG. 1.

4 is a diagram illustrating a semiconductor memory device according to an embodiment of the present disclosure.

FIG. 5 is a flowchart illustrating the operation of the semiconductor memory device illustrated in FIG. 4.

FIG. 6 is a diagram illustrating a semiconductor memory device according to an embodiment of the present disclosure.

FIG. 7 is a diagram illustrating in detail the second group of the semiconductor memory device illustrated in FIG. 6.

FIG. 8 is a flowchart illustrating the operation of the semiconductor memory device illustrated in FIG. 6 Figure.

9 is a diagram illustrating a semiconductor memory device according to an embodiment of the present disclosure.

FIG. 10 is a diagram illustrating in detail the fourth group of the semiconductor memory device illustrated in FIG. 9.

FIG. 11 is a flowchart illustrating the operation of the semiconductor memory device illustrated in FIG. 9.

FIG. 12 is a diagram illustrating a memory system including a semiconductor memory device according to an embodiment of the present disclosure.

FIG. 13 is a diagram illustrating an application example of the memory system of FIG. 12.

FIG. 14 is a diagram illustrating a computing system including the memory system illustrated with reference to FIG. 13.

Exemplary embodiments will now be described more fully hereinafter with reference to the accompanying drawings; however, the exemplary embodiments may be embodied in different forms and should not be interpreted as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the exemplary embodiments to those skilled in the art.

In the drawings, the size may be enlarged for clarity of illustration. It will be understood that when an element is referred to as being "between" two elements, the element can be the only element between the two elements, or one or more intervening elements may also be present . The same reference numbers refer to the same elements throughout.

Hereinafter, the embodiments will be described in more detail with reference to the drawings. The embodiments are described herein with reference to cross-sectional examples that are schematic examples of embodiments (and intermediate structures). Therefore, changes in shape from, for example, examples that are the result of manufacturing techniques and/or tolerances are expected. Therefore, the embodiments should not be interpreted as being limited to the specific shapes of the regions illustrated herein, but may include shape deviations caused by manufacturing, for example. In the drawings, the length and size of layers and regions may be exaggerated for clarity. The same reference numerals in the drawings denote the same elements.

The advantages and features of the present disclosure and the method of implementation thereof will be made clear with reference to the exemplary embodiments described later in detail together with the drawings. Therefore, the present disclosure is not limited to the following embodiments, but may be specifically implemented in other types. Rather, these embodiments are provided so that the present disclosure will be thorough and complete, and fully convey the technical spirit of the present disclosure to those skilled in the art.

It will be understood that when an element is referred to as being "coupled" or "connected" to another element, the one element can be directly coupled or connected to the other element, or intervening elements may be present therebetween. In this specification, when an element is referred to as an "include" or "include" element, unless the context clearly indicates otherwise, the element does not exclude another element, but may also include other elements.

FIG. 1 is a diagram illustrating a semiconductor memory device according to an embodiment of the present disclosure.

Referring to FIG. 1, the semiconductor memory device 100 may include a voltage generating circuit 110, a switching circuit 120, a pass circuit group 130, a memory unit 140, a control logic 150 and a block decoder 160.

The voltage generating circuit 110 may generate operating voltages having various levels in response to an operating signal output from the control logic 150 during a read operation, and may output these operating voltages to global word lines and global select lines. For example, the operating voltage may include a read voltage, a pass voltage, a selection transistor control voltage, a compensation voltage, and the like. The voltage generating circuit 110 may transmit operating voltages having various levels to the first global word line GWLs_A, the first global selection lines GDSL_A and GSSL_A, the second global word line GWLs_B, and the second global selection lines GDSL_B and GSSL_B. For example, in the case where the first memory block 141 is selected between the first memory block 141 and the second memory block 142 of the memory unit 140, the voltage generating circuit 210 may assign the first memory block The first global word line GWLs_A and the first global selection lines GDSL_A and GSSL_A of the block 141 send operating voltages, and can select the second global word line GWLs_B and the second global selection assigned to the unselected second memory block 142 The lines GDSL_B and GSSL_B send a voltage of zero volts or a compensation voltage lower than the operating voltage. The compensation voltage may be set, for example, in a range from zero volts to four volts. A voltage of zero volts can be obtained by coupling the selected line to the ground terminal. The switch circuit 120 may include a first switch circuit 121 and a second switch circuit 122.

The first switch circuit 121 may couple the first global word line GWLs_A to the first sub-global word line GWLs_A1, and may couple the first global field selection lines GDSL_A and GSSL_A to the first sub-global word selection lines GDSL_A1 and GSSL_A1. For example, the first switching circuit 121 may include a high-voltage transistor that is turned on or off in response to the selection control voltage CS_A. In response to the selection control voltage CS_A output from the control logic 150, the first switching circuit 121 may send the operating voltage or the compensation voltage applied through the first global word line GWLs_A to the first sub-global word line GWLs_A1, or may make the first sub-global The word line GWLs_A1 can float. Response to slave The selection control voltage CS_A output by the control logic 150, the first switch circuit 121 may send a plurality of operating voltages or compensation voltages input through the first global selection lines GDSL_A and GSSL_A to the first sub-global selection lines GDSL_A1 and GSSL_A1, or may make the A sub-global selection line GDSL_A1 and GSSL_A1 can float. The selection control voltage CS_A may be a voltage of zero volts or a high voltage higher than a plurality of operating voltages input through the first global word line GWLs_A and the first global selection lines GDSL_A and GSSL_A.

The second switching circuit 122 may couple the second global word line GWLs_B to the second sub-global word line GWLs_B1, and may couple the second global field selection lines GDSL_B and GSSL_B to the second sub-global word selection lines GDSL_B1 and GSSL_B1. For example, the second switching circuit 122 may include a high-voltage transistor that is turned on or off in response to the deselection control voltage CS_B. In response to the deselected control voltage CS_B output from the control logic 150, the second switching circuit 122 may send a plurality of operating voltages or compensation voltages input through the second global word line GWLs_B to the second sub-global word line GWLs_B1, or may make the first The two sub-global word lines GWLs_B1 can float. In response to the deselection control voltage CS_B output from the control logic 150, the second switch circuit 122 may send a plurality of operating voltages input through the second global selection lines GDSL_B and GSSL_B to the second sub-global selection lines GDSL_B1 and GSSL_B1, or may make The second sub-global selection lines GDSL_B1 and GSSL_B1 can float. The deselection control voltage CS_B may be a voltage in a range from zero volts to four volts or a high voltage higher than a plurality of operating voltages input through the second global word lines GWLs_B and the second global selection lines GDSL_B and GSSL_B.

During the read operation, when the first memory block 141 is selected between the first memory block 141 and the second memory block 142, in response to the selection control voltage CS_A output from the control logic 150, the first A switch circuit 121 can send to the first sub-global word line GWLs_A1 Send multiple operating voltages input through the first global word line GWLs_A. In addition, the first switching circuit 121 may transmit a plurality of operating voltages input through the first global selection lines GDSL_A and GSSL_A to the first sub-global selection lines GDSL_A1 and GSSL_A1. In response to deselecting the control voltage CS_B, the second switching circuit 122 assigned to the unselected second memory block 142 may enable the second sub-global word lines GWLs_B1 and the second sub-global selection lines GDSL_B1 and GSSL_B1 to float. That is, during the read operation, the switch circuit 120 may enable sub-global word lines and sub-global selection lines assigned to unselected memory blocks to float.

The pass circuit group 130 may include a first pass circuit 131 and a second pass circuit 132.

In response to the block pass signal BLKWL output from the block decoder 160, the first pass circuit 131 may electrically couple the first sub-global word line GWLs_A1 to the first word line WLs_A of the first memory block 141, and may The first sub-global selection lines GDSL_A1 and GSSL_A1 are electrically coupled to the first selection lines DSL_A and SSL_A of the first memory block 141. Here, the selection lines DSL_A and SSL_A may be local selection lines.

In response to the block pass signal BLKWL output from the block decoder 160, the second pass circuit 132 may electrically couple the second sub-global word line GWLs_B1 to the second word line WLs_B of the second memory block 142, and may The second sub-global selection lines GDSL_B1 and GSSL_B1 are electrically coupled to the second selection lines DSL_B and SSL_B of the second memory block 142.

The first pass circuit 131 and the second pass circuit 132 may share the signal line carrying the block pass signal BLKWL provided from the block decoder 160. Therefore, in response to the same block pass signal BLKWL, the first sub-global word line GWLs_A1 and the first word line WLs_A of the first memory block 141 may be electrically coupled to each other, and the first sub-global selection line GDSL_A1 and GSSL_A1 and the first selection lines DSL_A and SSL_A of the first memory block 141 may be electrically coupled to each other, and the second sub-global word line GWLs_B1 and the second word line WLs_B of the second memory block 142 may be electrically coupled to each other, and The second sub-global selection lines GDSL_B1 and GSSL_B1 and the second selection lines DSL_B and SSL_B of the second memory block 142 may be electrically coupled to each other. The first pass circuit 131 and the second pass circuit 132 may include a plurality of high voltage transistors that are turned on or off in response to the block pass signal BLKWL. Although the first pass circuit 131 and the second pass circuit 132 are coupled to the same signal line that provides the block pass signal BLKWL, the block pass signal can be turned on by turning on only one of the first switch circuit and the second switch circuit BLKWL is applied to only one of the first memory block 141 and the second memory block 142.

The memory unit 140 may include a first memory block 141 and a second memory block 142. Each of the first memory block 141 and the second memory block 142 may include a plurality of memory cells. For example, the plurality of memory cells may be non-volatile memory cells. Among the plurality of memory cells, the memory cells coupled to the same word line may be defined as one page. Each of the first memory block 141 and the second memory block 142 may include a plurality of cell strings. The first memory block 141 and the second memory block 142 may share a common source line and bit line.

The control logic 150 may control the voltage generating circuit 110 and the switching circuit 120 in response to a command CMD provided from an external device. For example, if a command related to a read operation is input, the control logic 150 may output an operation signal to the voltage generation circuit 110 in such a manner that various operation voltages are generated, and may output the selection control voltage CS_A and the deselection control voltage CS_B to use The first switch circuit 121 and the second switch circuit 122 for controlling the selected memory block and the unselected memory block assigned to the memory unit 140.

When the memory block corresponding to the column address ADDR is the first memory block 141 or the second memory block 142, the block decoder 160 may generate a block pass signal BLKWL with a high voltage level. The column address ADDR can be output from the control logic 150.

FIG. 2 is a flowchart illustrating operation according to the embodiment of the semiconductor memory device illustrated in FIG. 1.

The operation of the semiconductor memory device according to the embodiment of the present disclosure will be described with reference to FIGS. 1 and 2.

Here, it is assumed that the first memory block 141 is a selected memory block, which is a memory block selected between the first memory block 141 and the second memory block 142.

1) Enter the read command (S110)

When a read command CMD related to a read operation is input from an external device, the control logic 150 may generate a control signal and a control voltage for controlling the voltage generating circuit 110 and the switching circuit 120.

2) Generate operating voltage (S120)

The voltage generating circuit 110 may generate operating voltages having various levels for read operations in response to control signals provided from the control logic 150. For example, the operating voltage may include a read voltage, a pass voltage, a selection transistor control voltage, a compensation voltage, and the like. The voltage generating circuit 110 may provide the operating voltage to the first global word line GWLs_A and the first global selection lines GDSL_A and GSSL_A. In addition, the voltage generating circuit 110 may provide a voltage of zero volts to the second global word line GWLs_B and the second global selection lines GDSL_B and GSSL_B.

3) Apply a deselection control voltage to the switch circuit assigned to the unselected memory block (S130)

The deselection control voltage CS_B may be applied to the second switching circuit 122 assigned to the unselected second memory block 142. The high voltage selection control voltage CS_A output from the control logic 150 may be applied to the first switch circuit 121 assigned to the selected first memory block 141. The deselection control voltage CS_B can be set to zero volts.

4) Floating the global word line assigned to the unselected memory block (S140)

In response to the deselected control voltage CS_B output from the control logic 150, the second switch circuit 122 assigned to the unselected second memory block 142 can cause the second sub-circuit assigned to the unselected second memory block 142 The global word line GWLs_B1 and the second sub-global selection lines GDSL_B1 and GSSL_B1 float. For example, the first switching circuit 121 may transmit the first sub-global word line GWLs_A1 and the first sub-global selection lines GDSL_A1 and GSSL_A1 in response to the high-voltage selection control voltage CS_A output from the control logic 150 through the first global word line GWLs_A And multiple operating voltages input by the first global selection lines GDSL_A and GSSL_A. The second switching circuit 122 may be turned off in response to the deselection control voltage CS_B of zero volts, and may enable the second sub-global word lines GWLs_B1 and the second sub-global selection lines GDSL_B1 and GSSL_B1 to float.

5) Apply an operating voltage to the selected memory block (S150)

During a read operation, a voltage of zero volts can be applied to the common source line shared by the first memory block 141 and the second memory block 142, and the first memory block 141 and the second The bit lines shared by the memory block 142 are precharged.

In the case where the first memory block 141 is the selected memory block and the second memory block 142 is the unselected memory block, the block decoder 160 may generate The block of high voltage level passes the signal BLKWL.

In response to the block pass signal BLKWL, the first pass circuit 131 may electrically couple the first sub-global word lines GWLs_A1 and the first word line WLs_A to each other, and may couple the first sub-global selection lines GDSL_A1 and GSSL_A1 with the first selection line DSL_A And SSL_A are electrically coupled to each other.

In response to the block pass signal BLKWL, the second pass circuit 132 may electrically couple the second sub-global word line GWLs_B1 and the second word line WLs_B to each other, and may couple the second sub-global selection lines GDSL_B1 and GSSL_B1 with the second selection line DSL_B And SSL_B are electrically coupled to each other.

The read voltage and the pass voltage may be applied to the first word line WLs_A of the selected first memory block 141, and the selection transistor control voltage may be applied to the first selection lines DSL_A and SSL_A. All of the second word line WLs_B and the second selection lines DSL_B and SSL_B of the unselected second memory block 142 may be floated.

The potential levels of the floating second word line WLs_B and the floating second selection lines DSL_B and SSL_B can be increased by capacitive coupling with adjacent wiring lines and terminals. In the case where the potential levels of the second word line WLs_B and the second selection lines DSL_B and SSL_B exceed zero volts through the capacitive coupling phenomenon, it is possible to suppress the possibility of leakage in the channel of the drain selection transistor and the source selection transistor The generation of hot carriers (eg, hot holes) formed by the generation of electric current (eg, GIDL). Therefore, the probability of injecting and capturing hot carriers (eg, hot holes) in the channels of the unselected memory block can be reduced.

Table 1 below shows the potential levels of the word lines and selection lines of the selected memory block and the unselected memory block among the multiple memory blocks assigned to the pass circuit sharing a block pass signal Implementation.

As shown in Table 1, read voltages and pass voltages can be applied to the word lines of selected memory blocks, which are memory blocks selected from a plurality of memory blocks. Here, the selected memory block may be coupled to a pass circuit sharing a pass signal of a specific block. Therefore, the block pass signal can be applied not only to the selected memory block but also to the unselected memory block. The selection transistor control voltages Vssl and Vdsl of a positive voltage may be applied to the selection line of the selected memory block. As described above, all word lines and selection lines of unselected memory blocks can be floated. Therefore, during the read operation of the selected memory block, in the unselected memory block, hot carriers (eg, thermoelectric) are formed in the lower channels of the drain-select transistor and the source-select transistor. Hole) can be reduced.

FIG. 3 is a flowchart illustrating operations according to the embodiment of the semiconductor memory device illustrated in FIG. 1.

The operation of the semiconductor memory device according to the embodiment will be described with reference to FIGS. 1 and 3.

Here, it is assumed that the first memory block 141 is selected between the first memory block 141 and the second memory block 142.

1) Enter the read command (S210)

When a read command CMD related to a read operation is input from an external device, The control logic 150 may generate control signals and control voltages for controlling the voltage generating circuit 110 and the switching circuit 120.

2) Generate operating voltage (S220)

The voltage generating circuit 110 may generate operating voltages having various levels for read operations in response to control signals provided from the control logic 150. For example, the operating voltage may include a read voltage, a pass voltage, a selection transistor control voltage, a compensation voltage, and the like. The voltage generation circuit 110 may supply voltages such as read voltage, pass voltage, and selection transistor control voltage to the first global word line GWLs_A and the first global selection lines GDSL_A and GSSL_A. In addition, the voltage generating circuit 110 may provide a compensation voltage to the second global word line GWLs_B and the second global selection lines GDSL_B and GSSL_B.

3) Apply a compensation voltage to the global word line and the global selection line corresponding to the unselected memory block (S230)

The voltage generating circuit 110 may apply a compensation voltage to the second global word line GWLs_B corresponding to the unselected memory block 142 and the global selection lines GDSL_B and GSSL_B. For example, the voltage generating circuit 110 applies an operating voltage to the first global word line GWLs_A corresponding to the selected memory block 141 and the first global selection lines GDSL_A and GSSL_A. The voltage generating circuit 110 may apply a compensation voltage to the second global word line GWLs_B and the second global selection lines GDSL_B and GSSL_B corresponding to the unselected memory block 142. The compensation voltage applied to the second global word line GWLs_B may be a positive voltage, and may be set in a range between zero volts and four volts. The compensation voltage applied to the second global selection lines GDSL_B and GSSL_B may be a voltage of zero volts.

4) Apply deselection to the switch circuit corresponding to the unselected memory block Control voltage (S240)

The deselection control voltage CS_B may be applied to the second switch circuit 122 corresponding to the unselected second memory block 142. The high voltage selection control voltage CS_A output from the control logic 150 may be applied to the first switch circuit 121 corresponding to the selected first memory block 141. The deselection control voltage CS_B may be set to have a higher level than the compensation voltage. For example, the deselection control voltage CS_B may be set to four volts.

5) Apply an operating voltage to the selected memory block (S250)

During a read operation, a voltage of zero volts can be applied to the common source line shared by the first memory block 141 and the second memory block 142, and the first memory block 141 and the second The bit lines shared by the memory block 142 are precharged.

In the case where the first memory block 141 is the selected memory block and the second memory block 142 is the unselected memory block, the block decoder 160 may generate The block of high voltage level passes the signal BLKWL.

In response to the block pass signal BLKWL, the first pass circuit 131 can electrically couple the first sub-global word line GWLs_A1 to the first word line WLs_A of the first memory block 141, and the first sub-global selection line GDSL_A1 and GSSL_A1 is electrically coupled to the selection lines DSL_A and SSL_A of the first memory block 141.

In response to the block pass signal BLKWL, the second pass circuit 132 can electrically couple the second sub-global word line GWLs_B1 to the second word line WLs_B of the second memory block 142, and can connect the second sub-global select line GDSL_B1 and GSSL_B1 is electrically coupled to the second selection lines DSL_B and SSL_B of the second memory block 142.

The first word line WLs_A of the selected first memory block 141 can be applied The read voltage and the pass voltage are added, and the selection transistor control voltage can be applied to the first selection lines DSL_A and SSL_A. A compensation voltage in a range from zero volts to four volts may be applied to the second word line WLs_B of the unselected second memory block 142, and a compensation voltage of zero volts may be applied to the second selection lines DSL_B and SSL_B.

A zero-volt compensation voltage can be applied to the second selection lines DSL_B and SSL_B, so that hot carriers (e.g., due to the generation of leakage current (e.g., GIDL) in the lower channel of the drain-select transistor and the source-select transistor , Thermal holes) can be reduced. In addition, because the compensation voltage in the range from zero volts to four volts is applied to the second word line WLs_B, the probability of hot carriers (eg, hot holes) being injected and trapped in the channel of the memory block can be reduced .

Table 2 below shows the potential levels of the word lines and selection lines of the selected memory block and the unselected memory block among the plurality of memory blocks corresponding to the pass circuit sharing a block pass signal .

As shown in Table 2, the read voltage and the pass voltage can be applied to the word line of the memory block selected from the plurality of memory blocks corresponding to the pass circuit sharing the pass signal of one block, and selected The selection transistor control voltage Vssl and Vdsl which apply a positive voltage to the line. As described above, the word lines of the unselected memory blocks can be applied The compensation voltage of the level within the range of 0, and a zero-volt compensation voltage can be applied to the selection line. Therefore, during the read operation of the selected memory block, in the unselected memory block, hot carriers (eg, thermoelectric) are formed in the lower channels of the drain-select transistor and the source-select transistor. The probability of a hole) can be reduced, and the probability of hot carriers (eg, thermoelectric holes) injected and captured in the channel of the memory block can be reduced. The leakage current flowing through the cell string in the second memory block 242 can be reduced.

4 is a diagram illustrating a semiconductor memory device according to an embodiment of the present disclosure.

Referring to FIG. 4, the semiconductor memory device 200 may include a voltage generating circuit 210, a switching circuit 220, a pass circuit group 230, a memory unit 240, a control logic 250, a block decoder 260 and a selection line control circuit 270.

The voltage generation circuit 210 may generate operation voltages having various levels in response to operation signals output from the control logic 250 during a read operation, and may output these operation voltages to the global word line and the global selection line. For example, the operating voltage may include a read voltage, a pass voltage, a selection transistor control voltage, a compensation voltage, and the like. The voltage generating circuit 210 may transmit operating voltages having various levels to the first global word line GWLs_A, the first global selection lines GDSL_A and GSSL_A, the second global word line GWLs_B, and the second global selection lines GDSL_B and GSSL_B. For example, in the case where the first memory block 241 is selected between the first memory block 241 and the second memory block 242 of the memory unit 240, the voltage generating circuit 210 may be directed to the first memory area The first global word line GWLs_A and the first global selection lines GDSL_A and GSSL_A corresponding to the block 241 send operating voltages, and can select the second global word line GWLs_B and the second global selection assigned to the unselected second memory block 242 Line GDSL_B and GSSL_B Send a voltage of zero volts.

The switch circuit 220 may include a first switch circuit 221 and a second switch circuit 222.

The first switching circuit 221 may couple the first global word lines GWLs_A to the first sub-global word lines GWLs_A1, and may couple the first global field selection lines GDSL_A and GSSL_A to the first sub-global word selection lines GDSL_A1 and GSSL_A1. For example, the first switching circuit 221 may include a high-voltage transistor that is turned on or off in response to the selection control voltage CS_A. In response to the selection control voltage CS_A output from the control logic 250, the first switching circuit 221 may send a plurality of operating voltages input through the first global word line GWLs_A to the first sub-global word line GWLs_A1, or may make the first sub-global word Line GWLs_A1 floats. In response to the selection control voltage CS_A output from the control logic 250, the first switching circuit 221 may send a plurality of operating voltages input through the first global selection lines GDSL_A and GSSL_A to the first sub-global selection lines GDSL_A1 and GSSL_B1, or may make the first A sub-global selection line GDSL_A1 and GSSL_A1 are floating. The selection control voltage CS_A may be a voltage of zero volts or a high voltage higher than a plurality of operating voltages input through the first global word line GWLs_A and the first global selection lines GDSL_A and GSSL_A.

The second switching circuit 222 may couple the second global word line GWLs_B to the second sub-global word line GWLs_B1, and may couple the second global field selection lines GDSL_B and GSSL_B to the second sub-global word selection lines GDSL_B1 and GSSL_B1. For example, the second switching circuit 222 may include a high-voltage transistor that is turned on or off in response to the deselection control voltage CS_A. In response to the deselected control voltage CS_B output from the control logic 250, the second switching circuit 222 may send a plurality of input signals through the second global word line GWLs_B to the second sub-global word line GWLs_B1 The operating voltage may alternatively float the second sub-global word line GWLs_B1. In response to the deselection control voltage CS_B output from the control logic 250, the second switch circuit 222 may send a plurality of operating voltages input through the second global selection lines GDSL_B and GSSL_B to the second sub-global selection lines GDSL_B1 and GSSL_B1, or may make The second sub-global selection lines GDSL_B1 and GSSL_B1 float. The deselection control voltage CS_B may be a voltage of zero volts or a high voltage higher than a plurality of operating voltages input through the second global word line GWLs_B and the second global selection lines GDSL_B and GSSL_B.

During the read operation, when the first memory block 241 is selected between the first memory block 241 and the second memory block 242, in response to the selection control voltage CS_A output from the control logic 250, the first A switch circuit 221 sends a plurality of operating voltages input through the first global word line GWLs_A to the first sub-global word line GWLs_A, and can send input through the first global selection lines GDSL_A and GSSL_A to the first sub-global selection lines GDSL_A1 and GSSL_A1 Multiple operating voltages. The second switch circuit 222 corresponding to the unselected second memory block 242 floats the second sub-global word lines GWLs_B1 and the second sub-global selection lines GDSL_B1 and GSSL_B1 in response to the deselection control voltage CS_B. That is, the switch circuit 220 floats the sub-global word line and the sub-global selection line corresponding to the unselected memory block.

The pass circuit group 230 may include a first pass circuit 231 and a second pass circuit 232.

In response to the block pass signal BLKWL output from the block decoder 260, the first pass circuit 231 may electrically couple the first sub-global word line GWLs_A1 to the first word line WLs_A of the first memory block 241, and may The first sub-global selection lines GDSL_A1 and GSSL_A1 are electrically coupled to the first selection lines DSL_A and SSL_A of the first memory block 241.

In response to the block pass signal BLKWL output from the block decoder 260, the second pass circuit 232 may electrically couple the second sub-global word line GWLs_B1 to the second word line WLs_B of the second memory block 142, and may The second sub-global selection lines GDSL_B1 and GSSL_B1 are electrically coupled to the second selection lines DSL_B and SSL_B of the second memory block 242.

The first pass circuit 231 and the second pass circuit 232 may share the signal line carrying the block pass signal BLKWL provided from the block decoder 260. Therefore, in response to the same block pass signal BLKWL, the first sub-global word line GWLs_A1 may be electrically coupled to the first word line WLs_A of the first memory block 241, and the first sub-global selection lines GDSL_A1 and GSSL_A1 and the first The first selection lines DSL_A and SSL_A of the memory block 241 may be electrically coupled to each other, and the second sub-global word line GWLs_B1 may be electrically coupled to the second word line WLs_B of the second memory block 242, and the second sub-global selection The lines GDSL_B1 and GSSL_B1 and the second selection lines DSL_B and SSL_B of the second memory block 242 may be electrically coupled to each other. The first pass circuit 231 and the second pass circuit 232 may include a plurality of high voltage transistors that are turned on or off in response to the block pass signal BLKWL. Although the first pass circuit 231 and the second pass circuit 232 are coupled to the same signal line that provides the block pass signal BLKWL, it is possible to pass the block pass signal by turning on only one of the first switch circuit and the second switch circuit BLKWL is applied to only one of the first memory block 241 and the second memory block 242.

The memory unit 240 may include a first memory block 241 and a second memory block 242. Each of the first memory block 241 and the second memory block 242 may include a plurality of memory cells. For example, the plurality of memory cells may be non-volatile memory cells. Among the plurality of memory cells, the memory cells coupled to the same word line may be defined as one page. Each of the first memory block 241 and the second memory block 242 may include a plurality of Unit string. The first memory block 241 and the second memory block 242 may share a common source line and bit line.

The control logic 250 may control the voltage generating circuit 210 and the switching circuit 220 in response to a command CMD provided from an external device. For example, if a command related to a read operation is input, the control logic 250 may control the voltage generating circuit 210 in such a manner that various operating voltages are generated, and may output the selection control voltage CS_A and the deselection control voltage CS_B for control The first switch circuit 221 and the second switch circuit 222 corresponding to the selected memory block and the unselected memory block of the memory unit 240.

When the memory block corresponding to the column address ADDR is the first memory block 241 or the second memory block 24, the block decoder 260 may generate a block pass signal BLKWL with a high voltage level. The column address ADDR can be output from the control logic 250.

The selection line control circuit 270 may include a first source selection line controller 271, a first drain selection line controller 272, a second source selection line controller 273, and a second drain selection line controller 274.

The first source selection line controller 271 may be coupled to the first memory block 241, and may control the potential level of the first source selection line SSL_A coupled to the first memory block 241. For example, during the read operation, if the first memory block 241 is an unselected memory block, the first source selection line controller 271 may select the first source of the first memory block 241 The line SSL_A discharges, and thus adjusts the potential level of the first source selection line SSL_A to zero volts.

The first drain selection line controller 272 may be coupled to the first memory block 241, and may control the first drain selection line DSL_A coupled to the first memory block 241 Potential level. For example, during the read operation, if the first memory block 241 is an unselected memory block, the first drain selection line controller 272 may select the first drain of the first memory block 241 The line DSL_A discharges, and therefore the potential level of the first drain selection line DSL_A is adjusted to zero volts.

The second source selection line controller 273 may be coupled to the second memory block 242, and may control the potential level of the second source selection line SSL_B coupled to the second memory block 242. For example, during the read operation, if the second memory block 242 is an unselected memory block, the second source selection line controller 273 may select the second source of the second memory block 242 The line SSL_B discharges, and thus the potential level of the second source selection line SSL_B is adjusted to zero volts.

The second drain select line controller 274 may be coupled to the second memory block 242, and may control the potential level of the second drain select line DSL_B coupled to the second memory block 242. For example, during the read operation, if the second memory block 242 is an unselected memory block, the second drain selection line controller 274 may select the second drain of the second memory block 242 The line DSL_B discharges, and thus the potential level of the second drain selection line DSL_B is adjusted to zero volts.

The selection line control circuit 270 can be controlled by the control logic 250.

FIG. 5 is a flowchart illustrating the operation of the semiconductor memory device illustrated in FIG. 4.

The operation of the semiconductor memory device according to the embodiment will be described with reference to FIGS. 4 and 5.

Here, it is assumed that the first memory block 241 is the selected memory block, which is A memory block selected between the first memory block 241 and the second memory block 242.

1) Enter the read command (S310)

When a read command CMD related to a read operation is input from an external device, the control logic 250 may generate a control signal and a control voltage for controlling the voltage generating circuit 210 and the switching circuit 220.

2) Generate operating voltage (S320)

The voltage generating circuit 210 may generate operating voltages having various levels for reading operations in response to control signals provided from the control logic 250. For example, the operating voltage may include a read voltage, a pass voltage, a selection transistor control voltage, a compensation voltage, and the like. The voltage generating circuit 210 may provide the operating voltage to the first global word line GWLs_A and the first global selection lines GDSL_A and GSSL_A. In addition, the voltage generating circuit 210 may provide a voltage of zero volts to the second global word line GWLs_B and the second global selection lines GDSL_B and GSSL_B.

3) Apply a deselection control voltage to the switch circuit assigned to the unselected memory block (S330)

The deselection control voltage CS_B is applied to the second switching circuit 222 assigned to the unselected second memory block 242. The high voltage selection control voltage CS_A output from the control logic 250 may be applied to the first switching circuit 221 assigned to the selected first memory block 241. The deselection control voltage CS_B can be set to zero volts.

4) Floating the global word line corresponding to the unselected memory block (S340)

In response to the deselected control voltage CS_B output from the control logic 250, the second switch circuit 222 corresponding to the unselected second memory block 242 can cause the second sub-circuit assigned to the unselected second memory block 242 Global word line GWLs_B1 and the second sub-global selection line GDSL_B1 and GSSL_B1 are floating. For example, the first switching circuit 221 may send the first sub-global word line GWLs_A1 and the first sub-global selection lines GDSL_A1 and GSSL_A1 in response to the high-voltage selection control voltage CS_A output from the control logic 250 through the first global word line GWLs_A And multiple operating voltages input by the first global selection lines GDSL_A and GSSL_A. The second switching circuit 122 may be turned off in response to the deselection control voltage CS_B of zero volts, and may enable the second sub-global word lines GWLs_B1 and the second sub-global selection lines GDSL_B1 and GSSL_B1 to float.

5) Apply a compensation voltage to the selection line of the unselected memory block (S350)

The second source selection line controller 273 coupled to the unselected second memory block 242 may apply a compensation voltage to the second source selection line SSL_B of the second memory block 242. The second drain selection line controller 274 may apply a compensation voltage to the second drain selection line DSL_B of the second memory block 242. The compensation voltage can be at zero volts.

6) Apply operating voltage to the selected memory block (S360)

During the read operation, a voltage of zero volts can be applied to the common source line shared by the first memory block 241 and the second memory block 242, and the first memory block 241 and the second The bit lines shared by the memory block 242 are precharged.

In the case where the first memory block 241 is a selected memory block and the second memory block 242 is an unselected memory block, the block decoder 260 may respond to the row address ADDR The block of high voltage level passes the signal BLKWL.

In response to the block pass signal BLKWL, the first pass circuit 231 can electrically couple the first sub-global word line GWLs_A1 to the first word line WLs_A of the first memory block 241, and the first sub-global selection line GDSL_A1 and GSSL_A1 is electrically coupled to the first memory The selection lines DSL_A and SSL_A of block 241.

In response to the block pass signal BLKWL, the second pass circuit 232 can electrically couple the second sub-global word line GWLs_B1 to the second word line WLs_B of the second memory block 242, and can connect the second sub-global word selection line GDSL_B1 and GSSL_B1 is electrically coupled to the second selection lines DSL_B and SSL_B of the second memory block 242.

A read voltage and a pass voltage may be applied to the first word line WLs_A of the selected first memory block 241, and a selection transistor control voltage may be applied to the first selection lines DSL_A and SSL_A. The second word line WLs_B of the unselected second memory block 242 may float.

The potential level of the floating second word line WLs_B can be increased by capacitive coupling with adjacent wiring lines and terminals. When the potential level of the second word line WLs_B exceeds zero volts through capacitive coupling, the formation of leakage current (eg, GIDL) in the lower channel of the drain-select transistor and the source-select transistor can be suppressed Generation of hot carriers (eg, hot holes). Therefore, the probability of injecting and capturing hot carriers (eg, hot holes) in the channels of the unselected memory block can be reduced. In addition, the selection line control circuit 270 can apply a voltage of zero volts to the second drain selection line DSL_B and the source selection line SSL_B of the second memory block 242, so that the drain of the second memory block 242 can be made Select transistor and source select transistor cutoff. Therefore, the leakage current flowing through the cell string in the second memory block 242 can be reduced.

Table 3 below shows the potential levels of the word lines and selection lines of the selected memory block and the unselected memory block among the plurality of memory blocks assigned to the pass circuit sharing a block pass signal .

As shown in Table 3, read voltages and pass voltages can be applied to the word lines of selected memory blocks, which are memory blocks selected from a plurality of memory blocks. Here, the selected memory block may be coupled to a pass circuit sharing a pass signal of a specific block. Therefore, the block pass signal can be applied not only to the selected memory block but also to the unselected memory block. The selection transistor control voltages Vssl and Vdsl of a positive voltage may be applied to the selection line of the selected memory block. As described above, the word lines of unselected memory blocks can be floated, and a voltage of zero volts can be applied to the selected lines. Therefore, during the read operation of the selected memory block, the probability of forming hot carriers (eg, hot holes) in the lower channel of the source selection transistor in the unselected memory block can be reduced And, the selective transistor can be turned off, so that the leakage current can be reduced.

FIG. 6 is a diagram illustrating a semiconductor memory device according to an embodiment of the present disclosure.

6, the semiconductor memory device 300 may include a voltage generating circuit 310, a pass circuit group 320, a selection line switch circuit 320, a memory unit 340, a control logic 350, and a block decoder 360.

The voltage generation circuit 310 may generate operation voltages having various levels in response to operation signals output from the control logic 350 during a read operation, and may operate these operations The voltage is output to the global word line and the global select line. For example, the operating voltage may include a read voltage, a pass voltage, a selection transistor control voltage, a compensation voltage, and the like. The voltage generating circuit 310 may transmit operating voltages having various levels to the first global word line GWLs_A, the first global selection lines GDSL_A and GSSL_A, the second global word line GWLs_B, and the second global selection lines GDSL_B and GSSL_B. For example, in the case where the first memory block 341 is selected between the first memory block 341 and the second memory block 342 of the memory unit 340, the voltage generating circuit 310 may assign the first memory block The first global word line GWLs_A and the first global selection lines GDSL_A and GSSL_A of the block 341 send operating voltages, and can select the second global word line GWLs_B and the second global selection assigned to the unselected second memory block 342 The lines GDSL_B and GSSL_B send a voltage of zero volts or a compensation voltage lower than the operating voltage. The compensation voltage can be set in a range from zero volts to four volts.

The pass circuit group 320 may include a first pass circuit 321 and a second pass circuit 322.

In response to the block pass signal BLKWL output from the block decoder 360, the first pass circuit 321 may electrically couple the first global word line GWLs_A to the first word line WLs_A of the first memory block 341, and may A global selection line GDSL_A and GSSL_A is electrically coupled to the first sub-selection lines DSL_A and SSL_A corresponding to the first memory block 341.

In response to the block pass signal BLKWL output from the block decoder 360, the second pass circuit 322 may electrically couple the second global word line GWLs_B to the second word line WLs_B of the second memory block 342, and may The two global selection lines GDSL_B and GSSL_B are electrically coupled to the second sub-selection lines DSL_B and SSL_B assigned to the second memory block 342.

The first pass circuit 321 and the second pass circuit 322 share bearer decoding from the block The block provided by the device 360 passes through the signal line of the signal BLKWL. Therefore, in response to the same block pass signal BLKWL, the first global word line GWLs_A and the first word line WLs_A of the first memory block 341 may be electrically coupled to each other, and the first global selection lines GDSL_A and GSSL_A are assigned to the first The first sub-select lines DSL_A and SSL_A of a memory block 341 may be electrically coupled to each other, and the second global word line GWLs_B and the second word line WLs_B of the second memory block 342 may be electrically coupled to each other, and the second global The selection lines GDSL_B and GSSL_B and the second sub-selection lines DSL_B and SSL_B assigned to the second memory block 342 may be electrically coupled to each other. The first pass circuit 321 and the second pass circuit 322 may include a plurality of high voltage transistors that are turned on or off in response to the block pass signal BLKWL. Although the first pass circuit 321 and the second pass circuit 322 are coupled to the same signal line that provides the block pass signal BLKWL, it is possible to pass the block pass signal by turning on only one of the first switch circuit and the second switch circuit BLKWL is applied to only one of the first memory block 341 and the second memory block 342.

The selection line switch circuit 330 may include a first drain selection line switch circuit 331, a first source selection line switch circuit 332, a second drain selection line switch circuit 333, and a second source selection line switch circuit 334.

The first drain select line switch circuit 331 may be coupled between the first sub-drain select line DSL_A and the first drain select line DSL_A1 of the first memory block 341, and may control the first drain select line DSL_A1 Potential level. For example, in the case where the first memory block 341 is selected between the first memory block 341 and the second memory block 342 of the memory unit 340, the first drain select line switch circuit 331 may respond to The drain selection control voltage CS_DSL_A output from the control logic 350 transmits the operation voltage input through the first sub-drain selection line DSL_A to the first drain selection line DSL_A1 of the first memory block.

The first source selection line switch circuit 332 may be coupled between the first sub-source selection line SSL_A and the first source selection line SSL_A1 of the first memory block 341, and may control the first source selection line SSL_A1 Potential level. For example, in the case where the first memory block 341 is selected between the first memory block 341 and the second memory block 342 of the memory unit 340, the first source selection line switch circuit 332 may respond to The source selection control voltage CS_SSL_A output from the control logic 350 transmits the operation voltage input through the first sub-source selection line SSL_A to the first source selection line SSL_A1 of the first memory block.

The second drain select line switch circuit 333 may be coupled between the second sub-drain select line DSL_B and the second drain select line DSL_B1 of the second memory block 342, and may control the second drain select line DSL_B1 Potential level. For example, in the case where the second memory block 342 is not selected, the second drain select line switch circuit 333 may cause the second drain select line DSL_B1 in response to the drain deselection control voltage CS_DSL_B output from the control logic 350 Can float.

The second source selection line switch circuit 334 may be coupled between the second sub-source selection line SSL_B and the second source selection line SSL_B1 of the second memory block 342, and may control the second source selection line SSL_B1 Potential level. For example, in the case where the second memory block 342 is selected between the first memory block 341 and the second memory block 342 of the memory unit 340, the second source selection line switch circuit 334 may respond to The source output from the control logic 350 deselects the control voltage CS_SSL_B and sends the operation voltage input through the second sub-source selection line SSL_B to the second source selection line SSL_B1 of the second memory block, or causes the second source Select line SSL_B1 is floating.

That is, the selection line switch circuit 330 can selectively make the unselected The drain selection line and the source selection line of the memory block float.

The selection line control circuit 330 may be controlled by the control logic 350.

The memory unit 340 may include a first memory block 341 and a second memory block 342. Each of the first memory block 341 and the second memory block 342 may include a plurality of memory cells. For example, the plurality of memory cells may be non-volatile memory cells. Among the plurality of memory cells, the memory cells coupled to the same word line may be defined as one page. Each of the first memory block 341 and the second memory block 342 may include a plurality of cell strings. The first memory block 341 and the second memory block 342 may share a common source line and bit line.

The control logic 350 may control the voltage generation circuit 310 and the selection line switch circuit 330 in response to a command CMD input from an external device. For example, when a read command related to a read operation is input, the control logic 350 may control the voltage generating circuit 310 to generate various operating voltages, and may output the drain selection control voltage CS_DSL_A, the source selection control voltage CS_SSL_A, the drain The deselect control voltage CS_DSL_B and the source deselect control voltage CS_SSL_B to control the first drain select line switch circuit 331, the first of the selected memory block and the unselected memory block assigned to the memory unit 340, the first The source selection line switch circuit 332, the second drain selection line switch circuit 333, and the second source selection line switch circuit 334.

When the memory block corresponding to the column address ADDR is the first memory block 341 or the second memory block 342, the block decoder 360 can generate a block pass signal BLKWL with a high voltage level and output The block passes the signal BLKWL. The column address ADDR can be output from the control logic 350.

The first group GRA may include a first pass circuit 321 and a first drain selection line The switch circuit 331, the first source selection line switch circuit 332, and the first memory block 341.

The second group of GRBs may include a second pass circuit 322, a second drain select line switch circuit 333, a second source select line switch circuit 334, and a second memory block 342.

FIG. 7 is a diagram illustrating in detail the second group of the semiconductor memory device illustrated in FIG. 6.

The first group GRA and the second group GRB of FIG. 6 may have the same structure; therefore, for convenience, only the second group GRB will be described in detail, and it is assumed that the second group GRB corresponds to an unselected memory.

The second group of GRBs may include a second pass circuit 322, a second drain select line switch circuit 333, a second source select line switch circuit 334, and a second memory block 342.

The second pass circuit 322 may include a plurality of high voltage transistors that electrically couple the second global word line GWLs_B to the second in response to the block pass signal BLKW output from the block decoder 360 Sub word line WLs_B1, and electrically couples the second global selection lines GDSL_B and GSSL_B to the second sub selection lines DSL_B and SSL_B.

The second drain selection line switching circuit 333 may include a first transistor Tr1. The first transistor Tr1 may be coupled between the second sub-drain selection line DSL_B and the second drain selection line DSL_B1 of the second memory block 342, and may respond to the drain deselection control voltage CS_DSL_B so that the second The drain selection line DSL_B1 can float.

The second source selection line switching circuit 334 may include a second transistor Tr2.

The second transistor Tr2 may be coupled between the second sub-source selection line SSL_B and the second source selection line SSL_B1 of the second memory block 342, and may respond to the source deselection control voltage CS_SSL_B Select the gate of the transistor SST applied through the second The compensation voltage sent by the source selection line SSL_B1 may enable the second source selection line SSL_B to float.

For example, in the case where the second memory block 342 is an unselected memory block during the read operation, the first deselection control voltage CS_DSL_B and the source deselection control voltage CS_SSL_B can be used to make the first The transistor Tr1 and the second transistor Tr2 are turned off. As a result, the second drain selection line DSL_B1 and the second source selection line SSL_B1 may float. The drain deselection control voltage CS_DSL_B and the source deselection control voltage CS_SSL_B may be zero volts.

In another example, when the second memory block 342 is an unselected memory block during the read operation, the first transistor Tr1 may be turned off in response to the drain deselection control voltage CS_DSL_B, and therefore the The second selection line DSL_B1 can be floated. The second transistor Tr2 can be turned on in response to the source deselection control voltage CS_SSL_B, and a compensation voltage of 0V transmitted through the second source selection line SSL_B can be applied to the gate of the source selection transistor SST to make the source select Transistor SST is off. The drain deselection control voltage CS_DSL_B may be a voltage of zero volts, and the source deselection control voltage CS_SSL_B may be a voltage in a range from zero volts to four volts.

The second memory block 342 may include a plurality of cell strings ST1 to STm respectively coupled between the common source line CsL and the plurality of bit lines BL1 to BLm.

The plurality of cell strings ST1 to STm may have the same structure as each other. The first cell string ST1 may include a source selection transistor SST, a plurality of memory cells MC0 to MCn, and a drain selection transistor DST coupled in series between the common source line CSL and the bit line BL1. The gates of the plurality of memory cells MC0 to MCn may be coupled to corresponding second word lines WLs_B.

FIG. 8 is a flowchart illustrating the operation of the semiconductor memory device illustrated in FIG. 6.

The operation of the semiconductor memory device according to the embodiment will be described with reference to FIGS. 6, 7 and 8.

Here, it is assumed that the first memory block 341 is selected between the first memory block 341 and the second memory block 342 for the read operation.

1) Enter the read command (S410)

When a read command CMD related to a read operation is input from an external device, the control logic 350 may generate a control signal and a control voltage for controlling the voltage generating circuit 310 and the switching circuit 330.

2) Generate operating voltage (S420)

The voltage generating circuit 310 may generate operating voltages having various levels for read operations in response to control signals provided from the control logic 350. For example, the operating voltage may include a read voltage, a pass voltage, a selection transistor control voltage, a compensation voltage, and the like. The voltage generating circuit 310 may provide the read voltage, the pass voltage, the selection transistor control voltage, etc. to the first global word line GWLs_A and the first global selection lines GDSL_A and GSSL_A. In addition, the voltage generating circuit 310 may provide a compensation voltage to the second global word line GWLs_B and the second global selection lines GDSL_B and GSSL_B.

3) Apply a compensation voltage to the global word line and the global selection line corresponding to the unselected memory block (S430)

The voltage generating circuit 310 can assign the unselected second memory block The second global word line GWLs_B of 342 and the global selection lines GDSL_B and GSSL_B apply a compensation voltage. For example, the voltage generating circuit 310 may apply an operating voltage to the first global word line GWLs_A and the first global selection lines GDSL_A and GSSL_A assigned to the selected first memory block 341. The voltage generating circuit 310 may apply a compensation voltage to the second global word line GWLs_B and the second global selection lines GDSL_B and GSSL_B assigned to the unselected second memory block 342. The compensation voltage applied to the second global word line GWLs_B may be a positive voltage, and for example, may be set in a range from zero volts to four volts. The compensation voltage applied to the second global selection lines GDSL_B and GSSL_B may be a voltage of zero volts.

4) Apply a deselection control voltage to the selection line switch circuit assigned to the unselected memory block and float the selection line (S440)

The drain deselection control voltage CS_DSL_B and the source deselection control voltage may be applied to the second drain select line switch circuit 333 and the second source select line switch circuit 334 assigned to the unselected second memory block 342, respectively CS_SSL_B. In this case, the high-voltage drain selection control voltage CS_DSL_A output from the control logic 350 may be applied to the first drain selection line switch circuit 331 assigned to the first memory block 341. The high-voltage source selection control voltage CS_SSL_A output from the control logic 350 may be applied to the first source selection line switch circuit 332. The zero-volt drain deselect control voltage CS_DSL_B output from the control logic 350 may be applied to the second drain select line switch circuit 333 assigned to the unselected second memory block 342. The source deselection control voltage CS_SSL_B of zero volts output from the control logic 350 may be applied to the second source selection line switch circuit 334. As a result, the second drain selection line DSL_B1 and the second source selection line SSL_B1 may float.

5) Apply an operating voltage to the selected memory block (S450)

During a read operation, a voltage of zero volts can be applied to the common source line shared by the first memory block 341 and the second memory block 342, and the first memory block 341 and the second The bit lines shared by the memory block 342 are precharged.

In the case where the first memory block 341 is the selected memory block and the second memory block 342 is the unselected memory block, the block decoder 360 may generate The block of high voltage level passes the signal BLKWL.

In response to the block pass signal BLKWL, the first pass circuit 321 can electrically couple the first global word line GWLs_A to the first word line WLs_A of the first memory block 341, and can electrically connect the first global select lines GDSL_A and GSSL_A It is coupled to the first sub-select lines DSL_A and SSL_A.

In response to the block pass signal BLKWL, the second pass circuit 322 can electrically couple the second global word line GWLs_B to the second word line WLs_B of the second memory block 342, and can electrically connect the second global select lines GDSL_B and GSSL_B Coupled to the second sub-select lines DSL_B and SSL_B.

The read voltage and the pass voltage may be applied to the first word line WLs_A of the selected first memory block 341, and the selection transistor control voltage may be applied to the first selection lines DSL_A1 and SSL_A1. A compensation voltage ranging from zero volts to four volts may be applied to the second word line WLs_B of the unselected second memory block 342, and a compensation voltage of zero volts may be applied to the second selection lines DSL_B1 and SSL_B1. As a result, the second selection lines DSL_B1 and SSL_B1 of the unselected second memory block 342 may float.

The potential levels of the floating second selection lines DSL_B and SSL_B can be increased by capacitive coupling with adjacent wiring lines and terminals. In the second word line WLs_B and the second selection When the potential levels of the line selection DSL_B1 and SSL_B1 exceed zero volts through capacitive coupling, it is possible to suppress the leakage current (for example, GIDL) in the channel of the drain selection transistor and the source selection transistor. The generation of formed hot carriers (eg, hot holes). Therefore, the probability of injecting and capturing hot carriers (eg, hot holes) in the channel of the unselected memory block can be reduced, and the leakage of the cell string flowing through the second memory block 342 can be reduced Current.

The following "Table 4" shows the potentials of the word lines and the selection lines assigned to the selected memory block and the unselected memory block among the plurality of memory blocks that share a block pass signal. Level.

As shown in Table 4, read voltages and pass voltages can be applied to the word lines of selected memory blocks, which are memory blocks selected from a plurality of memory blocks. Here, the selected memory block may be coupled to a pass circuit sharing a pass signal of a specific block. Therefore, the block pass signal can be applied not only to the selected memory block but also to the unselected memory block. A selection transistor control voltage of 5.5 volts can be applied to the selection line of the selected memory block. As described above, zero volts or compensation voltage can be applied to the word lines of unselected memory blocks, and zero volt compensation power can be applied to the selected lines Press, or select line can float. Therefore, during the read operation of the selected memory block, in the unselected memory block, hot carriers (eg, thermoelectric) are formed in the lower channels of the drain-select transistor and the source-select transistor. The probability of a hole) can be reduced, and the probability of hot carriers (eg, thermoelectric holes) injected and captured in the channel of the memory block can be reduced. In addition, the leakage current flowing through the cell string in the second memory block 342 can be reduced.

9 is a diagram illustrating a semiconductor memory device according to an embodiment of the present disclosure.

Referring to FIG. 9, the semiconductor memory device 400 may include a voltage generating circuit 410, a pass circuit 420, a memory unit 430, control logic 440 and a block decoder 450.

The voltage generation circuit 410 may generate operation voltages having various levels in response to operation signals output from the control logic 440 during a read operation, and may output these operation voltages to a global word line and a global selection line. For example, the operating voltage may include a read voltage, a pass voltage, a selection transistor control voltage, a compensation voltage, and the like. The voltage generation circuit 410 may transmit operating voltages having various levels to the first global word line GWLs_A, the first global selection lines GDSL_A and GSSL_A, the second global word line GWLs_B, and the second global selection lines GDSL_B and GSSL_B. For example, in the case where the first memory block 431 is selected between the first memory block 431 and the second memory block 432 of the memory unit 430, the voltage generating circuit 410 may assign the first memory block The first global word line GWLs_A and the first global selection lines GDSL_A and GSSL_A of the block 341 send operating voltages, and can select the second global word line GWLs_B and the second global selection assigned to the unselected second memory block 342 The lines GDSL_B and GSSL_B send a voltage of zero volts or a compensation voltage lower than the operating voltage. The compensation voltage can be set in a range from zero volts to four volts.

The pass circuit group 420 may include a first drain select line pass circuit 421, a first word line pass circuit 422, a first source select line pass circuit 423, a second drain select line pass circuit 424, and a second word line pass circuit 425 and the second source selection line pass circuit 426.

The first drain selection line passing circuit 421 can be coupled between the first global drain selection line GDSL_A and the first drain selection line DSL_A of the first memory block 431, and can control the first drain selection line DSL_A Potential level. For example, when the first memory block 431 is selected between the first memory block 431 and the second memory block 432 of the memory unit 430, the first drain selection line through the circuit 421 can respond to The block drain select control voltage BLKDSL_A output from the control logic 440 transmits the operating voltage applied to it through the first global drain select line GDSL_A to the first drain select line DSL_A of the first memory block 431.

The first word line passing circuit 422 may be coupled between the first global word line GWLs_A and the first word line WLs_A of the first memory block 431, and may control the potential level of the first word line WLs_A. For example, when the first memory block 431 is selected between the first memory block 431 and the second memory block 432 of the memory unit 430, the first word line through the circuit 422 can respond to the slave area The block output by the block decoder 450 transmits the operation voltage input to it through the first global word line GWLs_A to the first word line WLs_A of the first memory block 431 through the signal BLKWL.

The first source selection line passing circuit 423 may be coupled between the first source selection line GSSL_A and the first source selection line SSL_A of the first memory block 431, and may control the potential of the first source selection line SSL_A Level. For example, when the first memory block 431 is selected between the first memory block 431 and the second memory block 432 of the memory unit 430, the first source selection line through the circuit 423 can respond to Block source output from control logic 440 The control voltage BLKSSL_A is selected to transmit the operation voltage input to the first source selection line SSL_A of the first memory block 431 through the first global source selection line GSSL_A.

The second drain selection line passing circuit 424 may be coupled between the second global drain selection line GDSL_B and the second drain selection line DSL_B of the second memory block 432, and may control the second drain selection line DSL_B Potential level. For example, in the case where the unselected memory block in the first memory block 431 and the second memory block 432 of the memory unit 430 is the second memory block 432, the second drain selection line The second drain selection line DSL_B is floated by the circuit 424 in response to the block drain deselecting the control voltage BLKDSL_B output from the control logic 440.

The second word line is coupled between the second global word line GWLs_B and the second word line WLs_B of the second memory block 432 through the circuit 425, and controls the potential level of the second word line WLs_B. For example, in the case where the second memory block 432 is an unselected memory block of the memory unit 430, the second word line pass circuit 425 may respond to the block pass signal BLKWL output from the block decoder 450 The compensation voltage input to the second word line WLs_B of the second memory block 432 through the second global word line GWLs_B is sent.

The second source selection line passing circuit 426 may be coupled between the second source selection line GSSL_B and the second source selection line SSL_B of the second memory block 432, and may control the potential of the second source selection line SSL_B Level. For example, in the case where the second memory block 432 is the selected memory block of the memory unit 430, the second source selection line through the circuit 426 may respond to the block source deselection output from the control logic 440 Control the voltage BLKSSL_B to send the compensation voltage input to the second source selection line SSL_B of the second memory block 432 through the second global source selection line GSSL_B, or may make the second source selection line SSL_B Can float.

That is, the drain selection line and the source selection line of the unselected memory block can be selectively floated by the circuit 420.

The first drain select line pass circuit 421 and the second drain select line pass circuit 424 and the first source select line pass circuit 423 and the second source select line pass circuit 426 of the pass circuit 420 may be controlled by the control logic 440. The first word line pass circuit 422 and the second word line pass circuit 425 of the pass circuit 420 can be controlled by the block decoder 450.

The first drain select line pass circuit 421 and the second drain select line pass circuit 424, the first source select line pass circuit 423 and the second source select line pass circuit 426, and the first word line pass circuit of the pass circuit 420 422 and the second word line pass circuit 425 may include a plurality of high voltage transistors.

The memory unit 430 may include a first memory block 431 and a second memory block 432. Each of the first memory block 431 and the second memory block 432 may include a plurality of memory cells. In an embodiment, the plurality of memory cells may be non-volatile memory cells. Among the plurality of memory cells, the memory cells coupled to the same word line are defined as one page. Each of the first memory block 431 and the second memory block 432 may include a plurality of cell strings.

The first memory block 431 and the second memory block 432 may share a common source line and bit line.

The control logic 440 may control the voltage generation circuit 410 in response to a command CMD input from an external device, and control the first drain selection line pass circuit 421 and the second drain selection line pass circuit 424 and the first source electrode through the circuit 420 Select line through circuit 423 and second source 极选线进行电路426。 The pole selection line through the circuit 426. For example, in response to a read command related to a read operation, the control logic 440 may control the voltage generating circuit 410 to generate various operating voltages. In addition, the control logic 440 may output the block drain select control voltage BLKDSL_A, the block source select control voltage BLKSSL_A, the block drain deselect control voltage BLKDSL_B, and the block source deselect control voltage BLKSSL_B in order to control the The first drain select line pass circuit 421 and the second drain select line pass circuit 424 and the first source select line pass circuit 423 and the second source select of the selected memory block and the unselected memory block线更新电路426.

When the memory block corresponding to the column address ADDR is the first memory block 431 or the second memory block 432, the block decoder 450 may generate a block pass signal BLKWL with a high voltage level. The column address ADDR may be output from the control logic 440.

The third group of GRCs may include a first drain select line pass circuit 421, a first word line pass circuit 422, a first source select line pass circuit 423, and a first memory block 431.

The fourth group of GRDs may include a second drain select line pass circuit 424, a second word line pass circuit 425, a second source select line pass circuit 426, and a second memory block 432.

FIG. 10 is a diagram illustrating in detail the fourth group of the semiconductor memory device illustrated in FIG. 9.

The third group GRC and the fourth group GRD of FIG. 9 may have the same structure; therefore, for convenience, only the fourth group GRD will be described in detail, and it is assumed that the fourth group GRD corresponds to an unselected memory.

The fourth group of GRDs may include a second drain select line pass circuit 424, a second word line pass circuit 425, a second source select line pass circuit 426, and a second memory block 432.

The second drain select line pass circuit 424, the second word line pass circuit 425, and the second source select line pass circuit 426 may include the first transistor MT1 to the k-th transistor MTk. For example, the second source selection line passing circuit 426 may include the first transistor MT1. The second word line passing circuit 425 may include second transistor MT2 to (k-1)th transistor MTk-1. The second drain selection line passing circuit 424 may include a k-th transistor MTk.

The first transistor MT1 may couple or decouple the second global source selection line GSSL_B and the second source selection line SSL_B in response to the block source deselection control voltage BLKSSL_B. The second transistor MT2 to the (k-1)th transistor MTk-1 may couple or decouple the second global word line GWLs_B and the second word line WLs_B to each other in response to the block pass signal BLKWL. In response to the block-drain deselection control voltage BLKDSL_B, the k-th transistor MTk couples or decouples the second global drain selection line GDSL_B and the second drain selection line DSL_B to each other.

During the read operation of the selected memory block, the first transistor MT1 and the k-th transistor MTk may be turned off in response to the block source deselection control voltage BLKSSL_B and the block drain deselection control voltage BLKDSL_B, and the second The transistor MT2 to the k-1th transistor MTk-1 can be turned on in response to the block pass signal BLKWL. Therefore, the second source selection line SSL_B and the second drain selection line DSL_B may float, and the voltage applied to the second global word line GWLs_B may be transmitted to the second word line WLs_B. For example, in the case where the second global word line GWLs_B is a line assigned to an unselected memory block, a voltage of zero volts may be applied to the second global word line GWLs_B, and thus may also be sent to the second word line WLs_B Zero volts.

The second memory block 432 includes a plurality of cell strings ST1 to STm respectively coupled between the common source line CSL and the plurality of bit lines BL1 to BLm.

The plurality of cell strings ST1 to STm may have the same structure. The first cell string ST1 may include a source selection transistor SST, a plurality of memory cells MC0 to MCn, and a drain selection transistor DST coupled in series between the common source line CSL and the bit line BL1. The gates of the plurality of memory cells MC0 to MCn are coupled to the corresponding second word lines WLs_B.

FIG. 11 is a flowchart illustrating the operation of the semiconductor memory device illustrated in FIG. 9.

The operation of the semiconductor memory device according to the present embodiment will be described with reference to FIGS. 9, 10 and 11.

Here, it is assumed that between the first memory block 431 and the second memory block 432, the first memory block 431 is the selected memory block and the second memory block 432 is the unselected memory Block.

1) Enter the read command (S510)

When a read command CMD related to a read operation is input from an external device, the control logic 440 generates a control signal and a control voltage for controlling the voltage generating circuit 410 and the pass circuit 420.

2) Generate operating voltage (S520)

The voltage generating circuit 410 may generate operating voltages having various levels for read operations in response to control signals provided from the control logic 440. For example, the operating voltage may include a read voltage, a pass voltage, a selection transistor control voltage, a compensation voltage, and the like. The voltage generation circuit 410 may provide the read voltage, the pass voltage, the selection transistor control voltage, etc. to the first global word line GWLs_A and the first global selection lines GDSL_A and GSSL_A. In addition, the voltage generating circuit 410 may provide the second global word line GWLs_B and the second global selection line GDSL_B And GSSL_B to provide compensation voltage.

3) Apply a compensation voltage to the global word line corresponding to the unselected memory block (S530)

The voltage generating circuit 410 may apply a compensation voltage to the second global word line GWLs_B assigned to the unselected second memory block 432. For example, the voltage generating circuit 410 may apply an operating voltage to the first global word line GWLs_A and the first global selection lines GDSL_A and GSSL_A assigned to the selected first memory block 431. The voltage generation circuit 410 may apply a zero-volt compensation voltage to the second global word line GWLs_B assigned to the unselected second memory block 432.

4) Apply a deselection control voltage to the selection line assigned to the unselected memory block through the circuit and float the selection line (S540)

The block drain deselection control voltage BLKDSL_B and the block source deselection may be applied to the second drain selection line pass circuit 424 and the second source selection line pass circuit 426 assigned to the unselected second memory block 432, respectively Control voltage BLKSSL_B. The block drain deselection control voltage BLKDSL_B and the block source deselection control voltage BLKSSL_B may be voltages of zero volts. As a result, the second drain selection line DSL_B and the second source selection line SSL_B may float.

5) Apply an operating voltage to the selected memory block (S550)

During the read operation, a voltage of zero volts can be applied to the common source line shared by the first memory block 431 and the second memory block 432, and the first memory block 341 and the second The bit lines shared by the memory block 342 are precharged.

The first memory block 431 is the selected memory block and the second memory In the case where the volume block 432 is an unselected memory block, the block decoder 450 can generate a block pass signal BLKWL with a high voltage level in response to the column address ADDR. Since the block pass signal BLKWL is commonly applied to the first word line pass circuit 422 and the second word line pass circuit 425, the first global word line GWLs_A may be electrically coupled to the first word line WLs_A, and the second global word line GWLs_B may be electrically coupled to the second word line WLs_B.

The potential levels of the floating selection lines DSL_B and SSL_B can be increased by capacitive coupling with adjacent wiring lines and terminals. In the case where the potential levels of the selection lines DSL_B and SSL_B exceed zero volts by the phenomenon of capacitive coupling, the generation of leakage current (eg, GIDL) that may be in the channel of the drain selection transistor and the source selection transistor can be suppressed The formation of hot carriers (eg, hot holes). Therefore, the probability of injecting and capturing hot carriers (eg, hot holes) in the channels of the unselected memory block can be reduced, and the leakage of the cell string flowing through the second memory block 432 can be reduced Current.

FIG. 12 is a diagram illustrating a memory system including a semiconductor memory device according to an embodiment of the present disclosure.

Referring to FIG. 12, the memory system 1000 may include a semiconductor memory device 100 and a controller 1100.

The semiconductor memory device 100 may be the same as the semiconductor memory device described with FIG. 1, FIG. 4, FIG. 6, or FIG. 9; therefore, any repeated detailed description will be omitted or simplified.

The controller 1100 is coupled to the host Host and the semiconductor memory device 100. The controller 1100 is configured to access the semiconductor memory device 100 in response to a request from the host Host. For example, the controller 1100 is configured to control reading, writing, erasing, and background operations of the semiconductor memory device 100. The controller 1100 is configured between the host Host and the semiconductor memory device 100 Provide an interface between. The controller 1100 is configured to drive firmware for controlling the semiconductor memory device 100.

The controller 1100 includes a RAM (random access memory) 1110, a processing circuit 1120, a host interface 1130, a memory interface 1140, and an error correction block 1150. The RAM 1110 is used as at least one of the operation memory of the processing circuit 1120, the cache memory between the semiconductor memory device 100 and the host Host, and the buffer memory between the semiconductor memory device 100 and the host Host. The processing circuit 1120 controls the overall operation of the controller 1100. In addition, the controller 1100 may temporarily store program data provided from the host Host during the writing operation.

The host interface 1130 includes a protocol for performing data exchange between the host Host and the controller 1100. In an exemplary embodiment, the controller 1100 is configured to communicate with the host Host through at least one of various interface protocols such as the following: universal serial bus (USB) protocol, multimedia card (MMC) protocol, Peripheral Component Interconnect (PCI) protocol, PCI-Express (PCI-E) protocol, Advanced Attachment Technology (ATA) protocol, Serial ATA protocol, Parallel ATA protocol, Small Computer Small Interface (SCSI) protocol, strong compact Disk Interface (ESDI) agreement, Integrated Drive Electronics (IDE) agreement, special agreement, etc.

The memory interface 1140 is connected to the semiconductor memory device 100. For example, the memory interface includes an inverse interface or an inverse or interface.

The error correction block 1150 uses an error correction code (ECC) to detect and correct errors in the data received from the semiconductor storage device 100. The processing circuit 1120 may adjust the read voltage according to the error detection result from the error correction block 1150 and control the semiconductor memory device 100 to perform re-reading. In an exemplary embodiment, an error correction block may be provided as an element of the controller 1100.

The controller 1100 and the semiconductor memory device 100 may be integrated into a single semiconductor device. In an exemplary embodiment, the controller 1100 and the semiconductor memory device 100 may be integrated into a single semiconductor device to form a memory card. For example, the controller 1100 and the semiconductor memory device 100 may be integrated into a single semiconductor device and form such as Personal Computer Memory Card International Association (PCMCIA), Compact Flash Card (CF), Smart Media Card (SM or SMC), Memory stick multimedia cards (MMC, RS-MMC or MMCmicro), SD cards (SD, mimiSD, microSD or SDHC), universal flash storage devices (UFS) and other such memory cards.

The controller 1100 and the semiconductor memory device 100 may be integrated into a single semiconductor device to form a solid state drive (SSD). SSDs include storage devices formed to store data into semiconductor memory. When the memory system 1000 is used as an SSD, the operation speed of the host Host coupled to the memory system 2000 can be significantly improved.

In another embodiment, the memory system 1000 may be provided as one of various components of an electronic device such as: a computer, an ultra-mobile PC (UMPC), a workstation, a netbook, a personal digital assistant (PDA), a portable Computers, Internet tablets, wireless phones, mobile phones, smartphones, e-books, portable multimedia players (PMP), game consoles, navigation devices, black boxes, digital cameras, 3D TVs, digital audio Recorders, digital audio players, digital picture recorders, digital picture players, digital video recorders, digital video players, devices capable of sending/receiving information in a wireless environment, various devices used to form home networks , One of various electronic devices used to form a computer network, one of various electronic devices used to form a remote information processing network, an RFID device, one of various elements used to form a computing system, etc.

In an exemplary embodiment, the semiconductor memory device 100 or the memory The body system 1000 is embedded in various types of packages. For example, the semiconductor memory device 100 or the memory system 2000 may be packaged in a type such as the following: package-on-package (PoP), ball grid array (BGA), chip-scale package (CSP), plastic leaded chip carrier ( PLCC), plastic dual in-line package (PDIP), die for Waffle components, die in wafer form, chip on board (COB), ceramic dual in-line package (CERDIP), plastic measurement quad flat pack (MQFP) , Thin quad flat package (TQFP), small outline package (SOIC), reduced outline package (SSOP), thin small outline package (TSOP), thin quad flat package (TQFP), system-in-package (SIP), multi-chip package ( MCP), wafer level manufacturing package (WFP), wafer level processing stack package (WSP), etc.

FIG. 13 is a diagram illustrating an application example of the memory system of FIG. 12.

13, the memory system 2000 may include a semiconductor memory device 2100 and a controller 2200. The semiconductor memory device 2100 may include a plurality of memory chips. The semiconductor memory chips can be divided into multiple groups.

In FIG. 13, each of the plurality of groups is illustrated to communicate with the controller 2200 through the first channel CH1 to the k-th channel CHk. Each semiconductor memory chip may have the same configuration as any of the semiconductor memory devices 100, 200, 300, and 400 described with reference to FIG. 1, FIG. 4, FIG. 6, or FIG.

Each group can communicate with the controller 2200 through a common channel. The controller 2200 may have the same configuration as the controller 1100 described with reference to FIG. 12, and may control a plurality of memory chips of the semiconductor memory device 2100 through a plurality of channels CH1 to CHk.

14 is a diagram illustrating a computing system including the memory system illustrated with reference to FIG. 13 Traditional diagram.

Referring to FIG. 14, the computing system 3000 may include a central processing circuit 3100, a RAM 3200, a user interface 3300, a power supply 3400, a system bus 3500, and a memory system 2000.

The memory system 2000 may be electrically coupled to the CPU 3100, RAM 3200, user interface 3300, and power supply 3400 through the system bus 3500. Data provided through the user interface 3300 or processed by the CPU 3100 may be stored in the memory system 2000.

In FIG. 14, the semiconductor memory device 2100 is illustrated as being coupled to the system bus 3500 through the controller 2200. However, the semiconductor memory device 2100 may be directly coupled to the system bus 3500. The functions of the controller 2200 can be performed by the CPU 3100 and the RAM 3200.

In FIG. 14, it is illustrated that the memory system 2000 described with reference to FIG. 13 is used. However, the memory system 2000 may be replaced with the memory system 1000 described with reference to FIG. 12. In an embodiment, the computing system 3000 may include all the memory systems 1000 and 2000 described with reference to FIGS. 12 and 13.

Although exemplary embodiments of the present disclosure have been disclosed for illustrative purposes, those skilled in the art will appreciate that various modifications, additions, and substitutions are possible. Therefore, the scope of the present disclosure must be defined by the appended patent application scope and equivalents of the patent application scope, and not by the specification preceding them.

Claims (19)

A method of operating a semiconductor memory device, the method comprising the steps of: performing a read operation on a selected memory block; during the read operation, in response to a block pass signal, the selected memory The local word line of the block is coupled to the first sub-global word line and the local word line of the unselected memory block is coupled to the second sub-global word line; and during the read operation, coupling to the The local selection line of the unselected memory block can float, so that the potential level of the local word line coupled to the unselected memory block increases. The method according to item 1 of the patent application scope, wherein, in order to enable the local selection line coupled to the unselected memory block to float, the global selection line is coupled to the local selection line Sub-global selection line isolation. According to the method described in item 1 of the patent application scope, the method further includes the step of: when the local selection line coupled to the unselected memory block is floating, causing the global word line and the The second sub-global word lines are decoupled from each other so that the local word lines coupled to the unselected memory block are floating. The method according to item 3 of the patent application scope, wherein the voltage applied to the global selection line coupled to the unselected memory block and the global selection line coupled to the selected memory block The voltage of is the same, and the voltage applied to the global word line coupled to the unselected memory block is the same as the voltage applied to the global word line coupled to the selected memory block. According to the method described in item 1 of the patent application scope, the method further includes the following steps: When the local selection line floats, the local word line coupled to the unselected memory block is pulled to ground. The method according to item 5 of the patent application scope, wherein the step of pulling the local word line coupled to the unselected memory block to ground includes the steps of: coupling the unselected memory The global word line of the body block is pulled to ground; and the global word line, the second sub-global word line coupled to the unselected memory block and the unselected memory area are coupled The local word lines of the block are coupled to each other. According to the method described in item 1 of the patent application scope, the method further includes the step of pulling some of the local selection lines coupled to the unselected memory block to ground. The method according to item 7 of the patent application scope, wherein among the local selection lines coupled to the unselected memory block, a local drain selection line is floating, and a local source selection line Was pulled to ground. A method of operating a semiconductor memory device, the method comprising the steps of: performing a read operation of a selected memory block; during the read operation, in response to a block pass signal, the selected memory The local word line of the block is coupled to the first sub-global word line and the local word line of the unselected memory block is coupled to the second sub-global word line; and during the read operation, it will be coupled to the The local selection line of the unselected memory block is pulled to ground. The method according to item 9 of the patent application scope, wherein the step of pulling the local selection line coupled to the unselected memory block to ground includes the following steps: Pulling the global selection line coupled to the unselected memory block to ground; and coupling the global selection line and the local selection line coupled to the unselected memory block to each other. According to the method described in item 9 of the patent application scope, the method further includes the step of: when the local selection line coupled to the unselected memory block is pulled to ground, the coupling to the unselected A compensation voltage is applied to the local word line of the memory block. The method according to item 11 of the patent application range, wherein the compensation voltage is set to a positive voltage. According to the method described in item 9 of the patent application scope, the method further includes the steps of: pulling the local selection line coupled to the unselected memory block to ground, so as to couple the unselected memory The global selection line of the volume block and the local selection line are decoupled from each other. A semiconductor memory device includes: a plurality of memory blocks; a local selection line and a local word line coupled to corresponding memory blocks; a voltage generating circuit, the voltage generating circuit is configured to The global selection line and the global word line output various levels of operating voltages; the selection line pass circuit is configured to selectively couple or decouple the global selection line and the local selection line; word A line pass circuit configured to collectively couple or decouple the global word line and the local word line in response to a block pass signal; a block decoder, the block decoder Is configured to generate the block pass signal for controlling the shared word line pass circuit; and Control logic configured to control the voltage generation circuit, the selection line pass circuit, and the block decoder in response to a command. The semiconductor memory device according to item 14 of the patent application range, wherein the voltage generation circuit is coupled to the selection line passing circuit via the global selection line, and is coupled to the word line via the global word line Through the circuit. The semiconductor memory device according to item 15 of the patent application range, wherein during the read operation of the selected memory block among the memory blocks, the voltage generating circuit selects the line and Among the global word lines, global selection lines and global word lines assigned to unselected memory blocks are pulled to ground. The semiconductor memory device according to item 14 of the patent application range, wherein the control logic is configured to output an operation signal for controlling the voltage generating circuit in response to the command, for controlling the selection line The control voltage of the pass circuit and the block pass signal for controlling the block decoder. The semiconductor memory device according to item 14 of the patent application range, wherein during the read operation of the selected memory block among the memory blocks, the control logic is coupled such that it is coupled to the unselected memory The local selection line and the global selection line of the bulk block are decoupled from each other to control the selection line passing circuit. The semiconductor memory device according to item 14 of the patent application range, wherein during the read operation of the selected memory block among the memory blocks, the control logic is coupled such that it is coupled to the unselected memory The local word lines and the global word lines of the bulk block are coupled to each other to control the word lines to pass through the circuit.

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