TWI846267B - Semiconductor package - Google Patents

Abstract

A semiconductor package is provided. The semiconductor package includes: a package substrate; first substrate pads and at least one second substrate pad, disposed on a peripheral region of the package substrate; a semiconductor chip and a dummy chip, stacked on the package substrate; an electrode layer, covering a top surface of the dummy chip; and first and second chip pads, disposed on a peripheral region of the semiconductor chip. The first chip pads are directly connected to the first substrate pads via first bonding wires. The second chip pads are connected to the electrode layer via second bonding wires, and the electrode layer is connected to the at least one second substrate pad via third bonding wires.

Description

Semiconductor Package

The present invention relates to a semiconductor package.

As the electronics industry develops, the size of some semiconductor chips is getting larger and larger. For example, memory chips may have a larger size due to their larger storage capacity and more input/output terminals. As a result, the contours of these semiconductor chips may be closer to the edge of the package substrate that provides support and routing from below. In other words, the package substrate may have only a more limited area to be set up for the pads used to connect to the upper semiconductor chip by wire bonding. In some cases, the width of the peripheral area of the package substrate for setting the pads becomes quite narrow, and only a single row of pads can be set up. This causes the pads to be arranged in a rather dense manner. As a result, the lines connected to these pads in the package substrate become quite dense and have a very narrow line width, resulting in problems such as excessively high line impedance and unstable voltage transmitted to the upper semiconductor chip.

One aspect of the present disclosure provides a semiconductor package, comprising: a package substrate; a plurality of first substrate pads and at least one second substrate pad, disposed on the peripheral area of the package substrate; a semiconductor chip and a dummy chip, stacked on the package substrate; an electrode layer, covering the top surface of the dummy chip; and a plurality of first chip pads and a plurality of second chip pads, disposed on the peripheral area of the semiconductor chip, wherein the plurality of first chip pads are directly connected to the plurality of first substrate pads via a plurality of first bonding wires, the plurality of second chip pads are connected to the electrode layer via a plurality of second bonding wires, and the electrode layer is connected to the at least one second substrate pad via a plurality of third bonding wires.

In some embodiments, the plurality of first chip pads, the plurality of second chip pads, the plurality of first substrate pads, the plurality of first bonding wires, and the plurality of second bonding wires are arranged along the first side and the second side of the semiconductor chip, and the at least one second substrate pad and the plurality of third bonding wires are arranged on the other side of the semiconductor chip.

In some embodiments, the at least one second substrate pad includes a plurality of second substrate pads, each of which is connected to a plurality of the plurality of third bonding wires.

In some embodiments, the plurality of second chip pads, the plurality of second bonding wires, the electrode layer, the plurality of third bonding wires, and the at least one second substrate pad are configured to transmit the same fixed voltage signal.

In some embodiments, the at least one second substrate pad is larger in individual area than the plurality of first substrate pads.

In some embodiments, the top circuit layer of the package substrate includes a plurality of first circuits and at least one second circuit, the plurality of first circuits are connected to the plurality of first substrate pads, the at least one second circuit is connected to the at least one second substrate pad, and the at least one second circuit has a larger individual line width than the plurality of first circuits.

In some embodiments, the dummy chip is stacked on the semiconductor chip, and the area of the dummy chip and the area of the electrode layer are respectively smaller than the area of the semiconductor chip.

In some embodiments, the plurality of first bonding wires extend longitudinally across the semiconductor chip from the plurality of first chip pads to the plurality of first substrate pads, the plurality of second bonding wires extend longitudinally across the dummy chip from the plurality of second chip pads to the electrode layer, and the plurality of third bonding wires extend longitudinally across the dummy chip and the semiconductor chip from the electrode layer to the at least one second substrate pad.

In some embodiments, the semiconductor chip is stacked on the dummy chip and the electrode layer, and the area of the semiconductor chip is smaller than the area of the dummy chip and the area of the electrode layer, respectively.

In some embodiments, the plurality of first bonding wires extend from the plurality of first chip pads longitudinally across the semiconductor chip and the dummy chip to the plurality of first substrate pads, the plurality of second bonding wires extend from the plurality of second substrate pads longitudinally across the semiconductor chip to the electrode layer, and the plurality of third bonding wires extend from the electrode layer longitudinally across the dummy chip to the at least one second substrate pad.

10, 20: Semiconductor packaging

100:Packaging substrate

102, 104: substrate pad

106a, 106b: Lines

108a, 108b: Conductive hole

110, 210: semiconductor chip

112, 128, 212, 228: chip glue

114, 114a, 114b, 214, 214a, 214b: chip pads

116, 124, 126, 216, 224, 226: bonding wires

120, 220: Virtual chip

122, 222: Electrode layer

GND: Ground voltage signal

PW-1, PW-2: Power voltage signal

SG-A, SG-B, SG-C, SG-D, SG-E, SG-F, SG-G, SG-H, SG-I, SG-J, SG-K, SG-L, SG-M, SG-N, SG-O, SG-P: Operation signal

FIG. 1A is a three-dimensional schematic diagram of a semiconductor package according to some embodiments of the present disclosure.

FIG. 1B is a schematic top view of the semiconductor package shown in FIG. 1A .

FIG1C is a schematic plan view of the top layer circuit of the package substrate shown in FIG1A.

FIG2 is a three-dimensional schematic diagram of a semiconductor package according to other embodiments of the present disclosure.

FIG. 1A is a three-dimensional schematic diagram of a semiconductor package 10 according to some embodiments of the present disclosure.

Referring to FIG. 1A , the semiconductor package 10 includes a package substrate 100 for carrying a semiconductor chip. The package substrate 100 may be a circuit board, which may include conductive features (wires, vias, etc.) embedded in an insulating layer stack. In some embodiments, the package substrate 100 is a core substrate, wherein the insulating layer is stacked on opposite sides of a core layer. In an alternative embodiment, the package substrate 100 is a coreless substrate without a core layer, and has a smaller overall thickness than a core substrate.

The semiconductor chip 110 is attached to the package substrate 100 by the back side, and the integrated circuit in the semiconductor chip 110 is connected from the active side of the semiconductor chip 110 to the package substrate 100 by wire bonding. As an example, the semiconductor chip 110 may be a memory chip. However, the semiconductor chip 110 may also be a semiconductor chip with other functions. The present disclosure is not limited to the function of the semiconductor chip 110. In addition, in this article, the active side represents the surface of the semiconductor chip on one side where the semiconductor elements and circuits are arranged. In contrast, the back side of the semiconductor chip relative to the active side can be defined by the back side of the semiconductor substrate carrying the semiconductor elements and circuits.

In some embodiments, the semiconductor chip 110 is attached to the package substrate 100 with a wafer adhesive 112. In these embodiments, the wafer adhesive 112 may be pre-set on the back side of the semiconductor chip 110 before attaching the semiconductor chip 110, and the wafer adhesive 112 attaches the semiconductor chip 110 to the package substrate 100 when the semiconductor chip 110 is placed on the package substrate 100.

A plurality of chip pads 114 are disposed on the peripheral area of the active surface of the semiconductor chip 110 and may be arranged along the outline of the semiconductor chip 110. However, the chip pads 114 may be arranged along only a portion of the outline of the semiconductor chip 110, rather than along the entire outline of the semiconductor chip 110. In some embodiments, the semiconductor chip 110 has a rectangular outline, and the chip pads 114 are arranged along two opposite sides of the semiconductor chip 110, while the other two sides of the semiconductor chip 110 are not provided with chip pads 114. The chip pads 114 may serve as input/output terminals of the semiconductor chip 110. Among them, some chip pads 114 can be used to transmit fixed voltage signals (such as power voltage signals and ground voltage signals), while other chip pads 114 can be used to transmit various operation signals. As will be described in more detail later, the semiconductor chip 110 is indirectly connected to the package substrate 100 through a set of chip pads 114 (also referred to as chip pads 114a) for transmitting power voltage signals, and is directly connected to the package substrate 100 through other chip pads 114 (also referred to as chip pads 114b). In some embodiments, the chip pads 114a are periodically arranged between the chip pads 114b.

The bonding wire 116 connects the chip pad 114b to the substrate pad 102 on the package substrate 100 to achieve a direct connection between the semiconductor chip 110 and the package substrate 100. In the embodiment where the chip pad 114b is arranged along two opposite sides of the semiconductor chip 110, the substrate pad 102 is also arranged on the package substrate 100 along the two opposite sides of the semiconductor chip 110 to shorten the length of the bonding wire 116 connecting the chip pad 114b and the substrate pad 102.

On the other hand, the dummy chip 120 is stacked on the semiconductor chip 110, and the electrode layer 122 is disposed on the top surface of the dummy chip 120, so that the chip pad 114a is indirectly connected to the substrate pad 104 on the package substrate 100 through the electrode layer 122. The main function of the dummy chip 120 is to carry the electrode layer 122. As an example, the dummy chip 120 may include a semiconductor substrate, but the semiconductor substrate may not have semiconductor elements and circuits formed thereon. In addition, the area of the dummy chip 120 may be smaller than the area of the semiconductor chip 110. In this way, the dummy chip 120 can be placed on the central area of the semiconductor chip 110 without covering the chip pad 114 located on the peripheral area of the semiconductor chip 110.

The electrode layer 122 may cover the upper surface of the virtual chip 120 and may include a single layer or multiple layers of conductive material. The chip pad 114a on the semiconductor chip 110 is connected to the electrode layer 122 upwardly by a bonding wire 124 that crosses the side wall of the virtual chip 120. Since the chip pad 114a connected to the electrode layer 122 is used to transmit the same fixed voltage signal (such as a power voltage signal), the chip pad 114a may be connected to the electrode layer 122 in common. Compared to the chip pad 114, the electrode layer 122 has a larger area and may have a lower impedance.

In addition, the electrode layer 122 is connected downward to the substrate pad 104 on the package substrate 100 through the bonding wire 126. Since the electrode layer 122 is located above the semiconductor chip 110 and the dummy chip 120, the bonding wire 126 crosses the sidewalls of the dummy chip 120 and the semiconductor chip 110 to connect the electrode layer 122 to the substrate pad 104, and has a longer length than the bonding wire 124. Similar to the bonding wire 124, the bonding wire 126 is also used to transmit the same fixed voltage signal (e.g., a power voltage signal). Therefore, a group of bonding wires 126 can share the same substrate pad 104, and the substrate pad 104 can have a larger area than the substrate pad 102. For example, two or more substrate pads 104 can be provided on the package substrate 100, and these substrate pads 104 are respectively connected to a group of bonding wires 126, and have a larger length or width than the substrate pad 102. However, there can also be only a single substrate pad 104 on the package substrate 100, and all bonding wires 126 are connected to this substrate pad 104.

In the embodiment where the chip pad 114, the substrate pad 102, and the bonding wires 116 and 124 are arranged along two opposite sides of the semiconductor chip 110, the bonding wire 126 and the substrate pad 104 can be arranged along the other two sides of the semiconductor chip 110. In this way, even if the semiconductor chip 110 has a large size and it is not possible to arrange multiple rows of substrate pads on each side of the semiconductor chip 110, the position of the substrate pad 104 can be staggered from the position of the substrate pad 102.

Since the chip pad 114a arranged between the chip pads 114b is indirectly connected to the substrate pad 104 far away from the substrate pad 102 via the electrode layer 122, it is not necessary to arrange an additional substrate pad 102 along the chip pad 114a. In other words, no substrate pad 102 is arranged at the extension of the chip pad 114a, so that the arrangement of the substrate pad 102 has a gap at the extension of the chip pad 114a. As described in more detail below with reference to FIG. 1C, reducing the density of the substrate pad 102 can make the circuits in the package substrate 100 distributed in a more dispersed manner, and less restricted by line width and pitch.

In some embodiments, the dummy chip 120 is attached to the active surface of the semiconductor chip 110 with a wafer glue 128. In these embodiments, the wafer glue 128 may be pre-placed on the bottom surface of the dummy chip 120 before attaching the dummy chip 120, and the wafer glue 128 attaches the dummy chip 120 to the semiconductor chip 110 when the dummy chip 120 is placed on the semiconductor chip 110.

Although not shown, the semiconductor package 10 may also include a package body that encapsulates components located on the package substrate 100. In addition, an electrical connector (such as a solder ball or a bump) may be provided on the bottom side of the package substrate 100 to serve as an input/output terminal of the semiconductor package 10.

FIG. 1B is a top view schematic diagram of a semiconductor package 10 according to some embodiments. FIG. 1C is a plan view schematic diagram of the top layer circuit of a package substrate 100 according to these embodiments.

As described above, various signals can be transmitted between the semiconductor chip 110 and the package substrate 100. Among them, some signals are indirectly transmitted between the semiconductor chip 110 and the package substrate 100 through the electrode layer 122. In contrast, other signals are directly transmitted between the package substrate 100 and the semiconductor chip 110.

Referring to FIG. 1B , in some embodiments, the power voltage signal PW-1 is indirectly transmitted between the semiconductor chip 110 and the package substrate 100 through the signal path established by the chip pad 114a, the bonding wire 124, the electrode layer 122, the bonding wire 126 and the substrate pad 104. On the other hand, the power voltage signal PW-2, the operation signals SG-A to SG-P and the ground voltage signal GND are directly transmitted between the semiconductor chip 110 and the package substrate 100 through the signal path established by the chip pad 114b, the bonding wire 116 and the substrate pad 102.

In the signal path directly connecting the semiconductor chip 110 and the package substrate 100, the signal paths of the operating signals SG-A to SG-P can be respectively adjacent to at least one signal path coupled to the ground voltage signal GND, thereby obtaining the shielding provided by the ground signal GND. In addition, the signal paths of some operating signals can even be respectively located between two signal paths coupled to the ground voltage signal GND, and be shielded on both sides by the ground voltage signal GND. On the other hand, the signal paths of other operating signals can be respectively adjacent to a signal path coupled to the power voltage signal PW-2 on the other side. For example, the signal paths of the operating signals SG-B, SG-C, SG-D, SG-E, SG-F, SG-G, SG-J, SG-K, SG-L, SG-M, SG-N, and SG-O may be located between two signal paths coupled to the ground voltage signal GND. In addition, the paths of the operating signals SG-A, SG-H, SG-I, and SG-P may be located between a signal path coupled to the ground voltage signal GND and a signal path coupled to the power voltage signal PW-2.

For each operating signal path that is shielded by the ground signal GND on both sides (i.e., each signal path coupled to the operating signals SG-B, SG-C, SG-D, SG-E, SG-F, SG-G, SG-J, SG-K, SG-L, SG-M, SG-N, SG-O), it can be separated from the signal path of the ground voltage signal GND on both sides by different distances. Taking the signal path of the operation signal SG-B as an example, a set of chip pads 114b, bonding wires 116 and substrate pads 102 for transmitting the operation signal SG-B can be closely coupled to a set of chip pads 114b, bonding wires 116 and substrate pads 102 coupled to the ground voltage signal GND on one side, and can be separated from another set of chip pads 114b, bonding wires 116 and substrate pads 102 coupled to the ground voltage signal GND on the other side via a chip pad 114a for indirectly transmitting the power voltage signal PW-1.

On the other hand, the signal path established by the chip pad 114a, the bonding wire 124, the electrode layer 122, the bonding wire 126 and the substrate pad 104 and used to indirectly transmit the power voltage signal PW-1 between the semiconductor chip 110 and the packaging substrate 100 can be staggered from the signal path directly connected between the semiconductor chip 110 and the packaging substrate 100. In the example shown in FIG. 1B , the signal paths that directly connect the semiconductor chip 110 to the package substrate 100 can be arranged on opposite sides of the semiconductor chip 110, and the signal paths that indirectly connect the semiconductor chip 110 to the package substrate 100 can go through the electrode layer 122 on the semiconductor chip 110 to the substrate pads 104 located on the other two sides of the semiconductor chip 110. Based on this design, it is possible to avoid all signal paths being concentrated on both sides of the semiconductor chip 110. As will be described in more detail below, the routing area in the top wiring layer of the package substrate 100 can be at least partially released.

Referring to FIG. 1C , in the top circuit layer of the package substrate 100, a plurality of circuits 106b are connected to the substrate pads 102 for directly transmitting the voltage power signal PW-2, the operation signals SG-A to SG-P, and the ground voltage signal GND between the semiconductor chip 110 and the package substrate 100. In addition, the circuits 106b in the top circuit layer are connected downward to other circuit layers through the vias 108b. In the embodiment where the chip pads 102 are arranged on the peripheral area of the package substrate 100 along the opposite sides of the semiconductor chip 110, the circuits 106b extend inward from the two sides of the package substrate 100 to the vias 108b. In addition, because the arrangement of the substrate pads 102 has a gap at the extension of the chip pads 114a (as described in reference to FIG. 1B ), some adjacent substrate pads 102 are separated by a larger gap, so that the lines 106b connected to these substrate pads 102 are also separated by a larger gap. In this way, the line 106b can have a lower arrangement density, so that the line width and pitch of the line 106b are less restricted. Therefore, it can be ensured that the line 106b can have a sufficiently low impedance, and it can further ensure that the transmitted signal (i.e., the voltage power signal PW-2, the operation signals SG-A to SG-P, and the ground voltage signal GND) can be stably provided to the semiconductor chip 110.

In addition, the line 106a in the top circuit layer of the package substrate 100 is connected to the substrate pad 104 for indirectly transmitting the voltage power signal PW-1 between the semiconductor chip 110 and the package substrate 100. In addition, the via 108a in the top circuit layer connects the line 106a to other circuit layers. In an embodiment where the substrate pads 102 are arranged along two opposite sides of the semiconductor chip 110 and the substrate pads 104 are arranged along the other two opposite sides of the semiconductor chip 110, the substrate pads 102 and 104 may surround the semiconductor chip 110 on the peripheral area of the package substrate 100, and the line 106a in the package substrate 100 may extend from the peripheral area inward to the via 108a. In addition, the line 106a connected to the substrate pad 104 may have a larger line width and lower impedance than the line 106b connected to the substrate pad 102. Moreover, each line 106a may be connected to a set of vias 108a. In the example shown in FIG. 1C , each line 106a can be connected to three vias 108a.

Although not shown, the package substrate 100 also has other circuit layers to route the circuits 106a, 106b in the top circuit layer to the electrical connectors located on the bottom side of the package substrate 100.

FIG. 2 is a three-dimensional schematic diagram of a semiconductor package 20 according to other embodiments of the present disclosure. The semiconductor package 20 is similar to the semiconductor package 10 described with reference to FIGS. 1A to 1C . For the sake of brevity, the parts of the semiconductor package 20 that are the same or similar to the semiconductor package 10 will not be fully described below. In other words, the parts that are omitted represent the same or similar to the semiconductor package 10.

Referring to FIG. 2 , the semiconductor package 20 has a semiconductor chip 210, a dummy chip 220, and an electrode layer 222 covering the dummy chip 220. In terms of structure and function, the semiconductor chip 210 may be the same as the semiconductor chip 110 described with reference to FIG. 1A . In addition, the dummy chip 220 and the electrode layer 222 are similar to the dummy chip 120 and the electrode layer 122 described with reference to FIG. 1A . In other words, the main function of the dummy chip 220 is to carry the electrode layer 222, and it may not have semiconductor components and circuits.

As a difference, the semiconductor chip 210 is stacked on the dummy chip 220 and the electrode layer 222, rather than being disposed under the dummy chip 220 and the electrode layer 222. In addition, the area of the semiconductor chip 210 may be smaller than the area of the dummy chip 220. This allows the semiconductor chip 210 to be positioned on the central area of the dummy chip 220 and the electrode layer 222, while the peripheral area of the dummy chip 220 and the electrode layer 222 is not covered by the semiconductor chip 210. Furthermore, the wafer glue 212 disposed on the back side of the semiconductor chip 210 attaches the semiconductor chip 210 to the electrode layer 222. On the other hand, the chip glue 228 disposed on the bottom surface of the dummy chip 220 attaches the dummy chip 220 to the top surface of the package substrate 100.

Compared to the semiconductor chip 110 and the dummy chip 120 covered with the electrode layer 122 illustrated in reference to FIG. 1A , the semiconductor chip 210 and the dummy chip 220 covered with the electrode layer 222 have a different stacking sequence. Therefore, the method of indirectly and directly connecting the semiconductor chip 210 to the package substrate 100 must also be adjusted accordingly.

The chip pads 214 disposed on the active surface of the semiconductor chip 210 and arranged along two opposite sides of the semiconductor chip 210 include chip pads 214a and chip pads 214b. The chip pads 214a are arranged between the chip pads 214b, and the semiconductor chip 210 is indirectly connected to the package substrate 100 through the chip pads 214a through the electrode layer 222. On the other hand, the semiconductor chip 210 is directly connected to the package substrate 100 through the chip pads 214b. Similar to the chip pads 114a described with reference to FIG. 1A, the chip pads 214a can be used to transmit a fixed voltage signal, such as a power voltage signal. In addition, similar to the chip pad 114b described with reference to FIG. 1A , the chip pad 214b can be used to transmit a fixed voltage signal, an operating signal, and a ground voltage signal.

To achieve direct connection between the semiconductor chip 210 and the package substrate 100, the bonding wire 216 connects the chip pad 214b downward to the substrate pad 102 located on the package substrate 100 and arranged along the chip pad 214b. On the other hand, to achieve indirect connection between the semiconductor chip 210 and the package substrate 100, the bonding wire 224 connects the chip pad 214a downward to the electrode layer 222, and the bonding wire 226 connects the electrode layer 222 downward to the substrate pad 104 (which may be one or more substrate pads 104) on the package substrate 100. The bonding wires 216 and 224 may cross over the two sides of the semiconductor chip 210 where the chip pads 214a and 214b are arranged. The bonding wire 216 crosses the side wall of the semiconductor chip 210 and the side wall of the dummy chip 220 to connect the chip pad 214b to the substrate pad 102 on the package substrate 100, and the bonding wire 224 crosses the side wall of the semiconductor chip 210 to connect the chip pad 214a to the electrode layer 222. On the other hand, the bonding wire 226 can extend outside the two sides of the semiconductor chip 210 where the chip pads 214a and 214b are not provided, and cross the side wall of the dummy chip 220 to connect the electrode layer 222 to the substrate pad 104 provided on the package substrate 100. As a result, the bonding wire 216 can have a longer length compared to the bonding wires 224 and 226. In addition, similar to the bonding wire 126 described with reference to FIG. 1A, a set of bonding wires 226 can be connected to the same substrate pad 104.

Although not shown, the semiconductor package 20 may also include a package body that encapsulates the components located on the package substrate 100. In addition, the bottom side of the package substrate 100 may also be provided with electrical connectors (such as solder balls or bumps) to serve as input/output terminals of the semiconductor package 20. In addition, the package substrate 100 may have a top circuit layer and other circuit layers as described with reference to FIG. 1C, and the substrate pads 102 and 104 on the package substrate 100 are connected to these electrical connectors located on the bottom side of the package substrate 100.

In summary, the disclosed embodiment provides a semiconductor package, including a semiconductor chip and a dummy chip stacked on a package substrate, and the surface of the dummy chip is covered with an electrode layer. A first chip pad and a second chip pad are arranged on the peripheral area of the semiconductor chip along the opposite sides of the semiconductor chip. The first chip pad is directly connected to the first substrate pad on the package substrate, and the second chip pad for transmitting the same fixed voltage signal is indirectly connected to the second substrate pad on the package substrate through the electrode layer. In particular, the first chip pad and the second chip pad can be connected to the first substrate pad and the electrode layer on two sides of the semiconductor chip, respectively, and the electrode layer can be connected to the second substrate pad on the other two sides of the semiconductor chip. In other words, the large-area electrode layer can be used to route the second chip pad to a position where the first substrate pad is not provided. In this way, it can be avoided that all substrate pads are concentrated on two sides of the semiconductor chip. In addition, even if the semiconductor chip has a large size and it is impossible to configure multiple rows of substrate pads on each side of the semiconductor chip, the positions of the first and second substrate pads can be staggered. Therefore, it can be avoided that the top layer circuits connected to the first and second substrate pads in the package substrate are distributed too concentratedly. In this way, the line width and pitch of the top-layer lines are less restricted, so it can be ensured that these lines have low enough impedance to stably transmit signals to the semiconductor chip.

10:Semiconductor packaging

100:Packaging substrate

102, 104: substrate pad

110: Semiconductor chip

112, 128: chip glue

114, 114a, 114b: chip pads

116, 124, 126: Bonding wires

120: Virtual chip

122:Electrode layer

Claims (9)

A semiconductor package comprises: a package substrate; a plurality of first substrate pads and at least one second substrate pad, arranged on a peripheral area of the package substrate; a semiconductor chip and a dummy chip, stacked on the package substrate; an electrode layer, covering the top surface of the dummy chip; and a plurality of first chip pads and a plurality of second chip pads, arranged on a peripheral area of the semiconductor chip, wherein the plurality of first chip pads are directly connected to the plurality of first substrate pads via a plurality of first bonding wires, and the plurality of second chip pads are directly connected to the plurality of first substrate pads via a plurality of first bonding wires. The chip pad is connected to the electrode layer via a plurality of second bonding wires, and the electrode layer is connected to the at least one second substrate pad via a plurality of third bonding wires, wherein the plurality of first chip pads, the plurality of second chip pads, the plurality of first substrate pads, the plurality of first bonding wires and the plurality of second bonding wires are arranged along the first side and the second side of the semiconductor chip, and the at least one second substrate pad and the plurality of third bonding wires are arranged on the other side of the semiconductor chip. A semiconductor package as described in claim 1, wherein the at least one second substrate pad includes a plurality of second substrate pads, each of which is connected to a plurality of the plurality of third bonding wires. A semiconductor package as described in claim 1, wherein the plurality of second chip pads, the plurality of second bonding wires, the electrode layer, the plurality of third bonding wires, and the at least one second substrate pad are configured to transmit the same fixed voltage signal. A semiconductor package as described in claim 1, wherein the at least one second substrate pad is larger in individual area than the plurality of first substrate pads. A semiconductor package as described in claim 1, wherein the top circuit layer of the package substrate includes a plurality of first circuits and at least one second circuit, the plurality of first circuits are connected to the plurality of first substrate pads, the at least one second circuit is connected to the at least one second substrate pad, and the at least one second circuit has a larger individual line width than the plurality of first circuits. A semiconductor package as described in claim 1, wherein the dummy chip is stacked on the semiconductor chip, and the area of the dummy chip and the area of the electrode layer are respectively smaller than the area of the semiconductor chip. A semiconductor package as described in claim 6, wherein the plurality of first bonding wires extend longitudinally from the plurality of first chip pads across the semiconductor chip to the plurality of first substrate pads, the plurality of second bonding wires extend longitudinally from the plurality of second chip pads across the dummy chip to the electrode layer, and the plurality of third bonding wires extend longitudinally from the electrode layer across the dummy chip and the semiconductor chip to the at least one second substrate pad. A semiconductor package as described in claim 1, wherein the semiconductor chip is stacked on the dummy chip and the electrode layer, and the area of the semiconductor chip is smaller than the area of the dummy chip and the area of the electrode layer, respectively. A semiconductor package as described in claim 8, wherein the plurality of first bonding wires extend longitudinally from the plurality of first chip pads across the semiconductor chip and the dummy chip to the plurality of first substrate pads, the plurality of second bonding wires extend longitudinally from the plurality of second chip pads across the semiconductor chip to the electrode layer, and the plurality of third bonding wires extend longitudinally from the electrode layer across the dummy chip to the at least one second substrate pad.

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