JP2001313348A - Multiple line grid array package having multiple line grids and electrical circuit patterns - Google Patents

Abstract

(57) [Summary] (with correction) [PROBLEMS] To provide a multiple line grid array package capable of suppressing signal transmission delay and noise and effectively reducing the number of layers, that is, the thickness of a package body. provide. A package body having a first surface and a second surface opposite to the first surface, a first electric circuit pattern formed on the first surface of the package body and having a plurality of input / output nodes, A second electric circuit pattern 45 formed on the second surface, a multiple line grid 40 connected to the package body and having a non-conductive grid body and a plurality of conductors formed on the inner and / or outer peripheral surface of the grid body; Has,
It is connected to the same number of input / output nodes 48 as the number of conductive lines 41 formed on the grid 40.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a multiple line grid array package.
In particular, the present invention relates to a multiple line grid array package in which electric circuit patterns are formed on upper and lower surfaces of a package body.

[0002]

2. Description of the Related Art In a conventional FBGA package, since the gap between adjacent pads is large, the surface area of the package body layer must be large in order to receive a predetermined number of pads on the package body layer surface. was there. In addition, since the number of electrode wires that can be accepted by each layer of the package body is small, the number of layers of the package body must be large. However, many via holes (vias) are required to electrically connect the layers.
hole). This will be described in detail with reference to FIG.

As shown in FIG. 1, for example, in the case of an FBGA package having two or more insulating layers with a pitch of 0.8 mm, a gap (for example, a pitch of 0.8 mm) between a pad 10a and a pad 10b closest to the pad 10a is one. Since only one electrode wire 12 passes, the surface area of the package body on which the pads are arranged must be large. As shown in the figure, a 0.8 mm pitch FBGA has four I / O (input / output) nodes 10a, 10b,
Since only one via hole 14 can be arranged in the region surrounded by 10c and 10d, and the via hole 14 is an obstacle to the passage of the electrode wire, the routeability is limited. For this reason, there is a disadvantage that the number of insulating layers forming the package body must be large in order to receive a predetermined I / O for the same surface area of the package body. For example, a 200 I / O FBGA package must have four or more 0.8 mm pitch insulating layers to accommodate 200 I / O nodes. As described above, the conventional electric circuit pattern has a problem that the gap between a large number of input / output nodes is largely separated and the length of the electrode line is long, so that signal transmission is delayed and noise is generated. There is a problem that the number of insulating layers forming the package body must be large in order to accept the problem.

[0004] On the other hand, the present applicant has filed Japanese Patent Application No. 10-309191.
The publication describes a multiple line grid array package. In the above application, the multiple line grid array package has a semiconductor chip mounted thereon, and an input / output node for supplying an electrical signal to the semiconductor chip is exposed, and the input / output node of the package body is electrically connected to an external power supply. Have multiple line grids. Here, the “multiple line grid” means a grid in which a number of conductive lines are formed inside and / or on the outer peripheral surface of one non-conductive body.

Referring to FIG. 2, the structure of a multiple line grid array package will be described. The body 20 of the multiple line grid array package has four Ps with electrode lines (not shown) or input / output nodes 22 formed on the surface.
It has a structure in which CB layers 20a, 20b, 20c, and 20d are vertically stacked. Here, the electrode lines and the input / output node 22 are exposed on the uppermost PCB layer 20d of the package body 20, and the input / output node 22
Is electrically connected to the corresponding lower first and second electrode wires (not shown) by a conventional via contact method.

[0006] A semiconductor chip (not shown) is placed at the center of the package body 20. A multiple line grid 24 is attached to the input / output node 22, and an electric signal is supplied from an external power supply (not shown). 3A, 3B, and FIG.
As shown in FIGS.3C and 3D, multiple line grids 30
In the figure, a large number of conductor wires 32, 34, 36 and 38 are formed on the outer peripheral surface of a non-conductive body 31 or inside thereof.

[0007] Japanese Patent Application No. 10-309191 does not describe a specific configuration for electric circuit patterns formed on the upper and lower surfaces of a package body to which a multiple line grid is attached. More specifically, no specific configuration is described for the multiple line grid and the electrical circuit pattern, that is, the relationship between the electrode lines, the input / output nodes, and the via holes.

[0008]

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to use a multiple line grid having a large number of conductor lines and to arrange a large number of input / output nodes within a small area, so that the length of the electrode line is reduced. An object of the present invention is to provide an electric circuit pattern formed on the upper and lower surfaces of a package body, which can reduce a signal transmission delay and a noise.

The present invention provides a multiple line grid capable of suppressing signal transmission delay and noise and effectively reducing the number of layers, that is, the thickness of a package body, and a package provided with the multiple line grid. An object of the present invention is to provide a multiple line grid array package having an electric circuit pattern formed on an upper surface and a lower surface of a body.

[0010]

SUMMARY OF THE INVENTION The present invention has been made to achieve the above object, and a multiple line grid array package of the present invention comprises a first surface and a second surface opposite to the first surface. A package body, a first electric circuit pattern formed on a first surface of the package body and having a plurality of input / output nodes, and a second electric circuit pattern formed on a second surface of the package body. And a multiple line grid bonded to the package body and having a non-conductive grid body and a plurality of conductor lines formed on the inner and / or outer peripheral surface of the grid body, and formed on the grid. Part or all of the plurality of conductor lines are connected to input / output nodes of the first electric circuit pattern. Characterized in that it corresponds to the to-1.

Preferably, the package body has at least one layer, and the second electric circuit pattern has a plurality of electrode lines, wire bond pads, and via hole pads. Also, a plurality of input / output nodes of the first electric circuit pattern have various arrangements according to the positions of the conductor lines of the grid, and a part of the plurality of electric conductor lines has a first electric circuit pattern within an area where the grid is placed. And the remainder of the plurality of conductor lines are arranged on a first electric circuit pattern outside the area where the grid is placed,
A part of the plurality of via hole pads is arranged on a first electric circuit pattern within an area where a grid is placed, and the rest of the via hole pads are arranged on a first electric circuit pattern outside the area. preferable.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described below in detail with reference to the accompanying drawings. First, the structure of a multiple line grid having a large number of conductor wires described in Japanese Patent Application No. 10-309191 of the present applicant will be specifically described. As shown in FIG.3A, the multiple line grid applicable to the multiple line grid array package is rectangular, and has a large number of conductor lines 32 and a large number of grooves 31a.
And a grid body 31.

The grid shown in FIG. 3B also has a non-conductive grid main body 31 and a large number of conductor wires 34 formed on the outer peripheral surface of the non-conductive grid main body. As shown in FIG. 3B, a large number of semi-cylindrical conductor wires 34 are formed on the outer peripheral surface of the non-conductive grid main body 31 in parallel with the longitudinal direction of the grid. Many conductor wires are electrically insulated from each other.
As shown in FIG. 3C, a large number of cylindrical conductor wires 36 are formed inside the non-conductive grid main body 31, and the large number of conductor wires 36 are electrically insulated from each other. FIG. 3D shows a grid in which a large number of cylindrical conductor wires 38 are formed inside a non-conductive grid body 31 having a circular disk shape.
The multiple conductor wires 38 are electrically insulated from each other.

The conductor wires 32, 34, 36 and 38 shown in FIGS. 3A to 3D are formed such that the upper and lower surfaces thereof are slightly protruded from the upper and lower surfaces of the grid body 31. Therefore, as shown in FIGS. 4A and 4B, the grid 40 is attached to the package body 44 such that each of the protruding portions matches the corresponding input / output node 48. Of course,
It is obvious to those skilled in the art that the non-conductive grid body and the conductor wire can be changed to various other shapes.

In accordance with the present invention, each conductor line coated with a conductive material or placed inside the body of the grid, shown in FIGS. 3A-3D, serves as a unitary lead frame in conventional concepts. Therefore, one multiple line grid 30 has a large number of leads depending on the number of conductor lines 32, 34, 36, 38, and is therefore connected to a large number of input / output nodes.

For example, as shown in FIG. 3B, a grid 30 of a square disk shape has twelve conductor lines 34, and twelve input / output nodes are connected to one grid. Therefore, the conventional BG
The number of lead frames used for A, PGA, QFP packages and the like can be reduced to 1/12, and the surface area of the lead frame can be reduced to 1/12 or less. The same concept applies to FIGS. 3A, 3C and 3D.

FIG. 4A is a perspective view of a multiple line grid array package of the present invention, and a cross-sectional view taken along line II. As shown in FIGS.4A and 4B, the package body 44 has, for example, four PCB layers 44a, 44b, 44c and 44d, each of which is a non-conductive substrate, a metal electrode 42-1 or 42. -2 and via hole. As shown in FIG. 5B, an electric circuit pattern 47 having a number of corresponding input / output nodes 48 electrically connected to the conductor lines of the grid 40 is formed on the surface of the uppermost layer 44d. An electric circuit pattern 45 shown in FIG. 5A is provided on the bottom surface of the lowermost layer 44a.

Each of the package layers is thermally adhered to each other under pressure, and via holes 49 are made of conductive paste (paste).
Filled in e). A large number of electrodes 42-1 and 42-2 are formed on the respective upper surfaces of the package layers 44a, 44b, 44c and 44d, and the input / output node 48 is exposed on the uppermost surface of the package body 44.

As shown in FIGS. 4A and 4B, one grid 40 is connected to the same number of input / output nodes 48 as the number of conductor wires 41 formed on the inner and / or outer peripheral surface of the grid. That is, for example, in the multiple line grid shown in FIG. 3B, since 12 conductor lines 34 are formed on the outer peripheral surface of one grid body 31 having a square disk shape, the grid 30
It is connected to twelve input / output nodes. As shown in FIG. 4B, the input / output node 48 is bonded to the conductor wire 41 coated on the outer peripheral surface of the grid 40 by the solder 43. FIG. 4B shows two nodes. As described above, the grid is connected to the same number of input / output nodes as the number of conductor lines formed on the outer peripheral surface of the grid. The multiple line array package of the present invention includes an array type package, a chip scale package, a flip chip package, and a wafer level (wafer l) package.
evel) Package, connector, socket, wafer probe card (wafer probe)
card), land grid array (LGA), etc.

FIGS. 5A and 5B are plan views showing electric circuit patterns formed on the bottom and top surfaces of the package body. The electric circuit pattern formed on the package body has various forms according to the type of grid and the type of IC chip used. One of the important features of the present invention resides in the improvement of the electric circuit pattern formed on the bottom and top surfaces of the package body.

The electric circuit pattern of the present invention will be described in detail below. As shown in FIG. 5A, the bottom surface of the lowest layer of the package body 44 has a non-conductive substrate and an electric circuit pattern 45 formed on the surface of the substrate. Electric circuit pattern 45
Has a number of wire bond pads 52, a number of via hole pads 54, and a number of electrode lines 56. A large number of wire bond pads 52 may be formed on the package body by a wire bonding method, a wafer level packaging method, or a controlled collapsed chip connection method.
) is formed so as to be connected to the semiconductor chip by another connection method such as). The wire bond pads can be arranged on any area of the package body. Numerous via hole pads 54 serve to electrically connect layers of the package, and a large number of electrode lines are provided.
Reference numeral 56 serves to electrically connect the input / output node, the wire bond pad, and the via hole pad.

The top layer of the package body 44 shown in FIG. 5B
The electric circuit pattern 47 formed on the upper surface of 44d will be described in detail below. The electric circuit pattern shown in FIG. 5B is exemplary, and the present invention is not limited thereto. The pattern of the electric circuit is designed based on the following design rules.
For example, if the grid has eight conductor lines, as shown in FIG.
It is formed so as to correspond to each of the 40 conductor wires 41. The conductor wire 41 and the input / output node 48 are connected by solder 43 (see FIG. 4).

As shown in FIG. 5B, the arrangement of input / output nodes 48 forms a rectangular shape A. The arrangement of the input / output nodes has various shapes such as a triangular shape, a hexagonal shape, and an octagonal shape, and has various sizes according to the shape and size of the grid. Part of via hole pad 50a and electrode wire 4
6 are arranged outside the area A, for example, as shown in FIG.5B, grids, some other via hole pads 50b
The electrode lines 46a are arranged inside the area A where the grid is placed.

For example, as shown in FIG. 6, the design rule is that a maximum of three electrode lines 62a, 62b, 62c
It is placed between 64a and 64b, and the input / output node pitch is about 400μ
m, the diameter of the via hole is about 150 μm,
The line widths and gaps of the electrode lines 62a, 62b, 62c are about 75 μm, and each of the rectangular input / output nodes is about 200 μm × about 2 μm.
00 μm. At this time, 200 input / output nodes can be placed in a package body having two package layers, and the size of the package body is about 9.8 mm × about 9.8 mm.

This type of design rule can reduce manufacturing costs compared to other package designs, and has the smallest package board area and footprint on the PCB.
rint) area.

Even if the multiple line grid array package of the present invention is mounted on the surface of a printed circuit board and the input / output nodes are connected to the input / output nodes on the printed circuit board,
The design rules for the circuit patterns on the printed circuit board will be the same as the design rules described above. The electrical circuit patterns of the present invention include plastic and ceramic packages such as QFP, BGA, CSP and wafer level packages, connectors, sockets, wafer probe cards,
It can be applied to land grid arrays (LGA). Further, the electric circuit pattern of the present invention can be applied to a printed circuit board and a ceramic substrate used for a hybrid IC. Further, the electric circuit pattern of the present invention can be applied to ordinary PCB pattern design.

[0027]

According to the present invention, the gap between the grids is larger than the gap between the balls in the conventional package, so that more electrode lines can be arranged and a very small board area can be used. I / Os can be easily arranged. Also, since the grid can contain via holes, electrode wires, and the like inside the substrate area occupied by the uppermost layer of the package body, there is an advantage in space utilization. Therefore, since a large number of input / output nodes are arranged in a small area and the length of the electrode lines is reduced, a delay in signal transmission is suppressed, and an effect of noise reduction is obtained.

Although the present invention has been described with reference to the above embodiments, it will be apparent to those skilled in the art that various modifications can be obtained from the embodiments, and such modifications are also included in the scope of the present invention.

[Brief description of the drawings]

FIG. 1 is a partial plan view showing a part of an electric circuit pattern of a conventional FBGA package.

FIG. 2 is a perspective view schematically illustrating a multiple line grid array package having a multiple line grid disclosed in Japanese Patent Application No. 10-309191.

FIGS. 3A to 3D are perspective views showing the structure of a multiple line grid disclosed in Japanese Patent Application No. 10-309191.

FIG. 4A is a schematic perspective view showing a multiple line grid array package having a multiple line grid and an electric circuit pattern according to the present invention.

FIG. 4B is a cross-sectional view of the multiple line grid array package of the present invention, taken along line II of FIG. 4A, for explaining a coupling relationship between the package body and the multiple line grid.

FIG. 5A is a plan view showing an electric circuit pattern formed on the lower surface of the package body of the present invention.

FIG. 5B is a plan view showing an electric circuit pattern formed on the upper surface of the package body of the present invention.

FIG. 6 is a partial plan view showing a part of the electric circuit pattern of the present invention.

[Explanation of symbols]

 40: Multiple line grid 44: Package body 45: Lower electric circuit pattern 46: Electrode line 47: Upper electric circuit pattern 48: Input / output node 56: Electrode line

 ──────────────────────────────────────────────────続 き Continuing from the front page (72) Inventor Kim Sun Geun 175-7, Hyeongchang-dong, Jongno-gu, Seoul, South Korea 1-1103 Modern Heights Villa F-term (reference) 5E346 AA22 AA43 AA51 BB03 BB11 BB15 BB16 BB20 FF01 FF45 HH05 HH06 HH25

Claims (5)

[Claims] 1. A package body having a first surface and a second surface opposite to the first surface, and a first electric circuit formed on the first surface of the package body and having a number of input / output nodes. A pattern, a second electric circuit pattern formed on a second surface of the package body, and the package body;
A multiple line grid array package having a non-conductive grid body and a multiple line grid having a plurality of conductors formed on an inner and / or outer peripheral surface of the grid body, wherein the plurality of grids are formed on the grid. A multiple line grid array package, wherein a part or all of the conductors correspond one-to-one with the input / output nodes of the first electric circuit pattern. 2. The multiple line grid array package according to claim 1, wherein the package body has at least one layer. 3. The multiple line grid array according to claim 1, wherein the second electric circuit pattern has a plurality of electrode lines, wire bond pads, and via hole pads. package. 4. The multiple line grid array package according to claim 1, wherein a plurality of input / output nodes of the first electric circuit pattern have various arrangement forms according to positions of conductor lines of the grid. A part of the plurality of electrode lines is arranged in a first electric circuit pattern within an area where the grid is placed, and a remaining part of the plurality of electrode lines is arranged on a first electric circuit pattern outside the area where the grid is placed. The plurality of via-hole pads are arranged on a first electric circuit pattern within an area where the grid is placed, and the rest of the via-hole pads are arranged on a first electric circuit pattern outside the area. A multiple line grid array package characterized in that: 5. The multiple line grid array package according to claim 1, wherein a maximum of three electrode lines are arranged in a gap between adjacent grids on the first electric circuit pattern. Features a multiple line grid array package.