TWI845002B - Semiconductor package module and method for fabrication of the same - Google Patents
Semiconductor package module and method for fabrication of the same Download PDFInfo
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Description
本發明是有關於一種半導體封裝模組,特別是指一種具有電磁屏蔽功效的半導體封裝模組以及此半導體封裝模組的製造方法。The present invention relates to a semiconductor package module, in particular to a semiconductor package module with electromagnetic shielding effect and a manufacturing method of the semiconductor package module.
隨著電子產品功能多樣化的發展,電子產品內的半導體封裝模組需要容納越來越多的電子元件,而電子元件之間的裝設距離也逐漸縮減。為避免電子元件之間彼此干擾,必須在會相互影響的電子元件間設置電磁屏蔽材料(例如金屬),以達成電磁屏蔽的效果。就一般半導體封裝模組的電磁屏蔽而言,可分為阻絕單一模組內部的電子元件互相干擾的「模組內電磁屏蔽」以及阻絕多個模組之間的電子元件互相干擾的「模組間電磁屏蔽」。With the development of diversified functions of electronic products, the semiconductor package modules in electronic products need to accommodate more and more electronic components, and the installation distance between electronic components is gradually reduced. In order to avoid mutual interference between electronic components, electromagnetic shielding materials (such as metal) must be installed between the electronic components that will affect each other to achieve the electromagnetic shielding effect. As for the electromagnetic shielding of general semiconductor package modules, it can be divided into "intra-module electromagnetic shielding" to prevent mutual interference between electronic components in a single module and "inter-module electromagnetic shielding" to prevent mutual interference between electronic components in multiple modules.
模組內電磁屏蔽的製造方式是在電子元件被模封材料(molding compound)包覆之後,針對欲設置電磁屏蔽材料的區域進行雷射開槽。隨後,在槽中填入電磁屏蔽材料。這種先開槽後填充的做法,容易在填充電磁屏蔽材料時產生氣孔,進而影響電磁屏蔽的效果。The manufacturing method of electromagnetic shielding in the module is to laser cut grooves in the area where the electromagnetic shielding material is to be set after the electronic components are covered with molding compound. Then, the electromagnetic shielding material is filled in the groove. This method of cutting the groove first and then filling it is easy to produce air holes when filling the electromagnetic shielding material, thereby affecting the electromagnetic shielding effect.
另一方面,模組間電磁屏蔽的製造方式則是在切割包覆多個電子元件的模封材料而形成多個半導體封裝模組之後,通過濺鍍等方式在每個半導體封裝模組上形成電磁屏蔽層。然而,濺鍍製程易使電磁屏蔽層形成於封裝模組上不需要電磁屏蔽的部分,導致封裝模組受到電磁屏蔽層汙染而造成例如短路等問題。此外,在濺鍍製程中,各個封裝模組需要彼此分開並保持一定的間距,以確保能形成側向厚度足夠的電磁屏蔽層。然而,這種間隔放置的方式不僅額外佔據濺鍍腔體的空間,還必須耗費額外的時間來分開這些封裝模組,遂難以提升產能。On the other hand, the manufacturing method of electromagnetic shielding between modules is to form multiple semiconductor package modules by cutting the molding material covering multiple electronic components, and then forming an electromagnetic shielding layer on each semiconductor package module by sputtering or other methods. However, the sputtering process easily causes the electromagnetic shielding layer to be formed on the portion of the package module that does not require electromagnetic shielding, causing the package module to be contaminated by the electromagnetic shielding layer and causing problems such as short circuits. In addition, during the sputtering process, each package module needs to be separated from each other and maintain a certain distance to ensure that an electromagnetic shielding layer with sufficient lateral thickness can be formed. However, this spacing placement method not only takes up additional space in the sputtering chamber, but also requires additional time to separate these package modules, making it difficult to increase production capacity.
因此,本發明提供了一種半導體封裝模組以及其製造方法,藉以改善電磁屏蔽的效果與生產效率。Therefore, the present invention provides a semiconductor package module and a manufacturing method thereof to improve the electromagnetic shielding effect and production efficiency.
本發明提供了一種半導體封裝模組的製造方法,包含提供一線路基板,線路基板包含一第一表面與多個接地墊,其中接地墊位於第一表面上;在線路基板的一第一表面上,設置多個電子元件,其中電子元件的每一者位於接地墊的相鄰兩者之間;在接地墊的至少一者上,形成一導電結構,其中導電結構與第一表面的一部分形成至少一凹槽,且電子元件位於凹槽中;在凹槽的每一者中,填充一密封材料,其中密封材料完全覆蓋電子元件,並具有暴露於外界環境的一外表面;從外表面研磨導電結構與密封材料;在研磨導電結構與密封材料之後,在導電結構與密封材料上,形成一導電材料,其中導電材料電性連接於導電結構,而導電材料、導電結構以及線路基板完全包覆密封材料;以及沿著線路基板的法線方向切割導電材料、導電結構以及線路基板。The present invention provides a method for manufacturing a semiconductor package module, comprising providing a circuit substrate, the circuit substrate comprising a first surface and a plurality of ground pads, wherein the ground pads are located on the first surface; a plurality of electronic components are arranged on the first surface of the circuit substrate, wherein each of the electronic components is located between two adjacent ground pads; a conductive structure is formed on at least one of the ground pads, wherein the conductive structure and a portion of the first surface form at least one groove, and the electronic component is located in the groove; In one, a sealing material is filled, wherein the sealing material completely covers the electronic component and has an outer surface exposed to the external environment; the conductive structure and the sealing material are ground from the outer surface; after grinding the conductive structure and the sealing material, a conductive material is formed on the conductive structure and the sealing material, wherein the conductive material is electrically connected to the conductive structure, and the conductive material, the conductive structure and the circuit substrate completely cover the sealing material; and the conductive material, the conductive structure and the circuit substrate are cut along the normal direction of the circuit substrate.
本發明還提供一種半導體封裝模組,包含一線路基板,線路基板包含一第一表面、一第二表面以及多個接地墊,其中第一表面相對於第二表面,而接地墊設置於第一表面上;一導電結構,設置於第一表面上並電性連接接地墊的至少一者,其中導電結構在第一表面上形成至少一凹槽;至少一個電子元件,設置於凹槽,並電性連接線路基板;至少一個密封材料,填充於凹槽中,並包覆電子元件;一導電材料,設置於導電結構以及密封材料上,並覆蓋導電結構以及密封材料;以及多個焊料,設置於線路基板的第二表面上,其中導電結構包含一側表面,且其中導電材料不覆蓋導電結構的側表面。The present invention also provides a semiconductor package module, comprising a circuit substrate, the circuit substrate comprising a first surface, a second surface and a plurality of ground pads, wherein the first surface is opposite to the second surface, and the ground pad is arranged on the first surface; a conductive structure, arranged on the first surface and electrically connected to at least one of the ground pads, wherein the conductive structure forms at least one groove on the first surface; at least one electronic component, arranged in the groove and electrically connected to the circuit substrate; at least one sealing material, filled in the groove and covering the electronic component; a conductive material, arranged on the conductive structure and the sealing material, and covering the conductive structure and the sealing material; and a plurality of solders, arranged on the second surface of the circuit substrate, wherein the conductive structure comprises a side surface, and wherein the conductive material does not cover the side surface of the conductive structure.
基於上述,本發明的一特徵在於,先在電子元件周圍形成導電結構,以達成側向的電磁屏蔽,接著才將密封材料填入導電結構以及電子元件之間。此步驟順序可避免導電結構內部產生氣孔,確保側向電磁屏蔽的完整性,進而改善電磁屏蔽的效果。Based on the above, a feature of the present invention is that a conductive structure is first formed around the electronic component to achieve lateral electromagnetic shielding, and then the sealing material is filled between the conductive structure and the electronic component. This step sequence can avoid the formation of air holes inside the conductive structure, ensure the integrity of the lateral electromagnetic shielding, and thus improve the effect of electromagnetic shielding.
本發明至少一實施例揭露一種半導體封裝模組的製造方法,由圖1A至圖1H中的一系列步驟來說明本發明的至少一實施例。請參考圖1A所示,首先,提供線路基板100,其中線路基板100包含第一表面100f與多個接地墊102。接地墊102皆設置於線路基板100的同一面上。如圖1A所示,每一個接地墊102皆設置於線路基板100的第一表面100f上,並曝露於第一表面100f。At least one embodiment of the present invention discloses a method for manufacturing a semiconductor package module, and at least one embodiment of the present invention is described by a series of steps in FIG. 1A to FIG. 1H. Referring to FIG. 1A, first, a
在本實施例中,線路基板100還可包含介電層101,其中介電層101可以具有第一表面100f,而接地墊102可以凸出於第一表面100f。然而,在其他的實施例中,接地墊102可以不凸出於第一表面100f。舉例而言,接地墊102的頂面可以與第一表面100f切齊。此外,在其他的實施例中,線路基板100還可包含至少一層防焊層(solder mask,未繪示),其中防焊層可覆蓋第一表面100f並暴露接地墊102,並且凸出於這些接地墊102的頂面。In this embodiment, the
請接續參考圖1B所示,在線路基板100的第一表面100f上,設置多個電子元件104,且每個電子元件104可設置於相鄰的兩個接地墊102之間。設置於兩相鄰接地墊102之間的電子元件104並不限於一個,也可以是兩個以上的電子元件104。此外,除了接地墊102,線路基板100還可包含多個位於第一表面100f上的其他接墊(未繪示)。其中這些接墊可供電子元件104設置,以使電子元件104能通過這些接墊而電性連接線路基板100。Please continue to refer to FIG. 1B , on the
在本實施例中,電子元件104上更設置有多個焊點106,這些焊點106可以是錫球、銅柱或適用於電性連接的各種焊接結構。焊點106分別連接於上述接墊(未繪示),以使電子元件104可以通過這些焊點106與線路基板100電性連接。此外,在其他實施例中,可以利用打線的方式將電子元件104與線路基板100電性連接。其中電子元件104可以是已封裝的晶片(chip)或者未經封裝的晶粒(die)。In this embodiment, a plurality of
如圖1C所示,在設置電子元件104之後,隨後在線路基板100上形成導電結構108,且導電結構108與接地墊102其中至少一者直接接觸,以使導電結構108形成在其中至少一個接地墊102上。導電結構108可以包含例如導電膏、導電膠或其他具有電磁屏蔽功能的導電物質。在本揭露的至少一實施例中,可以利用噴塗、印刷、點膠或三維列印,在接地墊102上形成導電結構108,但形成導電結構108的方式不限於此。
As shown in FIG. 1C , after the
進一步而言,形成導電結構108更包含在接地墊102上形成多個導電層(未標示於圖中)。在如圖2所示的實施例中,導電結構108的材料可以為導電膏,並且包含多個導電層(未標示於圖中)。這些導電層沿著z軸方向堆疊,舉例而言,首先通過噴塗的方式在接地墊102上形成第一導電層109a,並對第一導電層109a進行預硬化。依照不同導電膏的特性,預硬化的方式可以是對導電層進行光照或者加熱。而對特定成分的導電膏而言,甚至可以省略預硬化的步驟。
Furthermore, forming the
隨後,以同樣的方式依序在第一導電層109a上形成第二導電層109b以及第三導電層109c。在本實施例中,第三導電層109c凸出於電子元件104的頂面。意即,在線路基板100上,導電結構108的高度(即厚度)大於電子元件104加上焊點106的總高度(即總厚度)。應特別注意,導電層的數量可以是一層以上,且不限於上述列舉的三層。
Subsequently, the second
請一併參考圖1C與圖3,其中圖3為圖1C中繪示的半導體封裝模組製造方法的上視圖。導電結構108與線路基板100的一部分形成至少一個凹槽110,其中導電結構108的形狀可為網狀,如圖3所示。具體來說,雖然從圖1C的剖視圖視角來看,導電結構108呈彼此分隔的多個單體,但導電結構108實質上為一連續壁結構,且此連續壁的側壁等同於凹槽110的側壁。導電結構108具有
遠離線路基板100並平行於x-y面的頂表面108t’,其中x-y面為平行於x軸與y軸的平面。由圖3可以得知,這些凹槽110彼此之間在x-y面上以導電結構108為分隔。雖然在本實施例中,凹槽110在x-y面上所呈現的形狀為長方形,但在其他各式各樣的實施例中,凹槽110在x-y面上所呈現的形狀不限於長方形。
Please refer to FIG. 1C and FIG. 3 together, wherein FIG. 3 is a top view of the semiconductor package module manufacturing method shown in FIG. 1C. The
如圖3所示,電子元件104分別設置於各個凹槽110中,且其中電子元件104不接觸導電結構108。在本實施例中,每一個凹槽110內僅設置一個電子元件104,然而,本發明其他實施例中單一凹槽110內的電子元件104數量不限於此,單一凹槽110內可設置兩個以上的電子元件104。
As shown in FIG. 3 , the
請接著參考圖1D所示,在形成導電結構108後,將密封材料112填入每一個凹槽110內,並使導電結構108與電子元件104完全隔離,即密封材料112能完全覆蓋電子元件104,以使導電結構108與電子元件104不會彼此接觸,且填充後的密封材料112可以在電子元件104的上方形成一個曝於外界環境的外表面112o’。密封材料112可以包含有機樹脂(如環氧樹脂)等絕緣材料或其相似物。
Please refer to FIG. 1D . After forming the
請一併參閱圖1D與圖1E,填充密封材料112之後,從頂表面108t’以及外表面112o’研磨導電結構108以及密封材料112,使得導電結構108與密封材料112分別形成新的頂表面108t以及新的外表面112o,其中頂
表面108t切齊外表面112o,如圖1E所示。在本發明的實施例中,可以通過例如雷射切割、離子束切割或者化學機械研磨等方式來研磨密封材料112以及導電結構108。
Please refer to FIG. 1D and FIG. 1E together. After filling the sealing
參考圖1E所示,在研磨密封材料112以及導電結構108之後,在線路基板100的第二表面100s上設置多個焊料114,且焊料114與線路基板100電性連接。應特別注意,在本實施例中,可以在上述研磨步驟之後直接設置焊料114,但在其他實施例中,設置焊料114的步驟與研磨步驟兩者順序不限於此。
Referring to FIG. 1E , after grinding the sealing
在設置焊料114以後,如圖1F所示,在密封材料112的外表面112o以及導電結構108的頂表面108t上形成導電材料116,從而形成半導體封裝連板10。具體而言,半導體封裝連板10可以是工作連板(working panel)或基板條(strip),所以半導體封裝連板10包含多個線路板單元(unit)。換句話說,一塊半導體封裝連板10可以製造出多個半導體封裝模組。
After the
導電材料116必須完全覆蓋密封材料112的外表面112o並且與導電結構108的頂表面108t相接,以在電子元件104周圍形成一個完整的遮蔽,進而達成電磁屏蔽的效果。在本發明的部分實施例中,形成導電材料116的方法可包含沉積,例如物理氣相沉積、化學氣相沉積或其他合適的製程,其中前述物理氣相沉積可以是濺鍍。如此,導電材料116能沉積在密封材料112的外表面112o以及導電結構108的頂表面108t兩者所形成的共平面
上。
The
在形成導電材料116之後,遂對半導體封裝連板10進行切割。如圖1G所示,以線路基板100的第二表面100s為起始,沿著線路基板100的法線方向切割,也就是從第二表面100s切割線路基板100。其中在切割過程中,刀具(未標示)依序通過線路基板100、導電結構108以及導電材料116,以形成多個完全分割的半導體封裝模組12,如圖1H所示。
After the
為達成電子元件104之間的電磁屏蔽,切割路徑必須位於兩相鄰的半導體封裝模組12之間。換句話說,切割路徑必須位於兩相鄰的電子元件104之間,並且通過線路基板100、導電結構108以及導電材料116。除此之外,切割路徑還必須不通過密封材料112,即不切割密封材料112,方可形成完整的電磁屏蔽。
In order to achieve electromagnetic shielding between
本發明更揭露一種半導體封裝模組,如圖4所示,本發明的一實施例的半導體封裝模組40包含線路基板400、導電結構408、電子元件404、密封材料412、導電材料416以及焊料414。線路基板400包含第一表面400f以及相對於第一表面400f的第二表面400s,並且包含多個接地墊402,其中接地墊402位於線路基板400的第一表面400f上。
The present invention further discloses a semiconductor package module. As shown in FIG4 , a
須說明的是,線路基板400的結構可實質上相同於圖1A中的線路基板100,其中接地墊402可與接地墊102相同。線路基板400與線路基板100兩者之間的主要
差異在於尺寸不同。前述實施例中的線路基板100可以為工作連板或基板條,而本實施例中的線路基板400可以為線路板單元。
It should be noted that the structure of the
請繼續參考圖4,導電結構408位於至少一個接地墊402上,並與接地墊402直接接觸。以圖4為例,導電結構408可直接接觸多個接地墊402。不過,在其他實施例中,導電結構408可以僅直接接觸單一個接地墊402。導電結構408具有一頂表面408t,此頂表面408t遠離線路基板400的第一表面400f。其中導電結構408的部分側表面408w與第一表面400f的一部分形成至少一個凹槽410。凹槽410中包含至少一個電子元件404,且電子元件404的數量則依照不同元件封裝的需求變動。
Please continue to refer to FIG. 4 , the
在本實施例中,電子元件404與線路基板400之間以多個焊點406電性連接,而焊點406不限於錫球,可以是適用於電性連接的各種焊接結構,例如焊柱。另一方面,裝設後的電子元件404仍須保持在凹槽410中,意即電子元件404連接焊點406後的高度(即厚度),不會超出導電結構408的頂表面408t。
In this embodiment, the
導電結構408可以包含能夠在線路基板400上沿著z軸方向層疊成型的材料,例如印刷導電膏、導電膠或相似的材料。但在其他實施例中,導電結構408的材料不限於此。
The
而在每一個凹槽410內,還包含了密封材料412,此密封材料412具有一外表面412o,且導電結構408的
頂表面408t與此外表面412o呈共平面。密封材料412填充於凹槽410中,並且填滿於電子元件404以及導電結構408之間的空隙,其中密封材料412完全包覆電子元件404,使電子元件404隔絕於導電結構408以及導電材料416。
Each
導電材料416設置於導電結構408以及密封材料412上,並且覆蓋於頂表面408t以及外表面412o所構成的共平面。由圖4可得,導電材料416完全覆蓋密封材料412的外表面412o並與導電結構408相連接,以形成一電磁屏蔽外殼。其中導電材料416分別與導電結構408以及密封材料412直接接觸。
The
雖然在本實施例中,導電材料416完全覆蓋導電結構408的頂表面408t,但在其他實施例中,導電材料416可以僅覆蓋導電結構408的頂表面408t的一部分。應特別注意,其中導電材料416不覆蓋導電結構408的側表面408w,且密封材料412暴露導電結構408的側表面408w的一部分。由圖4可以看出,此一部分屬於側表面408w的外側部分,而此處的「外側」是指半導體封裝模組40與外界接觸的一側(相對來說,側表面的「內側」部分則是指形成凹槽410的部分側表面408w)。此外,多個焊料414位於線路基板400的第二表面400s上,並且與線路基板400電性連接。其中焊料414可以包含錫、銅、銀、銦、鋅等適用於焊接的金屬及其合金。
Although in the present embodiment, the
綜上所述,本發明的實施例中,通過半導體封裝模 組側邊的導電結構以及頂部的導電材料,形成能電磁屏蔽電子元件的遮蔽結構。在製造方法的實施例方面,由於先形成側邊的導電結構,接著才在導電結構與線路基板共同形成的凹槽內填入密封材料,因此相較於一般的後填充(在已成型的模封材料上開槽,並在槽內填入導電結構)方法,依照上述實施例製造方法所揭示的順序,有助於形成不含氣孔的導電結構,進而提升電磁屏蔽的功效,並達到外觀平整的效果。 In summary, in the embodiment of the present invention, a shielding structure capable of electromagnetically shielding electronic components is formed by the conductive structure on the side of the semiconductor package module and the conductive material on the top. In the embodiment of the manufacturing method, since the conductive structure on the side is formed first, and then the sealing material is filled into the groove formed by the conductive structure and the circuit substrate, compared with the general post-filling method (grooving on the molded molding material and filling the conductive structure into the groove), the sequence disclosed in the manufacturing method of the above embodiment is helpful to form a conductive structure without pores, thereby improving the electromagnetic shielding effect and achieving a smooth appearance.
另一方面,由於導電結構已先形成側面的電磁屏蔽,當後續沉積頂部的電磁屏蔽層時,可在連板的狀態下進入沉積腔體,不需要再預留間隔放置的空間予側面沉積,故可提升沉積腔體的空間利用率,並省下分開多個半導體封裝模組的時間,進而提高產能。進一步而言,在沉積電磁屏蔽材料的過程中,沉積物質易汙染到模組底部的線路基板。相較於切割後的多個單板,未經切割的連板底部距離模組上方沉積範圍較遠,使得沉積物須經過較長路徑方能到達連板底部,故能降低線路基板(半導體封裝模組底部)被汙染的風險。 On the other hand, since the conductive structure has already formed the electromagnetic shielding on the side, when the electromagnetic shielding layer on the top is subsequently deposited, it can enter the deposition chamber in a connected state, and there is no need to reserve space for side deposition, so the space utilization of the deposition chamber can be improved, and the time of separating multiple semiconductor packaging modules can be saved, thereby improving production capacity. Furthermore, in the process of depositing electromagnetic shielding materials, the deposited substances are easy to contaminate the circuit substrate at the bottom of the module. Compared with multiple single boards after cutting, the bottom of the uncut connected board is farther away from the deposition range above the module, so the deposition must pass through a longer path to reach the bottom of the connected board, thus reducing the risk of contamination of the circuit substrate (the bottom of the semiconductor package module).
雖然本發明的實施例已揭露如上,然其並非用以限定本發明的實施例,任何所屬技術領域中具有通常知識者,在不脫離本發明實施例的精神和範圍內,當可作些許的更動與潤飾,故本發明實施例的保護範圍當視後附的申請專利範圍所界定者為準。 Although the embodiments of the present invention have been disclosed above, they are not intended to limit the embodiments of the present invention. Anyone with ordinary knowledge in the relevant technical field can make some changes and modifications without departing from the spirit and scope of the embodiments of the present invention. Therefore, the protection scope of the embodiments of the present invention shall be subject to the scope of the attached patent application.
10:半導體封裝連板 10: Semiconductor package connecting board
100、400:線路基板 100, 400: Circuit board
100f、400f:第一表面 100f, 400f: first surface
100s、400s:第二表面 100s, 400s: Second surface
101:介電層 101: Dielectric layer
102、402:接地墊 102, 402: Grounding pad
104、404:電子元件 104, 404: Electronic components
106、406:焊點 106, 406: Soldering points
108、408:導電結構 108, 408: Conductive structure
108t、108t’、408t:頂表面 108t, 108t’, 408t: top surface
109a:第一導電層 109a: first conductive layer
109b:第二導電層 109b: Second conductive layer
109c:第三導電層 109c: The third conductive layer
110、410:凹槽 110, 410: groove
112、412:密封材料 112, 412: Sealing material
112o、112o’、412o:外表面 112o, 112o’, 412o: outer surface
114、414:焊料 114, 414: Solder
116、416:導電材料 116, 416: Conductive materials
12、40:半導體封裝模組 12, 40: Semiconductor packaging module
408w:側表面 408w: side surface
圖1A至圖1H繪示本發明至少一實施例的半導體封裝模組製造方法的剖面圖。 圖2繪示圖1C的半導體封裝模組製造方法的另一實施例的剖面圖。 圖3繪示圖1C的半導體封裝模組製造方法的上視圖。 圖4繪示本發明至少一實施例的半導體封裝模組的剖面圖。 Figures 1A to 1H show cross-sectional views of a method for manufacturing a semiconductor package module according to at least one embodiment of the present invention. Figure 2 shows a cross-sectional view of another embodiment of the method for manufacturing a semiconductor package module according to Figure 1C. Figure 3 shows a top view of the method for manufacturing a semiconductor package module according to Figure 1C. Figure 4 shows a cross-sectional view of a semiconductor package module according to at least one embodiment of the present invention.
40: 半導體封裝模組
400: 線路基板
400f: 第一表面
400s: 第二表面
402: 接地墊
404: 電子元件
406:焊點
408: 導電結構
408w: 側表面
408t: 頂表面
410: 凹槽
412: 密封材料
412o: 外表面
414: 焊料
416: 導電材料
40: semiconductor package module
400:
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| TW201826487A (en) * | 2017-01-12 | 2018-07-16 | 美商艾馬克科技公司 | Semiconductor package with electromagnetic interference shielding and manufacturing method thereof |
| US20180240759A1 (en) * | 2017-02-23 | 2018-08-23 | Qorvo Us, Inc. | Integrated module with electromagnetic shielding |
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| TW201826487A (en) * | 2017-01-12 | 2018-07-16 | 美商艾馬克科技公司 | Semiconductor package with electromagnetic interference shielding and manufacturing method thereof |
| US20180240759A1 (en) * | 2017-02-23 | 2018-08-23 | Qorvo Us, Inc. | Integrated module with electromagnetic shielding |
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