TWI844687B - Wiring board having impervious base and embedded component and semiconductor assembly using the same - Google Patents

Abstract

A wiring board includes a multi-layer resin component or a heat dissipation component incorporated with an impervious base and a metallic sealing layer covering a binding layer between the multi-layer resin component and the impervious base or the heat dissipation component and the impervious base. The multi-layer resin component can create multi-layer routing capability within the impervious base, whereas the heat dissipation component offers a locally high heat conduction channel within the impervious base. The metallic sealing layer can prevent passage of moisture through the binding layer to protect a semiconductor device mounted on the top side of the impervious base or the heat dissipation component from moisture damage.

Description

Circuit board with anti-seepage base and embedded component and semiconductor assembly thereof

The present invention relates to a circuit board, and more particularly to a circuit board and a semiconductor assembly combining an embedded component with an anti-seepage base.

High-performance microprocessors and ASICs require high-performance circuit boards for signal interconnection. However, resin laminates are known to have a tendency to absorb moisture, thereby reducing the reliability of the assembly. In some applications, ceramic materials such as alumina or aluminum nitride have become popular material choices for hermetic packaging due to their ideal electrical insulation, high mechanical strength, low CTE (coefficient of thermal expansion) and good thermal conductivity. Therefore, multi-layer ceramic substrates have been developed based on such applications, including HTCC (high temperature co-fired ceramics) or LTCC (low temperature co-fired ceramics). However, manufacturing multi-layer circuit ceramic boards is very expensive and it is difficult to carry out fine wire routing.

In view of the various development stages and limitations of recent substrates, there is a pressing need to improve the electrical, thermal, and mechanical performance of substrates.

The object of the present invention is to provide a circuit board with a heterogeneous component incorporated therein. The circuit board has the following characteristics: a multi-layer resin component or a heat dissipation component is arranged in an impermeable base to establish a multi-layer wiring capability or a local high thermal conductivity path in the impermeable base.

Another object of the present invention is to provide a circuit board with a metal sealing layer, wherein the metal sealing layer covers a bonding layer between two heterogeneous materials to prevent moisture from passing through the bonding layer, thereby improving the reliability of the semiconductor assembly.

In accordance with the above and other purposes, the present invention provides a circuit board, comprising: an impermeable base having a top circuit on its top side, a bottom circuit on its bottom side, and an opening, wherein the water absorption rate of the impermeable base is 1% or less, and the inner side wall of the opening extends through the impermeable base between the top side and the bottom side; an embedded component disposed in the opening of the impermeable base; a bonding layer filling the gap between the outer peripheral side wall of the embedded component and the inner side wall of the opening, wherein the elastic modulus of the bonding layer is lower than the elastic modulus of the impermeable base; and a metal sealing layer completely covering the bottom surface of the bonding layer.

The present invention also provides a semiconductor assembly, which includes: the above-mentioned circuit board; a semiconductor device electrically connected to the circuit board; and an anti-seepage cover attached to the top side of the anti-seepage base to seal the semiconductor device inside.

The above and other features and advantages of the present invention will become more apparent through the following detailed description of the preferred embodiments.

In the following, an embodiment will be provided to illustrate the implementation of the present invention in detail. The advantages and effects of the present invention will be more obvious through the content disclosed by the present invention. The drawings attached hereto are simplified and used as examples. The number, shape and size of the components shown in the drawings can be modified according to the actual situation, and the configuration of the components may be more complicated. The present invention can also be practiced or applied in other aspects, and various changes and adjustments can be made without departing from the spirit and scope defined by the present invention.

[Example 1]

1-10 are diagrams of a method for manufacturing a circuit board in the first embodiment of the present invention, wherein the circuit board includes an anti-seepage base, an embedded component, a bonding layer, a stress adjustment component, a conductive layer, and a metal sealing layer.

Figures 1 and 2 are respectively a cross-sectional view and a top schematic view of the anti-seepage base 20 in the first embodiment of the present invention. In this embodiment, the anti-seepage base 20 includes an anti-seepage insulating layer 21, a top metal layer 23, a bottom metal layer 25 and a metallized through hole 27. The anti-seepage insulating layer 21 can be made of an inorganic material, and its water absorption rate is preferably less than 1% to meet the moisture-proof requirements. The top metal layer 23 and the bottom metal layer 25 are usually unpatterned copper layers, which are respectively located on the top and bottom sides of the anti-seepage insulating layer 21. Metallized through holes 27 extend through the barrier insulating layer 21 to provide electrical connection between the top metal layer 23 and the bottom metal layer 25.

3 and 4 are respectively a cross-sectional view and a top schematic view of an opening 205 formed in the anti-seepage base 20. The opening 205 has an inner wall extending from the top side to the bottom side of the anti-seepage base 20. The opening 205 of the anti-seepage base 20 can be formed by a variety of techniques, such as stamping, drilling or laser cutting.

5 and 6 are respectively a cross-sectional view and a top schematic view of the embedded member 30 inserted into the opening 205 of the anti-seepage base 20. The thickness of the embedded member 30 is substantially equal to the thickness of the anti-seepage base 20. The inner side wall of the opening 205 of the anti-seepage base 20 laterally surrounds the outer side wall of the embedded member 30 and is spaced from the outer side wall of the embedded member 30. Therefore, a gap 206 is located in the opening 205 between the inner side wall of the anti-seepage base 20 and the outer side wall of the embedded member 30. The gap 206 laterally surrounds the embedded member 30 and is laterally surrounded by the anti-seepage base 20. In this embodiment, the embedded component 30 is a multi-layer resin component, which generally has a higher thermal expansion coefficient and a lower elastic modulus than the anti-seepage base 20, and includes a plurality of resin layers 31, a plurality of inner wiring layers 33, a top metal film 35 and a bottom metal film 37. The resin layer 31 and the inner wiring layer 33 are formed alternately, and the top metal film 35 and the bottom metal film 37 completely cover the topmost resin layer 31 and the bottommost resin layer 31 from above and below, respectively. The inner wiring layer 33 is usually a patterned copper layer, and is electrically connected to each other and to the top metal film 35 through the metallized through-holes 39 in the resin layer 31. The top and bottom metal films 35, 37 are usually unpatterned copper layers, and their flat outer surfaces are substantially coplanar with the flat outer surfaces of the top and bottom metal layers 23, 25 of the barrier base 20.

7 and 8 are respectively a cross-sectional view and a top schematic view of the bonding layer 53 distributed in the gap 206. The bonding layer 53 (usually made of resin) fills the gap 206 and laterally covers, surrounds and conformally covers the inner side wall of the anti-seepage base 20 and the outer peripheral side wall of the embedded component 30. The bonding layer 53 provides a strong mechanical bond between the anti-seepage base 20 and the embedded component 30, and has a top surface and a bottom surface that are substantially coplanar with the outer surfaces of the top and bottom metal layers 23, 25 of the anti-seepage base 20 and the outer surfaces of the top and bottom metal films 35, 37 of the embedded component 30. Preferably, the elastic modulus of the bonding layer 53 is lower than the elastic modulus of the barrier substrate 20 to absorb stress caused by any mismatch in the coefficient of thermal expansion (CTE) between the barrier substrate 20 and the embedded component 30. For example, the elastic modulus of the bonding layer 53 can be less than 10 GPa to effectively release the thermo-mechanically induced stress in the heterogeneous materials. In addition, the bonding layer 53 preferably has a sufficient width of greater than 10 microns (preferably 25 microns or greater) in the gap 206 to absorb stress. To achieve significant results, a plurality of stress adjustment members 55 (whose CTE is lower than that of the bonding layer 53) can be dispersed in the bonding layer 53 to form a modified bonding matrix 50 in the gap 206, thereby effectively reducing the risk of resin cracking. Preferably, the CTE of the stress adjustment member 55 is at least 10 ppm/°C lower than the CTE of the bonding layer 53 to exhibit a significant effect. In this embodiment, the modified bonding substrate 50 contains at least 30% (volume percentage) of the stress adjustment member 55 based on the total volume of the gap 206, and the modified bonding substrate 50 preferably has a thermal expansion coefficient of 50 ppm/°C. Therefore, during thermal cycling, the internal expansion and contraction of the modified bonding substrate 50 can be slowed down to prevent cracking.

9 and 10 are respectively a cross-sectional view and a top schematic view of a structure having a top circuit 22, a bottom circuit 24, an external wiring layer 33, a conductive layer 62 and a metal sealing layer 64. The entire top surface of the structure can be metallized by various techniques such as electroplating, electroless plating, evaporation, sputtering or a combination thereof to form a top coating layer 63 (usually a copper layer) of a single-layer or multi-layer structure. For example, the entire top surface of the structure may be first exposed to electroless copper by immersing the structure in an activator solution, followed by electroless plating of a thin copper layer as a seed layer, and then electroplating a second copper layer of desired thickness onto the seed layer. Alternatively, the seed layer may be sputtered to form a thin film of a titanium/copper seed layer onto the entire top surface of the structure before depositing an electroplated copper layer onto the seed layer. Subsequently, through the metal patterning process of the top coating layer 63 and the top metal layer 23 and the top metal film 35, the top circuit 22 and the top wiring layer 33 can be formed on the top sides of the anti-seepage base 20 and the embedded component 30, respectively, and the conductive layer 62 is provided on the top surface of the bonding layer 53. The top circuit 22 of the anti-seepage base 20 has a combined thickness of the top metal layer 23 and the top coating layer 63, and is electrically connected to the top wiring layer 33 of the embedded component 30 through the conductive layer 62 on the top surface of the bonding layer 53. The top wiring layer 33 of the embedded component 30 has a combined thickness of the top metal film 35 and the top coating layer 63 and can serve as an electrical contact for chip connection. The conductive layer 62 has a thickness of the top coating layer 63 (approximately 0.5 to 50 microns) at its top surface contacting the bonding layer 53 and is integrally formed with the top circuit 22 and selected portions of the top wiring layer 33.

Furthermore, the entire bottom surface of the structure can also be metallized using the same activator solution, electroless copper seed layer, and electroplated copper layer to form a bottom coating layer 65. Once the desired thickness is reached, a metal patterning process is performed to form the bottom circuit 24 and the metal sealing layer 64. The bottom circuit 24 of the barrier base 20 has the combined thickness of the bottom metal layer 25 and the bottom coating layer 65, and is electrically connected to the top circuit 22 through the metallized through hole 27. The metal sealing layer 64 has the thickness of the bottom coating layer 65 (approximately 0.5 to 50 microns) and completely covers the bottom surface of the bonding layer 53. In this figure, the metal sealing layer 64 is integrated with the bottom metal film 37 of the embedded component 30 and the bottom metal layer 25 of the waterproof base 20, and extends laterally from the bottom metal film 37 to the bottom metal layer 25 of the waterproof base 20.

Since copper is a homogenous coating, the boundaries between metal layers may be difficult to detect or even undetectable. However, the boundaries between the top coating layer 63 and the bonding layer 53 and between the bottom coating layer 65 and the bonding layer 53 are clearly visible. Metal patterning techniques include wet etching, electrochemical etching, laser-assisted etching, and combinations thereof, and use an etching mask (not shown) to define the top circuit 22, the bottom circuit 24, the external wiring layer 33, the conductive layer 62, and the metal sealing layer 64.

Accordingly, as shown in FIGS. 9 and 10 , the completed circuit board 100 includes an impermeable base 20, an embedded component 30, a modified bonding matrix 50, a conductive layer 62, and a metal sealing layer 64. The impermeable base 20 laterally surrounds the outer peripheral side wall of the embedded component 30, and its water absorption rate is 1% or less, and can serve as a moisture barrier. The embedded component 30 of the present embodiment is shown as a multi-layer resin component, which provides a multi-layer wiring capability in the impermeable base 20. The low modulus bonding layer 53 not only provides a mechanical bonding force between the inner side wall of the impermeable base 20 and the outer peripheral side wall of the embedded component 30, but also provides a buffering effect to reduce the heat-induced stress between the impermeable base 20 and the embedded component 30. In particular, by adding the stress adjustment member 55 to the bonding layer 53, the risk of cracking caused by severe internal expansion and contraction of the bonding layer 53 can be reduced, thereby ensuring the reliability of the circuit board 100. The wiring layer 33 of the embedded component 30 is electrically connected to the top circuit 22 of the anti-seepage base 20 through the conductive layer 62, and is electrically connected to the bottom circuit 24 of the anti-seepage base 20 through the metallized through hole 27 of the anti-seepage base 20. The metal sealing layer 64 completely covers the bonding layer 53, the embedded component 30, and the interface between the waterproof base 20 and the bonding layer 53 and between the embedded component 30 and the bonding layer 53 from below, and further extends laterally below the bottom side of the waterproof base 20.

FIG11 is a cross-sectional view of a semiconductor assembly in which a semiconductor device 71 is electrically connected to the circuit board of FIG9. The semiconductor device 71 (shown as a chip) is mounted on the top side of the anti-seepage base 20 and is electrically connected to the top wiring layer 33 of the embedded component 30 and the top circuit 22 of the anti-seepage base 20 through bonding wires 81.

FIG. 12 is a cross-sectional view of the semiconductor assembly of FIG. 11 with an anti-seepage cover 91 on the circuit board 100. The anti-seepage cover 91 is installed on the top side of the anti-seepage base 20 to seal the semiconductor device 71 from above. To meet the moisture-proof requirements, the water absorption rate of the anti-seepage cover 91 is preferably 1% or less, and its CTE can match the CTE of the anti-seepage base 20 to reduce the peeling or cracking phenomenon at the interface caused by CTE mismatch. The semiconductor device 71 can be protected from moisture damage through the anti-seepage base 20 and the anti-seepage cover 91. Furthermore, since the metal sealing layer 64 completely covers the embedded component 30 and the bonding layer 53 from below, it is possible to prevent moisture from the surrounding environment from entering the interior of the semiconductor assembly through the resin embedded component 30 and the bonding layer 53.

[Example 2]

FIG. 13 is a cross-sectional view of a circuit board according to a second embodiment of the present invention.

For the purpose of brief description, any description in the above-mentioned embodiment 1 that can be used for the same application is incorporated here, and there is no need to repeat the same description.

The circuit board 200 is similar to the structure shown in FIG. 9 , except that the embedded component 30 is a heat dissipation component having a higher thermal conductivity than the waterproof base 20, and the metal sealing layer 64 does not completely cover the bottom side of the embedded component 30. In this embodiment, the water absorption rate of the embedded component 30 is preferably 1% or less to meet the moisture-proof requirements, and it includes an electrical isolation component 32, a top wiring layer 34, a bottom wiring layer 36 and metallized through holes 38. The electrical isolation component 32 can be made of a thermally conductive and electrically insulating inorganic material, and its water absorption rate is preferably less than or equal to 1%, and its thermal conductivity is higher than the thermal conductivity of the waterproof insulating layer 21. The top wiring layer 34 and the bottom wiring layer 36 are usually patterned copper layers, which are respectively located at the top and bottom sides of the electrical isolation member 32. The metallized through-holes 38 extend through the electrical isolation member 32 to provide electrical connection between the top wiring layer 34 and the bottom wiring layer 36. The top circuit 22 of the anti-seepage base 20 is electrically connected to the top wiring layer 34 of the embedded component 30 through the conductive layer 62 on the top surface of the bonding layer 53. The bottom circuit 24 of the anti-seepage base 20 is electrically connected to the top circuit 22 through the metallized through-holes 27. The metal sealing layer 64 completely covers the bottom surface of the bonding layer 53 and further extends laterally below the bottom sides of the impermeable base 20 and the embedded member 30. In the case where the CTE of the electrical isolator 32 matches the CTE of the impermeable base 20, the stress adjuster 55 may be unnecessary because even if the stress adjuster 55 is not dispersed in the bonding layer 53, the cracking problem of the low modulus bonding layer 53 will not be very serious.

FIG14 is a cross-sectional view of a semiconductor assembly in which a semiconductor device 71 is electrically connected to the circuit board 200 of FIG13. The semiconductor device 71 is flip-chip mounted on the top wiring layer 34 of the embedded component 30 through solder bumps 83, and the anti-seepage cover 91 is mounted on the top side of the anti-seepage base 20. Accordingly, the semiconductor device 71 is sealed in a moisture-proof shield formed by the anti-seepage base 20, the anti-seepage isolator 32, and the anti-seepage cover 91. In particular, since the metal sealing layer 64 completely covers the bottom surface of the bonding layer 53 and the interface between the waterproof base 20 and the bonding layer 53 and between the embedded component 30 and the bonding layer 53, it can limit the passage of moisture through the crack interface between the heterogeneous materials to protect the semiconductor device 71 from moisture damage. In addition, through the good thermal conductivity of the electrical isolation member 32, the embedded component 30 can provide a main heat conduction path for the semiconductor device 71 to effectively dissipate the heat generated by the semiconductor device 71.

[Example 3]

FIG. 15 is a cross-sectional view of a circuit board according to a third embodiment of the present invention.

For the purpose of brief description, any descriptions in the above embodiments that can be used for the same application are combined here, and there is no need to repeat the same descriptions.

The circuit board 300 is similar to the structure shown in FIG. 13 , except that the present embodiment uses a metal block as the embedded component 30. In addition to the metal sealing layer 64 below the embedded component 30 and the bonding layer 53, an additional metal sealing layer 66 is also provided to completely cover the top side of the embedded component 30 and the top surface of the bonding layer 53, and further extend laterally to the top side of the waterproof base 20. Therefore, the double metal sealing layers 64 and 66 completely cover the embedded component 30 and the bonding layer 53 from below and above, as well as the interface between the waterproof base 20 and the bonding layer 53 and between the embedded component 30 and the bonding layer 53, and further extend laterally to the top and bottom sides of the waterproof base 20.

FIG16 is a cross-sectional view of a semiconductor assembly in which a semiconductor device 71 is electrically connected to the circuit board 300 of FIG15. The semiconductor device 71 is mounted on the top metal sealing layer 66 and is electrically connected to the top circuit 22 of the impermeable base 20 through the bonding wire 81. In addition, an impermeable cover 91 is mounted on the top side of the impermeable base 20 to seal the semiconductor device 71 from above. Accordingly, the combination of the impermeable base 20, the double metal sealing layers 64, 66 and the impermeable cover 91 can prevent moisture from entering the interior of the semiconductor assembly from the surrounding environment. In addition, the heat generated by the semiconductor device 71 can be transferred to the embedded component 30 and further dissipated to the metal sealing layer 64 having a larger heat dissipation surface area than the embedded component 30.

The above-mentioned circuit boards and assemblies are merely illustrative examples, and the present invention can be implemented through many other embodiments. In addition, the above-mentioned embodiments can be used in combination with each other or with other embodiments based on design and reliability considerations. For example, the anti-seepage base can include a plurality of openings arranged in an array shape, and each opening can accommodate an embedded component therein.

As shown in the above embodiments, the present invention constructs a unique circuit board with better reliability. In a preferred embodiment, the anti-seepage base is bonded to and located around the outer peripheral side wall of the embedded component through the bonding layer, and the metal sealing layer completely covers the bottom surface of the bonding layer. As needed, the embedded component can be a multi-layer resin component for multi-layer wiring capability or a heat dissipation component as a local high thermal conductivity channel.

The multi-layer resin component generally has a higher coefficient of thermal expansion than the anti-seepage base and a lower elastic modulus than the anti-seepage base, and may include a plurality of wiring layers and a plurality of resin layers formed alternately to provide a multi-layer wiring capability for the circuit board. The top wiring layer and the inner wiring layer are patterned metal layers and are electrically connected to each other through metallized through-holes in the resin layer. Optionally, the multi-layer resin component may further include a bottom metal film that completely covers the bottom resin layer from below and/or one or more electrical components (such as resistors, capacitors, inductors, or any other active or passive components) embedded in the resin layer and electrically coupled to the wiring layer.

The heat sink preferably has a higher thermal conductivity than the impermeable base to provide primary heat conduction to the semiconductor device mounted thereon. The heat sink may be a metal block, or may include an electrical isolator and an optional top wiring layer, a bottom wiring layer, and metallized through holes. The electrical isolator may be made of a thermally conductive non-metallic material with a water absorption rate of 1% or less. The top wiring layer and the bottom wiring layer are respectively disposed on the top and bottom sides of the electrical isolator, and are electrically connected to each other through metallized through holes extending through the electrical isolator between the top and bottom sides. Accordingly, the heat sink not only provides a local high thermal conductivity channel in the waterproof base, but also provides an electrical contact for device connection.

The impermeable base surrounds the outer peripheral side wall of the embedded component, and its inner side wall is separated from the outer peripheral side wall of the embedded component and attached to the outer peripheral side wall of the embedded component by a bonding layer. In order to have the desired moisture-proof properties, the water absorption rate of the impermeable base is preferably 1% or less. In a preferred embodiment, the impermeable base includes a top circuit located on its top side, a bottom circuit located on its bottom side, and metallized through holes contacting the top circuit and the bottom circuit. The top circuit can be electrically connected to the top wiring layer of the embedded component through a conductive layer contacting the top surface of the bonding layer. The metallized through hole extends through the top and bottom sides of the anti-seepage base and serves as a vertical signal transmission channel. Therefore, the top wiring layer of the embedded component can be electrically connected to the bottom circuit of the anti-seepage base through the conductive layer, the top circuit and the metallized through hole. The conductive layer is integrally formed with the top wiring layer of the embedded component and the top circuit of the anti-seepage base, and the thickness of the conductive layer can be equal to or less than the thickness of the top wiring layer and the top circuit.

The bonding layer laterally covers, surrounds and conformally coats the opening side walls of the impermeable base and the outer peripheral side walls of the embedded component to provide a strong mechanical bonding force between the impermeable base and the embedded component. Preferably, the elastic modulus of the bonding layer is lower than the elastic modulus of the impermeable base and the embedded component to absorb the stress caused by any mismatch in the coefficient of thermal expansion (CTE) between the impermeable base and the embedded component. For example, the elastic modulus of the bonding layer may be lower than 10 Gpa to effectively reduce thermal stress in heterogeneous materials. In order to effectively release the thermal-mechanically induced stress, the bonding layer preferably has a sufficient width in the gap greater than 10 microns (preferably greater than 25 microns) to absorb the stress. Optionally, a plurality of stress modifiers (whose CTE is lower than the CTE of the bonding layer) may be mixed and dispersed in the bonding layer to form a modified bonding matrix with a smaller CTE. The CTE difference between the bonding layer and the stress modifiers may be 10 ppm/°C or more to show a significant effect. More specifically, the content of the stress modifiers may be at least 30% (volume percentage) based on the total volume of the modified bonding matrix, preferably more than 50%, and the CTE of the modified bonding matrix may be less than 50 ppm/°C.

The metal seal layer contacts and completely covers the bottom surface of the bonding layer, and further extends laterally below the bottom side of the waterproof base and the embedded component to completely cover the interface between the waterproof base and the bonding layer and between the embedded component and the bonding layer. In the case where the embedded component is a multi-layer resin component, the metal seal layer preferably also completely covers the bottom side of the multi-layer resin component, and can be coupled and integrated with the unpatterned bottom metal film (optionally present). Similarly, in another embodiment where the embedded component is a metal block, the metal seal layer can completely cover the metal block from below and be integrated with the metal block, and can further extend laterally below the bottom side of the waterproof base to completely cover any interface between the bonding layer and the heterogeneous materials. In addition, an additional metal seal layer can be provided as appropriate to completely cover the top surface of the bonding layer and the top side of the metal block, and further extend laterally to the top side of the waterproof base. Therefore, the additional metal seal layer can completely cover the interface between the metal block and the bonding layer and between the waterproof base and the bonding layer from above.

The present invention also provides a semiconductor assembly, which includes a semiconductor device (such as a chip), which is electrically connected to the above-mentioned circuit board using a variety of connection media including bumps (such as gold or solder bumps) or bonding wires. For example, the semiconductor device can be mounted face up on the top side of the anti-seepage base, and electrically coupled to the top wiring layer of the embedded component using bonding wires that contact the top wiring layer and the semiconductor device. In addition, the semiconductor device can be mounted face up on the embedded component, and electrically coupled to the top circuit of the anti-seepage base using bonding wires that contact the top circuit and the semiconductor device. Alternatively, the semiconductor device can be flip-chip coupled to the top wiring layer of the embedded component using a bump in contact with the top wiring layer, and thus electrically connected to the top circuit of the anti-seepage base through the conductive layer on the bonding layer. In addition, the semiconductor assembly may further include an anti-seepage cover disposed above the top side of the anti-seepage base to seal the semiconductor device inside. Preferably, the water absorption rate of the anti-seepage cover is 1% or less to prevent environmental moisture from entering the interior of the semiconductor assembly. In addition, the CTE of the anti-seepage cover can be matched with the CTE of the anti-seepage base to reduce the peeling or cracking phenomenon at the interface caused by CTE mismatch.

The assembly may be a first-level or second-level single crystal or polycrystalline device. For example, the assembly may be a first-level package containing a single chip or multiple chips. Alternatively, the assembly may be a second-level module containing a single package or multiple packages, each of which may contain a single chip or multiple chips. The chip may be a packaged chip or an unpackaged chip. In addition, the chip may be a bare chip, or a wafer-level packaged die, etc.

The term "covering" means incomplete as well as complete covering in the vertical and/or lateral directions. For example, in a preferred embodiment, the metal seal covers the resin layer of the multi-layer resin member, regardless of whether another component (such as a bottom metal film) is located between the resin layer and the metal seal.

The term "surrounding" refers to the relative position between components, regardless of whether there is another component between the components. For example, in a preferred embodiment, the anti-seepage base laterally surrounds the embedded component and is separated from the embedded component by a bonding layer.

The terms "disposed on/over" and "attached to" include both contact and non-contact between components. For example, in a preferred embodiment, a semiconductor device may be attached to a metal block, regardless of whether the semiconductor device contacts the metal block or is separated from the metal block by a metal encapsulation layer.

The terms "electrically connected" and "electrically coupled" refer to direct or indirect electrical connection. For example, in a preferred embodiment, the top wiring layer of the embedded component is electrically connected to the top circuit of the waterproof base through the conductive layer, but does not contact the top circuit.

The manufacturing method of the present invention is highly applicable and combines various mature electrical and mechanical connection technologies in a unique and advanced way. In addition, the manufacturing method of the present invention does not require expensive tools to implement. Therefore, compared with traditional technologies, this manufacturing method can greatly improve production, yield, performance and cost-effectiveness.

The embodiments described herein are for illustrative purposes, wherein the embodiments may simplify or omit elements or steps that are already known in the art to avoid blurring the features of the present invention. Similarly, for clarity of the drawings, the drawings may also omit repeated or unnecessary elements and element symbols.

100: Circuit board 20: Anti-seepage base 21: Anti-seepage insulation layer 22: Top circuit 23: Top metal layer 24: Bottom circuit 25: Bottom metal layer 27: Metallized through hole 200: Circuit board 205: Opening 206: Gap 30: Embedded component 31: Resin layer 32: Electrical isolation 33: Wiring layer 34: Top wiring layer 35: Top metal film 36 : Bottom wiring layer 37: Bottom metal film 38: Metallized through hole 39: Metallized through hole 300: Circuit board 50: Modified bonding substrate 53: Bonding layer 55: Stress adjuster 62: Conductive layer 63: Top coating layer 64: Metal sealing layer 65: Bottom coating layer 66: Metal sealing layer 71: Semiconductor device 81: Bonding wire 83: Solder bump 91: Anti-seepage cap

With reference to the accompanying drawings, the present invention can be more clearly understood through the detailed description of the following preferred embodiments, wherein: Figures 1 and 2 are respectively a cross-sectional view and a top schematic view of the anti-seepage base in the first embodiment of the present invention; Figures 3 and 4 are respectively a cross-sectional view and a top schematic view of an opening formed on the structures of Figures 1 and 2 in the first embodiment of the present invention; Figures 5 and 6 are respectively a cross-sectional view and a top schematic view of the structure of Figures 1 and 2 in the first embodiment of the present invention; In one embodiment, the structures of Figs. 3 and 4 provide a cross-sectional view and a top schematic view of an embedded component; Figs. 7 and 8 are respectively a cross-sectional view and a top schematic view of a modified bonding substrate formed on the structures of Figs. 5 and 6 in the first embodiment of the present invention; Figs. 9 and 10 are respectively a cross-sectional view and a top schematic view of an external wiring layer, top and bottom circuits, a conductive layer and a substrate formed on the structures of Figs. 7 and 8 in the first embodiment of the present invention. A metal sealing layer is used to complete the cross-sectional view and top schematic diagram of the circuit board; Figure 11 is a cross-sectional view of a semiconductor assembly installed on the circuit board of Figure 9 in the first embodiment of the present invention; Figure 12 is a cross-sectional view of a semiconductor assembly provided with an anti-seepage cover on the semiconductor assembly of Figure 11 in the first embodiment of the present invention; Figure 13 is a cross-sectional view of another circuit board in the second embodiment of the present invention; Figure 14 is a cross-sectional view of a semiconductor assembly installed on the circuit board of Figure 13 in the second embodiment of the present invention; Figure 15 is a cross-sectional view of another circuit board in the third embodiment of the present invention; and Figure 16 is a cross-sectional view of a semiconductor assembly installed on the circuit board of Figure 15 in the third embodiment of the present invention.

100: Circuit board

20: Anti-seepage base

21: Anti-seepage insulation layer

22: Top circuit

23: Top metal layer

24: Bottom circuit

25: Bottom metal layer

27: Metallized through hole

30: Embedded components

31: Resin layer

33: Wiring layer

35: Top metal film

37: Bottom metal film

62: Conductive layer

63: Top covering layer

64:Metal sealing layer

65: Bottom coating

Claims (9)

A circuit board comprises: An impervious base having a top circuit on its top side, a bottom circuit on its bottom side, and an opening, wherein the water absorption rate of the impervious base is 1% or less, and the inner side wall of the opening extends through the impervious base between the top side and the bottom side; An embedded component disposed in the opening of the impervious base; A bonding layer filling the gap between the outer peripheral side wall of the embedded component and the inner side wall of the opening, wherein the elastic modulus of the bonding layer is lower than the elastic modulus of the impervious base; and A metal sealing layer completely covering the bottom surface of the bonding layer. A circuit board as described in claim 1, wherein the elastic modulus of the bonding layer is lower than 10 GPa. The circuit board as described in claim 1 further includes a plurality of stress adjustment members distributed in the bonding layer and having a thermal expansion coefficient lower than that of the bonding layer. A circuit board as described in any one of claims 1 to 3, wherein the embedded component is a multi-layer resin component, which includes a plurality of alternating wiring layers and a plurality of resin layers and a bottom metal film, which completely covers the bottommost one of the resin layers and is coupled to the metal sealing layer. A circuit board as described in claim 4, wherein the topmost one of the wiring layers of the multi-layer resin member is electrically coupled to the top circuit of the anti-seepage base. A circuit board as described in claim 1 or 2, wherein the embedded component is a heat dissipation component whose thermal conductivity is higher than the thermal conductivity of the anti-seepage base. A circuit board as described in claim 6, wherein the heat sink comprises an electrical isolator having a water absorption rate of 1% or less. A semiconductor assembly, comprising: a circuit board as described in any one of claims 1 to 7; a semiconductor device electrically connected to the circuit board; and an anti-seepage cover attached to the top side of the anti-seepage base to seal the semiconductor device inside. A semiconductor assembly as described in claim 8, wherein the water absorption rate of the barrier cover is 1% or less.