TWI745072B - Wiring board with buffer layer and thermally conductive admixture - Google Patents

Abstract

The wiring board mainly includes an interconnect base, a thermal and electrical conductor, a binding layer, a top buffer layer, at least one thermally conductive admixture, and a top routing layer. The interconnect base is attached around peripheral sidewalls of the thermal and electrical conductor via the binding layer. The top buffer layer with the thermally conductive admixture dispersed therein covers the thermal and electrical conductor as well as the interconnect base and is between the top routing layer and the interconnect base/ thermal and electrical conductor. The top buffer layer has an elastic modulus lower than that of the thermal and electrical conductor so as to provide stress-buffering effect. The thermally conductive admixture dispersed in the top buffer layer allows heat generated by devices mounted on the top rouing layer to be conducted from the top routing layer to the thermal and electrical conductor. Accordingly, the wiring board of the present invention can exhibit excellent thermal and electrical performance and reliability.

Description

Circuit board with buffer layer and thermal conductive dopant

The present invention relates to a circuit board, especially a circuit board with a buffer layer and a heat-conducting dopant.

High-performance microprocessors and ASICs require high-performance circuit boards to be interconnected by signals. However, as the power increases, the large amount of heat generated by the semiconductor chip will degrade the performance of the device and cause thermal stress on the chip. Therefore, choosing an insulating substrate with better heat dissipation efficiency has become the key. Ceramic materials (such as aluminum oxide or aluminum nitride) have been widely used as substrate materials due to their ideal electrical insulation, high mechanical strength and good thermal conductivity. Although ceramic materials have both thermal conductivity and electrical insulation properties, they still cannot meet the required heat dissipation requirements in some applications, and the metallization technology, wiring technology and high cost involved in the application of ceramic materials in substrates also make Its application is restricted.

In addition, as the complexity of board design increases, heterogeneous integration routing components may be required in some applications to solve many electrical or thermal related requirements. However, due to the low CTE (Coefficient of Thermal Expansion) characteristics of ceramic materials, it is prone to cause great stress due to the mismatch of the coefficient of thermal expansion (CTE) when joining with the resin laminate, resulting in poor reliability.

In view of the various development stages and limitations of existing substrates, there is an urgent need to develop circuit boards that can meet the required thermoelectric performance and at the same time have high reliability.

The purpose of the present invention is to provide a circuit board, which is covered with a buffer layer mixed with thermal conductivity dopants above the thermoelectric conductor, so that the routing layer above the thermoelectric conductor can be electrically isolated from the thermoelectric conductor through the buffer layer, and the buffer layer is used at the same time The lower modulus of elasticity can provide stress buffering effect on the lateral extension surface. As a result, the circuit board of the present invention does not need to be based on electrical insulation considerations and is limited to only being able to select ceramic materials with insulation properties but thermal conductivity that cannot meet the heat dissipation requirements, which is beneficial to greatly improve the heat dissipation efficiency and the lower elasticity of the buffer layer Modulus characteristics also help to improve the reliability of the circuit board and its assembly. In particular, the present invention further utilizes a thermally conductive admixture to effectively conduct the heat generated by the device from the routing layer to the thermoelectric conductor, so as to prevent the buffer layer from hindering the heat conduction, thereby simultaneously meeting the requirements of excellent electrical and thermal performance and high reliability.

According to the above and other objectives, the present invention provides a circuit board including: an interconnection base having a top circuit layer on its top surface, a bottom circuit layer on its bottom surface, and extending from the top surface to the bottom surface A through hole; a thermoelectric conductor arranged in the through hole of the interconnection base; a bonding layer filled in a gap between the outer side wall of the thermoelectric conductor and the inner side wall of the through hole; a top buffer Layer extending laterally from a top surface of the thermoelectric conductor to the top surface of the interconnection base, wherein the elastic modulus of the top buffer layer is lower than the elastic modulus of the thermoelectric conductor, and the buffer layer The thermal conductivity is lower than the thermal conductivity of the thermoelectric conductor; at least one thermally conductive admixture dispersed in the top buffer layer, wherein the thermal conductivity of the at least one thermally conductive admixture is higher than the thermal conductivity of the top buffer layer; and a top The routing layer is electrically isolated from the thermoelectric conductor through the top buffer layer, is electrically connected to the top circuit layer of the interconnection base through conductive through holes, and is thermally connected to the via the at least one thermally conductive dopant Thermoelectric conductor.

The above and other features and advantages of the present invention can be more clearly understood by the detailed description of the following preferred embodiments.

Hereinafter, an example will be provided to illustrate the implementation aspects of the present invention in detail. The advantages and effects of the present invention will be more obvious through the content disclosed by the present invention. The drawings attached to this description are simplified and used as examples. The number, shape, and size of the components shown in the drawings can be modified according to actual conditions, and the configuration of the components may be more complicated. The present invention can also be practiced or applied in other aspects, and various changes and adjustments can be made without departing from the spirit and scope defined by the present invention.

[Example 1]

Figures 1-5 are diagrams of a manufacturing method of a circuit board in the first embodiment of the present invention. The circuit board includes an interconnection base, a thermoelectric conductor, a bonding layer, a top buffer layer, a thermal conductive dopant, and a top routing layer.

FIG. 1 is a cross-sectional view of the thermoelectric conductor 30 inserted into the through hole 201 of the interconnection base 20. The through hole 201 of the interconnection base 20 extends from the top surface to the bottom surface, and can be formed by various techniques, such as punching, drilling or laser cutting. The inner side wall of the interconnection base 20 through the opening 201 laterally surrounds the outer side wall of the thermoelectric conductor 30 and is spaced apart from the outer side wall of the thermoelectric conductor 30. Therefore, the gap 206 is located in the opening 201 between the inner side wall of the interconnection base 20 and the outer side wall of the thermoelectric conductor 30. The gap 206 laterally surrounds the thermoelectric conductor 30 and is laterally surrounded by the interconnection base 20. In this embodiment, the interconnection base 20 includes an insulating layer 21, an inner circuit layer 23, a top circuit layer 25, and a bottom circuit layer 27. The thermoelectric conductor 30 can be made of a thermally conductive and electrically conductive inorganic material, and its electrical conductivity is Above 100 W/mK. Each circuit layer (ie, inner circuit layer 23, top circuit layer 25, and bottom circuit layer 27) is usually a patterned copper layer, which is separated from each other by an insulating layer 21, and extends through the insulating layer 21 by a conductive member (ie The conductive through holes 22 and the conductive through holes 26) are electrically connected to each other. More specifically, in this embodiment, the inner circuit layers 23 are electrically connected to each other through the conductive through holes 22, and the top circuit layer 25 and the bottom circuit layer 27 are electrically connected to the inner circuit layers through the conductive through holes 26, respectively. twenty three. Accordingly, the top circuit layer 25 and the bottom circuit layer 27 can be electrically connected to each other. In addition, in this figure, the thickness of the interconnection base 20 is substantially equal to the thickness of the thermoelectric conductor 30, so the outer surfaces of the top circuit layer 25 and the bottom circuit layer 27 of the interconnection base 20 and the flat top of the thermoelectric conductor 30 respectively The surface and the bottom surface are substantially coplanar.

FIG. 2 is a cross-sectional view of the bonding layer 40 filling the gap 206. The bonding layer 40 laterally covers, surrounds and covers the inner sidewall of the interconnection base 20 and the outer sidewall of the thermoelectric conductor 30 in a lateral direction, so as to provide a firm mechanical joint between the interconnection base 20 and the thermoelectric conductor 30. Preferably, the bonding layer 40 is made of an organic material with an elastic modulus lower than that of the thermoelectric conductor 30 to absorb the stress caused by any coefficient of thermal expansion (CTE) mismatch between the interconnection base 20 and the thermoelectric conductor 30. For example, the elastic modulus of the bonding layer 40 may be lower than the elastic modulus of the thermoelectric conductor 30 by at least about 100 Gpa. In this embodiment, in order to achieve a significant effect, the bonding layer 40 is made of a material with an elastic modulus less than about 10 Gpa (which is lower than the elastic modulus of both the interconnection base 20 and the thermoelectric conductor 30) to effectively Release the stress caused by thermo-mechanical properties in heterogeneous materials.

FIG. 3 is a cross-sectional view of the top buffer layer 51 covering the top surfaces of the interconnection base 20 and the thermoelectric conductor 30 and the thermal conductive dopants 53 dispersed in the top buffer layer 51. The elastic modulus of the top buffer layer 51 is preferably lower than the elastic modulus of the thermoelectric conductor 30, so as to facilitate the absorption of thermal-mechanical stress in the structure. For example, the top buffer layer 51 can be made of an organic material whose elastic modulus is lower than the elastic modulus of the thermoelectric conductor 30 by at least about 100 Gpa to provide the required stress buffering effect, thereby ensuring the reliability of the structure. Thereby, in addition to the thermal-mechanical stress induced in the structure can be absorbed by the bonding layer 40 between the interconnection base 20 and the thermoelectric conductor 30 (its elastic modulus is usually smaller than the elastic modulus of the top buffer layer 51), the top The buffer layer 51 can further provide a stress buffering effect on the lateral extension surface. In addition, since the thermal conductivity of the top buffer layer 51 is generally lower than the thermal conductivity of the thermoelectric conductor 30, this embodiment further uses the thermal conductivity dopant 53 whose thermal conductivity is higher than that of the top buffer layer 51, so that heat can effectively pass through the top buffer layer 51. Conducted to the thermoelectric conductor 30. In order to achieve the desired thermal conductivity, the thermal conductive dopant 53 can be made of an inorganic material whose thermal conductivity is higher than the thermal conductivity of the top buffer layer 51 by at least about 10 W/mk. Thereby, the thermal conductive dopant 53 can be mixed in the top buffer layer 51 in an appropriate amount (about 30% by weight) to achieve the required heat dissipation effect, and it does not need to be mixed in a large amount in the top buffer layer 51 to achieve the desired heat dissipation effect. Therefore, a large amount of thermally conductive dopants 53 can be prevented from adversely affecting the stress buffering effect of the top buffer layer 51. In other words, through the above-mentioned parameter adjustment of elastic modulus and thermal conductivity, this embodiment can achieve the desired stress buffer and heat dissipation benefits at the same time. In order to further improve the reliability of the structure, the thermal expansion coefficient of the thermally conductive admixture 53 is preferably lower than the thermal expansion coefficient of the top buffer layer 51. For example, the thermal expansion coefficient of the thermally conductive admixture 53 may be lower than the thermal expansion coefficient of the top buffer layer 51 by at least About 5 ppm/℃ to reduce the stress caused by the expansion and contraction of the structure. Accordingly, the combination of the dual parameters of the elastic coefficient of the top buffer layer 51 and the thermal expansion coefficient of the thermally conductive dopant 53 can reduce the adverse effect of stress on the reliability of the structure.

FIG. 4 is a cross-sectional view of the blind hole 57 formed in the top buffer layer 51. The blind hole 57 extends through the top buffer layer 51 and is aligned with a selected part of the top circuit layer 25. The blind hole 57 can be formed by various techniques, such as laser drilling, plasma etching, and lithography, and it usually has a diameter of 50 microns. Pulse laser can be used to improve the efficiency of laser drilling. Alternatively, a scanning laser beam can be used with a metal mask.

FIG. 5 is a cross-sectional view of a top routing layer 61 formed. A top routing layer 61 is formed on the top buffer layer 51 by a metal deposition and metal patterning process. The top routing layer 61 extends upward from the top circuit layer 25 and fills the blind holes 57 to form a conductive through hole 67 directly contacting the top circuit layer 25 and extends laterally on the top buffer layer 51. Therefore, the top routing layer 61 can provide horizontal signal routing in the X and Y directions and vertical routing through the blind holes 57 to serve as electrical connections for the top circuit layer 25.

The top routing layer 61 can be deposited as a single layer or multiple layers by various techniques, such as electroplating, electroless plating, evaporation, sputtering, or a combination thereof. For example, first immerse the structure in an activator solution to cause the top buffer layer 51 to react with electroless copper, and then coat a thin copper layer as a seed layer by electroless plating, and then electroplating A second copper layer of required thickness is formed on the seed layer. Alternatively, before depositing an electroplated copper layer on the seed layer, the seed layer may be sputtered to form a seed layer film such as titanium/copper. Once the required thickness is reached, various techniques can be used to pattern the coating layer to form the top routing layer 61, such as wet etching, electrochemical etching, laser-assisted etching or a combination thereof, and an etching mask (not shown) , To define the top routing layer 61.

At this stage, the production of the circuit board 100 has been completed, which includes the interconnection base 20, the thermoelectric conductor 30, the bonding layer 40, the top buffer layer 51, the thermal conductive dopant 53, and the top routing layer 61. The interconnection base 20 is bonded to the periphery of the thermoelectric conductor 30 by the bonding layer 40 and provides horizontal and vertical signal routing. The top routing layer 61 is electrically isolated from the thermoelectric conductor 30 through the top buffer layer 51 and electrically connected to the top circuit layer 25 of the interconnection base 20 through the conductive through hole 67. The top buffer layer 51 can not only serve as an electrical isolation layer between the top routing layer 61 and the thermoelectric conductor 30, it also provides a stress buffering effect on the lateral extension surface because it has a smaller elastic modulus than the thermoelectric conductor 30, which is combined with vertical extension The stress relief provided by the surface bonding layer 40 is beneficial to improve the reliability of the structure. The thermal conductive dopant 53 has a higher thermal conductivity than the top buffer layer 51, so that the heat generated by the chip (not shown) assembled on the top routing layer 61 can be conducted to the thermoelectric conductor 30, thereby increasing the heat of the assembly. efficacy.

[Example 2]

Fig. 6 is a cross-sectional view of a circuit board according to a second embodiment of the present invention.

For the purpose of brief description, any description that can be used for the same application in the above embodiment 1 is incorporated here, and the same description is not required to be repeated.

The circuit board 200 is similar to the structure shown in FIG. 5, except that the top buffer layer 51 further contains a reinforcing dopant 55, which is mixed with the thermally conductive dopant 53 in the top buffer layer 51 to improve the top buffer layer. 51 reliability. More specifically, the reinforced admixture 55 is preferably a fibrous inorganic material with an elastic modulus greater than that of the top buffer layer 51. For example, the elastic modulus of the reinforced admixture 55 may be higher than that of the top buffer layer 51 by at least about 10 GPa. Accordingly, the combination of the top buffer layer 51 with a lower elastic modulus and the reinforcement admixture 55 with a higher elastic modulus can not only achieve the stress buffer effect, but also maintain proper stiffness. In addition, the reinforcing admixture 55 may have a characteristic that the thermal expansion coefficient is smaller than the thermal expansion coefficient of the top buffer layer 51, so as to reduce the stress caused by the internal expansion and contraction of the structure together with the thermally conductive admixture 53.

[Example 3]

Fig. 7 is a cross-sectional view of a circuit board according to a third embodiment of the present invention.

For the purpose of brief description, any description that can be used for the same application in the above-mentioned embodiments is incorporated herein, and the same description does not need to be repeated.

The circuit board 300 is similar to the structure shown in FIG. 5, except that it further includes a bottom buffer layer 52 and a bottom routing layer 62. The bottom buffer layer 52 laterally extends from the bottom surface of the thermoelectric conductor 30 to the bottom surface of the interconnection base 20 to cover the interconnection base 20, the thermoelectric conductor 30 and the bonding layer 40 from below. Similar to the top buffer layer 51, the elastic modulus of the bottom buffer layer 52 is lower than the elastic modulus of the thermoelectric conductor 30, for example, the elastic modulus of the bottom buffer layer 52 is lower than the elastic modulus of the thermoelectric conductor 30 by at least about 100 Gpa , In order to provide the stress buffering effect of the lateral extension surface from the bottom of the structure. The bottom routing layer 62 is connected to the thermoelectric conductor 30 through a metalized through hole 66 and is electrically connected to the bottom circuit layer 27 of the interconnection base 20 through a conductive through hole 68. Thereby, the chip (not shown) assembled on the top routing layer 61 can be electrically connected to the bottom routing layer 62 through the interconnection base 20, and the heat generated by the chip can be conducted to the top routing layer 61 through the top buffer layer The thermal conductive dopant 53 in 51 is transferred to the thermoelectric conductor 30, and then transferred to the bottom routing layer 62 through the metalized through hole 66 for further dissipation. In addition, in this embodiment, the thermally conductive dopant 53 in the top buffer layer 51 has a coefficient of thermal expansion smaller than that of the top buffer layer 51 as described above, and it can also have a characteristic that the modulus of elasticity is greater than that of the top buffer layer 51, such as The elastic modulus of the thermally conductive admixture 53 can be higher than the elastic modulus of the top buffer layer 51 by at least about 50 GPa, so that the top buffer layer 51 mixed with the thermally conductive admixture 53 has proper stiffness.

[Example 4]

Fig. 8 is a cross-sectional view of a circuit board according to a fourth embodiment of the present invention.

For the purpose of brief description, any description that can be used for the same application in the above-mentioned embodiments is incorporated herein, and the same description does not need to be repeated.

The circuit board 400 is similar to the structure shown in FIG. 7 except that it further includes a reinforcement admixture 55 dispersed in the top buffer layer 51 and an additional thermal conductive admixture 54 and an additional reinforcement admixture 56 dispersed in the bottom buffer layer 52. And the bottom routing layer 62 does not include metallized through holes connected to the thermoelectric conductor 30. The thermal conductivity of the bottom buffer layer 52 is generally lower than the thermal conductivity of the thermoelectric conductor 30. According to this, in order to enable the thermal energy conducted to the thermoelectric conductor 30 to be effectively dissipated to the bottom routing layer 62, the thermal conductivity of this embodiment is higher than that of the bottom buffer layer. The thermal conductivity of the thermally conductive dopant 54 of 52, for example, the thermal conductivity of the thermally conductive dopant 54 is higher than the thermal conductivity of the bottom buffer layer 52 by at least about 10 W/mk, so as to achieve the required heat dissipation efficiency. In addition, the thermal expansion coefficient of the thermally conductive admixture 54 can be less than the thermal expansion coefficient of the bottom buffer layer 52. For example, the thermal expansion coefficient of the thermally conductive admixture 54 can be lower than the thermal expansion coefficient of the bottom buffer layer 52 by at least about 5 ppm/°C to reduce the internal structure. Stress caused by expansion and contraction. Furthermore, the reinforcing admixtures 55, 57 are preferably fibrous inorganic materials with a modulus of elasticity greater than that of the top and bottom buffer layers 51, 52, so as to provide stress buffering effects on the top and bottom buffer layers 51, 52 while being sufficient to maintain Appropriate rigidity. Similarly, the thermal expansion coefficients of the reinforcing admixtures 55 and 56 can also be smaller than the thermal expansion coefficients of the top and bottom buffer layers 51 and 52, so as to reduce the stress caused by the expansion and contraction of the structure together with the thermally conductive admixtures 53, 54.

As shown in the above embodiments, the present invention constructs a unique circuit board with better reliability, which mainly includes an interconnection base, a thermoelectric conductor, a bonding layer, a top buffer layer, at least one thermally conductive admixture, and A top routing layer. Optionally, the circuit board of the present invention may further include a bottom buffer layer and a bottom routing layer. The above-mentioned circuit board is only an illustrative example, and the present invention can be implemented by other various embodiments. In addition, the above-mentioned embodiments can be mixed and matched with each other or used with other embodiments based on considerations of design and reliability. For example, the interconnection base may include a plurality of through holes arranged in an array shape, and each through hole can accommodate a thermoelectric conductor inside.

The interconnection base is located around the peripheral sidewall of the thermoelectric conductor, and includes a top circuit layer on its top surface, a bottom circuit layer on its bottom surface, and an insulating layer between the top circuit layer and the bottom circuit layer, serving as a circuit board Provide multi-layer winding capability. In addition, the interconnection base may optionally include at least one inner circuit layer and at least one additional insulating layer, where each inner circuit layer is located between the top circuit layer and the bottom circuit layer, and each inner circuit layer is connected to At least one insulating layer is separated between the top circuit layers and between each inner circuit layer and the bottom circuit layer. The top circuit layer, the bottom circuit layer, and the optional inner circuit layer can be electrically connected to each other through conductive elements (such as conductive through holes and/or conductive vias). Accordingly, the top circuit layer can be electrically connected to the bottom circuit layer, so as to provide an electrical conduction path between two opposite sides of the circuit board.

The thermoelectric conductor can be composed of an inorganic material with electrical and thermal conductivity, and the thermal conductivity of the inorganic material is preferably above 100 W/mK to provide excellent heat dissipation benefits. In a preferred embodiment, the thickness of the thermoelectric conductor is substantially equal to the thickness of the interconnection base, so that the top and bottom surfaces of the thermoelectric conductor and the outer surfaces of the top and bottom circuit layers of the interconnection base are respectively Substantially coplanar. also. The thermal expansion coefficient and elastic modulus of thermoelectric conductors are usually different from the thermal expansion coefficient and elastic modulus of the interconnection base.

The bonding layer laterally covers, surrounds and uniformly covers the through-hole sidewall of the interconnection base and the peripheral sidewall of the thermoelectric conductor, so as to provide a firm mechanical bonding force between the interconnection base and the thermoelectric conductor. Preferably, the elastic modulus of the bonding layer is lower than the elastic modulus of the interconnection base and the thermoelectric conductor. For example, the bonding layer can be made of an organic material with an elastic modulus lower than the elastic modulus of the thermoelectric conductor by about 100 Gpa or more. Absorb the stress caused by any coefficient of thermal expansion (CTE) mismatch between the interconnection base and the thermoelectric conductor. More specifically, the elastic modulus of the bonding layer can be lower than 10 Gpa to effectively reduce the thermal stress in the heterogeneous material.

The top buffer layer covers and contacts the interconnection base, the thermoelectric conductor and the bonding layer from the top side, and the optional bottom buffer layer covers and contacts the interconnection base, the thermoelectric conductor and the bonding layer from the bottom side. The top buffer layer and the bottom buffer layer can be made of an organic insulating material whose elastic modulus is smaller than that of the thermoelectric conductor, so as to provide a stress buffer effect on the lateral extension surface. Furthermore, the elastic modulus of the top buffer layer and the bottom buffer layer is preferably lower than the elastic modulus of the thermoelectric conductor by about 100 Gpa or more, and may be higher than the elastic modulus of the bonding layer. As a result, the top buffer layer and the bottom buffer layer can not only serve as the electrical isolation layer between the top routing layer and the thermoelectric conductor and between the bottom routing layer and the thermoelectric conductor, respectively, but their elastic modulus characteristics are more conducive to reducing stress on the circuit board. Adverse effects caused by reliability.

In addition to being dispersed in the top buffer layer, the thermally conductive dopant can also be selectively dispersed in the bottom buffer layer, so that the heat generated by the semiconductor device (such as a chip) assembled on the top routing layer can pass through the top buffer layer. The thermally conductive dopant is conducted to the thermoelectric conductor, and then the thermally conductive dopant in the bottom buffer layer is transferred from the thermoelectric conductor to the bottom routing layer for further dissipation. In order to achieve the required heat dissipation efficiency, the thermally conductive admixture is preferably made of an inorganic material whose thermal conductivity is higher than the thermal conductivity of the buffer layer by about 10 W/mk or more. In addition, the thermal expansion coefficient of the thermally conductive admixture is preferably lower than the thermal expansion coefficient of the buffer layer. For example, the thermal expansion coefficient of the thermally conductive admixture can be lower than the thermal expansion coefficient of the buffer layer by about 5 ppm/℃ or more to reduce the internal expansion and contraction of the structure. Stress. In order to make the composite composed of the buffer layer and the thermally conductive admixture have proper rigidity, the elastic modulus of the thermally conductive admixture can be greater than the elastic modulus of the buffer layer, for example, the elastic modulus of the thermally conductive admixture can be higher than that of the buffer layer Above about 50 GPa, it is enough to maintain proper rigidity while the buffer layer provides stress buffering effect.

The top routing layer is a patterned metal layer, which extends laterally above the top surface of the thermoelectric conductor and the interconnection base, and is electrically isolated from the thermoelectric conductor through the top buffer layer, and is formed by a conductive through hole penetrating the top buffer layer. It is electrically connected to the top circuit layer of the interconnection base. Similarly, the bottom routing layer is a patterned metal layer, which extends laterally below the thermoelectric conductor and the bottom surface of the interconnection base, and is electrically connected to the bottom circuit layer of the interconnection base through conductive through holes that penetrate the bottom buffer layer. Sexual connection. In addition, the bottom routing layer can be thermally connected to the thermoelectric conductor through the metallized through hole penetrating the bottom buffer layer.

The circuit board of the present invention may optionally further include at least one reinforcing admixture, which is dispersed in the top buffer layer and/or the bottom buffer layer. The reinforcing admixture may be a fibrous inorganic material with an elastic modulus greater than that of the buffer layer. For example, the elastic modulus of the reinforcing admixture may be higher than the elastic modulus of the buffer layer by about 10 GPa or more to increase the rigidity of the material layer. In addition, the thermal expansion coefficient of the reinforcement admixture can also be smaller than the thermal expansion coefficient of the buffer layer, so as to reduce the stress caused by the expansion and contraction of the structure together with the thermal conductivity admixture.

The present invention also provides a semiconductor assembly in which a semiconductor device (such as a chip) is connected to the top routing layer of the circuit board. Specifically, the semiconductor device can overlap the thermoelectric conductor and be electrically coupled to the top routing layer. Accordingly, the semiconductor device can be electrically connected to the interconnection base, and the heat generated by the semiconductor device can be conducted from the top routing layer to the thermoelectric conductor through the thermally conductive dopant in the top buffer layer to further escape.

The assembly can be a first-stage or a second-stage single crystal or polycrystalline device. For example, the assembly may be a first-level package including a single chip or multiple chips. Alternatively, the assembly may be a second-level module including a single package or multiple packages, wherein each package may include a single or multiple chips. The semiconductor element can be a packaged chip or an unpackaged chip. In addition, the semiconductor device can be a bare chip or a wafer-level package die.

The term "covering" means incomplete and complete coverage in the vertical and/or lateral directions. For example, in a preferred embodiment, the top buffer layer covers the interconnection base and the thermoelectric conductor, and the interconnection base laterally covers the peripheral sidewalls of the thermoelectric conductor, regardless of whether another element (such as the bonding layer) is located on the mutual Between the base and the thermoelectric conductor.

The term "connected" includes contact and non-contact with single or multiple components. For example, in a preferred embodiment, the semiconductor device can be connected to the top side of the thermoelectric conductor, regardless of whether the semiconductor device is separated from the thermoelectric conductor by bumps, top routing layer, and top buffer layer.

The term "surround" refers to the relative position of components, regardless of whether there is another component between them. For example, in a preferred embodiment, the interconnection base laterally surrounds the thermoelectric conductor and is separated from the thermoelectric conductor by a bonding layer.

The terms "electrical connection" and "electrical coupling" mean direct or indirect electrical connection. For example, in a preferred embodiment, the top routing layer can be electrically connected to the bottom routing layer through the interconnection base, but not in contact with the bottom routing layer.

The circuit board prepared by this method has high reliability, low price, and is very suitable for mass production. The manufacturing method of the present invention has high applicability, and combines various mature electrical and mechanical connection technologies in a unique and progressive way. In addition, the manufacturing method of the present invention can be implemented without expensive tools. Therefore, compared with the traditional technology, this manufacturing method can greatly improve the yield, yield, performance and cost-effectiveness.

The embodiments described here are for illustrative purposes, and these embodiments may simplify or omit elements or steps that are well known in the art so as not to obscure the characteristics of the present invention. Similarly, in order to make the drawings clear, the drawings may also omit redundant or unnecessary components and component symbols.

100, 200, 300, 400: circuit board 20: Interconnect base 201: piercing 206: Gap 21: Insulation layer 22: Conductive vias 23: inner circuit layer 25: Top circuit layer 26, 67: Conductive through holes 27: bottom circuit layer 30: thermoelectric conductor 40: Bonding layer 51: top buffer layer 52: bottom buffer layer 53, 54: Thermally conductive admixture 55, 56: reinforcement admixture 57: Blind Hole 61: Top routing layer 62: bottom routing layer 66: Metallized through holes

With reference to the accompanying drawings, the present invention can be more clearly understood by the detailed description of the following preferred embodiments, in which: Figure 1 is a cross-sectional view of the thermoelectric conductor inserted into the interconnection base in the first embodiment of the present invention; 2 is a cross-sectional view of the bonding layer provided in the structure of FIG. 1 in the first embodiment of the present invention; 3 is a cross-sectional view of the top buffer layer and the thermal conductive dopant provided in the structure of FIG. 2 in the first embodiment of the present invention; 4 is a cross-sectional view of the blind hole formed in the structure of FIG. 3 in the first embodiment of the present invention; 5 is a cross-sectional view of the top routing layer formed on the structure of FIG. 4 to complete the production of the circuit board in the first embodiment of the present invention; Figure 6 is a cross-sectional view of another circuit board in the second embodiment of the present invention; Figure 7 is a cross-sectional view of another circuit board in the third embodiment of the present invention; Fig. 8 is a cross-sectional view of another circuit board in the fourth embodiment of the present invention.

100: circuit board

20: Interconnect base

21: Insulation layer

23: inner circuit layer

25: Top circuit layer

26, 67: Conductive through holes

27: bottom circuit layer

30: thermoelectric conductor

40: Bonding layer

51: top buffer layer

53: Thermally conductive admixture

61: Top routing layer

Claims (8)

A circuit board includes: an interconnection base having a top circuit layer on its top surface, a bottom circuit layer on its bottom surface, and a through hole extending from the top surface to the bottom surface; a thermoelectric conductor, which Set in the through hole of the interconnection base; a bonding layer filled in a gap between the outer side wall of the thermoelectric conductor and the inner side wall of the through hole; a top buffer layer from a top of the thermoelectric conductor The surface extends laterally to and the top surface of the interconnection base, wherein the elastic modulus of the top buffer layer is lower than the elastic modulus of the thermoelectric conductor by at least 100 Gpa, and the thermal conductivity of the top buffer layer is lower than that of the thermoelectric conductor The thermal conductivity; at least one thermally conductive admixture, which is dispersed in the top buffer layer, wherein the thermal conductivity of the at least one thermally conductive admixture is higher than the thermal conductivity of the top buffer layer; and a top routing layer, which penetrates the top The buffer layer is electrically isolated from the thermoelectric conductor, and is electrically connected to the top circuit layer of the interconnection base through a conductive through hole, and is thermally connected to the thermoelectric conductor through the at least one thermally conductive dopant. The circuit board according to claim 1, wherein the thermal expansion coefficient of the at least one thermally conductive admixture is lower than the thermal expansion coefficient of the top buffer layer. The circuit board according to claim 2, wherein the coefficient of thermal expansion of the at least one thermally conductive admixture is lower than the coefficient of thermal expansion of the top buffer layer by at least 5 ppm/°C. The circuit board according to any one of claims 1 to 3, wherein the thermal conductivity of the at least one thermally conductive dopant is higher than the thermal conductivity of the top buffer layer by at least 10 W/mk. The circuit board according to claim 4, further comprising at least one reinforcing admixture dispersed in the top buffer layer. The circuit board according to claim 1, further comprising: a bottom buffer layer extending laterally from a bottom surface of the thermoelectric conductor to the bottom surface of the top base, wherein the elastic modulus of the bottom buffer layer is lower than the bottom surface of the top base The elastic modulus of the thermoelectric conductor; and a bottom routing layer, which is electrically connected to the bottom circuit layer of the interconnection base through an additional conductive through hole. The circuit board according to claim 6, wherein the thermal conductivity of the bottom buffer layer is lower than the thermal conductivity of the thermoelectric conductor, and the circuit board further includes at least one additional thermally conductive admixture dispersed in the bottom buffer layer, the at least The thermal conductivity of an additional thermally conductive admixture is higher than the thermal conductivity of the bottom buffer layer. The circuit board according to claim 6 or 7, wherein the bottom routing layer is further connected to the thermoelectric conductor through a metalized through hole.

Images