TWI840813B - Wafer offset correction method for maskless exposure machine - Google Patents

Abstract

A chip offset correction method for a maskless exposure machine comprises the following steps: calculating the positions of the chips bonded to the substrate to define the coordinates of the chips on the substrate; dividing the chips according to the coordinates of the chips on the substrate to form a plurality of bonding areas corresponding to the chips; calculating the conductive lines of the chips in the bonding areas, and calculating a compensation line between each conductive line and the conductive line corresponding to the adjacent chip that crosses the separation boundary; and forming a digital exposure layer according to each conductive line and each compensation line.

Description

Wafer offset correction method for maskless exposure machine

The present invention is related to the yellow light lithography process, and in particular to a chip offset correction method for a maskless exposure machine.

The current maskless exposure technology uses a photoresist layer on the wafer, and then uses the digital pattern to output the corresponding pattern of ultraviolet light to irradiate the wafer. The part of the photoresist layer irradiated by the ultraviolet light will be easily dissolved. After the development and etching processes, the remaining photoresist layer is removed, and the preset pattern is formed on the wafer.

However, when the processed lattice on the wafer is bonded, the chip is inevitably not bonded in the correct position and has asymmetry or skew problems. In particular, the shapes and sizes of heterogeneous chips are different, which causes the conductive wires between heterogeneous chips to be offset or skewed, making it difficult to connect the conductive wires. If the conductive wires corresponding to the heterogeneous chips are directly connected to each other, it is easy for the conductive wires to contact and interfere with each other, resulting in short circuit problems.

In view of this, how to solve the above problems is the primary issue that this invention aims to solve.

The main purpose of the present invention is to provide a chip offset correction method for a maskless exposure machine, which calculates the compensation line across the separation boundary so that the skewed conductive lines of each chip can be connected correspondingly, so as to achieve the effect of correcting the error caused by the offset caused by die bonding.

To achieve the above-mentioned purpose, the present invention provides a chip offset correction method for a maskless exposure machine, wherein a plurality of chips are combined on a substrate, the chips have a plurality of contacts, and a conductive line is formed on each of the contacts by predetermined exposure, including the following steps: a. Calculating the positions of the chips bonded to the substrate to define the coordinates of the chips on the substrate; b. Delineating separation boundaries between the chips according to the coordinate values of the chips on the substrate to form a plurality of bonding areas corresponding to the chips; c. Calculating the conductive lines of the chips located in their bonding areas, and calculating a compensation line between each conductive line and the conductive line correspondingly connected to the adjacent chip that crosses the separation boundary; d. Forming a digital exposure layer according to each conductive line and each compensation line.

Preferably, the separation boundary is a virtual line that demarcates the bonding areas.

Preferably, the separation boundary is a virtual strip area with a predetermined width to demarcate the bonding areas.

Preferably, the coordinate values of the edges and corners of the chips are calculated using projection geometry to measure the shapes of the chips after displacement, and the separation boundaries are divided accordingly, and each of the conductive lines and each of the compensation lines are calculated to form the exposure layer.

The above-mentioned purposes and advantages of the present invention can be easily understood from the detailed description and accompanying drawings of the following selected embodiments.

1: Chip

11: Contact

12: Conducting wires

2: Substrate

21: Connection hole

3: Bonding area

31: Separating Boundaries

4: Compensation line

Figure 1 is a flow chart of the steps of the present invention.

Figure 2 is a schematic diagram of the reference drawing of this invention.

Figure 3 is a schematic diagram of the results after calibration of the present invention.

Figure 4 is a schematic diagram showing that the separation boundary of the present invention is a virtual strip area.

First, please refer to Figures 1 to 3, which are the chip offset correction method of the maskless exposure machine provided by the present invention, which is applied to the combination of multiple chips 1 and a substrate 2, wherein, as shown in Figure 2, there is a reference image file having reference state information such as the correct shape and position of the chips 1 on the substrate 2, the chips 1 are arranged on the substrate 2 at intervals, the chips 1 have multiple contacts 11, and the substrate 2 has multiple contact holes 21. The contacts 11 can be respectively predetermined to be exposed to form a conductive wire 12, wherein a part of the conductive wire 12 is predetermined to extend to the corresponding position of the contact hole 21 on the substrate 2, and another part of the conductive wire 12 is predetermined to be connected to the conductive wire 12 of the adjacent chip 1.

When the chip 1 is bonded to the substrate 2, it is inevitable that it will not be bonded in the correct position and there will be asymmetry or skewness, so that the conductive wires 12 between each chip 1 will also be offset or skewed, causing some conductive wires 12 to be unable to correctly extend to the corresponding connection hole 21 position on the substrate 2, and other conductive wires 12 are difficult to connect with the conductive wires 12 of the adjacent chip 1.

Accordingly, please continue to refer to Figures 1 and 3. As shown in Figure 1, the step flow of the chip offset correction method of the maskless exposure machine provided by the present invention is firstly to obtain the state information containing the shape and position of the chips 1 by a pre-scanning means. In this embodiment, the scanning means uses projection geometry to project each point in the three-dimensional space onto a two-dimensional plane, and connects each point projected on the plane to form a geometric figure, that is, to project and calculate the position where the edges and corners of the chips 1 are bonded to the substrate 2, so as to define the coordinates of the chips 1 on the substrate 2.

Then, according to the coordinate values of the chips 1 on the substrate 2, the shapes and offsets of the chips 1 after displacement are measured, and a separation boundary 31 is drawn between the chips 1 to form a plurality of bonding areas 3 corresponding to the chips 1. The conductive wires 12 of the chips 1 are respectively located in the corresponding bonding areas 3 without exceeding the separation boundary 31, wherein the separation boundary 31 is a virtual line.

Then, the conductive wires 12 pre-exposed on the chips 1 and located in their bonding areas 3 are calculated, and accordingly, a compensation line 4 is calculated that crosses the separation boundary 31 between each conductive wire 12 and the conductive wire 12 correspondingly connected to the adjacent chip 1. The compensation line 4 connects each conductive wire 12 and the corresponding conductive wire 12. Accordingly, as the chip 1 tilts, the tilted conductive wire 12 can be connected to the corresponding conductive wire 12 in the adjacent bonding area 3 by the compensation line 4.

Finally, a digital exposure layer is formed based on each of the conductive lines 12 and each of the compensation lines 4, and then exposed, developed, and etched to form a continuous and uninterrupted wiring between the chips 1 to generate the required circuit diagram.

It should be particularly noted that, as shown in FIG. 4 , the separation boundary 31 can be a virtual strip region with a predetermined width, and each compensation line 4 vertically crosses the separation boundary 31, so that each compensation line 4 is arranged parallel to each other in the separation boundary 31 and has a beam-forming effect, thereby avoiding the problem of the compensation lines 4 interfering with each other due to the dense arrangement of the skewed conductive wires 12 of each chip 1.

In addition, the correction method for the deviation of each contact 11 is to compare the state information containing the shape and position of the chips 1 obtained by the pre-scanning means with the reference state information such as the correct shape and position of each chip 1 on the substrate 2 in the reference image file. After the comparison, the difference between the two can be obtained, and then the compensation value for correcting the reference state to be consistent with the actual shape and position of the chip 1 is calculated. Then, the compensation line 4 is calculated according to the compensation value, so that the conductive wire 12 can be connected to the corresponding position of the contact hole 21 through the compensation line 4 as shown in Figure 3, and a continuous and uninterrupted wiring is formed between each contact 11 of the chip 1 and the corresponding contact hole 21 to correct the error caused by the deviation of the correct position of the contact 11 due to die bonding.

By using the correction method of the present invention, the skewed conductive wires 12 of each chip 1 are connected correspondingly through the compensation wires 4 crossing the separation boundary 31, avoiding the problem of short circuit caused by direct connection of the skewed conductive wires 12, which causes mutual contact interference, so as to achieve the effect of correcting the error caused by the offset of the die bonding.

The disclosure of the above embodiments is only used to illustrate the present invention, not to limit the present invention, so any changes in numerical values or replacement of equivalent components should still fall within the scope of the present invention.

In summary, those who are familiar with this technology should be able to understand that this invention can indeed achieve the above-mentioned purpose and actually complies with the provisions of the Patent Law, so they can apply for it in accordance with the law.

Claims (4)

A chip offset correction method for a maskless exposure machine, wherein a plurality of chips are bonded to a substrate, the chips have a plurality of contacts, and a conductive line is formed on the contacts respectively by predetermined exposure, comprising the following steps: a. calculating the positions of the chips bonded to the substrate to define the coordinates of the chips on the substrate; b. drawing separation boundaries between the chips according to the coordinate values of the chips on the substrate to form a plurality of corresponding The bonding area of the chips is accommodated, and the conductive wires of the chips are respectively located in the corresponding bonding area without exceeding the separation boundary; c. Calculate the conductive wires of the chips located in their bonding area, and calculate a compensation line across the separation boundary between each conductive wire and the conductive wire correspondingly connected to the adjacent chip, and the two ends of each compensation line are respectively connected to the conductive wire of one of the adjacent chips; d. Form a digital exposure layer according to each conductive wire and each compensation line. The chip offset correction method of the maskless exposure machine as described in claim 1, wherein the separation boundary is a virtual line to divide the bonding areas. The chip offset correction method of the maskless exposure machine as described in claim 1, wherein the separation boundary is a virtual strip area with a predetermined width, which divides the bonding areas. The chip offset correction method of the maskless exposure machine as described in claim 1, wherein the coordinate values of the chip edges and corners are calculated using projection geometry to measure the shape of the chip after offset, and the separation boundary is divided accordingly, and each of the conductive lines and each of the compensation lines are calculated to form the digital exposure layer.