TWI810039B - Method of forming a semiconductor structure - Google Patents

Abstract

A method of forming a semiconductor structure includes following operations. A wafer layout is designed. A mask pattern is provided based on the wafer layout, wherein the mask pattern includes a street pattern with a street aligned pattern and a die pattern with a die aligned pattern. Perform an optical proximity correction for the die pattern and the street pattern. A mask is manufactured based on the mask pattern processed by the optical proximity correction. A streets and dies are formed on a semiconductor wafer based on the mask.

Description

Methods of Forming Semiconductor Structures

The present disclosure relates to methods of forming semiconductor devices.

With the advancement of technology, the size of semiconductor components can be reduced, but the price is that the required lithography technology must become more and more refined. This makes it increasingly difficult to tolerate small displacements or deviations during the manufacturing process of semiconductor devices. For example, when performing lithography on a wafer, when the pattern density used is high and the size is small, the depth of focus (DOF) is very small, resulting in a limited processing window, which cannot tolerate, for example, a slight unevenness of the semiconductor wafer table. Or the condition of the yellow light machine is poor. This makes the lithography result deviate from the designed pattern, resulting in unexpected short circuit or misalignment, which affects the function of the semiconductor device.

Therefore, how to provide a technical solution to improve the above problems is one of the issues that people in the industry want to solve.

An aspect of the present disclosure relates to a method of manufacturing a semiconductor device.

According to one or more embodiments of the present disclosure, a method of forming a semiconductor structure includes the following procedures. A wafer layout is designed, wherein the wafer layout includes a scribe street layout with a scribe street aligned layout and a die layout with a die aligned layout. designing a mask pattern based on the wafer layout, wherein the mask pattern includes a scribe pattern corresponding to the scribe layout and a grain pattern corresponding to the die layout, the scribe pattern has a scribe alignment pattern corresponding to the scribe alignment layout, and The die layout has a die alignment pattern corresponding to the die alignment layout. Optical proximity correction is performed on the grain pattern and the scribe line pattern of the mask pattern. A reticle is fabricated based on the optical proximity corrected reticle pattern. A dicing line corresponding to the dicing line pattern and a plurality of crystal grains corresponding to the grain pattern and surrounded by the dicing lines are formed on the semiconductor wafer based on the mask.

In one or more embodiments of the present disclosure, performing optical proximity correction on the scribe line pattern of the reticle pattern includes performing optical proximity correction on the scribe line alignment pattern of the scribe line pattern. Performing optical proximity correction on the scribe line pattern of the mask pattern includes performing optical proximity correction on the scribe line alignment pattern of the scribe line pattern.

In some embodiments, performing optical proximity correction to a die pattern of the reticle pattern includes performing optical proximity correction to a die alignment pattern of the die pattern. Forming dies on a semiconductor wafer includes forming dies after forming scribe line alignment marks, wherein at least one of the dies includes a die alignment mark corresponding to a die alignment pattern.

In some embodiments, a method of forming a semiconductor structure includes the following procedures. Electrical measurements are performed on the scribe line alignment marks after forming the scribe line alignment marks and before forming dies.

In some embodiments, the scribe line alignment mark includes a first elongated conductor and a second elongated conductor extending along a first direction, a first conductive via on the first elongated conductor and a first conductive via on the second elongated conductor. on the second conductive via. A method of forming a semiconductor structure includes the following procedures. The electrical properties of the first long conductor and the second long conductor are measured through the first conductive via hole and the second conductive via hole.

In some embodiments, the scribe line alignment mark includes a third elongated conductor and a fourth elongated conductor extending along a second direction perpendicular to the first direction, a third conductive via on the third elongated conductor and a third conductive via on the third elongated conductor. The fourth conductive via hole on the fourth strip conductor. A method of forming a semiconductor structure includes the following procedures. The electrical properties of the third elongated conductor and the fourth conductive via are measured through the third conductive via and the fourth conductive via.

In some embodiments, the scribe line alignment pattern of the mask pattern includes a first strip pattern corresponding to the first strip conductor and a second strip pattern corresponding to the second strip conductor. The first strip pattern and the second strip pattern extend along the first direction. The optical proximity correction for the scribe line alignment pattern further includes the following process. A light-shielding strip extending along a first direction is formed within each of the first strip pattern and the second strip pattern.

In some embodiments, the scribe line alignment pattern of the mask pattern includes a first strip pattern corresponding to the first strip conductor and a second strip pattern corresponding to the second strip conductor. The first strip pattern and the second strip pattern extend along the first direction. The optical proximity correction for the scribe line alignment pattern further includes the following process. A plurality of first light-shielding strips extending along the first direction are arranged on the plurality of first edges of the first strip pattern and the second strip pattern along the first direction. A plurality of second light-shielding strips extending along the second direction are arranged on the second strip pattern and the plurality of second edges of the second strip pattern along the second direction perpendicular to the first direction.

In some embodiments, the first light-shielding strip and the second light-shielding strip do not extend to the junction of the first edge and the second edge.

In one or more embodiments of the present disclosure, the method of forming a semiconductor structure further includes the following processes. Wafers are diced along dicing streets to separate die from each other.

To sum up, by performing optical proximity correction on the scribe line layout, it is possible to increase the tolerance when the wafer encounters unexpected offset in the semiconductor manufacturing process, and avoid the occurrence of misalignment or unexpected short circuit.

It is to be understood that both the foregoing general description and the following detailed description are examples and are intended to provide further explanation of the claimed disclosure.

The following is a detailed description of the embodiments in conjunction with the accompanying drawings, but the provided embodiments are not used to limit the scope of the disclosure, and the description of the structure and operation is not used to limit the order of its execution. Any recombination of components The structure and the devices with equivalent functions are all within the scope of this disclosure. In addition, the drawings are for illustrative purposes only and are not drawn to original scale. For ease of understanding, the same or similar elements will be described with the same symbols in the following description.

In addition, the words (terms) used in the entire specification and the scope of the patent application, unless otherwise specified, generally have the ordinary meaning of each word used in this field, in the disclosed content and in the special content . Certain terms used to describe the disclosure are discussed below or elsewhere in this specification to provide those skilled in the art with additional guidance in describing the disclosure.

In this document, terms such as "first" and "second" are only used to separate elements or operating methods with the same technical term, and are not intended to represent an order or limit the present disclosure.

In addition, similar terms such as "comprising", "including", "providing" are all open-ended restrictions in this document, meaning including but not limited to.

Further, in this article, unless the article is specifically limited in the context, "a" and "the" can generally refer to one or more. It will be further understood that the terms "comprising", " Including", "having" and similar words indicate the features, regions, integers, steps, operations, elements and/or components described therein, but do not exclude one or more other features, regions, Integers, steps, operations, elements, components, and/or groups thereof.

Please refer to Figure 1. FIG. 1 is a schematic diagram of a semiconductor processing facility 100 according to an embodiment of the present disclosure. As shown in FIG. 1 , in this embodiment, the semiconductor processing equipment 100 includes a light source 110 , a light source processing chamber 120 , a mask 130 and a wafer stage 140 . In FIG. 1 , the light source 110 is configured to emit light L1 to the light source processing chamber 120 . Subsequently, the light L1 is processed inside the light source processing chamber 120 , and is emitted from the light source processing chamber 120 as light L2 after processing. The photomask 130 is disposed behind the light source processing chamber 120 to receive the light L2. In some embodiments, the photomask 130 may be disposed on a support frame, which is not shown here for the purpose of simple illustration. After passing through the mask 130 , the light L2 is transformed into a light L3 reflecting the mask pattern of the mask 130 . The wafer stage 140 is configured to carry the substrate 205 . The substrate 205 is, for example, a semiconductor wafer. In this way, the substrate 205 receives the light L3 reflecting the mask pattern of the mask 130 to form one or more semiconductor devices on the substrate 205 .

It should be noted that for the purpose of simple description, FIG. 1 only illustrates some components of the semiconductor processing equipment 100, some functional components, including but not limited to one or more components of the light source 110 and the light source processing chamber 120, one or more A plurality of chambers for accommodating, one or more support structures for supporting functional components, one or more components for performing a semiconductor process on the substrate 205, and one or more for controlling one or more processes in the semiconductor process The processing system is omitted.

In this way, the semiconductor processing equipment 100 can perform a photolithography process on the substrate 205 through the mask pattern on the mask 130 to form one or more semiconductor devices on the substrate 205 . Please refer to Figure 2. FIG. 2 is a schematic diagram of a semiconductor structure 200 according to an embodiment of the present disclosure.

As shown in FIG. 2 , in this embodiment, the semiconductor structure 200 includes a substrate 205 , a dicing line 210 and a plurality of dies 220 . In this embodiment, the substrate 205 is a semiconductor wafer. The dicing lines 210 and a plurality of crystal grains 220 are formed on the substrate 205 , and the crystal grains 220 are arranged at equal intervals in a direction X and a direction Y perpendicular to each other. In some embodiments, each die 220 may include integrated integrated circuits and external pins, and these integrated integrated circuits may include one or more integrated circuits and semiconductor elements, while the outer die 220 Connected pins can be connected with internal integrated circuits or lines.

Scribing streets 210 are provided to define the boundaries of individual dies. In detail, almost no functional elements are disposed on the dicing line 210 opposite to the die 220 . One or more testing lines can be formed on the dicing line 210 , but these lines do not affect the function of the die 220 itself. In this way, a plurality of crystal grains 220 may be diced along the dicing line 210 subsequently, so that the plurality of crystal grains 220 are separated from each other.

One or more dies 230 are formed incompletely on the edge of the substrate 205 for the purpose of facilitating the execution of the semiconductor process. Subsequently, when cutting along the dicing line 210 to separate the plurality of dies 220 from each other, these incomplete dies 230 will be discarded.

Please refer to Figure 2 and Figure 3 at the same time. Fig. 3 shows a part R1 of Fig. 2 . In this embodiment, the semiconductor structure 200 further includes a scribe line alignment mark 211 and a die alignment mark 221 . FIG. 3 schematically shows the positions of the scribe line alignment marks 211 and the die alignment marks 221 . In FIG. 3 , the die alignment mark 221 is formed at the position of the die 220 , and the scribe line alignment mark 211 is located in the scribe line 210 . After the die 220 and the dicing street 210 are formed, the dicing line alignment mark 211 will be formed in the dicing street 210 together, and the die alignment mark 221 will be formed in the die 220 together. In this way, after the semiconductor structure 200 is formed, the scribe line alignment mark 211 and the die alignment mark 221 can be inspected, for example, the electrical properties of the scribe line alignment mark 211 and the die alignment mark 221 are measured, or The respective alignment relationship between the scribe line alignment mark 211 and the die alignment mark 221 is confirmed by optical measurement, so as to confirm whether the inside of the formed die 220 is reliable, and thereby eliminate faulty and damaged die 220 .

In this way, after preliminary inspection of the crystal grains 220 on the semiconductor structure 200 , a plurality of crystal grains 220 can be cut out from the semiconductor structure 200 . The diced die 220 can be independently packaged on other semiconductor substrates.

For further description of how to perform inspection through the die alignment mark 221 , please refer to FIG. 4 . FIG. 4 shows a schematic top view of a scribe line alignment layout 311 . The scribe line alignment layout 311 is a layout corresponding to the scribe line alignment marks 211 .

In this embodiment, as shown in FIG. 4, the scribe line alignment layout 311 includes a plurality of strip conductors 3121, strip conductors 3122, strip conductors 3123, strip conductors 3124, strip conductors 3125, strip conductors 3126, strip conductor 3127 and strip conductor 3128. The strip conductor 3121 , the strip conductor 3123 , the strip conductor 3126 , and the strip conductor 3128 extend along the direction Y, and the strip conductor 3122 , the strip conductor 3124 , the strip conductor 3125 , and the strip conductor 3127 extend along the direction X.

In FIG. 4 , the strip conductors 3121 , the strip conductors 3124 , the strip conductors 3125 and the strip conductors 3128 may have similar widths. The strip conductors 3122 , the strip conductors 3123 , the strip conductors 3126 and the strip conductors 3127 may have similar widths. In detail, the width of the strip conductor 3121 in the direction X is smaller than the width of the strip conductor 3122 in the direction Y. The width of the strip conductor 3124 in the direction Y is smaller than the width of the strip conductor 3123 in the direction X. The width of the strip conductor 3125 in the direction Y is smaller than the width of the strip conductor 3126 in the direction Y. The width of the strip conductor 3128 in the direction X is smaller than the width of the strip conductor 3127 in the direction Y.

Further, in this embodiment, the scribe line alignment layout 311 includes a plurality of conductive vias 3161 , conductive vias 3162 , conductive vias 3163 and conductive vias 3164 . A plurality of conductive vias 3161 are formed on the elongated conductor 3121 . A plurality of conductive vias 3162 are formed on the elongated conductor 3124 . A plurality of conductive vias 3163 are formed on the elongated conductor 3125 . A plurality of conductive vias 3164 are formed on the elongated conductor 3128 .

Through the design of the scribe line alignment layout 311, once the small-sized long conductors (such as the long conductor 3121, the long conductor 3124, the long conductor 3125, and the long conductor 3128) are unexpectedly reversed or misplaced, it will be possible to Electrical properties are measured through the layout of the conductive vias (such as the conductive vias 3161 , the conductive vias 3162 , the conductive vias 3163 , and the conductive vias 3164 ), for example, to measure whether different adjacent elongated conductors 3121 are connected. If it is turned on, unexpected inversion or dislocation will occur, reflecting that the formed semiconductor structure 200 may have defects.

Similarly, the die alignment mark 221 in FIG. 3 can also be mapped to a layout similar to the scribe line alignment layout 311 and verified in a similar manner.

Please refer to Figure 4 and Figure 5A at the same time. FIG. 5A shows a part R2 of FIG. 4 , which schematically shows a part R2 of a plurality of elongated conductors 3125 and a plurality of conductive vias 3163 formed on the elongated conductors 3125 . In the partial R2 of the scribe line alignment layout 311 shown in FIG. 5A, the elongated conductors 3125 have a width W1 in the direction Y, and the elongated conductors 3125 are arranged at equal intervals of the width W3 in the direction Y, and are arranged in the long The conductive via 3163 on the bar conductor 3125 has a width W2 in the direction Y.

Please refer to Figure 4 and Figure 5A at the same time. FIG. 5B shows a part R3 of FIG. 4 , and schematically shows a part R3 of a plurality of elongated conductors 3128 and a plurality of conductive vias 3164 formed on the elongated conductors 3128 . In the partial R3 of the scribe line alignment layout 311 shown in FIG. 5B, the strip conductors 3128 have a width W4 in the direction X, and the strip conductors 3125 are arranged at equal intervals with a width W6 in the direction X, and are arranged in the long The conductive via 3164 on the bar conductor 3128 has a width W5 in the direction Y.

In some embodiments, by way of example and not limitation, the width W1 is 350 nanometers (nm), the width W2 is 250 nm, the width W3 is 150 nm, the width W4 is 350 nm, and the width W5 is 250 nm. m, and the width W6 is 150 nm.

Based on the scribe line alignment layout 311 shown in FIGS. 4 to 5B , a mask pattern corresponding to the scribe line alignment layout 311 can be designed. Please refer to Figure 6A and Figure 6B. FIG. 6A shows a partial mask pattern corresponding to FIG. 5A according to an embodiment of the present disclosure. FIG. 6B shows a partial mask pattern corresponding to FIG. 5B according to an embodiment of the present disclosure. Wherein, for the purpose of illustration, FIG. 6A and FIG. 6B only show the mask patterns for forming the elongated conductors 3121 - 3128 of the scribe line alignment layout 311 .

For example, in FIG. 6A , the scribe line alignment pattern in the mask pattern includes a plurality of strip patterns 4125 corresponding to the strip conductors 3125 . The strip pattern 4125 has a width W7 in the direction Y, and a plurality of strip patterns 4125 are arranged at equal intervals with a width W8 in the direction Y.

Similarly, in FIG. 6B , the scribe line alignment pattern in the mask pattern includes a plurality of strip patterns 4128 corresponding to the strip conductors 3128 . The strip pattern 4128 has a width W9 in the direction X, and a plurality of strip patterns 4128 are arranged at equal intervals with a width W10 in the direction X.

In some embodiments, by way of example and not limitation, the width W7 is 350 nm, the width W8 is 150 nm, the width W9 is 350 nm, and the width W10 is 150 nm.

Based on the mask patterns in FIG. 6A and FIG. 6B , it will be possible to design a mask that is actually used for lithography. Please refer to Figure 7A and Figure 7B. FIG. 7A shows a partial mask 512 corresponding to FIG. 6A according to an embodiment of the present disclosure. FIG. 7B shows a partial mask 512 corresponding to FIG. 6B according to an embodiment of the present disclosure.

In FIG. 7A and FIG. 7B, the partial mask 512 corresponding to the strip pattern 4125 of the mask of FIG. 6A and the strip pattern 4128 of the mask of FIG. 6B is produced respectively. Specifically, in part of the mask 512 shown in Figure 7A, openings O1 corresponding to a plurality of elongated patterns 4125 are formed on the mask 512 along the direction X, and in the mask 512 shown in Figure 7B Partially, the openings O2 corresponding to the plurality of elongated patterns 4128 are formed on the mask 512 along the direction Y.

Please go back to Figure 1. In this way, by arranging the photomask 512 in the semiconductor processing equipment 100, that is, setting the photomask 512 as the photomask 130 in the semiconductor processing equipment 100, the lithography process can be performed on the substrate 205 to form the corresponding scribe line alignment layout 311 The scribe line alignment marks 211.

Please refer to Figure 8A and Figure 8B. FIG. 8A shows a schematic top view of the elongated conductor of the scribe line alignment mark 211 according to an embodiment of the present disclosure, wherein FIG. 8A is an exemplary optical top view. Fig. 8B is a partial schematic cross-sectional view of Fig. 8A.

In the embodiment shown in FIG. 8A, since the depth of focus (depth of focus, referred to as DOF, a parameter related to the resolution of the lithography process) is limited due to the design of the mask 512 in FIGS. 7A and 7B, the formed A plurality of long conductors of the scribe line alignment mark 211 are reversed to generate an unexpected connection.

In detail, in the embodiment shown in FIG. 8A, the strip conductor 2121 corresponds to the strip conductor 3121 of the scribe alignment layout 311 in FIG. 4 , and the strip conductor 2122 corresponds to the scribe alignment layout in FIG. 4 The strip conductor 3122 of 311, the strip conductor 2123 corresponds to the strip conductor 3123 of the cutting line alignment layout 311 in the fourth figure, and the strip conductor 2124 corresponds to the strip conductor 3124 of the cutting line alignment layout 311 in the fourth figure, and the long strip conductor 2124 corresponds to the cutting line alignment layout 311 in the fourth figure. The strip conductor 2125 corresponds to the strip conductor 3125 of the slit line alignment layout 311 in FIG. 4, the strip conductor 2126 corresponds to the strip conductor 3126 of the slit line alignment layout 311 in FIG. The strip conductor 3127 and the strip conductor 2128 of the scribe alignment layout 311 correspond to the strip conductor 3128 of the scribe alignment layout 311 in FIG. 4 .

Figure 8A is an example optical top view. The elongated conductors 2121-2128 formed by optical photography in FIG. 8A, because the width of the interval between the elongated conductor 2121, the elongated conductor 2124, the elongated conductor 2125, and the elongated conductor 2128 is relatively narrow, and the widths of the intervals in FIG. 7A, FIG. The DOF of the mask 512 in Figure 7B is limited, and the strip conductors 2121, 2124, 2125, and 2128 are blurred and cannot be distinguished in Figure 8A.

Also refer to Figure 8A and Figure 8B. In the partial schematic cross-sectional view shown in FIG. 8B , a plurality of strip conductors 206 , strip conductors 207 , strip conductors 208 , and strip conductors 209 corresponding to the designed strip conductors 2128 are formed on the substrate 205 . The strip conductors 206 , the strip conductors 207 , the strip conductors 208 , and the strip conductors 209 have different widths in the direction X. In some embodiments, the distances between the strip conductors 206 , the strip conductors 207 , the strip conductors 208 , and the strip conductors 209 in the direction X are not the same. This reflects the line fall phenomenon due to the limited DOF.

For example, due to the limited DOF, when the semiconductor processing equipment 100 shakes/shifts in the position of the substrate 205 due to unexpected accidents, resulting in one of the long conductors 207 having a larger width in the direction X, the adjacent long conductors The strip conductor 206 and the strip conductor 208 of 207 are also affected and have a smaller width in the direction X.

It should be noted that there should only be two to three strip conductors on the cross section of Figure 8B, but the strip conductor 207 occupies a larger width in the direction X, resulting in four strip conductors 206, The strip conductor 207 , the strip conductor 208 , and the strip conductor 209 .

Continuing from FIG. 8A and FIG. 8B , FIG. 9 shows a partial schematic cross-sectional view of the formed scribe line alignment mark 211 according to an embodiment of the present disclosure. FIG. 9 is a continuation of the cross section of FIG. 8B , further forming via holes 216 corresponding to the conductive via holes 3164 in the scribe line alignment layout 311 . The through hole 216 is formed with another photomask than the photomask 512 . An oxide layer 213 and an underlying layer 214 are further formed on the substrate 205 . A photoresist layer 215 is further formed on the top surface of the underlying layer 214 . The photoresist layer 215 is patterned through a photomask to form an opening 215O. Through the opening 215O of the photoresist layer 215 , a through hole 216 can be formed, and the through hole 216 extends along the direction Z to the top surface of the substrate 205 . The substrate 205 , the strip conductors 206 - 209 , the oxide layer 213 , the underlying layer 214 and the through hole 216 can be regarded as the formed scribe line alignment mark 211 .

As shown in Figure 9, since the strip conductor 207 occupies a larger width in the direction X, the through hole 216 on the left side of Figure 9 is connected to the strip conductor 207, while the through hole 216 on the right side of Figure 9 is not connected to The strip conductor 208 is next to the strip conductor 207 .

In this way, by measuring the scribe line alignment mark 211 through the through hole 216 , it is possible to obtain defects in the through hole 216 and the elongated conductors 206 - 209 . Then, the cross section of the scribe line alignment mark 211 in FIG. 9 is inspected by optical measurement, that is, the alignment problem of the semiconductor structure 200 can be confirmed through the scribe line alignment mark 211 .

Also, please go back to Figure 2 and Figure 3. In one or more embodiments of the present disclosure, the die alignment marks 221 in the die 220 can also be aligned by designing the die alignment layout (for example, as shown in FIGS. 4 to 5B ). layout 311), design the grain alignment mask pattern (such as the design of the scribe line alignment pattern shown in Figure 6A to Figure 6B), and manufacture another corresponding one according to the designed grain alignment mask pattern A photomask (such as the design of the photomask 512 shown in FIGS. 7A to 7B ) is used to form the die alignment marks 221 through the photomask. The die alignment mark 221 may have a structure similar to that of the scribe line alignment mark 211 to confirm corresponding alignment characteristics through conductive vias.

In order to improve the alignment fall-off problem caused by limited DOF, please refer to Fig. 10A and Fig. 10B. FIG. 10A illustrates a partial mask pattern corresponding to FIG. 5A according to an embodiment of the present disclosure. FIG. 10B shows the partial mask pattern corresponding to FIG. 5B according to an embodiment of the present disclosure. It should be noted that for purposes of clarity of illustration, similar elements have been given the same reference numerals.

Compared with the mask pattern in FIG. 6A , in FIG. 10A , each strip pattern 4125 is further provided with light-shielding strips S1 and S2 extending along the direction X. The light-shielding strip S1 and the light-shielding strip S2 have the same width W11 in the direction Y. FIG. 10A can be regarded as an optical proximity correction for the photoresist pattern in FIG. 6A , and each strip pattern 4125 is additionally provided with a light-shielding strip S1 and a light-shielding strip S2 extending along the direction X to shield light along the direction X.

In this embodiment, the length of the light-shielding strip S1 and the light-shielding strip S2 in the direction X is smaller than the length of the strip pattern 4125 in the direction X, so that the light-shielding strip S1 and the light-shielding strip S2 will not touch any edge of the strip pattern 4125 .

Similarly, compared to the mask pattern in FIG. 6B , in FIG. 10B , each strip pattern 4128 is further provided with light-shielding strips S3 and S4 extending along the direction Y. The light-shielding strip S3 and the light-shielding strip S4 have the same width W12 in the direction Y. FIG. 10B can be regarded as an optical proximity correction for the photoresist pattern in FIG. 6B , and each strip pattern 4128 is additionally provided with a light-shielding strip S3 and a light-shielding strip S4 extending along the direction Y to shield light along the direction Y.

In addition, in this embodiment, the length of the light-shielding strip S3 and the light-shielding strip S4 in the direction Y is smaller than the length of the strip pattern 4128 in the direction Y, which prevents the light-shielding strip S3 and the light-shielding strip S4 from contacting the strip pattern 4128. either edge.

In one or more embodiments of the present disclosure, for example but not limited thereto, the width W11 is within a range of 3 nm to 45 nm, and the width W12 is within a range of 3 nm to 45 nm.

Continuing from Figure 10A and Figure 10B, please refer to Figure 11A and Figure 11B. FIG. 11A shows a partial mask corresponding to FIG. 10A according to an embodiment of the present disclosure. FIG. 11B shows a partial mask corresponding to FIG. 10B according to an embodiment of the present disclosure.

Continuing from FIG. 10A, the light-shielding strips S1 and S2 are arranged on the strip pattern 4125, and the partial mask in FIG. 11A is formed according to the mask pattern in FIG. 10A. Compared with the partial mask in FIG. 7A , the partial mask in FIG. 11A is further provided with light-shielding bars C1 and C2 extending along the direction X in the opening O1 of the mask 512 corresponding to the elongated pattern 4125 . The light-shielding strip C1 and the light-shielding strip C2 respectively correspond to the light-shielding strip S1 and the light-shielding strip S2 in FIG. 10A .

In the embodiment shown in FIG. 11A, each opening O1 includes opposite edges E1 and E3 extending along the direction X, and an edge E2 extending along the direction Y, and the light-shielding strip C1 and the light-shielding strip C2 do not touch the edge E1, the edge Either of E2 and edge E3.

On the other hand, the partial mask in FIG. 11B is formed according to the optical proximity corrected mask pattern in FIG. 10B. Compared with the partial mask in FIG. 7B , the partial mask in FIG. 11B is further provided with light-shielding bars C3 and C4 extending along the direction Y in the opening O2 of the mask 512 corresponding to the elongated pattern 4128 . The light-shielding strip C3 and the light-shielding strip C4 respectively correspond to the light-shielding strip S3 and the light-shielding strip S4 in FIG. 10B .

In the embodiment shown in FIG. 11B, each opening O2 includes opposite edges E4 and E6 extending along the direction Y, and an edge E5 extending along the direction X, and the light-shielding strip C3 and the light-shielding strip C4 do not touch the edge E4, the edge Either of E5 and edge E6.

FIG. 11A schematically shows the arrangement of the light-shielding strips C1 and C2 along the direction X. FIG. In this embodiment, not only the shading strip C1 and the shading strip C2 are provided for the local mask corresponding to the elongated conductor 3125 in the scribe line alignment layout 311 of FIG. The partial mask corresponding to the middle and long conductor 3124 is provided with a light-shielding bar C1 and a light-shielding bar C2. Further, FIG. 11B schematically shows the arrangement of the light-shielding strips C3 and C4 along the direction Y. However, in this embodiment, not only the shading bars C3 and C4 are provided for the local mask corresponding to the elongated conductor 3128 in the scribe line alignment layout 311 of FIG. The partial mask corresponding to the middle and long conductor 3121 is provided with a light-shielding bar C3 and a light-shielding bar C4.

In this way, global optical proximity correction can be performed on the mask corresponding to the scribe line alignment layout 311 in FIG. 4 . This is beneficial to the accuracy of the scribe line alignment layout 311 realized by the mask 512 and the light shielding bars C1 - C4 in FIGS. 11A and 11B . In this way, the DOF of the overall semiconductor structure 200 can be increased, and the tolerance to the unintended offset of the substrate 205 affecting the lithography result can be improved.

FIG. 12A shows a schematic top view of the elongated conductor of the scribe line alignment mark 211 according to an embodiment of the present disclosure. FIG. 12A can be regarded as a schematic top view of the long conductor of the scribe line alignment mark 211 . The strip marks 2121-2128 in FIG. 12A are formed by the photomask lithography in FIG. 11A and FIG. 11B.

In the optical top view diagram shown in FIG. 12A, the strip marks 2121~2128 are formed by photolithography of the optical proximity corrected mask 512 and the shading strips C1~C4, and the strip marks 2121~2128 conform to FIG. 4 According to the design of the scribe line alignment layout 311 , there is no unintended overlap between adjacent ones of the strip marks 2121 - 2128 .

Please refer further to Fig. 12B. FIG. 12B shows a partial schematic cross-sectional view of FIG. 12A.

In FIG. 12B, the plurality of elongated conductors 212 (corresponding to the plurality of elongated conductors 2128 in FIG. 12A ) formed on the substrate 205 can have similar widths in the direction X, and be spaced at the same pitch from each other. . In some embodiments of the present disclosure, each strip conductor 212 has a width in the direction X of 300 nm to 400 nm. In some embodiments, the strip conductor 212 may have different widths along the direction X on the top surface of the substrate 205 and inside the substrate 205, and the width of the strip conductor 212 along the direction X is between 300 nm and 400 nm. range between. For example, along the direction X, the strip conductor 212 has a width of 381 nm on the top surface of the substrate 205 , and then shrinks inwardly into the substrate 205 , so that the bottom of the strip conductor 212 has a width of 345 nm.

In some embodiments, the strip conductors 212 are spaced apart from each other along the direction X by a distance between 100 nm and 200 nm. In some embodiments, each elongated conductor 212 has a width of between 345 nm and 155 nm in the direction X, for example, and is spaced apart from each other by a distance between 121 nm and 155 nm.

In this way, continue to FIG. 12B, please refer to FIG. 13. FIG. 13 shows a partial schematic cross-sectional view of a scribe line alignment mark 211 according to an embodiment of the present disclosure. Similar to FIG. 9, in FIG. 13B, vias 216 corresponding to the conductive vias 3164 in the scribe line alignment layout 311 are further formed. The through hole 216 is formed with another photomask than the photomask 512 . An oxide layer 213 and an underlying layer 214 are further formed on the substrate 205 . A photoresist layer 215 is further formed on the top surface of the underlying layer 214 . The photoresist layer 215 is patterned through a photomask to form an opening 215O. Through the opening 215O of the photoresist layer 215 , a through hole 216 can be formed, and the through hole 216 extends along the direction Z to the top surface of the substrate 205 . The substrate 205 , the plurality of strip conductors 212 , the oxide layer 213 , the underlying layer 214 and the via 216 can be regarded as the formed scribe line alignment marks 211 .

In FIG. 13 , each conductive via 216 can be connected to a corresponding one of the elongated conductors 212 as designed by the scribe line alignment layout 311 of FIG. 4 . In this way, through electrical measurement and optical photography, it is possible to verify that the elongated conductor 212 complies with the design of the scribe line alignment layout 311 , thereby ensuring that the formed scribe line 210 is also precisely formed according to the designed scribe line layout.

In some embodiments, the scribe line alignment mark 211 can perform electrical measurement through the through holes 216 corresponding to the conductive via holes 3161~3164 of the scribe line alignment layout 311, so as to realize the measurement of the long conductor 2121 and the long conductor 2124. , Alignment measurement of the strip conductor 2125 and the strip conductor 2128.

Back to Figure 2. Along with the formation of the scribe line alignment mark 211 , the scribe line 210 is also lithographically formed on the substrate 205 . Subsequently, the die 220 and the die alignment mark 221 are also formed on the substrate 205 through corresponding one or more layers of photomasks to form the semiconductor structure 200 .

To sum up, the optical proximity correction is performed on the mask corresponding to the scribe line alignment layout 311 , and the optical proximity correction is actually performed on the scribe line mask pattern of the lithography line 210 . Similarly, in this embodiment, optical proximity correction can be performed on the mask corresponding to the die 220 and the die alignment mark 221 . In this way, optical proximity correction is performed on the mask patterns of two different masks corresponding to the dicing line 210 and the die 220 , which can improve the DOF of the overall semiconductor structure 200 .

In one or more embodiments of the present disclosure, by performing optical proximity correction on the mask pattern of the mask forming the die 220 and the dicing line 210 , the range of DOF for forming the semiconductor structure 200 can be significantly increased. In some embodiments, if only the optical proximity correction is performed on the mask pattern of the mask forming the die 220 , the DOF of the semiconductor structure 200 is in the range of −0.04 μm to −0.1 μm. In some embodiments, if the optical proximity correction is performed on the mask pattern of the mask forming the die 220 and the dicing line 210 at the same time, the DOF of the semiconductor structure 200 is about -0.02 μm to -0.14 μm, which is significantly improved. The ability to tolerate unintended deflection of the substrate 205 is achieved.

It should be noted that FIGS. 11A to 11B schematically illustrate one of the optical proximity correction methods for the mask pattern. Please refer to FIG. 14A and FIG. 14B to illustrate another embodiment of optical proximity correction. FIG. 14A illustrates a partial mask pattern corresponding to FIG. 5A according to an embodiment of the present disclosure. FIG. 14B shows the partial mask pattern corresponding to FIG. 5B according to an embodiment of the present disclosure.

Compared with the mask pattern in FIG. 6A , in FIG. 14A , each strip pattern 4125 is further provided with light-shielding strips S5 , S7 extending along direction X, and light-shielding strips S6 extending along direction Y. FIG. 14A can also be regarded as an optical proximity correction for the photoresist pattern in FIG. 6A. For each elongated pattern 4125, a light-shielding strip S5 and a light-shielding strip S7 extending along the direction X are additionally provided to shield light along the direction X, and A light shielding strip S6 extending along the direction Y is additionally provided to shield light along the direction Y. As shown in FIG. 14A , the light-shielding strips S5 , S6 and S7 are arranged along the edges of the strip pattern 4125 , but the light-shielding strips S5 , S6 and S7 do not extend to the edge junction of the strip pattern 4125 .

In other words, the length of the light-shielding strip S5 and the light-shielding strip S7 in the direction X is smaller than the length of the strip pattern 4125 in the direction X, and the length of the light-shielding strip S6 in the direction Y is shorter than the length of the strip pattern 4125 in the direction Y, so that The light-shielding strip S5 , the light-shielding strip S6 and the light-shielding strip S7 do not touch the junction of any edge of the strip pattern 4125 .

Similarly, compared to the mask pattern in FIG. 6B , in FIG. 14B , each elongated pattern 4128 is further provided with light-shielding strips S8 , S10 extending along the direction Y, and light-shielding strips S9 extending along the direction Y. Figure 14B can also be regarded as an optical proximity correction for the photoresist pattern in Figure 6B. For each strip pattern 4128, a light-shielding strip S8 and a light-shielding strip S10 extending along the direction Y are additionally provided to shield light along the direction X, and A light shielding strip S9 extending along the direction X is additionally provided to shield light along the direction X. As shown in FIG. 14B , the light-shielding strips S8 , S9 and S10 are arranged along the edges of the strip pattern 4128 , but the light-shielding strips S8 , S9 and S10 do not extend to the boundary of the strip pattern 4128 .

In other words, the length of the light-shielding strip S8 and the light-shielding strip S10 in the direction Y is smaller than the length of the strip pattern 4128 in the direction Y, and the length of the light-shielding strip S9 in the direction X is shorter than the length of the strip pattern 4128 in the direction X, so that The light-shielding strip S8 , the light-shielding strip S9 , and the light-shielding strip S10 do not touch the junction of any edge of the strip pattern 4128 .

Continuing from Figure 14A and Figure 14B, please refer to Figure 15A and Figure 15B. FIG. 15A shows a partial mask corresponding to FIG. 14A according to an embodiment of the present disclosure. FIG. 15B shows a partial mask corresponding to FIG. 14B according to an embodiment of the present disclosure.

Continuing from FIG. 14A, the light-shielding strips S5-S7 are arranged on the strip pattern 4125, and the partial mask in FIG. 15A is formed according to the mask pattern in FIG. 14A. Compared with the partial mask in FIG. 7A , the partial mask in FIG. 15A is further provided with light-shielding bars C5 , C6 and C7 extending along the direction X in the opening O1 of the mask 512 corresponding to the elongated pattern 4125 . In the embodiment shown in FIG. 15A, each opening O1 includes opposite edges E1 and E3 extending along the direction X, and an edge E2 extending along the direction Y, and light-shielding strips C5 and C7 are respectively arranged along the edges E1 and E3 to shield light. The strip C6 is disposed along the edge E2, but none of the light-shielding strips C5-C7 touches the junction of any two of the edge E1, the edge E2, and the edge E3. The shading strips C5 , C6 and C7 respectively correspond to the shading strips S5 , S6 and S7 in FIG. 14A .

On the other hand, the partial mask in FIG. 15B is formed according to the optical proximity corrected mask pattern in FIG. 14B. Compared with the partial mask shown in FIG. 7B, in the embodiment shown in FIG. 15B, each opening O2 includes opposite edges E4 and E6 extending along the direction Y, and an edge E5 extending along the direction X, and the shading strip C8 The light-shielding strip C10 is arranged along the edges E4 and E6 respectively, and the light-shielding strip C9 is arranged along the edge E5, but none of the light-shielding strips C8-C10 touches the junction of any two of the edge E4, the edge E5, and the edge E6. The shading strips C8 , C9 and C10 respectively correspond to the shading strips S8 , S9 and S10 in FIG. 14B .

In this way, global optical proximity correction can be implemented on the mask corresponding to the scribe line alignment layout 311 in FIG. 4 . This is beneficial to realize the accuracy of the scribe line alignment layout 311 through the mask 512 and light-shielding strips C5~C10 in Fig. 14A and Fig. 14B, and the scribe line alignment layout 311 according to Fig. The strip conductors are arranged so as to achieve precise alignment similar to the alignment mark 211 of the cutting line in FIG. 13 .

For a summary of one or more methods of forming a semiconductor device disclosed herein, please refer to FIG. 16 . FIG. 16 shows a flowchart of a method 600 for forming a semiconductor device according to an embodiment of the present disclosure. The method 600 includes a process 601 to a process 606 , and can be implemented by the semiconductor processing equipment 100 .

In process 601, a wafer layout is designed. In order to form the semiconductor structure 200 , a wafer layout is designed, wherein the wafer layout includes a die layout corresponding to the die 220 and a dicing street layout corresponding to the dicing street 210 .

Also refer to Figure 2. As shown in FIG. 2 , in some embodiments, die 220 has die alignment marks 221 and scribe lines 210 have scribe line alignment marks 211 . The plurality of dies 220 may have integrated circuits formed by different functional elements, for example, the dies 220 may be integrated memory chips. For the purpose of simple illustration, FIG. 2 only shows one of the die 220 and its die alignment mark 221 .

The corresponding scribe line alignment layout 311 of the scribe line alignment mark 211 having the scribe line 210 in the wafer layout is shown in FIGS. 4, 5A and 5B.

In some implementation manners, the process 601 can be implemented by layout design software. For example, the semiconductor processing equipment 100 may have a layout design room (not shown in FIG. 1 ). The layout design room may include processors, storage devices, communication interfaces, input and output interfaces for relevant personnel to design wafer layouts. Relevant personnel execute the layout design software stored in the storage device through the input and output interface to design the wafer layout. In some embodiments, the wafer layout can be stored in GDS format.

Back to Figure 16. In process 602, a mask pattern is designed based on the designed wafer layout. The mask pattern includes a die pattern corresponding to the die layout of the die 220 and a scribe pattern corresponding to the scribe layout of the scribe 210 , wherein the scribe pattern includes a scribe alignment pattern corresponding to the scribe alignment layout 311 . As shown in FIG. 6A and FIG. 6B , FIG. 6A and FIG. 6B show the strip pattern 4125 and the strip pattern 4128 in the scribe line alignment pattern of the mask pattern.

In some embodiments, the semiconductor processing equipment 100 may have a photomask preparation chamber (not shown in FIG. 1 ). The mask preparation room may include a processor, a storage device, a communication interface, and an input and output interface. The mask preparation room receives the wafer layout designed by the layout design room through the communication interface, and converts it into a mask pattern through the internal database and related programs of the storage device. The format of the mask pattern is, for example, MEBES.

In the process 603, the optical proximity correction is performed on the grain pattern corresponding to the grain layout and the scribe pattern corresponding to the scribe layout in the mask pattern, wherein the optical correction is performed on the scribe alignment pattern of the scribe pattern, such as FIG. 10A, Additional shading strips S1-S4 are provided as shown in FIG. 10B, or additional shading strips S5-S10 are additionally provided as shown in FIG. 14A and FIG. 14B.

In one or more embodiments of the present disclosure, optical proximity correction is essentially performed on two different mask patterns of the die pattern corresponding to the die layout and the scribe pattern corresponding to the scribe layout in the mask pattern, so that The overall DOF of the formed semiconductor structure 200 can be improved.

In some embodiments, optical proximity correction may be performed on the reticle pattern by the reticle preparation chamber of the semiconductor processing facility 100, thereby using lithography enhancement techniques to compensate for image errors such as self-diffraction, interference, and other process effects and similar image errors, as shown in Figures 10A to 10B, and 14A to 14B. In all embodiments, the optical proximity correction can be implemented by modifying the mask pattern in the mask preparation room of the semiconductor processing equipment 100 , for example, modifying the MEBES format file of the mask pattern.

In process 604 , a reticle is fabricated based on the optical proximity corrected reticle pattern. In one embodiment, the scribe line alignment pattern is formed according to FIG. 10A and FIG. 10B , and the corresponding mask is shown in FIG. 11A and FIG. 11B , which has a mask 512 and additional light-shielding bars C1 - C4 . In another embodiment, the scribe line alignment pattern is formed according to FIG. 14A and FIG. 14B, and the corresponding mask is shown in FIG. 15A and FIG. 15B, for example, which has a mask 512 and additional light-shielding bars C5-C10. .

In some implementations, the reticle may be fabricated by a reticle preparation chamber of the semiconductor processing facility 100 . Subsequently, the manufactured photomask is provided as the photomask 130 of the semiconductor processing apparatus 100 .

In process 605 , a plurality of dies 220 and dicing lines 210 surrounding the plurality of dies 220 are formed on the wafer through a photomask, as shown in FIG. 2 , to form a semiconductor structure 200 .

In some embodiments, the photolithography process includes patterning a photoresist, such as a positive photoresist or a negative photoresist. In some embodiments, the photolithography process includes forming a photomask, an anti-reflection structure, or other suitable photolithographic structures. In some embodiments, the material removal process may include a suitable etching process. The opening is then filled with a conductive material, such as metal or other suitable conductive material, such as by deposition or other suitable forming process, such as forming the conductor 212 and the via 216 .

In some embodiments, the die 220 has a die alignment mark 221 and the scribe line 210 has a scribe line alignment mark 211 . Further, the formed scribe line alignment marks 211 are shown in FIG. 12A to FIG. 12B , and the elongated conductors 2121 - 2128 conforming to the scribe line alignment layout 311 are designed not to overlap with each other. In FIG. 13 , the conductive vias 216 correspond to the vias 3161 - 3164 of the scribe line alignment layout 311 , and can be respectively connected to the corresponding elongated conductors 212 . In some embodiments, the die alignment mark 221 may have a structure similar to the scribe line alignment mark 211 .

In process 606 , after forming the semiconductor structure 200 , alignment measurements are performed through the die alignment marks 221 and the scribe line alignment marks 211 . For example, electrical property measurements can be performed on the conductive via 216 in FIG. 13 .

In some embodiments, the die 220 may be singulated along the scribe line 210 after the alignment measurement is performed in the process 606 to ensure the yield of the die 220 . Afterwards, the die 220 may be packaged on other semiconductor substrates to form a package structure.

To sum up, it can improve the size reduction of the lithography process, and the DOF of the semiconductor structure process is very small, so that the whole process is susceptible to the unevenness of the semiconductor wafer or the condition of the yellow light machine, resulting in the out-of-focus of the conductor pattern wires in the dicing line. Alignment issues between vias and conductors arise. For conductors with smaller line widths and some thicker graphics such as alignment graphics in the formed semiconductor structure, it is suitable for yellow light processes with high numerical apertures. Optical proximity correction can be used for modification, and shading strips are set inside or on the boundaries of the graphics. The overall DOF of the graphics is significantly increased, and the stability of the process is improved. With the disclosed method of forming a semiconductor structure, by performing optical proximity correction on both the mask pattern and the die pattern of the dicing line, the overall DOF can be significantly increased.

Although the present disclosure has been disclosed above in terms of implementation, it is not intended to limit this disclosure. Any person with ordinary knowledge in the field may make various changes and modifications without departing from the spirit and scope of this disclosure. Therefore, this disclosure The scope of protection shall be determined by the scope of the attached patent application.

It will be apparent to those skilled in the art that various modifications and changes can be made in the structure of the embodiments of this disclosure without departing from the scope or spirit of the present disclosure. In view of the foregoing, it is intended that this disclosure cover modifications and variations of this invention provided they come within the scope of the appended protection.

100:Semiconductor processing equipment 110: light source 120: Light source processing room 130: mask 140: Wafer table 200: Semiconductor Structures 205: Substrate 206~209: Conductor 210: Cutting Road 211: Cutting lane alignment mark 212: Conductor 213: oxide layer 214: Underlying layer 215: photoresist layer 215O: opening 216: Through hole 220: grain 221: Die Alignment Mark 230: grain 311: Cutting lane alignment layout 3121~3128: Long conductor 3161~3164: Conductive vias 4125,4128: strip pattern 512: mask 600: method 601~606: Process C1~C10: shading strip E1, E2, E3, E4, E5, E6: Edge L1, L2, L3: Rays O1, O2: opening S1~S10: shading strip W1~W12: Width X, Y, Z: direction

The advantages and drawings of the present disclosure should be better understood from the following embodiments and with reference to the accompanying drawings. The descriptions of these drawings are merely examples of implementations, and thus should not be considered as limiting individual implementations or limiting the scope of patent claims for inventions. FIG. 1 shows a schematic diagram of semiconductor processing equipment according to an embodiment of the present disclosure; FIG. 2 shows a schematic diagram of a semiconductor structure according to an embodiment of the present disclosure; Figure 3 shows part of Figure 2; FIG. 4 shows a schematic top view of a scribe line alignment layout; Figure 5A shows part of Figure 4; Figure 5B shows part of Figure 4; FIG. 6A shows a partial mask pattern corresponding to FIG. 5A according to an embodiment of the present disclosure; FIG. 6B shows a partial mask pattern corresponding to FIG. 5B according to an embodiment of the present disclosure; FIG. 7A shows a partial mask corresponding to FIG. 6A according to an embodiment of the present disclosure; FIG. 7B shows a partial mask corresponding to FIG. 6B according to an embodiment of the present disclosure; FIG. 8A shows a schematic top view of a long conductor of a scribe line alignment mark according to an embodiment of the present disclosure; Figure 8B shows a partial schematic cross-sectional view of Figure 8A; FIG. 9 shows a partial schematic cross-sectional view of a scribe line alignment mark according to an embodiment of the present disclosure; FIG. 10A shows a partial mask pattern corresponding to FIG. 5A according to an embodiment of the present disclosure; FIG. 10B shows a partial mask pattern corresponding to FIG. 5B according to an embodiment of the present disclosure; FIG. 11A shows a partial mask corresponding to FIG. 10A according to an embodiment of the present disclosure; FIG. 11B shows a partial mask corresponding to FIG. 10B according to an embodiment of the present disclosure; FIG. 12A shows a schematic top view of a strip conductor of a scribe line alignment mark according to an embodiment of the present disclosure; Figure 12B shows a partial schematic cross-sectional view of Figure 12A; FIG. 13 shows a partial schematic cross-sectional view of a scribe line alignment mark according to an embodiment of the present disclosure; FIG. 14A shows a partial mask pattern corresponding to FIG. 5A according to an embodiment of the present disclosure; FIG. 14B shows a partial mask pattern corresponding to FIG. 5B according to an embodiment of the present disclosure; FIG. 15A shows a partial mask corresponding to FIG. 14A according to an embodiment of the present disclosure; FIG. 15B shows a partial mask corresponding to FIG. 14B according to an embodiment of the present disclosure; and FIG. 16 is a flowchart illustrating a method of forming a semiconductor device according to an embodiment of the present disclosure.

Domestic deposit information (please note in order of depositor, date, and number) none Overseas storage information (please note in order of storage country, institution, date, and number) none

600: method

601~606: Process

Claims (9)

A method of forming a semiconductor structure, comprising: designing a wafer layout, wherein the wafer layout includes a scribe layout having a scribe alignment layout and a die layout having a die alignment layout; based on the wafer circular layout design a mask pattern, wherein the mask pattern includes a scribe pattern corresponding to the scribe layout and a die pattern corresponding to the die layout, the scribe pattern has a scribe alignment layout corresponding The scribe line alignment pattern, and the grain pattern has a grain alignment pattern corresponding to the grain alignment layout; the optical proximity correction is performed on the grain pattern and the scribe line pattern of the mask pattern, wherein the Performing optical proximity correction on the scribe line pattern of the mask pattern includes performing optical proximity correction on the scribe line alignment pattern of the scribe line pattern; manufacturing a reticle based on the optical proximity corrected reticle pattern; and based on the reticle forming a dicing line corresponding to the dicing line pattern and a plurality of crystal grains corresponding to the grain pattern and surrounded by the dicing line on a semiconductor wafer, wherein forming the dicing line on the semiconductor wafer is included in the dicing line A scribe line alignment mark corresponding to the scribe line alignment pattern is formed. The method as claimed in claim 1, wherein: performing optical proximity correction on the grain pattern of the mask pattern comprises performing optical proximity correction on the grain alignment pattern of the grain pattern; and on the semiconductor wafer forming the grains includes forming the scribe line pair The dies are formed after alignment marks, wherein at least one of the dies includes a die alignment mark corresponding to the die alignment pattern. The method as claimed in claim 1, further comprising: after forming the scribe line alignment mark and before forming the dies, performing electrical measurement on the scribe line alignment mark. The method as claimed in claim 1, wherein the scribe line alignment mark comprises a first strip conductor and a second strip conductor extending along a first direction, a first strip conductor on the first strip conductor A conductive via hole and a second conductive via hole on the second elongated conductor, the method further includes: connecting the first elongated conductor and the second conductive via hole through the first conductive via hole and the second conductive via hole Long conductors for electrical measurements. The method as claimed in claim 4, wherein the scribe line alignment mark includes a third strip conductor and a fourth strip conductor extending along a second direction perpendicular to the first direction, on the third strip A third conductive via hole on the conductor and a fourth conductive via hole on the fourth elongated conductor, the method further includes: pairing the third strip through the third conductive via hole and the fourth conductive via hole The conductor conducts electrical property measurement with the fourth conductive via. The method as claimed in claim 4, wherein the scribe line alignment pattern of the mask pattern includes a first strip corresponding to the first strip conductor The pattern corresponds to a second strip pattern of the second strip conductor, the first strip pattern and the second strip pattern extend along the first direction, and performing optical proximity correction on the scribe line alignment pattern further includes : A light-shielding bar extending along the first direction is formed within each of the first strip pattern and the second strip pattern. The method as claimed in claim 4, wherein the scribe line alignment pattern of the mask pattern includes a first strip pattern corresponding to the first strip conductor and a second strip pattern corresponding to the second strip conductor pattern, the first strip pattern and the second strip pattern extend along the first direction, and performing optical proximity correction on the scribe line alignment pattern further includes: between the first strip pattern and the second strip pattern A plurality of first light-shielding strips extending along the first direction are arranged on a plurality of first edges along the first direction; A plurality of second shading strips extending along the second direction are arranged on the plurality of second edges in a second direction. The method according to claim 7, wherein the first shading strips and the second shading strips do not extend to a plurality of junctions between the first edges and the second edges. The method as claimed in claim 1, further comprising: dicing the wafer along the dicing line to separate the dies from each other.