TWI840741B - Manufacturing method of package structure of electronic device - Google Patents

Abstract

A manufacturing method of a package structure of an electronic device including steps below is provided. Providing a carrier plate including a composite structure, wherein the carrier plate has a first surface and a second surface opposite to each other. Forming an anti-warpage structure on the first surface of the carrier plate. Forming a redistribution structure on the second surface of the carrier plate.

Description

Method for manufacturing packaging structure of electronic components

The present invention relates to a method for manufacturing a packaging structure, and in particular to a method for manufacturing a packaging structure of an electronic component.

In the process of manufacturing electronic components, different materials used to form the packaging structure of the electronic components have different physical properties (such as thermal expansion coefficients), which causes the manufactured packaging structure to easily produce warping. When applied to electronic components, it will easily cause the circuit structure in the electronic components to short-circuit and/or abnormal signal transmission, thereby reducing the reliability and electrical properties of the manufactured electronic components.

The present disclosure provides a method for manufacturing a packaging structure of an electronic component. When the manufactured packaging structure is applied to an electronic component, the electronic component can have improved reliability and/or electrical properties.

According to some embodiments of the present disclosure, a method for manufacturing a package structure includes the following steps. First, a carrier is provided, wherein the carrier includes a composite structure and has a first surface and a second surface opposite to each other. Then, an anti-warp structure is formed on the first surface of the carrier. Thereafter, a redistribution structure is formed on the second surface of the carrier.

According to other embodiments of the present disclosure, a method for manufacturing a packaging structure is provided, which includes the following steps. First, a carrier is provided. Then, an encapsulation structure is formed on the carrier, the encapsulation structure including a semiconductor chip and an encapsulation layer and having a third surface and a fourth surface opposite to each other, wherein a connection pad is provided on the surface of the semiconductor chip close to the carrier, and the encapsulation layer exposes the semiconductor chip, wherein the third surface of the encapsulation structure faces the carrier. Thereafter, an anti-warp structure is formed on the fourth surface of the encapsulation structure. Next, the carrier is removed. Then, a redistribution structure is formed on the third surface of the encapsulation structure.

In order to make the above features and advantages of the present disclosure more clearly understood, embodiments are given below and described in detail with reference to the accompanying drawings.

The present disclosure can be understood by referring to the following detailed description and the accompanying drawings. It should be noted that in order to facilitate the reader's understanding and the simplicity of the drawings, the multiple drawings in the present disclosure only depict a portion of the electronic device, and the specific components in the drawings are not drawn according to the actual scale. In addition, the number and size of each component in the figure are only for illustration and are not used to limit the scope of the present disclosure.

Certain terms are used throughout this disclosure and in the accompanying patent claims to refer to specific components. It should be understood by those skilled in the art that electronic device manufacturers may refer to the same component by different names. This document is not intended to distinguish between components that have the same function but different names. In the following description and patent claims, the words "include", "contain", "have" and the like are open-ended words, and therefore should be interpreted as "including but not limited to..." Therefore, when the terms "include", "contain" and/or "have" are used in the description of this disclosure, they specify the existence of corresponding features, regions, steps, operations and/or components, but do not exclude the existence of one or more corresponding features, regions, steps, operations and/or components.

The directional terms mentioned herein, such as "up", "down", "front", "back", "left", "right", etc., are only with reference to the directions of the accompanying drawings. Therefore, the directional terms used are used to illustrate, but not to limit the present disclosure. In the accompanying drawings, each diagram depicts the general characteristics of the methods, structures and/or materials used in a particular embodiment. However, these diagrams should not be interpreted as defining or limiting the scope or nature covered by these embodiments. For example, for the sake of clarity, the relative size, thickness and position of each film layer, region and/or structure may be reduced or exaggerated.

When a corresponding component (such as a film layer or region) is referred to as being "on another component", it may be directly on the other component, or other components may exist between the two. On the other hand, when a component is referred to as being "directly on another component", there is no component between the two. In addition, when a component is referred to as being "on another component", the two have a top-down relationship in a top-down direction, and the component may be above or below the other component, and the top-down relationship depends on the orientation of the device.

The terms "approximately," "equal to," "equal" or "same," "substantially" or "substantially" are generally interpreted as being within 20% of a given value, or within 10%, 5%, 3%, 2%, 1% or 0.5% of a given value or range.

The ordinal numbers used in the specification and patent application, such as "first", "second", etc., are used to modify the components. They do not imply or represent any previous ordinal number of the component (or components), nor do they represent the order of one component to another component, or the order of the manufacturing method. The use of these ordinal numbers is only used to make a component with a certain name clearly distinguishable from another component with the same name. The patent application and the specification may not use the same terms. Accordingly, the first component in the specification may be the second component in the patent application.

It should be noted that the following embodiments can replace, reorganize, and mix the features of several different embodiments to complete other embodiments without departing from the spirit of the present disclosure. The features of each embodiment can be mixed and matched as long as they do not violate the spirit of the invention or conflict with each other.

The electrical connection or coupling described in the present disclosure may refer to direct connection or indirect connection. In the case of direct connection, the endpoints of the components on the two circuits are directly connected or connected to each other by a conductor segment, and in the case of indirect connection, there are switches, diodes, capacitors, inductors, other suitable components, or combinations of the above components between the endpoints of the components on the two circuits, but not limited to these.

In the present disclosure, the thickness, length and width can be measured by an optical microscope, and the thickness can be measured by a cross-sectional image in an electron microscope, but it is not limited to this. In addition, any two values or directions used for comparison may have a certain error. If the first value is equal to the second value, it implies that there may be an error of about 10% between the first value and the second value; if the first direction is perpendicular to the second direction, the angle between the first direction and the second direction may be between 80 degrees and 100 degrees; if the first direction is parallel to the second direction, the angle between the first direction and the second direction may be between 0 degrees and 10 degrees.

The electronic component may have the composite layer circuit structure of the embodiment disclosed herein. The electronic device to which the electronic component disclosed herein is applicable may include display, antenna (such as liquid crystal antenna), light emission, sensing, touch, splicing, other suitable functions, or a combination of the above functions, but is not limited thereto. The electronic device includes a rollable or flexible electronic device, but is not limited thereto. The display device may, for example, include liquid crystal, light emitting diode (LED), quantum dot (QD), fluorescence, phosphor, other suitable materials or a combination of the above. The light emitting diode may, for example, include an organic light emitting diode (OLED), a micro light emitting diode (micro-LED, mini-LED) or a quantum dot light emitting diode (QLED, QDLED), but is not limited thereto. The electronic components may include transistors, circuit boards, chips, dies, integrated circuits (ICs), or combinations thereof or other suitable electronic components, but are not limited thereto.

Exemplary embodiments of the present disclosure are exemplified below, in which the same reference numerals are used in the drawings and description to represent the same or similar parts.

1A to 1C are partial cross-sectional schematic diagrams of a method for manufacturing a packaging structure of an electronic component according to a first embodiment of the present disclosure.

Please refer to FIG. 1A , a carrier CP is provided, wherein the carrier CP includes a composite structure and has a first surface s1 and a second surface s2 opposite to each other. In the present embodiment, the carrier CP includes a first substrate CP1, a second substrate CP2 and an adhesive layer AL1, and the first substrate CP1 and the second substrate CP2 are bonded to each other through the adhesive layer AL1. In detail, the adhesive layer AL1 is disposed between the first substrate CP1 and the second substrate CP2 so that the first substrate CP1 and the second substrate CP2 adhere to each other, thereby having sufficient rigidity to withstand subsequent processes to be performed. The first substrate CP1 and the second substrate CP2 may be, for example, a glass substrate, a silicon substrate, a sapphire substrate or other suitable substrates. In the present embodiment, the first substrate CP1 and the second substrate CP2 are glass substrates, and therefore, the first substrate CP1 and the second substrate CP2 form a double-layer glass structure (Glass on Glass; GOG). In some embodiments, the first substrate CP1 and the second substrate CP2 may have a thickness greater than or equal to 0.5 mm and less than or equal to 1.8 mm (0.5 mm ≦ substrate thickness ≦ 1.8 mm), but the present disclosure is not limited thereto. In some embodiments, the first substrate CP1 and the second substrate CP2 may have a thermal expansion coefficient greater than or equal to 3 ppm/K and less than or equal to 12 ppm/K (3 ppm/K ≦ substrate thermal expansion coefficient ≦ 12 ppm/K), respectively. The thermal expansion coefficient of the first substrate CP1 may be substantially the same as the thermal expansion coefficient of the second substrate CP2; or the thermal expansion coefficient of the first substrate CP1 may be greater than the thermal expansion coefficient of the second substrate CP2, but the present disclosure is not limited thereto. However, the present disclosure is not limited thereto. In some embodiments, the carrier CP has a panel-level size (that is, the area of the carrier CP is greater than or equal to 50 cm x 50 cm). Based on this, the subsequent process to be performed in this embodiment may be the application of fan-out panel level package (FOPLP), wherein the fan-out panel level package includes the above-mentioned redistribution structure first (RDL first) process or chip first process. In this embodiment, the fan-out panel level package adopts a carrier CP with a panel-level size, which can greatly improve the production capacity compared to the wafer-level package. At the same time, the carrier CP with a panel-level size has a rectangular outline, which can also greatly improve the utilization rate of the carrier CP compared to the wafer-level package. Therefore, the packaging structure of the electronic components manufactured in this embodiment can be used to achieve high production requirements.

Referring to FIG. 1B , an anti-warp structure AW is formed on the first surface s1 of the carrier CP. In the present embodiment, the anti-warp structure AW may be a single-layer structure including an organic material, but the present disclosure is not limited thereto. In some embodiments, the anti-warp structure AW may have a thickness greater than or equal to 0.02 millimeters (mm) and less than or equal to 0.2 millimeters (0.02 millimeters ≦ thickness ≦ 0.2 millimeters), but the present disclosure is not limited thereto. In some embodiments, the anti-warp structure AW includes an organic compound having an epoxy group, and the anti-warp structure AW may have a thermal expansion coefficient greater than that of the first substrate CP1. For example, the organic compound having an epoxy group included in the anti-warp structure AW may include an aromatic group such as bisphenol A, benzene, biphenyl, naphthalene, or the anti-warp structure AW may have a thermal expansion coefficient greater than or equal to 30 ppm/K and less than or equal to 180 ppm/K (30 ppm/K≦thermal expansion coefficient≦180ppm/K), but the present disclosure is not limited thereto. In other embodiments, the anti-warp structure AW may have a thermal expansion coefficient greater than or equal to 30 ppm/K and less than or equal to 60 ppm/K (30 ppm/K≦thermal expansion coefficient≦60ppm/K).

Please refer to FIG. 1C , a redistribution structure RDL is formed on the second surface s2 of the carrier CP. In some embodiments, before forming the redistribution structure RDL on the second surface s2 of the carrier CP, a release layer RL may be selectively formed on the second surface s2 of the carrier CP. The provision of the release layer RL allows components subsequently disposed on the carrier CP to be easily separated therefrom. The material of the release layer RL may be, for example, a suitable organic material, but the present disclosure is not limited thereto. In the present embodiment, forming the redistribution structure RDL on the second surface s2 of the carrier CP includes performing the following steps, but the present disclosure is not limited thereto.

First, a metal layer M1 is formed on the second surface s2 of the carrier CP. In some embodiments, before forming the metal layer M1, a seed layer SEED1 may be formed first. The method for forming the seed layer SEED1 may, for example, be formed by a physical vapor deposition process or a chemical vapor deposition process, but the present disclosure is not limited thereto. The material of the seed layer SEED1 may, for example, be metal, and may, for example, have a single-layer structure of a single metal or a composite layer structure of multiple sub-layers formed of different metals, wherein the sub-layers are stacked on each other. For example, the seed layer SEED1 of the present embodiment may include a titanium layer and a copper layer stacked on the titanium layer, and have a composite layer structure, but the present disclosure is not limited thereto. In the present embodiment, forming the metal layer M1 may include performing the following steps. A mask layer (not shown) is formed on the second surface s2 of the carrier CP, wherein the mask layer includes a plurality of openings that expose a portion of the seed layer SEED1, and subsequently the metal layer M1 is formed in the openings by, for example, growing the seed layer SEED1 using an electroplating process. Based on this, the material of the metal layer M1 may be, for example, the same as the material of the seed layer SEED1, but is not limited thereto. In the present embodiment, the material of the metal layer M1 includes copper. In addition, in some embodiments, the metal layer M1 may have a thickness greater than or equal to 0.002 mm and less than or equal to 0.005 mm (0.002 mm≦thickness≦0.005 mm), but the present disclosure is not limited thereto. When the metal layer M1 is a copper layer, it may have, for example, a thermal expansion coefficient greater than or equal to 20 ppm/K and less than or equal to 30 ppm/K (20 ppm/K≦thermal expansion coefficient≦30 ppm/K).

Next, an insulating layer IL1 is formed on the second surface s2 of the carrier CP, wherein the insulating layer IL1 includes an opening OP1 exposing a portion of the metal layer M1. The method for forming the insulating layer IL1 may, for example, include the following steps. First, an insulating material layer (not shown) covering the metal layer M1 is formed on the second surface s2 of the carrier CP, wherein the insulating material layer may, for example, be formed using a chemical vapor deposition process or other suitable processes, and the present disclosure is not limited thereto. Next, a patterning process is performed on the insulating material layer to form an insulating layer IL1 having a plurality of openings OP1, wherein the openings OP1 expose a portion of the metal layer M1. The material of the insulating layer IL1 may be, for example, an organic material, an oxide, a nitride, a phosphosilicate glass, a borophosphosilicate glass or a combination thereof, but the present disclosure is not limited thereto. In the present embodiment, the material of the insulating layer IL1 is polyimide or epoxy. In addition, in some embodiments, the insulating layer IL1 may have a thickness greater than or equal to 0.01 mm and less than or equal to 0.1 mm (0.01 mm≦thickness≦0.1 mm), but the present disclosure is not limited thereto. When the material of the insulating layer IL1 is polyimide, the insulating layer IL1 may, for example, have a thermal expansion coefficient greater than or equal to 30 ppm/K and less than or equal to 60 ppm/K (30ppm/K≦thermal expansion coefficient≦60ppm/K); or the insulating layer IL1 may, for example, have a thermal expansion coefficient greater than or equal to 30 ppm/K and less than or equal to 35 ppm/K (30ppm/K≦thermal expansion coefficient≦35ppm/K). When the material of the insulating layer IL1 is epoxy resin, the insulating layer IL1 may, for example, have a thermal expansion coefficient greater than or equal to 10 ppm/K and less than or equal to 40 ppm/K (10ppm/K≦thermal expansion coefficient≦40ppm/K); or the insulating layer IL1 may, for example, have a thermal expansion coefficient greater than or equal to 15 ppm/K and less than or equal to 20 ppm/K (15ppm/K≦thermal expansion coefficient≦20ppm/K).

In this embodiment, the above steps of forming a metal layer and an insulating layer may be repeated to form a redistribution structure RDL as shown in FIG. 1C , wherein the redistribution structure RDL may be used as a wiring layer of an electronic component to provide a required conductive transmission path. For example, as shown in FIG. 1C , the redistribution wiring structure RDL may include a seed layer SEED1, a metal layer M1, an insulating layer IL1 having a plurality of openings OP1, a seed layer SEED2, a metal layer M2, an insulating layer IL2 having a plurality of openings OP2, a seed layer SEED3, a metal layer M3, an insulating layer IL3 having a plurality of openings OP3, a seed layer SEED4, a metal layer M4, and an insulating layer IL4, but the present disclosure is not limited thereto. It is worth noting that the manufacturing method of the package structure 10 of the present embodiment is described using the above method as an example; however, the forming method of the package structure of the present disclosure is not limited thereto. For example, after forming the redistribution wiring structure RDL, the process of forming a semiconductor chip can be continued, that is, the manufacturing method of the package structure 10 of the present embodiment is a redistribution wiring structure first (RDL first) process. In addition, although the package structure 10 of the present disclosure embodiment is used in panel-level packaging as an example, the present disclosure is not limited to this. The package structure disclosed in the present disclosure can also be applied to various semiconductor devices and/or semiconductor manufacturing processes.

Since a heating process is performed during the formation of the redistribution structure RDL, and the thermal expansion coefficients of the metal layers (for example, metal layers M1, M2, M3 and M4) and the insulating layers (for example, insulating layers IL1, IL2, IL3 and IL4) included in the redistribution structure RDL are greater than the thermal expansion coefficients of the first substrate CP1 and/or the second substrate CP2, after the redistribution structure RDL is set on the second surface s2 of the carrier CP, the edge of the carrier CP will have a tendency to bend toward the direction facing the redistribution structure RDL. In order to solve this technical problem, the present embodiment first sets an anti-warp structure AW on the first surface s1 of the carrier CP opposite to the second surface s2, and the thermal expansion coefficient of the anti-warp structure AW is also greater than the thermal expansion coefficient of the carrier CP. Therefore, after the anti-warp structure AW is set on the first surface s1 of the carrier CP, the edge of the carrier CP will have a tendency to warp in the direction facing the anti-warp structure AW. Based on this, the present embodiment can reduce the warp phenomenon of the package structure 10 caused by the different thermal expansion coefficients of the redistribution structure RDL and the carrier CP when the temperature changes by setting the anti-warp structure AW, so as to improve the reliability and/or electrical properties of the electronic components including the package structure 10. For example, if the thermal expansion coefficient of the anti-warp structure AW is substantially the same as the thermal expansion coefficient of the redistribution structure RDL (for example, the same as the average value of the thermal expansion coefficients of the metal layer and the insulation layer), the package structure 10 may not produce warp.

2A to 2D are partial cross-sectional schematic diagrams of a method for manufacturing a packaging structure of an electronic component according to a second embodiment of the present disclosure. It should be noted that some embodiments of FIG. 2A to FIG. 2D may use the structural numbers and partial contents of the embodiments of FIG. 1A to FIG. 1C , wherein the same or similar numbers are used to represent the same or similar structures, and the description of the same technical contents is omitted.

2A , a carrier CP is provided, wherein the carrier CP includes a composite structure and has a first surface s1 and a second surface s2 opposite to each other. Here, the step of providing the carrier CP is substantially similar to the step shown in FIG. 1A , and will not be described in detail.

2B , an anti-warp structure AW is formed on the first surface s1 of the carrier CP. Here, the step of forming the anti-warp structure AW on the first surface s1 of the carrier CP is substantially similar to the step shown in FIG. 1B , and will not be described in detail here.

Please refer to FIG. 2C , an encapsulation structure E1 is formed on the second surface s2 of the carrier CP. Based on this, the main difference between the manufacturing method of the packaging structure of the present embodiment and the manufacturing method of the aforementioned packaging structure 10 is that before forming the redistribution wiring structure RDL on the second surface s2 of the carrier CP, it further includes a step of forming the encapsulation structure E1. In some embodiments, the encapsulation structure E1 has a third surface s3 facing the second surface s2 of the carrier CP, and the encapsulation structure E1 has a fourth surface s4 away from the second surface s2 of the carrier CP. In the present embodiment, forming the encapsulation structure E1 on the second surface s2 of the carrier CP includes performing the following steps, but the present disclosure is not limited thereto.

First, a semiconductor chip 100 is disposed on the second surface s2 of the carrier CP. The semiconductor chip 100 may include, for example, a packaged semiconductor die, but the present disclosure is not limited thereto. For example, the semiconductor chip 100 may include a semiconductor chip such as an application-specific integrated circuit chip, an analog chip, a digital chip, a voltage regulator chip, a sensor chip, or a memory chip. In some embodiments, a chip adhesive film DAL may be formed between the semiconductor chip 100 and the second surface s2 of the carrier CP so that the semiconductor chip 100 can be attached to the second surface s2 of the carrier CP. The material of the chip adhesive film DAL may include, for example, an organic material, an inorganic material, or other suitable adhesive materials, but the present disclosure is not limited thereto. In the present embodiment, the semiconductor chip 100 is configured in a face-up manner, that is, in some embodiments, a connection pad 102 is provided on a surface of the semiconductor chip 100 away from the carrier CP for electrical connection with a redistribution structure RDL to be provided subsequently.

Next, an encapsulation layer 200 is formed on the second surface s2 of the carrier CP, wherein the encapsulation layer 200 exposes a portion of the connection pad 102. The method for forming the encapsulation layer 200 may, for example, include the following steps. First, an encapsulation material layer (not shown) is formed on the second surface s2 of the carrier CP to surround and cover the semiconductor chip 100, wherein the encapsulation material layer may, for example, be formed using a molding process or other suitable processes, and the present disclosure is not limited thereto. Next, a planarization process (for example, by grinding) is performed on the encapsulation material layer until the connection pad 102 is exposed to form the encapsulation layer 200. The material of the encapsulation layer 200 may, for example, be an organic material or other suitable material, and the present disclosure is not limited thereto. In the present embodiment, the material of the encapsulation layer 200 may be epoxy resin, but is not limited thereto. In addition, in some embodiments, the encapsulation layer 200 may have a thickness greater than or equal to 0.1 mm and less than or equal to 0.2 mm (0.1 mm≦thickness≦0.2 mm), but the present disclosure is not limited thereto. Based on this, the encapsulation layer 200 may, for example, have a thermal expansion coefficient greater than or equal to 40 ppm/K and less than or equal to 60 ppm/K (40ppm/K≦thermal expansion coefficient≦60ppm/K); or the encapsulation layer 200 may, for example, have a thermal expansion coefficient greater than or equal to 40 ppm/K and less than or equal to 45 ppm/K (40ppm/K≦thermal expansion coefficient≦45ppm/K).

Please refer to Figure 2D, a redistribution structure RDL is formed on the second surface s2 of the carrier CP (more specifically, on the fourth surface s4 of the encapsulation structure E1). Here, the steps of forming the redistribution structure RDL are roughly similar to the steps shown in Figure 1C, and will not be repeated here. It is worth mentioning here that the manufacturing method of the packaging structure 20 of the present embodiment is a chip first process. In some embodiments, a plurality of conductive terminals 300 can be formed on the redistribution structure RDL. The conductive terminal 300 can, for example, be arranged on the metal layer M3 of the redistribution structure RDL and electrically connected thereto, so that the conductive terminal 300 can be electrically connected to the semiconductor chip 100 through the redistribution structure RDL. The conductive terminal 300 may be formed, for example, by a ball placement process and a reflow process, but the present disclosure is not limited thereto. In some embodiments, the conductive terminal 300 may be a solder ball as shown in FIG. 2D ; or may be configured as a conductive column or a conductive plug, but the present disclosure is not limited thereto.

Similar to the aforementioned embodiment, the present embodiment can reduce the warping of the package structure 20 caused by the different thermal expansion coefficients of the redistribution structure RDL and/or the encapsulation structure E1 and the carrier CP when the temperature changes by setting the anti-warping structure AW, thereby improving the reliability and/or electrical properties of the electronic components including the package structure 20.

3A to 3E are partial cross-sectional schematic diagrams of a method for manufacturing a packaging structure of an electronic component according to a third embodiment of the present disclosure. It should be noted that some embodiments of FIG. 3A to FIG. 3E may use the structural numbers and partial contents of the embodiments of FIG. 1A to FIG. 1C , wherein the same or similar numbers are used to represent the same or similar structures, and the description of the same technical contents is omitted.

Please refer to Figure 3A, a carrier CP' is provided, wherein the carrier CP' includes a single-layer structure and has a first surface s1 and a second surface s2 opposite to each other. In the present embodiment, the carrier CP' will be removed in a subsequent process, so the carrier CP' may not necessarily include a composite structure and have sufficient rigidity, but the present disclosure is not limited to this. The carrier CP' may be, for example, a glass carrier, a silicon carrier, a sapphire carrier or other suitable carriers. In the present embodiment, the carrier CP' is a glass carrier. In some embodiments, the carrier CP' may have a thickness greater than or equal to 0.5 mm and less than or equal to 1.8 mm (0.5 mm ≦ carrier thickness ≦ 1.8 mm), but the present disclosure is not limited to this. In some embodiments, the carrier CP' has a coefficient of thermal expansion greater than or equal to 3 ppm/K and less than or equal to 12 ppm/K (3ppm/K≦coefficient of thermal expansion≦12ppm/K). In some embodiments, the carrier CP' has a panel-level size. Based on this, in the subsequent process to be performed in this embodiment, for example, a chip may be placed on a carrier CP' having a panel-level size, that is, the manufacturing method of the packaging structure shown in this embodiment may be used, for example, for chip-first process applications. In this embodiment, since the fan-out panel-level package adopts a carrier CP' having a panel-level size, the packaging structure of the electronic components manufactured in this embodiment can also be used to meet the needs of high production capacity.

Referring to FIG. 3B , an encapsulation structure E2 is formed on the carrier CP’. In some embodiments, the encapsulation structure E2 includes a semiconductor chip 100 and an encapsulation layer 200 and has a third surface s3 and a fourth surface s4 facing each other. For example, the third surface s3 of the encapsulation structure E2 faces the second surface s2 of the carrier CP’, and the fourth surface s4 of the encapsulation structure E2 is away from the second surface s2 of the carrier CP’. In this embodiment, forming the encapsulation structure E2 on the second surface s2 of the carrier CP’ includes performing the following steps, but the present disclosure is not limited thereto.

First, a semiconductor chip 100 is disposed on the second surface s2 of the carrier CP’. The semiconductor chip 100 may, for example, include a packaged semiconductor die, but the present disclosure is not limited thereto. For example, the semiconductor chip 100 may include a semiconductor chip such as an application-specific integrated circuit chip, an analog chip, a digital chip, a voltage regulator chip, a sensor chip, or a memory chip. In addition, in some embodiments, a connection pad 102 is disposed on the second surface s2 of the semiconductor chip 100 close to the carrier CP’ for electrical connection with a redistribution structure RDL to be subsequently disposed. In some embodiments, an adhesive layer AL2 may be formed between the semiconductor chip 100 and the second surface s2 of the carrier CP’ so that the semiconductor chip 100 can be attached to the second surface s2 of the carrier CP’, but the present disclosure is not limited thereto. That is, in this embodiment, the semiconductor chip 100 is disposed face down, but the present disclosure is not limited thereto. The material of the adhesive layer AL2 may include, for example, a thermal release material, an organic material, an inorganic material or other suitable adhesive materials, but the present disclosure is not limited thereto.

Next, an encapsulation layer 200 is formed on the second surface s2 of the carrier CP’, wherein the encapsulation layer 200 exposes a portion of the semiconductor chip 100. The method for forming the encapsulation layer 200 may, for example, include the following steps. First, an encapsulation material layer covering and surrounding the semiconductor chip 100 is formed on the second surface s2 of the carrier CP, wherein the encapsulation material layer may, for example, be formed using a molding process or other suitable processes, and the present disclosure is not limited thereto. Next, a planarization process is performed on the encapsulation material layer until the semiconductor chip 100 is exposed to form the encapsulation layer 200. The material of the encapsulation layer 200 may, for example, be an organic material or other suitable material, and the present disclosure is not limited thereto. In the present embodiment, the material of the encapsulation layer 200 may be an epoxy resin. In addition, in some embodiments, the encapsulation layer 200 may have a thickness greater than or equal to 0.1 mm and less than or equal to 0.2 mm (0.1 mm≦thickness≦0.2 mm), but the present disclosure is not limited thereto. Based on this, the encapsulation layer 200 may, for example, have a thermal expansion coefficient greater than or equal to 40 ppm/K and less than or equal to 60 ppm/K (40ppm/K≦thermal expansion coefficient≦60ppm/K); or the encapsulation layer 200 may, for example, have a thermal expansion coefficient greater than or equal to 40 ppm/K and less than or equal to 45 ppm/K (40ppm/K≦thermal expansion coefficient≦45ppm/K).

3C , an anti-warp structure AW is formed on the fourth surface s4 of the encapsulation structure E2 . Here, the step of forming the anti-warp structure AW on the fourth surface s4 of the encapsulation structure E2 is substantially similar to the step shown in FIG. 1B , and will not be described in detail here.

Referring to FIG. 3D , the carrier CP’ is removed. In the present embodiment, the adhesive layer AL2 is removed while the carrier CP’ is removed. The carrier CP’ may be removed by, for example, performing a suitable stripping process, but the present disclosure is not limited thereto. In the present embodiment, after the carrier CP’ is removed, the third surface s3 of the encapsulation layer 200 exposes the connection pad 102.

Referring to FIG. 3E , a redistribution wiring structure RDL is formed on the third surface s3 of the encapsulation structure E2. Here, the step of forming the redistribution wiring structure RDL on the third surface s3 of the encapsulation structure E2 is roughly similar to the step shown in FIG. 1C , and will not be repeated here. It is worth mentioning here that the manufacturing method of the package structure 30 of this embodiment is a chip first process.

In addition, the package structures 10, 20 and 30 of the above-mentioned embodiments can be bonded to electronic components such as integrated circuit chips and/or printed circuit boards in subsequent manufacturing processes, but the present disclosure is not limited thereto. The above-mentioned bonding method can be, for example, by providing a bonding pad between the redistribution structure RDL and the electronic component, but the present disclosure is not limited thereto.

In summary, some embodiments of the present disclosure provide a method for manufacturing a packaging structure by disposing an anti-warp structure on a surface of a carrier opposite to a surface on which a redistribution structure and/or an encapsulation structure is disposed. This can reduce the warp of the packaging structure caused by the different thermal expansion coefficients of the redistribution structure and/or the encapsulation structure and the carrier when the temperature changes, thereby improving the reliability and/or electrical properties of the electronic components including the packaging structure.

Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present disclosure, rather than to limit them; although the present disclosure is described in detail with reference to the above embodiments, ordinary technicians in this field should understand that they can still modify the technical solutions described in the above embodiments, or replace part or all of the technical features therein with equivalent ones; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present disclosure. The features of the embodiments can be mixed and matched as long as they do not violate the spirit of the invention or conflict with each other.

10, 20, 30: packaging structure 100: semiconductor chip 102: connection pad 200: encapsulation layer 300: conductive terminal AL1, AL2: adhesive layer AW: anti-warp structure CP, CP’: carrier CP1: first substrate CP2: second substrate DAL: chip adhesive film E1, E2: encapsulation structure IL1, IL2, IL3, IL4: insulation layer M1, M2, M3, M4: metal layer OP1, OP2, OP3: opening RDL: redistribution structure RL: release layer s1: first surface s2: second surface s3: third surface s4: fourth surface SEED1, SEED2, SEED3, SEED4: seed layer

Figures 1A to 1C are partial cross-sectional schematic diagrams of a method for manufacturing a packaging structure of an electronic component according to a first embodiment of the present disclosure. Figures 2A to 2D are partial cross-sectional schematic diagrams of a method for manufacturing a packaging structure of an electronic component according to a second embodiment of the present disclosure. Figures 3A to 3E are partial cross-sectional schematic diagrams of a method for manufacturing a packaging structure of an electronic component according to a third embodiment of the present disclosure.

10: Packaging structure

AL1: Adhesive layer

AW: Anti-warp structure

CP: Carrier board

CP1: First substrate

CP2: Second substrate

IL1, IL2, IL3, IL4: Insulation layer

M1, M2, M3, M4: metal layer

OP1, OP2, OP3: Opening

RDL: redistribution structure

RL: Release layer

s1: first surface

s2: Second surface

SEED1, SEED2, SEED3, SEED4: seed layer

Claims (9)

A method for manufacturing a packaging structure of an electronic component, comprising: providing a carrier, wherein the carrier comprises a composite structure and has a first surface and a second surface opposite to each other; forming an anti-warping structure on the first surface of the carrier; and forming a redistribution structure on the second surface of the carrier, wherein before forming the redistribution structure on the second surface of the carrier, the method further comprises the following steps: forming a semiconductor chip on the second surface of the carrier, wherein a connection pad is disposed on a surface of the semiconductor chip away from the carrier; and forming an encapsulation layer on the second surface of the carrier, wherein the encapsulation layer exposes the connection pad, and the semiconductor chip is electrically connected to the redistribution structure through the connection pad. A method for manufacturing a packaging structure of an electronic component as described in claim 1, wherein the carrier comprises a first substrate, a second substrate and an adhesive layer, wherein the first substrate and the second substrate are bonded to each other through the adhesive layer. A method for manufacturing a packaging structure of an electronic component as described in claim 2, wherein the anti-warp structure has a thermal expansion coefficient greater than the thermal expansion coefficient of the first substrate. A method for manufacturing a packaging structure of an electronic component as described in claim 3, wherein the anti-warp structure has a thermal expansion coefficient greater than or equal to 30ppm/K and less than or equal to 180ppm/K, and the first substrate has a thermal expansion coefficient greater than or equal to 3ppm/K and less than or equal to 12ppm/K. A method for manufacturing a packaging structure of an electronic component as described in claim 1, wherein the anti-warp structure includes an organic compound having an epoxy group. The manufacturing method of the packaging structure of the electronic component as described in claim 1, wherein forming the redistribution structure on the second surface of the carrier includes the following steps: forming a metal layer on the second surface of the carrier; and forming an insulating layer on the second surface of the carrier, wherein the insulating layer includes an opening exposing a portion of the metal layer. A method for manufacturing a packaging structure of an electronic component, comprising: providing a carrier; forming an encapsulation structure on the carrier, the encapsulation structure comprising a semiconductor chip and an encapsulation layer and having a third surface and a fourth surface facing each other, wherein a connection pad is provided on a surface of the semiconductor chip close to the carrier, and the encapsulation layer exposes the semiconductor chip, wherein the third surface of the encapsulation structure faces the carrier; forming an anti-warp structure on the fourth surface of the encapsulation structure; removing the carrier; and forming a redistribution structure on the third surface of the encapsulation structure. A method for manufacturing a packaging structure of an electronic component as described in claim 7, wherein the anti-warp structure has a thermal expansion coefficient greater than or equal to 30ppm/K and less than or equal to 180ppm/K, and the carrier has a thermal expansion coefficient greater than or equal to 3ppm/K and less than or equal to 12ppm/K. A method for manufacturing a packaging structure of an electronic component as described in claim 7, wherein the anti-warp structure includes an organic compound having an epoxy group.

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