TWI739901B - Secure chips with serial numbers - Google Patents

Abstract

An electronic device comprising a semiconductor chip which comprises a plurality of structures. The chip is a member of a set of chips. The set of chips comprises a plurality of subsets of chips. The chip is a member of only one of the subsets. The structures of the chip include a set of common structures which is the same for all of the chips of the set, and a set of non-common structures. The non-common structures of the subset are different from the non-common structures in every other subset. A first portion of the non-common structures is adapted to store or generate a first predetermined value. The first predetermined value is readable from outside the semiconductor chip by automated reading means. The first portion of the non-common structures is functionally independent from the common structures.

Description

Security chip with serial number

The present invention relates to electronic devices including semiconductor wafers. More specifically, the present invention relates to an electronic device including a semiconductor chip having a common part and a unique part forming a unique circuit. The present invention further relates to a system for authentication between a plurality of remote terminals including such electronic devices and a host system based on an inquiry response program, remote terminals for use in such systems, and for use in such systems The method of verification in the system.

In the semiconductor industry, lithography systems are used to produce (ie, manufacture) electronic devices that are usually in the form of integrated circuits formed on silicon wafers (commonly referred to as semiconductor wafers). The lithography utilizes a reusable optical mask to project an image representing the pattern of the desired circuit structure onto the silicon wafer as part of the manufacturing process. The mask is repeatedly used to image the same circuit structure on different parts of the silicon wafer and on subsequent wafers, so that a series of the same chips are manufactured from each wafer, and each chip has the same circuit design.

Various technologies related to security such as data security, secure communication, traceability, verification, anti-counterfeiting, etc. produce a continuation of unique chips with unique circuits or codes or other unique hardware features used to diversify the chips Increasing demand. Such unique chips are known to us and often perform safety-related operations in obscure ways that require the chips to be truly unique. Known unique chips are usually manufactured after the chip is manufactured (for example) by using the conventional mask-based lithography to manufacture a series of identical chips and then after the manufacture, destroy certain connections in the chip, or by detecting and controlling Certain features are then implemented to evaluate the uniqueness of the chip. The mask used in this process is expensive to produce, and it is obviously too expensive to manufacture a unique mask for each single chip. For this reason, it is considered that mask-based lithography is not suitable for manufacturing a unique chip.

Semiconductor chips can be generated to contain predetermined data or program codes, that is, in the form of readable data, usually using mask ROM (MROM), erasable programmable read-only memory (EPROM) or electrically erasable Programmable read-only memory (EEPROM). The MROM variant uses mask-based lithography to generate a ROM containing data permanently stored in ROM. When a chip with a unique code is generated, it has the disadvantages of mask-based lithography identified above. EPROM and EEPROM allow data to be written to ROM later, but this disadvantageously takes the control of the program code away from the manufacturing process and introduces security risks.

It has been proposed to utilize maskless lithography for the purpose of producing unique wafers. Under unmasked lithography, a hard mask is not used, and the desired pattern representing the circuit design is instead transferred to the target (eg wafer) design layout data file such as GDSII or OASIS file containing the circuit design layout The form is input to the unmasked lithography system for exposure by the unmasked lithography system.

The unmasked lithography and data input system is disclosed in WO 2010/134026 in the name of the applicant of the present invention. WO 2010/134026 is incorporated herein by reference in its entirety. The disclosed maskless system directly uses a charged particle beamlet such as an electron beamlet to write the pattern onto the wafer. Since the desired pattern for exposing each wafer is expressed as a data rather than a mask, it becomes possible to use such a system to manufacture unique wafers. The pattern data input to the exposure system representing the unique electronic device or chip to be generated can be made unique to each unique electronic device to be generated by using different design layout data input files (such as GDSII or OASIS input files).

WO 2011/117253 and WO 2011/051301, both of which are assigned to the applicant of the present invention and incorporated herein by reference in their entirety, disclose various examples of electronic devices or wafers that can be produced using a charged particle lithography system.

The present invention solves the problems of the prior art and provides an electronic device including a semiconductor chip according to an aspect of the present invention. The semiconductor wafer may include a plurality of structures formed in the semiconductor wafer. The semiconductor wafer may be a member of a collection of semiconductor wafers, where the semiconductor wafers of the collection include multiple subsets of semiconductor wafers, and the semiconductor wafer is only a member of one of the subsets. The subsets of semiconductor wafers may each include only a single wafer so that each wafer of the set is unique, or each subset may include, for example, two wafers, so that each wafer has a single identical spare part. The set of semiconductor chips may be composed of chips that all have a single design for performing the same function. The chips all have the same input terminals and output terminals and are designed to operate in the same system, but each subset of the chips includes different A non-common circuit for the circuits formed in all other chips in the set. The set of semiconductor wafers may include, for example, all wafers formed from a single wafer.

The semiconductor wafer may include a plurality of structures formed in the semiconductor wafer. The multiple structures of the semiconductor wafer include a common structure set that is the same for all semiconductor wafers of the set, and is the same for all semiconductor wafers of the subset and different for all semiconductor wafers of the set that are not in the subset. A collection of non-common structures. At least the first part of the non-common structure is used to store or generate a first predetermined value, wherein the first predetermined value can be read from the outside of the semiconductor chip by an automatic reading component.

The non-common structure is functionally independent of the common structure. Therefore, although the power line or the ground line can be shared with the common structure, the non-common structure does not change or affect the function of the common structure.

The non-common structure may be formed in a region of the semiconductor wafer separated from the common structure, thereby separating the non-common structure from the common structure. The separation of non-common structure and common structure can be achieved within a single layer or by forming non-common structure and common structure in different layers.

The non-common structure is formed on at least one layer of the semiconductor wafer. A charged particle multi-beam lithography system can be used to form all of this at least one layer. Advantageously, other lithography systems, such as mask-based lithography systems, are not required to generate layers containing non-common structures, thereby reducing manufacturing complexity, reducing manufacturing costs, and reducing processing time in facilities.

The at least one layer including a non-common structure may further include a common structure. In this case, a charged particle multi-beam lithography machine can also be used to form a common structure in the at least one layer. Therefore, a charged particle multi-beam lithography machine can be used to form the entire layer including non-common structures and common structures. .

Automatic electromagnetic reading components (such as using non-contact sensors), optical reading components (such as using a small QR code embedded in the upper layer of the optical scanning chip), and electronic reading components (such as using probes or by At least one of receiving the output signal from the wafer) reads the first predetermined value from the outside of the semiconductor wafer. The first predetermined value may be, for example, a serial number, a cryptographic key such as a public key, an account number, a network address such as a media access control (MAC) address or an Internet protocol (IP) address, or an identification code.

The first predetermined value can be written multiple times in the semiconductor chip, so that, for example, the first reading can be read by the electronic reading member and the second reading can be read by the optical reading member. If the two readings do not produce the same value, it can be determined that the semiconductor wafer has been tampered with.

The first predetermined value can be read from the structure of the second part of the non-common structure, for example, by using an optical sensor for scanning the structure or other suitable sensors to detect the shape of the structure. The shape of the second part of the non-common structure can be used to store the first predetermined value, for example, by forming a metal layer in the shape of a small barcode or QR code, or a collection of optically recognizable metal lines, vias, or circuits. This layer is preferably in the middle or lower layer, that is, the top layer of a non-semiconductor wafer, or a structure that can be formed on more than one layer.

Optically readable values can be advantageously used to track wafers throughout the production process in a facility, thereby avoiding the need to mark or mark wafers in a separate marking step after production.

The first non-common circuit may be formed by the first portion of the non-common structure of the semiconductor wafer and the first portion of the common structure of the semiconductor wafer, wherein the circuit configuration of the first non-common circuit of the semiconductor wafers of each subset is different from that of each of the other subsets. The circuit configuration of any semiconductor chip.

The first non-common circuit may include a read-only memory circuit, which may be manufactured by a first predetermined value pre-stored in the read-only memory circuit. For example, the first predetermined value can be stored by the presence or absence of memory cell elements in the read-only memory circuit or by the connection or disconnection of the memory cell elements. When using the conventional ROM structure, the memory cell elements (such as A predetermined one of a transistor or a diode, etc.) to generate a ROM storing the first predetermined value. In this way, a read-only memory circuit with pre-stored values can be formed during the manufacturing process. This type of ROM that stores a predetermined value in its structure made during the chip manufacturing process can be made feasible by using maskless lithography, where the first predetermined value can be unique in the set of semiconductor chips.

The first non-common circuit may include a logic circuit to generate the first predetermined value. The first predetermined value can be stored by the presence or absence of interconnections in the logic circuit or the presence or absence of circuit elements in the logic circuit, so that the first predetermined value can be effectively stored in the structure of the logic circuit.

The memory circuit or logic circuit may include transistors (or other functional elements) and interconnections, which may be formed or not formed (or formed with varying structures) or connected, disconnected, or disconnected during the wafer manufacturing process. The OR transistor (or other active element) is connected to generate a logic circuit, and the logic circuit generates a first predetermined value. One convenient method is to use conductive vias in memory or logic circuits, where vias are formed or not formed during the manufacturing process to provide a memory circuit that will store a first predetermined value or a logic circuit that will generate a first predetermined value. In this way, the memory or logic circuit can pre-store the first predetermined value during the manufacturing process.

The first predetermined value of the semiconductor wafer may be different from the predetermined value of each other semiconductor wafer of the set of semiconductor wafers. In addition, the set of non-common structures of semiconductor wafers may be different from the set of non-common structures of every other semiconductor wafer of the set of semiconductor wafers. The first non-common circuit may include a memory or logic circuit that is the same for all semiconductor chips in the subset and different from all semiconductor chips in the set that are not in the subset, wherein the first predetermined value is uniquely Identify the first non-common circuit.

Common structures and non-common structures of semiconductor wafers can be interconnected to form one or more electronic circuits. The electronic device may include at least one input terminal and at least one output terminal, and the first non-common circuit may be connected to the input terminal and the output terminal, wherein the first predetermined value can be electronically read from the output terminal. The electronic device may include at least one input terminal for receiving an inquiry and at least one output terminal for outputting a response, and the electronic circuit may form an inquiry response circuit connected to the at least one input terminal and at least one output terminal, wherein the inquiry response circuit is used for Since the response is generated at the at least one output terminal based on the query applied to the at least one input terminal, the query and the response have a predetermined relationship. The response generated by the query response circuit may depend on both the query applied to the at least one input terminal and the first predetermined value.

The electronic device may also have a second non-common circuit formed by the second portion of the non-common structure of the semiconductor wafer and the second portion of the common structure of the semiconductor wafer. The circuit configuration of the second non-common circuit of the semiconductor chips in each subset may be different from the circuit configuration of any semiconductor chip in each of the other subsets. The second non-common circuit can be used to store or generate a second predetermined value that can be read from the outside of the semiconductor chip by the automatic reading component. The second non-common circuit may include a read-only memory circuit, which can be manufactured by a second predetermined value pre-stored in the read-only memory circuit, similarly as for the only non-common circuit formed by the first non-common circuit. Read the description of the memory circuit. The second non-common circuit may include a logic circuit for generating the second predetermined value, similarly as described for the logic circuit formed by the first non-common circuit. The first predetermined value of the wafer may have a value that uniquely identifies the second non-common circuit.

The plurality of structures may be formed in three or more than three layers of the semiconductor wafer, including one or more non-common layers containing non-common structures, such that at least one common layer is formed on the one or more non-common layers Above the layers, at least one of the common layers contains a common structure but no non-common structure. Optionally, all non-common structures may be formed on only one layer of the semiconductor wafer. The semiconductor wafer may also include at least a second common layer lower than the one or more non-common layers, and the second common layer contains a common structure but no non-common structure. In this way, layers containing non-common structures can be "buried" under other layers, making it more difficult to determine the structure without expensive reverse engineering of the wafer. The multiple structures of the electronic device may be formed in multiple layers of the semiconductor wafer, and the non-common structure may include at least one of the following: the connection between the metal layers of the multiple layers; the metal layer and the The connection between the gates in the contact layer of the plurality of layers; the connection in the local interconnection layer of the plurality of layers; and the P doping of the transistor or the diode of one of the plurality of layers Or N-doped diffusion region.

A maskless lithography process such as exposure using a charged particle multi-beam lithography system or an electron beam system can be used to form the non-common structure of the one or more common layers, and a mask-based lithography process can be used Form a common layer. The use of a maskless lithography process to form a non-common structure enables the formation of the first and second non-common circuits with extremely high information storage density, and the use of printed circuits, fuses, single-time programmable circuits and memory, etc. Compared to the previous method, the density is much higher. This extremely high information density enables non-common circuits to store extremely long predetermined values, such as extremely long cryptographic keys or multiple long cryptographic keys. The extremely small feature sizes of non-common structures and circuits that can be achieved when using maskless lithography (for example, feature sizes less than 50 nm) make non-common circuits smaller in area and/or distributed over multiple layers. Different from the previously known technology, this makes it more difficult to discover the data stored in the non-common circuit of the circuit layout of the non-common circuit by inspecting the chip or by reverse engineering the chip. When a maskless lithography process is used to form non-common structures such as connections between metal layers, these can be formed by merging two conductive vias to form double vias.

According to one aspect of the present invention, a system for verifying between multiple remote terminals and a host system based on a query response procedure is proposed. Each of the remote terminals may include an electronic device as described above.

According to another aspect of the present invention, a remote terminal for use in the system described above is proposed.

According to one aspect of the present invention, a verification method in the system described above is proposed. The method may include distributing the remote terminal to multiple users, sending the query autonomous system to one of the remote terminals, receiving a response from the remote terminal, and verifying to the remote terminal whether the response has a predetermined relationship with the query.

An electronic device as described above can be manufactured in which a maskless lithography system such as a charged particle multi-beam lithography system is used to form at least a part of a non-common structure. A mask-based lithography system may be used to form at least the first part of the common structure and a maskless lithography system may be used to form the first part of the non-common structure.

In one embodiment, the first predetermined value defined by the non-common structure can be read from the electronic device to track the electronic device during the manufacturing process.

The pattern data used to control the maskless lithography exposure system can be designed to include a common chip design portion that can be used to generate a common structure and a unique or non-common chip design portion that can be used to generate a non-common structure of a semiconductor wafer. Specifically, the unique or non-common wafer design portion can be added to the pattern data just before exposing the target (such as a wafer) on which the semiconductor will be formed. This can be in the form of unique pattern data or in the form of information used to generate unique pattern data. The pattern information may be based in part on the secret information provided to the maskless lithography system during the generation of the unique or non-common design layout portion. The secret data can be derived from a unique data generator such as a black box component. These measures enable the unique or non-common design data to be kept under the control of the operator of the lithography system, and to minimize the time period during which the design data is exposed to external detection or interference. This is the unique manufacturing method described above. Electronic devices enhance safety. Another benefit is that the required design time and processing time and memory can be kept low. This is because the common chip design part can be reused to generate multiple chips, avoiding the design and processing time normally required to generate unique chips.

The electronic device including the semiconductor wafer as described above and in the embodiments described below may include a unique (non-common) circuit to provide a function in a security system that depends on the uniqueness of the circuit. For example, an electronic device can be used in a secure communication or transaction system to provide verification services, where the first non-common circuit of a semiconductor chip includes data such as a mask ROM manufactured with a pre-stored value and used to output the value A storage circuit, where the value includes an ID number or code that uniquely identifies the electronic device. The second non-common circuit may include a logic or cryptographic circuit to receive an input value (such as a query input) and generate a unique output in response to the input, the input together with the ID to authenticate the electronic device to the security system.

In another example, the electronic device can be used in an equipment management system, where the first non-common circuit is used to output an ID number or code that uniquely identifies the electronic device as in the above example, and the second non-common circuit is used to respond to input Generate output to enable the function or feature of the circuit of the electronic device, or enable the function or feature of software running on the electronic device or on another device. The second non-common circuit can be used to apply a decryption algorithm dedicated to the electronic device, or to apply a decryption key dedicated to the electronic device to decrypt the input, which can be based on the algorithm or key of a specific chip To encrypt the input.

In another example, the electronic device can be used in a cryptographic data storage system, where the first non-common circuit is used to output an ID number or code that uniquely identifies the electronic device as in the above example, and the second non-common circuit is used to input Receiving data, performing encryption on the received data, and outputting encrypted data, where the encryption key and/or encryption algorithm used by the electronic device to encrypt the data is unique to the electronic device.

In another example, the electronic device can be used in a communication network, where the first and/or second non-common circuit includes a data storage circuit manufactured with a pre-stored value and used to output the value, such as a media access control (MAC) address or Internet Protocol (IP) address, which uniquely identifies the electronic device on the network. The electronic device can also be used in a manufacturing facility, where the first and/or second non-common circuit includes a data storage circuit manufactured to have a pre-stored value and used to output one or more values, such as an ID code Or a cryptographic key used to connect an electronic device with a personalization element in which the electronic device will be placed (such as a smart ID chip placed in a passport or bank card or ship, where the cryptographic key is placed in the personalized communication In the device) uniquely match. The electronic device can be used to output a pre-stored value in response to the query and read by the machine that places the electronic device in the personalization component.

In another example, the electronic device can be used to securely match the serial number with the cryptographic key. The extremely high information density of the chip layer written by maskless lithography, for example, enables the first non-common circuit to store the first predetermined value such as the serial number (which is short and easy to communicate and query) and makes the second non-common circuit The circuit can store a very long secret cryptographic key or multiple long cryptographic keys. The possibility of extremely large cryptographic keys allows, for example, one-time key (OTP) encryption that requires the key to have the same length as the message sent, and is impossible to crack. The extremely small feature size possible when using unmasked lithography also makes it extremely difficult to retrieve cryptographic keys by inspection or reverse engineering of the chip.

Various aspects and embodiments of the present invention will be further defined in the following description and the scope of the patent application.

Hereinafter, embodiments of the present invention will be described in more detail. However, it should be understood that these embodiments should not be regarded as limiting the scope of protection of the present invention.

1‧‧‧Lithography Machine

1A‧‧‧Charged Particle Lithography System

3‧‧‧Electron source

4‧‧‧Homogeneous extended electron beam

5‧‧‧Collimating lens

6A‧‧‧Aperture array

6B‧‧‧Second Orifice Array

7‧‧‧Small beam

9‧‧‧Beam Blanking Array

10‧‧‧Beam stop array

20‧‧‧Electronic Optics Cylinder

21‧‧‧Condenser lens array

22‧‧‧End Module

24‧‧‧wafer

25‧‧‧Wafer positioning system

30‧‧‧Data Path Subsystem

100‧‧‧Unique chip

101‧‧‧Common part

102‧‧‧Individualized area

102a‧‧‧Part One

102b‧‧‧Part II

102c‧‧‧Unique part

201‧‧‧Bottom metal layer

201a‧‧‧Common structure

201b‧‧‧Common structure

201c‧‧‧Common structure

202‧‧‧Isolation layer

202a‧‧‧Common structure

202b‧‧‧non-common structure

202c‧‧‧Common structure

203‧‧‧membrane

204‧‧‧membrane

205‧‧‧Resist

206‧‧‧Resist

207‧‧‧Conductive layer

208‧‧‧Floor

208a‧‧‧Common structure

208b‧‧‧Common structure

208c‧‧‧Common structure

209‧‧‧Floor

209a‧‧‧Common structure

209b‧‧‧Common structure

209c‧‧‧Common structure

211a‧‧‧Metal layer

211b‧‧‧Metal layer

217a‧‧‧Circular through hole

217b‧‧‧Circular through hole

217c‧‧‧Through hole

217d‧‧‧Through hole

217e‧‧‧Through hole

301A‧‧‧Photography System

301B‧‧‧Photography System

301C‧‧‧Photography System

301D‧‧‧Photography System

302‧‧‧Main System

303‧‧‧Cluster Interface

304‧‧‧Operator console

305‧‧‧Cluster component interface

306‧‧‧Cluster front end

307‧‧‧Micro shadow system interface

312‧‧‧Component control unit

314‧‧‧Data Network Hub

315‧‧‧Plug-in client

316‧‧‧Micro Shadow System

318‧‧‧Pattern data processing unit

319‧‧‧Pattern Streamer

320‧‧‧Data path

330‧‧‧Unique data generator

340‧‧‧External Provider

401‧‧‧Communication

402‧‧‧Communication

403‧‧‧Communication

405‧‧‧Communication

406‧‧‧Link

420‧‧‧Control network

421‧‧‧Data Network

430‧‧‧Unique chip design data

440‧‧‧Secret Information

1022‧‧‧Pretreatment

1071A‧‧‧Processing stage

1071B‧‧‧Streaming stage

1073‧‧‧Processing stage

2007‧‧‧GDS-II design layout data

2008‧‧‧Vector data

2009‧‧‧Data

3010‧‧‧Step

3011‧‧‧Step

3012‧‧‧4-bit grayscale bitmap format

3020‧‧‧Step

3021‧‧‧Picture system streamer bitmap data

3022‧‧‧Step

3030‧‧‧Step

3031‧‧‧Step

3032‧‧‧Step

3040‧‧‧Step

3041‧‧‧Step

3042‧‧‧Step

3043‧‧‧Step

The embodiment will now be described as an example only with reference to the accompanying schematic drawings, in which corresponding element symbols indicate corresponding parts, and in the drawings: FIG. 1 shows an exemplary embodiment of the present invention. Simplified unique chips and wafers with multiple unique chips.

Figure 2 shows a simplified schematic diagram of an exemplary embodiment of a charged particle multi-beam lithography system.

Fig. 3 is a conceptual diagram showing an exemplary maskless lithography system.

4A to 4D are schematic diagrams of exemplary embodiments of a network architecture used in the lithography system according to the present invention.

Fig. 5 shows an exemplary functional flow chart of an embodiment of displaying a data path using a solid line rasterization.

Figure 6 shows a process for producing a unique wafer according to an exemplary embodiment of the present invention.

Figure 7 shows a process for producing a unique wafer according to another exemplary embodiment of the present invention.

Figure 8 shows a process for producing a unique wafer according to another exemplary embodiment of the present invention.

FIG. 9 shows a method for combining mask-based lithography and maskless lithography to produce a unique wafer according to another exemplary embodiment of the present invention.

Figure 10 shows a unique chip having a unique portion including a unique circuit and associated unique predetermined values according to another exemplary embodiment of the present invention.

FIG. 11 shows a unique wafer having a layer storing unique predetermined values according to another exemplary embodiment of the present invention.

12A to 12D show conductive vias formed using a conventional process and a maskless lithography process according to another exemplary embodiment of the present invention.

The drawings are only meant for illustrative purposes, and are not intended to limit the scope or protection as defined by the scope of the patent application.

In the following examples, reference to "chip" or "semiconductor chip" refers to an integrated circuit fabricated on a semiconductor wafer. However, it should be understood that the present invention is not limited to wafers and is more generally applicable to generating electronic devices with individualized (e.g., unique) characteristics. Electronic devices may include chips or other types of electronic circuits that have one or more inputs and outputs and function to store data and process inputs to generate specific outputs.

The process of using charged particle multi-beam lithography to write patterns on a target such as a semiconductor wafer is also referred to herein as electron beam (e-beam) exposure. These exposure methods are maskless exposure methods, in which the pattern to be exposed on the target is reflected (usually) in the data streamed to the lithography system, rather than in a predefined mask. The charged particle/electron beam used to write a target such as a wafer during exposure is referred to herein as a beamlet.

Individualized chips are referred to herein as "unique" chips. This refers to a chip that is designed and manufactured with a unique circuit structure compared to other chips, so that the function of the unique chip is different from other chips. The unique chip is usually one chip in a larger collection of chips with the same purpose and the same general function but with slightly different circuits. For example, the chip set may include a read-only memory (ROM) with a certain data storage capacity, and each chip of the set is manufactured so that it stores a predetermined data value in the ROM, wherein the data value is Each wafer in the wafer set is different. In another example, the chip set may include a circuit for generating a predetermined output value when provided with a predetermined input value, wherein when the same input value is provided, the output value is the same for each chip in the chip set. Different; or wherein each chip in the chip set produces a unique combination of output values for the input value.

It should be noted that it is not ruled out that more than one chip in the chip set can have the same design, for example, to produce spare chips for use in the case of chip damage of the same design, or to use for some other reason. The reason produces the same batch of wafers. Therefore, the wafer set can be divided into subsets, where the wafers in each subset are designed to be the same, but they are designed to be different from the wafers in each of the other subsets. A unique chip that is designed to be different from every other chip can be called a truly unique chip, that is, the subset size is one.

The unique portion of the chip, the unique structure of the portion formed as the unique chip, and the unique design data of the portion used to generate the unique chip are also referred to herein as non-common portions, non-common structures, and non-common design data.

FIG. 1 shows an exemplary simplified diagram of a unique wafer 100 formed on a semiconductor wafer 24. The unique chip 100 includes a common part 101 and a unique or non-common part 102. The common portion 101 can be replicated in other wafers produced on the wafer 24 so that multiple wafers have the same common portion 101. The unique portion 102 may be different from all other wafers produced on the wafer 24. This is illustrated in the top of Figure 1, where wafer 24 is shown as containing 100 unique chips and 39 other unique chips, each unique chip having a different individualized area. The combination of the common part 101 and the unique part 102 can produce a complete circuit for the unique chip 100.

Certain specific structures (such as interconnection lines, conductive vias, terminals of transistors and diodes, active areas of transistors and diodes, etc.) can be selected and written for each chip on the wafer 24 The unique combination realizes the unique part 102, so that each chip on the wafer has a unique structure. A wafer is usually formed of multiple conductive layers, insulating layers, and semi-conductive material layers, and a variety of exposure operations can be used to form predefined structures in these layers.

Each chip on the wafer usually has conductive vias for making electrical connections between different conductive (metal) layers of the chip, as shown by the black dots in the middle part of FIG. 1. Each chip on the wafer 24 may have different combinations of vias formed by forming or not forming vias at possible via positions in the unique portion 102 of the chip, so as to create differences between the layers of each chip. The electrical interconnection group of the chip, so that each of the wafers has an electrically different circuit.

Each wafer on the wafer usually has one or more layers of semiconducting material with P-type dopants or N-type dopants added to form an active area of an active circuit element, such as those formed in Transistor or diode in the wafer. Each chip on the wafer 24 may have a different combination of active circuit elements formed by doping or non-doping each active circuit element in the unique portion 102 of the wafer or changing the doping, so that each of the wafers One has different electrical circuits.

Alternatively or in addition, other connections between the metal layers, connections between the metal layers and, for example, the gate in the contact layer, connections in the local interconnection layer, or other components of the circuit can be selectively formed on each wafer To realize the unique part 102 in the unique combination.

The common part 101 can be generated using lithography or charged particle multi-beam lithography. Typically, charged particle multi-beam lithography is used to create the unique portion 102. In addition, the pattern data used to control the beamlets in the charged particle lithography system can be designed to include a common chip design part for generating multiple chips on the wafer and a unique part for individualizing the area. For the reasons stated in the background art part, it is undesirable to generate the pattern data including the common chip design part and the unique chip design part at one time. Therefore, the lithography system has been used to enable the unique chip design portion to be inserted into the pattern data in the later stage of the pre-processing stage before exposure (that is, close to the actual patterning of the wafer). This will be explained in more detail in conjunction with FIGS. 4A to 4D and FIG. 5.

Figure 2 shows a simplified schematic diagram of an exemplary embodiment of a charged particle multi-beam lithography machine 1 that can be used to implement a maskless pattern writer. The lithography machine suitably includes a beamlet generator for generating a plurality of beamlets, a beamlet modulator for patterning the beamlets into modulated beamlets, and a beamlet modulator for projecting the beamlets on the surface of the target Beam projector on top. The target is, for example, a wafer. The beamlet generator usually includes a source and at least one orifice array. The beamlet modulator is usually a beamlet blanker with a blanking polarizer array and a beam stop array. A beamlet projector usually includes a scanning polarizer and a projection lens system.

In the embodiment illustrated in FIG. 2, the lithography machine 1 includes an electron source 3 for generating a homogeneous expanded electron beam 4. The beam energy is preferably kept relatively low, in the range of about 1 keV to 10 keV. To achieve this, the acceleration voltage is preferably lower, and the electron source is preferably kept between about -1kV to -10kV relative to the target at ground potential, but other settings can also be used.

The electron beam 4 from the electron source 3 may pass through a double octopole and then a collimating lens 5 for collimating the electron beam 4. As will be understood, the collimating lens 5 may be any type of collimating optical system. Subsequently, the electron beam 4 can impinge on a beam splitter, which in a suitable embodiment is an aperture array 6A. The aperture array 6A can block part of the beam and can allow a plurality of sub-beams 20 to pass through the aperture array. The array of apertures preferably includes a plate with perforations. Therefore, a plurality of parallel electron sub-beams 20 can be generated.

The second aperture array 6B can generate multiple beamlets 7 from each sub-beam. Small beams are also called electron beams. The system can generate a large number of beamlets 7, preferably about 10,000 to 1,000,000 beamlets, but it is of course possible to use more or fewer beamlets. It should be noted that other known methods can also be used to generate collimated beamlets. This allows the beamlet to be manipulated, which in turn benefits the operation of the system, especially when the number of beamlets is increased to 5000 or more. Such manipulation is performed in a plane such as a projection lens by, for example, a condenser lens, a collimator, or a lens structure that converges the sub-beams to the optical axis.

A condenser lens array 21 (or a group of condenser lens arrays) may be included after the sub-beam generation aperture array 6A, for focusing the sub-beams 20 toward the corresponding openings in the beam stop array 10. The second aperture array 6B can generate beamlets 7 from the sub-beams 20. The beamlet generating the aperture array 6B is preferably included in combination with the beamlet blanker array 9. For example, the two can be assembled together to form a sub-assembly. In FIG. 2, the aperture array 6B generates three small beams 7 from each sub-beam 20, which impact the beam stop array 10 at the corresponding openings so that the three small beams are separated by the projection lens system in the end module 22 The beam is projected onto the target. In practice, a larger number of beamlets can be generated by the aperture array 6B for each projection lens system in the end module 22. In one embodiment, 49 beamlets (configured in a 7×7 array) can be generated from each sub-beam and guided through a single projection lens system, although the number of beamlets per sub-beam can be increased to 200 or More.

The generation of the beamlet 7 from the intermediate stage of the beam 4 passing through the sub-beams 20 step by step has the advantage that the main optical operation can be performed by a relatively limited number of the sub-beams 20 and at a position relatively far away from the target. One such operation is to converge the sub-beams to a point corresponding to one of the projection lens systems. Preferably, the distance between the operation and the convergence point is greater than the distance between the convergence point and the target. Most suitably, an electrostatic projection lens combined with it is used. This convergence operation enables the system to meet the requirements of reducing spot size, increasing current, and reducing point spread, enabling reliable charged particle beam lithography to be performed at advanced nodes, especially at nodes with critical dimensions less than 90nm.

The beamlet 7 can then pass through the modulator array 9. This modulator array 9 may include a beamlet blanker array with a plurality of blankers, each of which can deflect one or more of the electronic beamlets 7. More specifically, the blanker can be an electrostatic polarizer having a first electrode and a second electrode, and the second electrode is a ground electrode or a common electrode. The beamlet blanker array 9 and the beam stop array 10 constitute a modulating element. Based on the beamlet control data, the modulation component 8 can add a pattern to the electronic beamlet 7. The pattern can be projected onto the target 24 by means of components present in the end module 22.

In this embodiment, the beam stop array 10 includes an array of apertures for allowing beamlets to pass through. The beam stop array in its basic form may comprise a substrate with perforations, which are usually circular holes, but other shapes may also be used. In one embodiment, the substrate of the beam stop array 8 is formed of a silicon wafer with a regularly spaced perforation array, and may be covered with a metal surface layer to prevent surface charging. In one embodiment, the metal may be a type that does not form a natural oxide surface layer, such as CrMo.

In one embodiment, the channels of the beam stop array 10 may be aligned with the holes in the beamlet blanker array 9. The beamlet blanker array 9 and the beamlet stop array 10 usually operate together to block the beamlet 7 or allow the beamlet 7 to pass. If the beamlet blanker array 9 deflects a beamlet, it will not pass through the corresponding aperture in the beamlet stop array 10 and instead will be blocked by the substrate of the beamlet blocking array 10. However, if the beamlet blanker array 9 does not deflect the beamlet, it will pass through the corresponding aperture in the beamlet stop array 10 and will then be a light spot projected on the target surface 13 of the target 24.

The lithography machine 1 may further include a data path for supplying beamlet control data, such as patterned bitmap data, to the beamlet blanker array 9. The beamlet control data can be transmitted using optical fiber. The modulated light beams from each fiber end can be projected onto the photosensitive elements on the small beam blanker array 9. Each light beam can hold a portion of the pattern data to control one or more modulators coupled to the photosensitive element.

Subsequently, the electronic beamlet 7 can enter the terminal module. In the following, the term "wavelet" refers to a modulated beamlet. The modulated beamlet effectively includes a temporally continuous part. Some of these continuous parts may have lower intensity and preferably zero intensity, that is, the part where the beam stops. Some sections may have zero intensity in order to allow the beamlet to be positioned to the starting position for subsequent scanning periods.

The end module 22 is preferably configured as an insertable and replaceable unit, which includes a plurality of components. In this embodiment, the end module may include a beam stop array 10, a scanning polarizer array 11, and a projection lens configuration 12, but not all of these need to be included in the end module and they may be configured differently.

After passing through the beamlet stop array 10, the modulated beamlet 7 can pass through the scanning polarizer array 11 that provides deflection of each beamlet 7 in the X direction and/or Y direction, the direction being substantially perpendicular to the The direction of the beamlet 7 is deflected. In this embodiment, the polarizer array 11 may be a scanning electrostatic polarizer that enables a relatively low driving voltage to be applied.

Then, the beamlet can pass through the projection lens configuration 12 and can be projected on the target surface 24 of the target (usually a wafer) in the target plane. For lithography applications, targets typically include wafers with a layer that is sensitive to charged particles or a layer of charged particle resist. The projection lens configuration 12 can focus small beams, for example, to generate a geometric spot size of about 10 nm to 30 nm in diameter. For example, the projection lens configuration 12 in this design provides a reduction of approximately 100 times to 500 times. In this preferred embodiment, the projection lens arrangement 12 is advantageously located close to the target surface.

In some embodiments, a beam protector may be located between the target surface 24 and the focusing projection lens configuration 12. The beam protector may be a foil or plate provided with necessary orifices for absorbing the resist released from the wafer before the resist particles can reach any of the sensitive elements in the lithography machine. particle. Alternatively or in addition, the scanning deflection array 9 may be provided between the projection lens arrangement 12 and the target surface 24.

Roughly speaking, the projection lens arrangement 12 focuses the beamlet 7 to the target surface 24. Therefore, it further ensures that the spot size of a single pixel is appropriate. The scanning polarizer 11 can deflect the beamlet 7 on the target surface 24. Therefore, it is necessary to ensure that the position of the pixel on the target surface 24 is appropriate on the micro-scale. In particular, the operation of the scanning polarizer 11 needs to ensure that the pixels fit well into the grid of pixels that ultimately form a pattern on the target surface 24. It should be understood that the large-scale positioning of pixels on the target surface can be suitably achieved by the existence of a wafer positioning system lower than the target 24.

This high-quality projection can be related to obtaining a lithography machine that provides reproducible results. Generally, the target surface 24 includes a resist film on top of the substrate. The part of the resist film can be chemically modified by applying a small beam of charged particles (ie, electrons). As a result of this, the irradiated portion of the film can be more or less soluble in the developer, resulting in a resist pattern on the wafer. The resist pattern on the wafer can then be transferred to the bottom layer by performing etching and/or deposition steps as known in semiconductor manufacturing technology. Obviously, if the irradiation is not uniform, the resist may not be developed in a uniform manner, causing errors in the pattern. In addition, many such lithography machines utilize multiple beamlets. The difference in irradiation should not be caused by the deflection step.

FIG. 3 shows a conceptual diagram of an exemplary charged particle lithography system 1A divided into three high-level subsystems: a wafer positioning system 25, an electron optical cylinder 20, and a data path 30. The wafer positioning system 25 moves the wafer 24 under the electron optical cylinder 20 in the x direction. The wafer position system 25 may be provided with a synchronization signal from the data path subsystem 30 to align the wafer with the electron beamlet generated by the electron optical cylinder 20. The electron optical cylinder 20 may include a charged particle multi-beam lithography machine 1 as shown in FIG. 2. The pattern bitmap data can also be used through the data path subsystem 30 to control the switching of the beamlet blanker array 9.

In FIGS. 4A to 4D, exemplary embodiments of the data path subsystem 30 are shown for the lithography systems 301A to 301D having the control and data interface forming the data path subsystem 30. The figure shows a hierarchical configuration with the following three interfaces: a cluster interface 303, a cluster component interface 305, and a micro shadow system interface 307. A number of micro-shadow systems 316 have been shown, each containing a charged particle multi-beam lithography machine 1 such as that shown in FIG. 2. It is possible that only one micro shadow system 316 exists.

The subsystem 316 includes, for example, a wafer load subsystem (WLS), a wafer positioning subsystem (WPS), and an illumination optics subsystem (illumination optics subsystem) for generating electronic beamlets. ILO), pattern streaming subsystem (PSS) used to stream beam switching data to lithography elements, and beam switching subsystem (BSS) used to switch electronic beamlet switches , Projection optics subsystem (POS), beam measurement subsystem (BMS) and metrology subsystem (MES) for projecting small beams onto the wafer.

Each subsystem 316 can operate independently and can include a memory for storing instructions and a computer processor for executing the instructions. The memory and the processor can be implemented as a plug-in client (PIC) 315 in each subsystem. Suitable implementations of the subsystem may include, for example, a personal computer running a Linux operating system. The subsystem may include a hard disk or non-volatile memory for storing its operating system so that each subsystem can be started from the disk or memory. These and other features discussed below enable a design in which each subsystem can be an independent unit that can be designed, constructed, and tested as an independent unit without considering the constraints imposed by other subsystems. For example, each subsystem can be designed to have enough memory and processing power to properly perform the functions of the subsystem during its operating cycle, without considering the memory and processing power requirements of other subsystems. When these requirements are in units of throughput, this is especially advantageous during system development and upgrades. With this design, the overall required memory and processing capacity can be increased, and backup of these components may need to be implemented in each subsystem. However, a simplified design can result in faster development and simpler upgrades.

The subsystem 316 can be designed to receive commands via the control network 420 and can execute the commands independently of other subsystems, report the result of the command execution when requested, and transmit any resulting execution data.

Subsystem 316 can be designed as an autonomous unit, but designed to be activated from, for example, a central disk or memory on a data network hub. This reduces the reliability problems and costs of individual hard disks or non-volatile memory in each subsystem, and allows easier subsystem software upgrades by updating the startup images of the subsystems in the central location.

The cluster interface 303 may include an interface for communication between the lithography cluster front end 306 and one or more main systems 302 and/or between the cluster front end 306 and one or more operator consoles 304.

The cluster component interface 305 may include an interface for communication between the cluster front end 306 and the lithography component network including the component control unit 312 and/or the data network hub 314. The component control unit 312 can communicate with the data network hub 314 via the link 406, wherein the communication is preferably a single direction from the component control unit 312 to the data network hub 314.

The micro shadow system interface 307 may include interfaces between the component control unit 312 and the micro shadow system 316 and between the data network hub 314 and the micro shadow system 316. The sub-system 316 can communicate with the component control unit 312 via the control network 420, and the sub-system 316 can communicate with the data network hub 314 via the data network 421.

The operator interface and the interface for higher-level host management and automated computers do not have individual lithography components except at the cluster front end 306.

Preferably, the data path 320 directly connects the pattern streamer 319 to the subsystem responsible for modulating or switching the charged particle beam. The pattern streamer 319 can stream the pattern data to the micro shadow system 316 to control the modulation and switching of the charged particle beam. The pattern data is usually streamed to the relevant subsystem in a bit-mapped format, because the amount of data is too large for the local storage at the subsystem.

The subsystem 316 can be connected to the component control unit 312 via a control network, which is also referred to as support subsystem control or SUSC. The component control unit 312 may include a memory and a computer processor for controlling the operation of the micro shadow system 316.

In the example of FIGS. 4A and 4B, the pattern data streamed from the pattern streamer 319 to the micro shadow system 316 may include data for the common chip design part and data for the unique chip design part. In FIG. 4A, a unique wafer design part can be added to the pattern data in the pattern data processing unit 318. In FIG. 4B, a unique wafer design part can be added to the pattern data in the pattern streamer 319.

In the examples in FIG. 4C and FIG. 4D, the pattern data streamed from the pattern streamer 319 to the micro shadow system 316 may include data for the common chip design part. In FIG. 4C, the unique chip design part can be added to the pattern data by the micro shadow system 316 under the control of the device control unit 312. In FIG. 4D, the unique chip design part can be added to the pattern data by the micro shadow system 316 under the control of the main system 302.

In FIGS. 4A to 4D, the pattern streamer 319 can be controlled by the component control unit 312 via the control network 420. In addition, the pattern streamer 319 may be part of the micro shadow system 316.

Fig. 5 shows an exemplary functional flow chart of an embodiment of displaying a data path using a solid line rasterization. In Figure 3, the functional flowchart is divided into four parts: 3010 is used to indicate the data format of the underlying data output/input; 3020 shows the data output/input (parallelogram) and functional elements (rectangle); 3030 is used Indicate the program steps performed at the overlying functional element; and 3040 is used to indicate the frequency of the processing steps usually performed, for example, 3041 per design, 3042 per wafer, or 3043 per area. Roman numerals I, II, and III indicate when the feature data collection and/or selection data can be provided to the data path.

The input to the process can be the GDS-II design layout document 2007 that defines the common chip design part, or the design layout in any other suitable format such as the OASIS document format. The pattern data processing system 318 can preprocess the 1022 GDS-II file once per design, as indicated by the arrow 3041 at the bottom.

Preferably, the pre-processing 1022 does not involve a unique wafer design part, so that the pattern data pre-processing system 318 can be located in a less secure environment. For safety reasons, it is also desirable to minimize the exposure time of the unique chip design. The security aspects of the chips that are commonly used in data security, traceability, and anti-counterfeiting applications are as important as uniqueness. The process in the dashed block, that is, from the software processing 1071A to the hardware processing 1073 is usually performed at the lithography machines 1 and 1A to achieve a safer operating environment. By inserting a unique chip design part at a later stage, the amount of time the code is used in the lithography system 301A to 301D can be reduced to a minimum.

The unique chip design part can be inserted into the pattern data at multiple stages indicated by the Roman numerals I, II, and III in the functional flow.

The unique chip design part can be inserted into the pattern data after processing the design layout data input (in this example, GDSII input, indicated by the Roman numeral I). At this stage, pattern data processing is usually carried out in a vector-based data format. Since this operation is usually performed at the pattern data processing unit 318 located in a less secure environment, the insertion of a unique chip design at stage I is the worst.

More preferably, the insertion of the unique chip design part into the pattern data can be performed in the software processing stage 1071A as indicated by the Roman numeral II, or in the streaming stage 1071B as indicated by the Roman numeral III. The S/W processing stage 1071A is usually performed once per wafer, as indicated by the second arrow 3042 at the bottom. The streaming stage 1071B is usually performed once per area or once per wafer, as indicated by the third arrow 3043.

The S/W processing stage 1071A and the streaming stage 1071B can be implemented at the pattern streamer 319. The hardware processing stage 1073 on the right side of the functional flow usually involves a blanker controlled by the pattern data 2009 including the common chip design part and the unique chip design part.

The GDS-II format pattern data can be processed 1022 offline, usually including proximity effect correction, resist heating correction, and/or smart boundary (collectively depicted as 3031). The generated corrected vector pattern data 2008 may be in a vector format and may include usage information, depicted as 3011. This offline process 1022 is usually performed once for a given pattern design for one or more batches of wafers. In the case of inserting a unique chip design part at this stage indicated by the Roman numeral I, offline processing 1022 may need to be performed more frequently, at most once per wafer or even once per region or wafer.

Then, online processing of the vector tool input data 2008 can be performed to rasterize the vector data 2008 to generate pattern system streamer (PSS) bitmap data 3021 in, for example, a 4-bit grayscale bitmap format 3012.

This processing is usually carried out in software. The unique chip design part can be added at this stage as indicated by the Roman numeral II. The pattern streamer 319 can then process the PSS format data 3021 to generate blanker format data 2009, which may include corrections involving full or partial pixel shifts in the X direction and/or Y direction for performing bit alignment as before The beam position calibration, area size adjustment, and/or area position adjustment performed by the image data are collectively depicted as 3032. As an alternative to entry point II, a unique design part can be added at this stage as indicated by the Roman numeral III. This process can be performed for each area. The blanker format pattern data 2009 can then be transmitted 3022 to the lithography system for exposing the wafer.

As indicated in FIG. 5, rasterization may be performed in the streaming stage 1071B, which usually involves real-time processing in hardware. The beam position calibration, area size adjustment, and/or area position adjustment 3032 can be performed on the vector format PSS format data 3021, and then the rasterization can convert this to the blanker format 2009. When correcting vector data, both full pixel shift and sub-pixel shift in the X direction and the Y direction can be performed.

The pre-processing 1022 of GDSII input 2007 is preferably performed so that the unique chip design part can be inserted in the later stage. Here, the bit space can be retained in the intermediate pattern data or the position holder can be added to the intermediate vector format data that the unique chip design data will be inserted later. Advantageously, in addition to the security advantages mentioned, this avoids the need to regenerate a large amount of pattern data before each wafer is exposed to each unique chip, which would require extremely high CPU power and extremely large amounts of memory.

In FIGS. 4A to 4D, the communication 402 between the cluster front end 306 and the SUSC 312 can be designed to transmit the processing program (PP) to the SUSC 312. For this purpose, a contract based on JavaScript Object Notation (JSON) can be used. The protocol preferably provides instructions for creating a processing procedure (PJ), sending the PP file and any related parameters to instruct the SUSC 312 to create a PJ based on the PP. Other commands can include Abort and Cancel commands.

The communication from the SUSC 312 to the cluster front end 306 may include response messages, progress reports, and error and alarm messages.

Preferably, only the component control unit protocol is used to strictly control the communication 401 between the SUSC 312 and the micro shadow system 316 across the control network 420 to ensure quasi real-time performance in the network. The communication 405 between the SUSD 314 and the cluster front end 306 can be designed to retrieve PJ results, job tracking, and login data from the SUSD 314. For this communication link, Hyper-Text Transfer Protocol (HTTP) can be used.

The communication 403 between the micro shadow system 316 and the SUSD 314 can be designed to collect data from the subsystem 316 in one direction. Various protocols such as syslog, HDF5, UDP, and other protocols can be used to convey data.

The User Datagram Protocol (UDP) can be used to send large-capacity data to send data without the need for large overhead signal exchange, error checking and correction. Due to the extremely low transmission overhead, the data can be regarded as being received in real time.

The hierarchical data format HDF5 can be used to transmit and store high-frequency data. HDF5 is well suited for storing and organizing large amounts of numerical data, but it is usually not used in UDP environments. Other data formats such as CSV or TCP can also be used, especially for low-level (low-volume) data.

The PP can be used to control the operation of the micro shadow system 316, which can include a sequence of actions to be performed. The component control unit 312 can be loaded with PP, and can schedule and execute the PP as requested by the main system 302 or the operator via the operator console 304.

Processing programs (PP) and processing procedures (PJ) can be based on SEMI standards, such as SEMI E30: "Generic Model for Communications and Control of Manufacturing Equipment (GEM)", SEMI E40: "Standard for Processing Management", SEMI E42: "Recipe Management Standard: Concepts, Behavior, and Message Services (Recipe Management Standard: Concepts, Behavior, and Message Services)" and/or SEMI E139: "Formulation and Parameter management (Specification for Recipe and Parameter Management; RaP) specification". PP can play a role in the formulation, for example, as defined in the SEMI E40 standard. Although the SEMI standard specifies many requirements on how to handle process recipes, the standards may contradictory, so that recipes are better avoided. Alternatively, an editable and unformatted PP can be used in the form of a so-called Binary Large Object (BLOB).

The PP can be a pre-planned and reusable part of an individual's commands, settings, and parameter sets that change between operations or processing cycles. PP can be designed by the lithography tool designer or produced by tool processing.

The PP can be uploaded to the micro-imaging system by the user. PP can be used to create PJ. The PJ may specify the processing to be applied to wafers or wafer sets by the micro shadow system 316. PJ can define which PP is used when processing a specified wafer set and can include parameters from the PP (and optionally from the user). PI can be a system activity initiated by the user or the host system.

PP can be used not only to control wafer processing, but also to service actions, calibration functions, lithography component testing, modify component settings, update and/or upgrade software. Preferably, no sub-system behavior occurs except for the specified in PP, except for some other allowed types, such as automatic initialization during power-on modules or sub-systems, periodic and unconditional behavior of sub-systems, As long as they do not affect the execution of PJ, and the response to unexpected power outages, emergencies or EMO activation.

PP can be divided into several steps. Most steps include commands and identify the subsystem that should execute the commands. Steps can also include parameters to be used to execute the command, and parameter constraints. PP can also include scheduling parameters to indicate when the steps should be executed, such as simultaneously, sequentially, or simultaneously.

To execute the command step of PJ, the component control unit 312 may send the command indicated in PJ to the subsystem indicated in the relevant step of PJ. The component control unit 312 can monitor the timing and can receive the result from the subsystem.

In the example of FIG. 4A, the pattern data processing system 318 may be configured to receive the unique chip design data 430 from the unique data generator 330 and insert the unique chip design data into the pattern data.

In the example of FIG. 4B, the pattern streamer 319 may be configured to receive the unique chip design data 430 from the unique data generator 330 and insert the unique chip design data into the pattern data.

In the example of FIG. 4C, the device control unit 312 may be configured to receive the unique chip design data 430 from the unique data generator 330 and control the insertion of the unique chip design data into the pattern data. The unique chip design data can be transmitted to the micro shadow system 316 through processing steps.

In the example of FIG. 4D, the main system 302 may be configured to receive the unique chip design data 430 from the unique data generator 330 and control the insertion of the unique chip design data into the pattern data. The unique chip design data can be transmitted to the micro shadow system 316 through processing steps.

Generally, the unique chip design data 430 may be in a format that can be directly inserted into the pattern data. Alternatively, the unique chip design data 430 includes information that enables the generation of data to be inserted into the pattern data.

The unique chip design data 430 may be generated by the unique data generator 330 based on the secret data 440 received from the external provider 340. Alternatively, the secret data may be generated in the unique data generator 330. The secret data 440 can be encrypted and decrypted by the unique data generator 330. The secret material 440 may include a secret key and/or a secret ID.

The unique data generator 330 can be implemented as a black box component. The unique chip design data 430 can be generated by black box components. The black box element can be a source external to the maskless lithography exposure system and is preferably located in the manufacturing section of the manufacturing facility. The black box may be owned by a third party such as the owner of the IP block or the owner of the manufactured chip or the owner of the key management infrastructure. Advantageously, the black box can be positioned in the manufacturing facility close to the operation of the lithography machine, thereby minimizing the public exposure of that unique wafer design information. This is in contrast to known wafer manufacturing solutions, where the black box used to individualize the wafers is usually located outside the manufacturing facility and used to individualize the wafers after they are produced.

The black box component may include an ID/key manager and a unique data generator 330 that cooperate when generating the unique chip design data 430. The ID/key manager can receive product ID/serial number information from the manufacturing database and receive batches of ID/key pairs from a key management service that may be located outside the maskless lithography exposure system. Product ID/serial number information and batch ID/key pairs can be used to control the generation of unique chip design data 430. In addition, the product ID/serial number information can be used to track the chip through the production process so that the chip can match its ID/serial number after production. Alternatively or in addition, the product ID/serial number information can be used to include the ID/serial number in or on the chip by a process that is not shown but is known per se.

Figure 6 shows the process of producing a unique wafer according to an exemplary embodiment of the present invention. In this embodiment, the same part of the lithography (with mask) can be used to generate the same part of the chip and the charged particle multi-beam lithography (without mask) can be used to generate the unique part of the chip. Mask-based lithography is a conventional method for manufacturing wafers, and conventional lithography equipment has been used in typical facilities to achieve low cost and high yield. However, it is impractical to use mask-based lithography to manufacture unique wafers because it would require a large number of (expensive) masks each with a different pattern. Maskless lithography using, for example, a charged particle multi-beam lithography system is a newly developed technology that has not been widely commercialized and still cannot achieve the same high throughput as a mask-based system.

A combination of mask-based lithography and maskless lithography is used to realize a unique wafer with low cost and high yield. Various methods can be used to combine mask-based lithography with unmasked lithography to produce unique wafers. Some examples are discussed with reference to Figures 6 to 8 below. These examples illustrate the process used to create unique patterns of conductive vias that interconnect the two conductive layers of a wafer. However, the part where the wafer is individualized to produce a unique wafer may be a layer other than the via layer. For example, the semiconductor layer can be individualized by generating a unique arrangement of transistors and diodes in each wafer by changing the doping of the active area of the transistors or diodes. This change in doping is extremely difficult to detect, even when the wafer is scraped off and the layers are analyzed, because the change in the amount of dopant in the semiconductor layer is difficult to detect, making it extremely difficult to reverse engineer the wafer. In other examples, the contact layer can be individualized by forming a unique connection arrangement between the metal layer and the gate, or the metal layer can be individualized by forming a unique connection arrangement between circuit elements, or These examples can be used in the combination of other components of the circuit, and other components of the circuit can be selectively formed in the unique combination of each chip to realize a unique chip.

At the beginning of the process of FIG. 6, the wafer may include a bottom metal layer 201 that has been previously patterned to form a conductive connection line and an insulating layer on top with a resist 205 (such as KrF resist) 202 (e.g. SiO ₂ ), as shown in Figure 6A.

To produce the same part (such as the common part 101), the resist 205 can be exposed to a mask based on a KrF laser, for example, followed by a development step in which the pattern defined by the mask is removed from the resist layer 205, such as Shown in Figure 6B. In the etching and stripping steps, these patterns can be etched into the insulating layer 202 and then the resist is removed, as shown in FIG. 6C.

Next, the conductive layer 207 is coated on the etched and peeled insulating layer, as shown in FIG. 6D. For example, chemical vapor deposition by tungsten (CVD-W) can be used, as shown in FIG. 6D. Chemical mechanical planarization (CMP) can be used to remove excess conductive material, resulting in a wafer with a bottom metal layer 201 and a layer 202 including insulating material, the layer 202 having conductive material present in locations where conductive vias are needed , As defined by the mask exposure shown in Figure 6E.

Then, to create the unique portion 102, the wafer may receive one or more etching barrier films to etch the insulating layer 202. For example, a spin-coated carbon (SOC) film 203 with an electron beam resist 206 and a silicon-containing anti-reflective coating (SiARC) hard mask 204 are formed on the top to cover the etched part from the lithography stage The insulating layer 202 is as shown in FIG. 6F. The resist 206 may be subjected to maskless electron beam exposure, followed by a development step, in which the pattern exposed by the electron beam is removed from the resist 206, as shown in FIG. 6G. In the etching and stripping steps, these patterns can be etched into the etching barrier films 203 and 204, and the resist can be removed, as shown in FIG. 6H. Next, the patterns generated in the etching barrier films 203, 204 can be etched into the insulating layer 202, and the films 203, 204 can be peeled off, as shown in FIG. 6I.

Next, the conductive layer 207 is coated on the etched and peeled insulating layer 202, as shown in FIG. 6J. For example, chemical vapor deposition by tungsten (CVD-W) can be used. Chemical mechanical planarization (CMP) can remove excess conductive material, as shown in FIG. 6K, resulting in a wafer with a bottom metal layer 201 and a layer 202 including insulating material, which has conductive vias present in The conductive material in the position of is as defined by the mask exposure and the non-mask exposure, as shown in FIG. 6K. The positions of the conductive vias defined by the mask exposure will be the same for each wafer in the set of wafers made using the same mask. However, the position of the conductive vias defined by the unmasked exposure will be different for each wafer in the set of wafers, so that each of the wafers in the set has a unique set of through holes.

After the process of FIG. 6, the upper metal layer can be deposited on the insulating layer 202 and patterned to produce a second set of conductive connection lines, so that the through holes formed in the insulating layer 202 serve as the bottom metal layer 201 and the upper metal layer 201. Electrical connections between layers. Since each wafer in the wafer set has a unique through hole arrangement, each wafer can be designed to have a unique circuit.

In the embodiment of Figure 6, two CMP steps may be required. The depression and secondary erosion generated by the CMP step can affect the thickness of the insulating layer of the conductive material including the through hole. This can have a negative impact on the analog and RF performance of the chip. Figure 7 shows an improved process for producing unique wafers in which only a single CMP step is required.

FIG. 7 shows the manufacturing process of a unique wafer according to another exemplary embodiment of the present invention. In this embodiment, mask-based lithography can be used to generate the same part of the chip (for example, the common part 101) and a maskless charged particle multi-beam lithography can be used to generate the individualized part of the chip (for example, the unique part 102). .

At the beginning of the process of FIG. 7, the wafer may include a bottom metal layer 201 that has previously been patterned to form conductive connection lines, and etching barrier films 203 and 204 (such as SOC+SiARC HM) and resist 205 (such as KrF). The insulating layer 202 (e.g., SiO ₂ ) under the resist) is as shown in FIG. 7A. Advantageously, the etched barrier films 203 and 204 can be used for both the mask-based lithography stage and the non-masked charged particle multi-beam lithography stage, thereby eliminating the need for the CMP step in the lithography stage, as will be described later Further explanation.

For producing the same part, the resist 205 can be mask-exposed using a KrF laser, for example, followed by a development step in which the structure defined by the mask is removed from the resist 205, as shown in FIG. 7B. In the etching and stripping steps, these structures can be etched into the SOC 204 and the resist removed, as shown in FIG. 7C.

Next, to create a unique portion, the wafer receives an electron beam resist 206 covering the etching barrier films 203 and 204 including the portions etched from the lithography stage, as shown in FIG. 7D. The resist 206 may be exposed to electron beams, followed by a development step, in which the pattern defined by the electron beams may be removed from the resist layer 206, as shown in FIG. 7E. In the etching and stripping steps, these patterns can be etched into the etching barrier films 203 and 204, and the resist 206 can be removed, as shown in FIG. 7F. Then the patterns produced in the etching barrier films 203, 204 in both the mask-based lithography stage and the mask-free charged particle multi-beam lithography stage can be etched into the insulating layer 202, and the films 203, 204 peels off, as shown in Figure 7G.

Then, the conductive layer 207 can be applied to the etched and peeled insulating layer 202 for both the same part and the unique part of the wafer, as shown in FIG. 7H. For example, chemical vapor deposition by tungsten (CVD-W) can be used. Chemical mechanical planarization (CMP) can remove excess conductive material, resulting in a wafer with a bottom metal layer 201 and a layer 202 including insulating material in positions defined by mask exposure and non-mask exposure With conductive material, as shown in Figure 7I.

As described with reference to FIG. 6, the upper metal layer can be deposited on the insulating layer 202 and patterned to produce a second set of conductive connection lines, so that the vias formed in the insulating layer 202 serve as the bottom metal layer and the upper metal layer Electrical connection between. Since each wafer in the wafer set has a unique through hole arrangement, each wafer can be produced with a unique circuit.

Figure 8 shows a process for producing a unique wafer according to another exemplary embodiment of the present invention. In this embodiment, unmasked charged particle multi-beam lithography can be used to generate all or part of the same part of the wafer (the common part 101) and the unique part 102 of the wafer.

At the beginning of the process of FIG. 8, the wafer may include a bottom metal layer 201 that has previously been patterned to form conductive connection lines, and etching barrier films 203 and 204 (such as SOC+SiARC HM) and an electron beam resist 206 ( The insulating layer 202 (e.g., SiO ₂ ) under the KrF resist, for example, is as shown in FIG. 8A.

The resist 206 may be exposed to electron beams, followed by a development step, in which the pattern defined by the electron beams may be removed from the resist layer 206, as shown in FIG. 8B. In the etching and stripping steps, these patterns can be etched into the etching barrier films 203 and 204, and the resist 206 can be removed, as shown in FIG. 8C. The pattern can then be etched into the insulating layer 202, and the etching barrier films 203, 204 can be stripped off, as shown in FIG. 8D.

Then, a conductive layer 207 can be applied to the etched and peeled insulating layer 202 for both the same portion and the unique portion of the wafer, as shown in FIG. 8E. For example, chemical vapor deposition by tungsten (CVD-W) can be used. Chemical mechanical planarization (CMP) can remove excess conductive material, resulting in a wafer with a bottom metal layer 201 and a layer 202 including insulating material, the layer having conductive material in the position defined by the electron beam, as shown in FIG. Shown in 8F.

An advantageous method for combining mask-based lithography and maskless lithography to produce unique wafers is to arrange individualized parts of the wafer on a single layer of the wafer, such as a single via layer, contact layer, etc. On the metal layer or semiconductor layer. You can then use maskless lithography/electron beam lithography to expose the entire layer containing individualized structures (such as vias, contacts, connecting lines, transistors, etc.), while using conventional mask-based lithography to expose all Other layers.

This description is shown in the embodiment shown in FIG. 9, showing the various layers of a unique wafer. In this example, the wafer can be considered to have a common portion 101 and a unique portion 102 in different areas of the wafer. These parts 101 and 102 are formed by multiple layers, and the structures formed in the common parts 101 and 102 (such as interconnection lines, vias, terminals of transistors and diodes, and active regions of transistors and diodes) Etc.) can form circuits such as logic circuits and data storage (memory) circuits or data storage structures. The structure formed in the common portion 101 is the same common structure as each wafer in the wafer set. The common structure of the common portion 101 is indicated in FIG. 9 as 201a, 202a, 208a, 209a, 201c, 202c, 208c, and 209c. The structure formed in the unique (non-common portion 102) may be the same common structure (indicated as 201b, 208b, and 209b in FIG. 9) for each wafer in the wafer set and a non-common structure unique to each wafer ( In Figure 9 it is indicated as a mixture of 202b).

In this example, mask-based lithographic exposure layers 201, 208, and 209 are used and are designed to be the same for each wafer in the set, that is, these layers include the same common for all wafers in the set. Structure (201a to 201c, 208a to 208c, and 209a to 209c). Therefore, the circuit formed by this common structure is the same in every chip.

The maskless lithography exposure layer 202 is used and the layer is different for each wafer in the wafer collection. It should be noted that the portion of the layer 202 in the common portion 101 contains the same common structure (202a and 202c) for each wafer, and the portion of the layer 202 in the unique portion 102 contains a non-common structure (202b) unique to each wafer. In this way, a unique circuit (also referred to as a non-common circuit) of each chip can be generated in the unique portion 102. For example, the wafers may have the same transistors, diodes, and connection lines for each wafer, but with a unique arrangement of conductive vias in the layer 202, which form a unique circuit in the unique portion 102 of each wafer.

It should be noted that the individualized portions of the wafer can also be formed on two or more layers of the wafer, using maskless lithography to expose the layers, and mask-based lithography to expose the remaining layers.

The layer of the wafer containing the individualized structure such as the non-common structure 202b in FIG. 9 preferably has one or more other layers formed above the individualized layer, and may have one or more formed below the individualized layer Other layers. This makes it more difficult to determine the structure of the individualized portion of the wafer by non-destructive inspection, especially when there are several layers above the individualized layer and/or the overlying layer contains structures or materials that are difficult to penetrate during inspection. This also applies when the individualized structure is formed on more than one layer, so that at least one of the individualized layers preferably has one or more overlying layers and may have one or more other layers underneath.

The embodiments of FIGS. 6 to 8 are described above using an example of an individualized portion of a wafer that includes a unique arrangement of conductive vias formed using maskless lithography. The structure of the unique chip can be further improved by merging adjacent conductive vias produced by the maskless lithography process to effectively form a larger single via, as shown in the examples shown in FIGS. 12A to 12D Portray. 12A shows a side view of a plurality of circular through holes 217a, 217b formed using a conventional mask-based lithography process to form an electrical connection between two metal layers 211a, 211b, and FIG. 12B shows a top view. Due to the limitations of the optical system used in the conventional lithography, it is difficult to combine these through holes into a single larger oblong shape in practice. Using the unmasked charged particle lithography system, there are no such constraints and the connecting metal layers 211a, 211b can be generated by exposing the two through holes 217c, 217d close to each other so that they are merged to form a double through hole. The larger oblong single through hole 217e is as shown in Fig. 12C and Fig. 12D showing the side view and the top view, respectively. This double via makes it possible to produce a more reliable connection between the two metal layers, which can conduct more current, and is further improved in the unique chip.

In the embodiment of FIGS. 6 and 7, a unique part of a wafer or layer containing individualized components/structures can be generated based on pattern data including a common chip design part and a unique chip design part, as discussed in conjunction with FIGS. 4A to 5 . The size of the common wafer design part may depend on the size of the same part of the wafer produced using lithography. When lithography is used to expose a larger part of the same part, the common chip design part in the pattern data can be smaller. If the unique part of the chip only has unique characteristics or mainly has unique characteristics, it is possible that the pattern data only includes the unique chip design part.

In the embodiment of FIG. 8, the pattern data may include a common wafer design part used to generate the same part of the wafer and a unique wafer design part used to generate a unique part of the wafer, as discussed in conjunction with FIGS. 4A to 5. In the embodiment of FIG. 9, the pattern data may include a common chip design portion used to generate the same portion of the individualized layer and a unique chip design portion used to generate the unique portion of the individualized layer, as described in conjunction with FIGS. 4A to 5 Discourse.

A maskless lithography exposure system can be used to embed a predetermined value such as a serial number or any other kind of identification code in the wafer so that it can be read electronically, optically or magnetically from the wafer by an automated means. In the following examples, the serial number is used as a non-limiting example of the predetermined value.

Figure 10 shows an embodiment of a unique wafer, including a unique wafer having multiple layers and including a common portion 101 and a unique portion 102, which can be formed using any of the methods described above. In this example, the unique portion includes a first portion 102a and a second portion 102b on the layer 102, wherein the first portion 102a stores a predetermined value uniquely associated with the second portion 102b.

In one embodiment, the first part 102a forms a mask ROM storing a serial number and the second part forms a circuit that generates a predetermined output value when a predetermined input value is provided, wherein when the same input value is provided, the output value is relative to the chip Each wafer in the set is different, or each of the wafers in the set produces a unique combination of output value versus input value. The serial number stored in the first part 102a is uniquely associated with the circuit formed by the second part 102b. The serial number can be read from the output of the chip, so that the unique chip can be identified by reading the serial number. The input value can be provided to the circuit of the chip and the resulting output value generated by the circuit can be read from the chip. The serial number and output value read from the chip can then be evaluated to safely determine the identification of the information about the chip.

The electronically readable serial number can be read wirelessly from the chip, for example, via one or more ports or pins of the electronic circuit connected to the chip or, for example, using an NFC or Bluetooth interface connected to the electronic circuit of the chip. The optically readable serial number can be written on the metal layer of the wafer. The shape of the metal layer can be used to encode the serial number, for example, in the form of a small barcode or QR code or a collection of optically recognizable metal lines, vias, or circuits. Figure 11 shows a top view of the layers of an exemplary semiconductor wafer 100 having a shape storing a serial number in a unique portion 102c, in this example, in the form of an optically readable QR code. The portion 102c having the QR code may form a portion of the first portion 102a as shown in FIG. 10, or a portion of a circuit formed by the second portion 102b as shown in FIG. This readable serial number can be read using an optical reader that scans the surface of the wafer, making it possible to pass through one or more of the upper layers of the wafer to access the serial number on the embedded wafer layer. A wafer-permeable reader such as an electron microscope or X-ray machine can be used to read the optically readable serial number written on a wafer layer covered by one or more other wafer layers.

Multiple serial numbers or identification codes can be embedded in the chip. Multiple serial numbers may be written on the same wafer layer of the same metal layer, or formed on different wafer layers, for example. It is possible that one or more serial numbers can be read electronically from the wafer, and one or more other serial numbers can be read optically from the wafer. The multiple serial numbers may be different serial numbers, copies of the same serial number in the same format, or copies of the same serial number in different formats. Non-limiting examples of formats are: size; way of expressing serial numbers; encrypted and unencrypted forms of the same serial number.

The serial number can be used to generate a unique chip and a unique correlation with the software code. The software code can only be accessed or used by the correct or verifiable serial number in the unique chip. Preferably, the software code is embedded in the chip, for example, in a ROM generated by the same maskless lithography system used to embed the serial number. The software code can be on the outside of the chip.

The serial number can be used in the authorization process associated with the query response circuit embedded in the chip, which is preferably generated using the same maskless lithography system as used to embed the serial number. The serial number can be read from the chip and used, for example, to obtain query and response pairs from a database. This response is the expected response to the inquiry and should be stored securely. When a maskless lithography exposure system is used to manufacture a chip, this query and response pair can be predefined and associated with a serial number. Sending the query to the chip can trigger the query response circuit to output a response, which can be compared with the expected response. In the case of matching responses, the chip or the components or software using the chip can be authorized or certified. In addition, any known remedies against man-in-the-middle attacks when communicating serial numbers, queries to the chip, and responses from the chip can be applied.

The predetermined value may be a public key or a private key used in a public-private key encryption scheme. Both the public key and the private key can be stored in the chip for use in a public-private key encryption scheme. Embedded cryptography or other mathematical functions embedded in the chip can be used to derive public and/or secret keys from one or more embedded predetermined values. Preferably, the same maskless lithography system used to generate the predetermined value has been used to generate the embedded function. The secret key can be embedded in a decryption circuit that has been generated using the same maskless lithography system used to generate the predetermined value.

The serial number can be used to implement the functionality or software part embedded in the chip. The same maskless lithography system used to generate the serial number can be used to generate embedded functionality or software. The embedded functionality or different parts of the software can function depending on the serial number. There may be a unique relationship between the serial number and the part to be activated. Alternatively, a series of serial numbers may be associated with the part to be activated. The serial number can be used in combination with the uniquely encrypted vector to implement the functionality of the chip depending on the uniquely encrypted vector. For example, a passport chip can be generated in which software for multiple countries is embedded, and software for only one country will be activated depending on the serial number. Therefore, it is possible to generate a chip with MROM containing software for multiple countries, where the serial number is used to activate the relevant software part for a specific country.

A chip with an embedded serial number can be used in conjunction with computer memory, where the serial number is used to encrypt the computer memory. Memory without a chip may not be decryptable and therefore inaccessible. Exchanging a chip with another chip can make the memory indecipherable and therefore inaccessible.

The chip can be used as a ROM mask for data personalization. Therefore, personalized and possibly unique data can be written onto the chip without the need for expensive non-volatile memory.

24‧‧‧wafer

100‧‧‧Unique chip

101‧‧‧Common part

102‧‧‧Unique part

Claims (15)

An electronic device including a semiconductor wafer, which includes a plurality of structures formed in the semiconductor wafer: wherein the semiconductor wafer may be a member of a semiconductor wafer set, wherein the semiconductor wafer set includes a plurality of semiconductor wafers. A subset, and the semiconductor wafer is only a member of one of the subsets; wherein the multiple structures of the semiconductor wafer include a common structure set that is the same as all the semiconductor wafers of the semiconductor wafer set, and A set of non-common structures (non-common structures), wherein the non-common structure of the semiconductor wafer of the subset is different from the non-common structure of the semiconductor wafer of each other subset; wherein at least a first part of the non-common structure is used To store or generate a first predetermined value; wherein the first predetermined value can be read from the outside of the semiconductor chip by an automatic reading component; and wherein the non-common structure is functionally independent from the common structure. According to the electronic device described in claim 1, wherein the non-common structure is formed in a region of the semiconductor wafer that is different from the common structure. The electronic device according to any one of items 1 to 2 of the scope of patent application, wherein the first predetermined value can be read from the outside of the semiconductor chip by at least one of the following: automatic electromagnetic reading means; Optical reading component; electronic reading component. For the electronic device described in any one of items 1 to 2 of the scope of patent application, wherein the first predetermined value can be read from the structure of the first part of the non-common structure and/or the non-common structure The shape of the first part of the common structure stores the first predetermined value. For the electronic device described in any one of items 1 to 2, wherein a first non-common circuit is composed of the first portion of the non-common structure of the semiconductor chip and one of the common structure of the semiconductor chip The first part is formed, and the circuit configuration of the first non-common circuit of the semiconductor chip in each subset is different from a circuit configuration of any semiconductor chip in each of the other subsets. For the electronic device described in any one of items 1 to 2, wherein the first non-common circuit includes at least one of the following: a read-only memory circuit, which is manufactured with pre-stored in the only Read the first predetermined value in the memory circuit; a logic circuit, wherein the logic circuit is used to generate the first predetermined value. For example, the electronic device according to any one of items 1 to 2 of the scope of patent application, wherein the electronic device includes at least one input terminal and at least one output terminal, and the first uncommon circuit is connected to the input terminal and the Output terminal, and wherein the first predetermined value can be read electronically from the output terminal. The electronic device according to any one of items 1 to 2 of the scope of the patent application, wherein the electronic device includes at least one input terminal for receiving a challenge and at least one output terminal for outputting a response, and The first non-common circuit forms an inquiry response circuit connected to the at least one input terminal and the at least one output terminal, wherein the inquiry response circuit is configured to apply to the at least one input at the at least one output terminal The terminal’s query generates a response, and the query and the response have a predetermined relationship. The electronic device according to any one of items 1 to 2 of the scope of the patent application, wherein the plurality of structures are formed on three or more layers of the semiconductor wafer, including one or more non-common structures. A plurality of non-common layers, and at least one common layer is above the one or more non-common layers, and the at least one common layer contains a common structure but no non-common structure. The electronic device according to any one of items 1 to 2 of the scope of patent application, wherein the plurality of structures are formed in a plurality of layers of the semiconductor wafer, and the non-common structure includes at least one of the following: the The connection between the metal layers of the plurality of layers; the connection between the metal layer and the gate in the contact layer of the plurality of layers; the connection in the local interconnection layer of the plurality of layers; and the connection in the plurality of layers One of the P-doped or N-doped diffusion regions of the transistor or the diode. A system for authentication (authentication) between multiple remote terminals and a main system based on a challenge-response procedure, wherein each of the remote terminals includes the first The electronic device of any one of item to item 10. A remote terminal for use in the system according to the 11th patent application. A method for verification in a system according to item 11 of the scope of patent application, the method comprising distributing the remote terminal to a plurality of users, sending an inquiry from the main system to one of the remote terminals, A response is received from the remote terminal, and the remote terminal is verified if the response has a predetermined relationship with the query. A method for manufacturing an electronic device as claimed in any one of items 1 to 10 of the scope of the patent application, which comprises using a maskless lithography exposure system to form at least a part of the non-common structure . The method of manufacturing an electronic device as described in item 14 of the scope of patent application, wherein from the electronic device The first predetermined value defined by the non-common structure is read to track the electronic device during the manufacturing process.

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