TWI738489B - Memory device - Google Patents

Abstract

A memory device is provided. The memory device includes a stacked structure, a tubular element, a conductive pillar and memory cells. The tubular element includes a dummy channel layer and penetrates the stacked structure. The conductive pillar is enclosed by the tubular element and extending beyond a bottom surface of the dummy channel layer. The memory cells are in the stacked structure and electrically connected to the conductive pillar.

Description

Memory device

The present invention relates to memory devices, and more particularly to memory devices having conductive posts surrounded by tubular elements.

Since planar memory devices, such as 2-dimensional memory devices, have reached the limit of capacity expansion and are difficult to meet market demand, the development of memory devices has shifted to 3-dimensional (3D) memory devices. However, the development of three-dimensional memory devices has brought many challenges, such as high cost, difficult integration process, structural stability of memory devices, electrical performance of memory devices, and complicated device design. In order to solve these problems, the development of new three-dimensional memory devices has become more and more important.

Therefore, there is a need to provide a memory device with an improved layout.

The present invention relates to a memory device.

According to an embodiment, a memory device is provided. The memory device includes a stacked structure, a tubular element, a conductive pillar, and a plurality of memory cells. The tubular element includes a dummy channel layer, and the tubular element penetrates the stacked structure. The conductive pillar is surrounded by the tubular element, and the conductive pillar extends beyond the bottom surface of the dummy channel layer. A plurality of memory cells are in a stacked structure and are electrically connected to the conductive pillars.

In order to have a better understanding of the above-mentioned and other aspects of the present invention, the following specific embodiments are described in detail in conjunction with the accompanying drawings.

The following are related embodiments, in conjunction with the drawings, to describe in detail the memory device and its manufacturing method proposed in this disclosure. However, this disclosure is not limited to this. The descriptions in the embodiments, such as the detailed structure, the steps of the manufacturing method, and the material application, are for illustrative purposes only, and the scope of the disclosure to be protected is not limited to the described aspects.

At the same time, it should be noted that this disclosure does not show all possible embodiments. Those in the relevant technical field can change and modify the structure and manufacturing method of the embodiments without departing from the spirit and scope of the present disclosure to meet the needs of practical applications. Therefore, other implementation aspects not mentioned in this disclosure may also be applicable. Furthermore, the drawings are simplified to clearly illustrate the content of the embodiments, and the size ratios in the drawings are not drawn in proportion to the actual product. Therefore, the description and the drawings are only used to describe the embodiments, rather than to limit the protection scope of the disclosure. The same or similar component symbols are used to represent the same or similar originals.

FIG. 1 is a schematic perspective view of a memory device 10 according to an embodiment of the present invention. The memory device 10 may include a three-dimensional non-volatile memory, such as NOR flash memory, NAND flash memory, or other types of memory. The memory device 10 may include a stack structure S. The stacked structure S may include a main stacked structure 100, a stepped structure 101 and an insulating stacked structure 102. The main stack structure 100, the stepped structure 101, and the insulating stack structure 102 may be arranged adjacent to each other. The main stacked structure 100, the stepped structure 101, and the insulating stacked structure 102 can be arranged so as not to overlap each other in the vertical direction, and the vertical direction is, for example, the Z direction. The main stack structure 100 and the stepped structure 101 may be arranged along the transverse direction, such as the Y direction, but the main stack structure 100 and the stepped structure 101 may not overlap each other in the longitudinal direction, and the longitudinal direction is, for example, the X direction. The main stack structure 100 and the insulation stack structure 102 may be arranged along the X direction, but the main stack structure 100 and the insulation stack structure 102 may not overlap each other in the Y direction. Similarly, the stepped structure 101 and the insulating stacked structure 102 may be arranged along the X direction, but the stepped structure 101 and the insulating stacked structure 102 may not overlap each other in the Y direction.

In an embodiment, as shown in Figure 1, the memory device 10 may have four stepped structures 101/101A/101B/101C, the stepped structure 101 and the stepped structure 101A are arranged adjacent to each other, and the insulating strip 103 makes the step The structure 101 is isolated from the stepped structure 101A. The step structure 101B and the step structure 101C are arranged adjacent to each other, and the insulating strip 103 isolates the step structure 101B from the step structure 101C. The step structure 101 and the step structure 101C are disposed on opposite sides of the main stack structure 100. The stepped structure 101A and the stepped structure 101B are disposed on opposite sides of the main stack structure 100. In an embodiment, the stepped structure 101 and the stepped structure 101C may be symmetrically arranged. In an embodiment, the stepped structure 101A and the stepped structure 101B may be symmetrically arranged. In an embodiment, the memory device 10 may have two insulating stacked structures 102/102A disposed on opposite sides of the main stacked structure 100; the stepped structure 101/101A/101B/101C and the insulating stacked structure 102/102A are disposed on the main stack Different sides of structure 100. In an embodiment, the two insulating stacked structures 102/102A may be symmetrically arranged.

The insulating strip 103 may extend along the Y direction to isolate the main stack structure 100 from the main stack structure 100A. According to different designs, the memory device 10 may have one or more main stacked structures 100/100A, one or more stepped structures 101/101A/101B/101C, and one or more insulating stacked structures 102/102A. As shown in FIG. 1, the insulating strip 103 may extend along the Y direction to isolate the stepped structure 101 from the stepped structure 101A, isolate the main stacked structure 100 from the main stacked structure 100A, and isolate the stepped structure 101B from the stepped structure 101C. In an embodiment, the insulating strip 103 may include an insulating material.

FIG. 2A is a schematic perspective view of the memory device 10, excluding the part of the memory device 10 corresponding to the insulating stacked structure 102 in FIG. Referring to FIG. 1 and FIG. 2A at the same time, the main stack structure 100 may include a plurality of conductive films 104 and a plurality of first insulating layers 105 stacked alternately along the Z direction. The plurality of conductive films 104 isolate the plurality of first insulating layers 105 from each other. In one embodiment, the conductive film 104 of the main stack structure 100 may include a conductive material, such as tungsten (W). The first insulating layer 105 of the main stack structure 100 may include an insulating material, and the insulating material includes an oxide, such as silicon oxide.

The step structure 101 may include a plurality of conductive step layers 106 and a plurality of insulating step layers 107 stacked alternately along the Z direction. The plurality of conductive step layers 106 isolate the plurality of insulating step layers 107 from each other. Each conductive step layer 106 has a different lateral area on the X-Y plane. For example, the lateral area of the conductive step layer 106 gradually decreases from the bottom surface 108 of the step structure 101 to the top surface 109 of the step structure 101. For example, the lateral area of the conductive step layer 106 at a lower level (the level closer to the bottom surface 108 of the step structure 101) is larger than that of the conductive step layer 106 at a higher level (the level farther from the bottom surface 108 of the step structure 101). The lateral area of layer 106. In an embodiment, the conductive step layer 106 of the step structure 101 may include a conductive material, such as tungsten. The insulating step layer 107 of the step structure 101 may include an insulating material, and the insulating material includes an oxide, such as silicon oxide.

The insulating stacked structure 102 may include a plurality of second insulating layers 110 and a plurality of third insulating layers 111 stacked alternately along the Z direction. The plurality of second insulating layers 110 isolate the plurality of third insulating layers 111 from each other. In an embodiment, the second insulating layer 110 of the insulating stacked structure 102 may include an insulating material, and the insulating material includes a nitride, such as silicon nitride. The third insulating layer 111 of the insulating stacked structure 102 may include an insulating material, and the insulating material includes an oxide, such as silicon oxide. In an embodiment, the second insulating layer 110 and the third insulating layer 111 may include different materials.

In an embodiment, the conductive film 104 of the main stack structure 100 may be electrically connected to the conductive step layer 106 of the step structure 101. The insulating stacked structure 102 may be electrically insulating. The conductive film 104 of the main stack structure 100 and the conductive step layer 106 of the step structure 101 can be used as the gate structure of the memory device 10.

In an embodiment, the plurality of first insulating layers 105 of the main stack structure 100, the plurality of insulating step layers 107 of the step structure 101, and the plurality of third insulating layers 111 of the insulating stack structure 102 have a one-to-one correspondence, in other words A first insulating layer 105, an insulating step layer 107 corresponding to the first insulating layer 105, and a third insulating layer 111 corresponding to the first insulating layer 105 may have the same height (or level) in the Z direction .

The memory device 10 may include a plurality of pillar structures 112 that are dispersedly arranged in the insulating stacked structure 102 and the stepped structure 101. The plurality of pillar structures 112 pass through the insulating stacked structure 102 and the stepped structure 101 in the Z direction. Each pillar structure 112 includes a tubular element 113 and a conductive pillar 114. The tubular element 113 penetrates the stack structure S. Specifically, the conductive pillar 114 is surrounded by the tubular element 113. In an embodiment, the column structure 112 may have a structure similar to a coaxial cable. The conductive pillar 114 and the tubular element 113 can extend along the Z direction and pass through the insulating stacked structure 102 and the stepped structure 101. The conductive pillar 114 may include a conductive material, such as tungsten.

In the insulating stacked structure 102, each pillar structure 112 passes through the same number of second insulating layers 110. In the stepped structure 101, a plurality of pillar structures 112 respectively pass through a different number of conductive stepped layers 106. For example, the stepped structure 101 may include a plurality of stepped portions 115 (as shown in FIG. 2A), the number of conductive stepped layers 106 included in each stepped portion 115 may be different, and the column structures 112 in the stepped structure 101 may be individually It is arranged in different stepped parts 115, specifically, a column structure 112 is arranged in a stepped part 115.

The memory device 10 may include a plurality of conductive plugs 116 disposed on the conductive step layer 106 of the step structure 101. Specifically, each conductive plug 116 can be disposed on the conductive stepped layer 106 of different levels in the stepped structure 101. A plurality of conductive plugs 116 can be individually arranged in different step portions 115. The conductive plug 116 is electrically connected to a conductive step layer 106 provided by the conductive plug 116, and the tubular element 113 and the conductive pillar 114 pass through the conductive step layer 106.

FIG. 2B shows one of the pillar structures 112 in the insulating stacked structure 102 shown in FIG. 1. FIG. 2C shows one of the pillar structures 112 in the step structure 101 shown in FIG. 1.

Referring to FIGS. 1 and 2B-2C, in the insulating stacked structure 102 and the stepped structure 101, the tubular element 113 may include a memory film 117, a dummy channel layer 118, and an insulating film 119. The conductive pillar 114 is surrounded by the tubular element 113, and the conductive pillar 114 extends beyond the bottom surface 120 of the dummy channel layer 118. In an embodiment, the bottom surface 120 of the dummy channel layer 118 may extend along the Z direction beyond the bottom surface 121 of the insulating stacked structure 102 and the bottom surface 108 of the stepped structure 101, and the conductive pillar 114 may extend beyond the insulating stack along the Z direction. The bottom surface 121 of the stack structure 102, the bottom surface 108 of the step structure 101 and the bottom surface 120 of the dummy channel layer 118.

The memory film 117 may include a multilayer structure known in the memory technology field, such as ONO (oxide-nitride-oxide) structure, ONONO (oxide-nitride-oxide-nitride-oxide) ) Structure, ONONONO (oxide-nitride-oxide-nitride-oxide-nitride-oxide) structure, SONOS (silicon-silicon oxide-silicon nitride-silicon oxide-silicon) structure, BE-SONOS ( Band gap silicon-silicon oxide-silicon nitride-silicon oxide-silicon) structure, TANOS (tantalum nitride-alumina-silicon nitride-silicon oxide-silicon) structure, MA BE-SONOS (metal-high dielectric constant Material energy band gap silicon-silicon oxide-silicon nitride-silicon oxide-silicon) structure and its combination. The memory film 117 may have a tube shape and surround the conductive pillar 114.

In one embodiment, the memory layer of the memory device 10 may include a memory film 117 and a memory material, and the memory material is formed between the memory film 117 and the conductive film 104 of the main stack structure 100. The memory layer may include any charge trapping structure known in the field of memory technology, such as ONO structure, ONONO structure, ONONONO structure, SONOS structure, BE-SONOS structure, TANOS structure, MA BE-SONOS structure and combinations thereof Wait. The charge trapping structure can use nitrides such as silicon nitride, or other similar high dielectric constant materials including metal oxides, such as aluminum oxide (alumina; Al ₂ O ₃ ), zirconium oxide (hafnium dioxide; HfO ₂ ) Wait. Memory cells can be defined in the memory layer. For example, when the memory layer includes a memory film 117 and a memory material, the memory film 117 can be understood as a tunneling oxide layer, and the memory film 117 can include silicon dioxide (SiO ₂ ) or Only silicon dioxide is included; and the memory material may include multilayer memory materials known in the memory technology field, such as aluminum oxide, titanium nitride (TiN), ONO structure, ONONO structure, ONONONO structure, SONOS structure , BE-SONOS structure, TANOS structure, MA BE-SONOS structure and their combinations, etc.

The dummy channel layer 118 is disposed between the memory film 117 and the conductive pillar 114. The dummy channel layer 118 may include a semiconductor material, such as a doped semiconductor material or an undoped semiconductor material. In one embodiment, the dummy channel layer 118 may include polysilicon (polysilicon), such as doped polysilicon or undoped polysilicon. The dummy channel layer 118 may have a tube shape and surround the conductive pillar 114. In an embodiment, the dummy channel layer 118 may mean the dummy channel layer 118 without a driving circuit. In an embodiment, the dummy channel layer 118 can be understood as an electrically floating element.

The insulating film 119 is disposed between the conductive pillar 114 and the dummy channel layer 118. The insulating film 119 may have a tube shape and surround the conductive pillar 114. The insulating film 119 may include a dielectric material, and the dielectric material includes an oxide (such as silicon oxide).

FIG. 3 is a schematic top view of the main stack structure 100 according to an embodiment of the present invention. Referring to FIGS. 1 and 3 at the same time, the memory device 10 may include a plurality of column elements 122 that are dispersedly arranged in the main stack structure 100. The pillar element 122 extends along the Z direction and passes through the main stack structure 100.

The pillar element 122 may include a memory film 117, a channel layer 118A, a source/drain pillar 123, a source/drain pillar 124, an insulating pillar 125, and an insulating film 119. The insulating pillar 125 is disposed between the source/drain pillar 123 and the source/drain pillar 124. The insulating pillar 125 isolates the source/drain pillars 123 from the source/drain pillars 124 from each other. One of the source/drain post 123 and the source/drain post 124 is a source, and the other is a drain. The insulating film 119 is disposed between the channel layer 118A and the source/drain post 123, the source/drain post 124, and the insulating post 125. The channel layer 118A is provided between the insulating film 119 and the memory film 117. The channel layer 118A may have a tube shape and surround the source/drain pillar 123, the source/drain pillar 124, the insulating film 119, and the insulating pillar 125. The memory film 117 may have a tube shape and surround the channel layer 118A. The memory film 117 of the pillar element 122 may be similar to the memory film 117 of the tubular element 113. The source/drain pillar 123 and the source/drain pillar 124 may include a doped semiconductor material, such as N+ polysilicon, or may include an undoped semiconductor material. The insulating pillar 125 may include an insulating material, and the insulating material includes a nitride, such as silicon nitride.

The memory device 10 may include a plurality of memory cells disposed in the main stack structure 100 and the main stack structure 100A. The memory cell can be defined in the memory film 117 at the intersection of the conductive film 104 and the channel layer 118A of the pillar element 122. The pillar element 122 can be understood as an active pillar element. In an embodiment, the main stack structure 100 may be disposed in an array region, and the step structure 101 may be disposed in a staircase region.

The difference between the dummy channel layer 118 of the tubular element 113 and the channel layer 118A of the pillar element 122 is that when a voltage is applied to the memory device 10, the dummy channel layer 118 is not used to provide channels for electrons or holes.

FIG. 4 is a schematic perspective view of the pillar element 122A in the main stack structure 100 according to another embodiment of the present invention. The difference between the pillar element 122A shown in FIG. 4 and the pillar element 122 shown in FIG. 3 is explained as follows. The pillar element 122A includes a channel layer 118B, a source/drain pillar 123, a source/drain pillar 124, and an insulating film 119. The insulating film 119 isolates the source/drain post 123 from the source/drain post 124. The channel layer 118B shown in FIG. 4 is different from the channel layer 118A shown in FIG. 3 in that the channel layer 118B has an open-loop shape, and the channel layer 118B has opposite ends electrically connected to the source/drain. The pole 123 and the source/drain pole 124. The difference between the memory film 417 shown in FIG. 4 and the memory film 117 shown in FIG. 3 is that the memory film 417 is disposed on the upper surface and the lower surface of the conductive film 104 of the main stack structure 100, and can extend on the pillar elements Between the outer side wall of 122A and the conductive film 104.

In one embodiment, in the schematic perspective view of the main stack structure 100, the memory film 117 shown in FIG. Between the films 104, the arrangement of the memory film 417 shown in FIG. 4 is similar.

Please refer to FIG. 1 again, the memory device 10 may include a poly semiconductor layer (poly semiconductor) 126 located under the main stacked structure 100, the stepped structure 101 and the insulating stacked structure 102. In other words, the polycrystalline semiconductor layer 126 is located under the memory cell. The tubular element 113, the conductive pillar 114 and the pillar element 122 pass through the polycrystalline semiconductor layer 126. The polycrystalline semiconductor layer 126 may include a doped semiconductor material, such as P+ polysilicon, or an undoped semiconductor material. The conductive pillar 114 may have an upper conductive pillar end 127 and a lower conductive pillar end 128 opposite to the upper conductive pillar end 127. The conductive column end 127 on the conductive column 114 is located above the insulating stacked structure 102 and the stepped structure 101. The conductive pillar end 128 under the conductive pillar 114 is located under the polycrystalline semiconductor layer 126.

The memory device 10 may include a transistor 161, a lower conductive structure 163 and a lower conductive structure 165. The lower conductive structure 163 is electrically connected between the conductive column end 128 under the conductive column 114 and one of the drain and the source of the transistor 161. The lower conductive structure 165 is electrically connected between the conductive column end 128 under the conductive column 114 and the other of the drain and source of the transistor 161.

FIG. 5 is a schematic top view of the memory device 10 according to an embodiment of the present invention. The difference between Fig. 1 and Fig. 5 is that the memory device 10 shown in Fig. 5 includes more main stacked structures 100/100A/100B/100C, and more stepped structures 101/101A/101B/101C /101D/101E/101F/101G, Figure 5 does not show the insulating stacked structure 102/102A. Please refer to FIG. 1 and FIG. 5 at the same time, the memory device 10 may include a conductive layer 130. The conductive layer 130 may be disposed above the main stacked structure 100, the stepped structure 101 and the insulating stacked structure 102. The conductive layer 130 may include an upper conductive structure 171, an upper conductive structure 173, an upper conductive structure 181, an upper conductive structure 183, and an upper conductive structure 191, and is disposed above the pillar element 122 and/or the pillar structure 112.

The upper conductive structure 173 may be electrically connected to a conductive pillar 114 of a pillar structure 112 in the insulating stacked structure 102. The upper conductive structure 171 may be electrically connected to the plurality of conductive pillars 114 of the other plurality of pillar structures 112 in the insulating stacked structure 102. The upper conductive structure 171 is electrically connected between one of the source or drain of the pillar element 122 and the conductive pillar 114. The upper conductive structure 171 is electrically connected between the memory cell and the conductive column end 127 on the conductive column 114 in the insulating stacked structure 102. A conductive pillar 114 of a pillar structure 112 in the insulating stack structure 102 is electrically connected between the lower conductive structure 165 and the upper conductive structure 173. The plurality of conductive pillars 114 of the other plurality of pillar structures 112 in the insulating stacked structure 102 are electrically connected between the lower conductive structure 163 and the upper conductive structure 171.

The upper conductive structure 183 may be electrically connected to a conductive pillar 114 of a pillar structure 112 in the insulating stacked structure 102A. The upper conductive structure 181 may be electrically connected to the plurality of conductive pillars 114 of the other plurality of pillar structures 112 in the insulating stacked structure 102A. The upper conductive structure 181 is electrically connected between the other of the source or drain of the pillar element 122 (for example, the one electrically connected with respect to the upper conductive structure 171) and the conductive pillar 114. The upper conductive structure 181 is electrically connected between the memory cell and the conductive column end 127 on the conductive column 114 in the insulating stacked structure 102A. A conductive pillar 114 of a pillar structure 112 in the insulating stacked structure 102A is electrically connected between the lower conductive structure 165 and the upper conductive structure 183. The plurality of conductive pillars 114 of the other plurality of pillar structures 112 in the insulating stacked structure 102A are electrically connected between the lower conductive structure 163 and the upper conductive structure 181.

In one embodiment, for example, the source of the pillar element 122 is electrically connected to the upper conductive structure 171, the conductive pillar 114 in the insulating stacked structure 102, the upper conductive structure 173, the lower conductive structure 163, the transistor 161, and the lower conductive structure 165. . The upper conductive structure 171, the conductive pillar 114 in the insulating stack structure 102, the upper conductive structure 173, and the plurality of lower conductive pillars 114 (that is, effective conductive pillars or active conductive pillars) electrically connected to the insulating stack structure 102 The lower conductive structure 163 and the lower conductive structure 165 between the ends 128 of the conductive pillars can be used as source lines. For example, the upper conductive structure 173 can be used as a global source line or a common source line. Transistor 161 (switch) can be used as a source line transistor (source line switch). The conductive pillar 114 in the insulating stacked structure 102 can be used as a source line contact structure for the memory cell.

In one embodiment, for example, the drain of the pillar element 122 is electrically connected to the upper conductive structure 181, the conductive pillar 114 in the insulating stacked structure 102A, the upper conductive structure 183, the lower conductive structure 163, the transistor 161, and the lower conductive structure 165 . The upper conductive structure 181, the conductive pillar 114 in the insulating stacked structure 102A, the upper conductive structure 183, and the plurality of lower conductive pillars 114 (that is, effective conductive pillars or active conductive pillars) electrically connected to the insulating stacked structure 102A The lower conductive structure 163 and the lower conductive structure 165 between the ends 128 of the conductive pillars can be used as bit lines. For example, the upper conductive structure 181 can be used as a local bit line, and the upper conductive structure 183 can be used as a global bit line or a common bit line. The plurality of conductive pillars 114, the lower conductive structure 163, the transistor 161, and the lower conductive structure 165 in the insulating stacked structure 102A are electrically connected to the global bit line. Transistor 161 (switch) can be used as a bit line transistor (bit line switch). The conductive pillar 114 in the insulating stacked structure 102A can be used as a bit line contact structure for the memory cell.

The upper conductive structure 191 may be electrically connected between the conductive plug 116 and the conductive column end 127 on the conductive column 114 of the column structure 112 in the step structure 101. The semiconductor device 129 may include a transistor 192 and a lower conductive structure 194. The lower conductive structure 194 is electrically connected to the transistor 192. The lower conductive structure 194 is electrically connected between the transistor 192 and the conductive column end 128 of the conductive column 114 of the column structure 112 in the step structure 101. In many embodiments, the conductive pillars 114 (ie, effective conductive pillars or active conductive pillars) of the pillar structure 112 in the ladder structure 101, the upper conductive structure 191, the conductive plug 116, and the lower conductive structure 194 can be used as characters String. Transistor 192 (switch) can be used as a word line transistor (character line switch). The conductive pillar 114 in the stepped structure 101 can be used for the word line contact of the memory cell.

Part of the conductive pillars 114 of the plurality of pillar structures 112 in the stepped structure 101 can be electrically floating, and thus are called dummy conductive pillars. For example, as shown in Figure 5, the conductive pillars 114 of the plurality of pillar structures 112 in the stepped structure 101, the stepped structure 101B, the stepped structure 101D, and the stepped structure 101F are electrically floating, and the stepped structure 101A, the stepped structure The conductive pillars 114 of the plurality of pillar structures 112 in the step structure 101E and the step structure 101G are 101C.

The decoder can be arranged under the main stack structure 100 and the ladder structure 101. The bit line transistor and the source line transistor can be disposed on the substrate (not shown), adjacent to the peripheral region of the memory device 10. In one embodiment, the bit line transistor and the source line transistor may be disposed on the substrate and located in the area directly under the memory device 10 to form a structure (CMOS under array) in which the driving circuit is placed under the array.

In an embodiment, the lower conductive structure 163 and the lower conductive structure 165 may include, but are not limited to, a first lower metal layer (BM1), a second lower metal layer (BM2), a third lower metal layer (BM3), and multiple layers. A plurality of lower vias (vias) between the lower metal layers and providing electrical connections between the plurality of lower metal layers.

In an embodiment, the conductive layer 130 may include a first upper metal layer (TM1) and/or a second upper metal layer (TM2).

The tubular element 113 in the stepped structure 101 and the insulating stacked structure 102 may have the same transverse cross-sectional size (for example, diameter), for example, the cross-sectional size (for example, diameter) on the X-Y plane. The cross-sectional size of the tubular element 113 may be greater than the cross-sectional size of the column element 122. For example, on the X-Y plane, the cross-sectional diameter of the tubular element 113 is larger than the cross-sectional diameter of the column element 122.

FIGS. 6-15 are exemplary illustrations of a method for manufacturing the memory device 10 according to an embodiment of the present invention.

Please refer to FIG. 6, the semiconductor device 129 is provided under the polycrystalline semiconductor layer 126. The semiconductor device 129 may have the aforementioned structure (refer to FIG. 1). In an embodiment, the semiconductor device 129 may include, but is not limited to, a first lower metal layer (BM1), a second lower metal layer (BM2), a third lower metal layer (BM3), and a plurality of lower metal layers disposed between And a plurality of lower via holes for electrical connection between the plurality of lower metal layers are provided. The semiconductor device 129 may include other conductive lines formed in or on the inter-layer dielectric layer. This disclosure does not limit this. In one embodiment, the semiconductor device 129 is formed on a substrate (not shown) in a front-end-of-line (FEOL) process.

The semiconductor device may include a dielectric layer 136 (upper dielectric layer). In an embodiment, the dielectric layer 136 may be formed on the third lower metal layer (BM3). The dielectric layer 136 may include a dielectric material, and the dielectric material includes an oxide, such as silicon oxide. Then, the polycrystalline semiconductor layer 126 is formed on the dielectric layer 136. The polycrystalline semiconductor layer 126 may include a doped semiconductor material, such as P+ polysilicon, or an undoped semiconductor material. In one embodiment, the dielectric layer 136 and the polycrystalline semiconductor layer 126 may be formed by a deposition process, such as a chemical vapor deposition (CVD) process.

The insulating stacked structure 102' is formed on the polycrystalline semiconductor layer 126. The insulating stacked structure 102' may include a plurality of second insulating layers 110' and a plurality of third insulating layers 111' stacked alternately, for example, along the Z direction. The plurality of second insulating layers 110' isolate the plurality of third insulating layers 111' from each other. In an embodiment, the second insulating layer 110' may include an insulating material, and the insulating material includes a nitride, such as silicon nitride. The third insulating layer 111' may include an insulating material, and the insulating material includes an oxide, such as silicon oxide. In an embodiment, the second insulating layer 110' and the third insulating layer 111' comprise different materials. In one embodiment, the insulating stacked structure 102' may be formed by sequentially depositing the third insulating layer 111' and the second insulating layer 110'.

Referring to FIG. 7, the insulating stacked structure 102' is patterned, for example, by photolithography processing to form a first hole 137, a second hole 138, and a third hole in the insulating stacked structure 102'.孔139. The first hole 137, the second hole 138, and the third hole 139 pass through the insulating stacked structure 102' and the polycrystalline semiconductor layer 126 in the Z direction. The first hole 137, the second hole 138, and the third hole 139 expose the sidewalls of the insulating stacked structure 102' and the polycrystalline semiconductor layer 126. In one embodiment, the first hole 137, the second hole 138, and the third hole 139 can be formed by etching the insulating stacked structure 102', such as wet etching or dry etching. (dry etching), and then stop the etching when the etching process slightly exceeds the bottom surface 140 of the polycrystalline semiconductor layer 126. In an embodiment, the polycrystalline semiconductor layer 126 may be regarded as an etch stop layer. The etching process can stop in the dielectric layer 136. In an embodiment, the first hole 137, the second hole 138, and the third hole 139 may gradually narrow from the top surface 141 of the insulating stacked structure 102' to the bottom surface 140 of the polycrystalline semiconductor layer 126 along the Z direction. In an embodiment, each of the first hole 137, the second hole 138, and the third hole 139 may have a shape along the Z direction from the top surface 141 of the insulating stacked structure 102' to the bottom surface of the polycrystalline semiconductor layer 126 140 gradually becomes smaller in the transverse cross-sectional size (for example, the transverse cross-sectional size on the XY plane). In one embodiment, on any XY plane (the XY plane is intersected with the first hole 137, the second hole 138 and the third hole 139), the transverse cross-sectional size of the first hole 137 is smaller than that of the second hole 138 The transverse cross-sectional size of the first hole 137 is smaller than the transverse cross-sectional size of the third hole 139, and the transverse cross-sectional size of the second hole 138 is approximately the same as the transverse cross-sectional size of the third hole 139.

Referring to FIG. 8, the memory film 117 and the channel layer 118' are formed on the insulating stacked structure 102' and are lined in the first hole 137, the second hole 138, and the third hole. In the first hole 137, the second hole 138, and the third hole, the memory film 117 and the channel layer 118' are formed on the inner sidewall and bottom of the first hole 137, the second hole 138, and the third hole. In one embodiment, the memory film 117 and the channel layer 118' can be formed by a deposition process, for example, a chemical vapor deposition process. In one example, the memory film 117 and the channel layer 118' are formed in a furnace.

The memory film 117 may include a multilayer structure known in the memory technology field, such as ONO structure, ONONO structure, ONONONO structure, SONOS (silicon-silicon oxide-silicon nitride-silicon oxide-silicon) structure, BE-SONOS structure, TANOS Structure, MA BE-SONOS structure and its combination. The channel layer 118' may include a semiconductor material, such as a doped semiconductor material or an undoped semiconductor material. In one embodiment, the channel layer 118' may include polysilicon, such as doped polysilicon or undoped polysilicon.

Referring to FIG. 9, the memory film 117 and the channel layer 118' on the insulating stacked structure 102' are removed to expose the top of the insulating stacked structure 102' and form a flat top surface on the X-Y plane. The channel layer 118' may include the dummy channel layer 118, the channel layer 118A, etc. as shown in FIG. 1. In this processing stage, the channel layer 118' and the memory film 117 at the bottom of the first hole 137, the second hole 138 and the third hole 139 are removed to expose the dielectric layer 136. In other words, the channel layers 118/118A at the bottom of the first hole 137, the second hole 138 and the third hole 139 are not connected to avoid current leakage paths. The channel layer 118/118A may have a tube shape and have two open ends. In one embodiment, the memory film 117 on the insulating stacked structure 102', the channel layer 118' on the insulating stacked structure 102', and the channel layer 118' at the bottom of the first hole 137, the second hole 138, and the third hole 139, The removal of the memory film 117 can be performed by etching-back processing.

Referring to FIG. 10, the insulating film 119 is formed in the first hole 137, the second hole 138, and the third hole 139. The insulating film 119 may include a dielectric material, and the dielectric material includes an oxide, such as silicon oxide. In one embodiment, the insulating film 119 can be formed by the following steps: depositing the insulating film 119 on the insulating stacked structure 102', and filling the first hole 137, the second hole 138, and the third hole 139; removing the insulating stack The insulating film 119 on the structure 102' exposes the top surface 141 of the insulating stacked structure 102', for example, by chemical-mechanical planarization processing or etch back processing; the first opening 142, the second opening 143 and the third opening 144 are respectively formed in the insulating film 119 in the first hole 137, the second hole 138 and the third hole 139, for example, by wet etching or dry etching. The first opening 142, the second opening 143 and the third opening 144 extend along the Z direction and expose the sidewalls of the insulating film 119 in the first hole 137, the second hole 138 and the third hole 139. In one embodiment, the etching process for forming the first opening 142, the second opening 143 and the third opening 144 can be stopped at the insulating film 119. In an embodiment, the first opening 142, the second opening 143 and the third opening 144 may be located at the center of the first hole 137, the second hole 138 and the third hole 139, respectively.

In one embodiment, on any XY plane (the XY plane is intersected with the first opening 142, the second opening 143 and the third opening 144), the transverse cross-sectional size of the first opening 142 is smaller than that of the second opening. The transverse cross-sectional size of the hole 143, the transverse cross-sectional size of the first opening 142 is smaller than the transverse cross-sectional size of the third opening 144, and the transverse cross-sectional size of the second opening 143 is approximately the same as the transverse cross-sectional size of the third opening 144.

Referring to FIG. 11, the insulating pillars 125 are formed in the first opening 142, the second opening 143, and the third opening 144, respectively. The insulating pillar 125 may include an insulating material, and the insulating material includes a nitride, such as silicon nitride. The insulating pillar 125 may be formed by a deposition process, for example, a chemical vapor deposition process.

Please refer to FIG. 12, the source/drain post 123 and the source/drain post 124 are formed on opposite sides of the insulating post 125 in the first opening 142. The insulating pillar 125 isolates the source/drain pillars 123 from the source/drain pillars 124 from each other. The source/drain post 123 and the source/drain post 124 can be formed by the following steps: two narrow openings are formed on the opposite side of the insulating post 125 in the first opening 142, and these narrow openings can make the channel The sidewalls of the layer 118A and/or the sidewalls of the insulating pillars 125 are exposed; the source/drain pillars 123 and the source/drain pillars 124 are respectively formed in the narrow openings to fill the narrow openings. In one embodiment, the narrow opening can be formed by etching, for example, wet etching or dry etching. The narrow openings may not overlap each other. In an embodiment, the source/drain pillars 123 and the source/drain pillars 124 may be formed by a deposition process, such as a chemical vapor deposition process. The source/drain pillar 123 and the source/drain pillar 124 may include a doped semiconductor material, such as N+ polysilicon, or may include an undoped semiconductor material. Disposing the insulating pillar 125 between the source/drain pillar 123 and the source/drain pillar 124 helps to increase the process window to avoid the occurrence of PLG-to-PLG punch.

Referring to FIG. 13, the trench 145 is formed in the insulating stacked structure 102'. The trench 145 passes through the insulating stacked structure 102' in the Z direction. The trench 145 exposes the sidewalls of the insulating stacked structure 102' and the polycrystalline semiconductor layer 126. In one embodiment, the insulating stacked structure 102' may be etched, such as wet etching or dry etching, to form the trench 145, and the etching process is stopped at the polycrystalline semiconductor layer 126.

Referring to FIG. 14, an etching process is performed through the trench 145 to remove part of the second insulating layer 110' (that is, the second insulating layer 110' around the first hole 137 and the second hole 138) to form a third insulating layer. The space between the layers 111'. In one embodiment, the etching process may use phosphoric acid (H ₃ PO ₄ ). By controlling the time of the etching process, part of the second insulating layer 110' (that is, the second insulating layer 110' around the first hole 137 and the second hole 138) can be removed, while leaving other parts of the second insulating layer 110' The layer 110' (ie, the second insulating layer 110' around the third hole 139). In other words, the second insulating layer 110' around the third hole 139 will not be removed during the etching process. Then, the dielectric film 146 may be linedly formed in the space between the third insulating layers 111'. The conductive material 147, such as tungsten, may be formed to fill the space between the third insulating layers 111' to form the conductive film 104 and the conductive step layer 106 as shown in FIG. 1. The dielectric film 146 may include a storage layer and a barrier layer (not shown). The dielectric film 146 may include a high-k material. In an embodiment, the conductive film 104 can be used as a gate electrode. In one embodiment, the dielectric film 146 and the conductive film 104 can be formed by a HKMG (High-k Metal Gate) process. The process included in Figure 14 can be understood as a gate replacement process.

In one embodiment, the memory layer of the memory device 10 may include the memory film 117 and the dielectric film 146 shown in FIG. 14. In other words, the dielectric film 146 can be used as a memory material. The memory layer may include any charge trapping structure known in the field of memory technology, such as ONO structure, ONONO structure, ONONONO structure, SONOS structure, BE-SONOS structure, TANOS structure, MA BE-SONOS structure, and combinations thereof. The charge trapping structure can use nitrides such as silicon nitride, or other similar high dielectric constant materials including metal oxides, such as aluminum oxide (Al ₂ O ₃ ), zirconium oxide (HfO ₂ ), and the like. Memory cells can be defined in the memory layer. For example, when the memory layer includes the memory film 117 and the dielectric film 146, the memory film 117 can be understood as a tunneling oxide layer, and the memory film 117 can include silicon dioxide (SiO ₂ ) or only silicon dioxide; The dielectric film 146 can be used as a memory material, and the dielectric film 146 can include a multilayer memory material known in the memory technology field, such as aluminum oxide, titanium nitride (TiN), ONO structure, ONONO structure, ONONONO structure , SONOS structure, BE-SONOS structure, TANOS structure, MA BE-SONOS structure and their combinations, etc.

Then, the insulating strip 103 is formed to fill the trench 145, for example, by a deposition process.

Referring to FIG. 15, the conductive pillar 114 is formed in the insulating film 119 in the second hole 138 and the third hole 139. The conductive pillar 114 extends along the Z direction, passes through the dielectric layer 136, and contacts the semiconductor device 129, for example, contacts the third lower metal layer (BM3). The conductive pillar 114 may include a conductive material, such as tungsten. In one embodiment, the conductive pillars 114 may be formed by the following steps: by etching, for example, by wet etching or dry etching, removing formed in the second opening 143 and the third opening 144 The insulating pillars 125 (as shown in Figures 10-11); the etching process can be stopped at the bottom surface 148 of the dielectric layer 136; the deep openings are formed by the etching process; the conductive pillars 114 are respectively formed in the deep through the deposition process In the opening, for example, chemical vapor deposition is used. The conductive pillar 114 is electrically connected to the semiconductor device 129. In this processing stage, the conductive pillar 114 formed in the second hole 138 can be understood as the conductive pillar 114 in the stepped structure 101 shown in FIG. 1, and the conductive pillar 114 formed in the third hole 139 can be understood as The conductive pillar 114 in the insulating stacked structure 102A shown in FIG. 1.

The present disclosure provides a memory device that has bit line contacts, source line contacts, and/or word line contacts surrounded by a dummy channel layer, and the bit line contacts, source line contacts, and/or word line contacts can be The tubular element is protected and electrically insulated. Due to this configuration, additional isolation regions for electrically insulating bit line contacts, source line contacts, and/or word line contacts in the memory device can be omitted, which can improve the space efficiency of the memory device and reduce production Cost, can increase the design freedom of the memory device, and can improve the process integration. In addition, the present disclosure provides a memory device with a polycrystalline semiconductor layer. The polycrystalline semiconductor layer is used as an etch stop layer. The polycrystalline semiconductor layer helps to improve the uniformity of the holes used for the pillar elements and at the same time can improve the etching process. Controllable.

It should be noted that the above-mentioned drawings, structures and steps are used to describe some embodiments or application examples of the present disclosure, and the present disclosure is not limited to the scope and application of the above-mentioned structures and steps. Other embodiments with different structural aspects, such as known components of different internal components, can be applied, and the structure and steps of the examples can be adjusted according to actual application requirements. Therefore, the structure of the drawings is only used for illustration, not for limiting the present invention. Generally, the knowledgeable person should know that the relevant structures and steps of the application of the present disclosure, such as the arrangement or configuration of the relevant elements and layers in the semiconductor structure, or the details of the manufacturing steps, may be required by the actual application. Adjust and change accordingly.

In summary, although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention. Those with ordinary knowledge in the technical field of the present invention can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to those defined by the attached patent application scope.

10: Memory device S: Stacked structure 100, 100A, 100B, 100C: main stack structure 101, 101A, 101B, 101C, 101D, 101E, 101F, 101G: ladder structure 102, 102A, 102': Insulation stack structure 103: Insulation strip 104: conductive film 105: first insulating layer 106: conductive step layer 107: Insulation step layer 108, 120, 121, 140, 148: bottom surface 109,141: top surface 110, 110': second insulating layer 111,111': third insulating layer 112: Cylinder structure 113: Tubular element 114: Conductive column 115: Step 116: conductive plug 117,417: Memory film 118: Dummy channel layer 118A, 118B, 118': channel layer 119: Insulating film 122, 122A: Column element 123,124: source/drain column 125: Insulating column 126: Polycrystalline semiconductor layer 127: Upper conductive column end 128: Lower conductive column end 129: Semiconductor Devices 130: conductive layer 136: Dielectric layer 137: The first hole 138: second hole 139: The third hole 142: first opening 143: second opening 144: third opening 145: groove 146: Dielectric film 147: Conductive materials 161,192: Transistor 163, 165, 194: lower conductive structure 171, 173, 181, 183, 191: upper conductive structure X, Y, Z: direction

Figure 1 is a schematic perspective view of a memory device according to an embodiment of the present invention; Figure 2A is a schematic perspective view of a memory device according to an embodiment of the present invention; FIG. 2B shows one of a plurality of pillar structures in the insulating stacked structure shown in FIG. 1; Figure 2C shows one of the multiple pillar structures in the stepped structure shown in Figure 1; Figure 3 is a schematic top view of a main stack structure according to an embodiment of the present invention; Figure 4 is a schematic perspective view of a memory device according to an embodiment of the present invention; Figure 5 is a schematic top view of a memory device according to an embodiment of the present invention; and FIGS. 6-15 are exemplary illustrations of a method for manufacturing a memory device according to an embodiment of the present invention.

10: Memory device

S: Stacked structure

100, 100A: Main stack structure

101, 101A, 101B, 101C: ladder structure

102, 102A: Insulation stack structure

103: Insulation strip

106: conductive step layer

107: Insulation step layer

121: bottom surface

110: second insulating layer

111: third insulating layer

112: Cylinder structure

113: Tubular element

114: Conductive column

116: conductive plug

122: Column element

126: Polycrystalline semiconductor layer

127: Upper conductive column end

129: Semiconductor Devices

130: conductive layer

161,192: Transistor

163, 165, 194: lower conductive structure

171, 173, 181, 183, 191: upper conductive structure

X, Y, Z: direction

Claims (10)

A memory device including: A stacked structure; A tubular element including a dummy channel layer, and the tubular element penetrates the stacked structure; A conductive pillar surrounded by the tubular element, and the conductive pillar extends beyond a bottom surface of the dummy channel layer; and A plurality of memory cells are electrically connected to the conductive pillar in the stacked structure. The memory device according to claim 1, wherein the dummy channel layer has a tubular shape, and the tubular element further includes: A memory film, wherein the dummy channel layer is between the memory film and the conductive pillar, wherein the memory film has a tube shape; and An insulating film between the conductive pillar and the dummy channel layer, The insulating film has a tube shape. The memory device according to claim 1, wherein the conductive pillar is used as a bit line contact structure (contact), a source line contact structure or a word line contact structure for the memory cells. The memory device according to claim 1, further comprising a semiconductor device located below, and the semiconductor device is electrically connected to a lower conductive pillar end of the conductive pillar, wherein the semiconductor device comprises a bit line switch (switch) Or a source line switch. The memory device according to claim 1, wherein the stacked structure includes an insulating stacked structure, the tubular element and the conductive pillar pass through the insulating stacked structure, and the memory device further includes an upper conductive layer electrically connected to the Between the memory cell and one of the upper conductive column ends of the conductive column, the conductive column is used as a bit line contact structure or a source line contact structure. The memory device according to claim 5, wherein the conductive layer includes a local bit line and a global bit line, and the local bit line passes through the insulating stack structure The conductive pillar is electrically connected to the global bit line. The memory device according to claim 1, wherein the stacked structure includes an insulating stacked structure, the memory device further includes a lower conductive structure and a plurality of pillar structures, the lower conductive structure is located under the insulating stacked structure, and the pillars Each of the body structures includes the tubular element and the conductive pillar, and each of the pillar structures passes through the insulating stack structure, and the plurality of lower conductive pillar ends of the conductive pillars are electrically conductive through the lower conductive pillars. The structures are electrically connected to each other. The memory device according to claim 1, wherein the stacked structure includes a stepped structure, the stepped structure includes a plurality of conductive stepped layers, and the memory device further includes a conductive plug that is electrically connected to and disposed on the On a conductive stepped layer of the conductive stepped layers, wherein the tubular element passes through the conductive stepped layer of the conductive stepped layers. The memory device according to claim 8, wherein the tubular element and the conductive pillar further pass through another conductive level, and the other conductive level is located below the one conductive level. The memory device according to claim 8, further comprising a conductive layer located above, and the conductive layer is electrically connected between the conductive plug and the conductive pillar.

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