TWI857842B - 3d memory - Google Patents

Abstract

A 3D memory including a plurality of tiles, a bit line transistor structure, a first upper conductive layer, and a second upper conductive layer. The bit line transistor structure is disposed between a first sub-tile and a second sub-tile in the plurality of tiles. The first upper conductive layer includes a plurality of local bit lines, a plurality of local source lines and a conductive pattern. The plurality of local bit lines include a first group of local bit lines and a second group of local bit lines separated from each other, wherein two adjacent local bit lines among the plurality of local bit lines are disposed on two adjacent local source lines. The conductive pattern is disposed between the first group of local bit lines and the second group of local bit lines, and between the two adjacent local source lines. The second upper conductive layer is disposed on the first upper conductive layer and includes a global bit line. The global bit line is electrically connected to the plurality of local bit lines through the conductive pattern. The provided 3D memory could be a 3D AND flash memory or a 3D NOR flash memory with high capacity and high performance.

Description

Three-dimensional memory

The present disclosure relates to a three-dimensional memory.

Non-volatile memory has the advantage that the stored data will not disappear after power failure, so it is widely used in personal computers and other electronic devices. The three-dimensional memory commonly used in the industry currently includes NOR memory and NAND memory. In addition, another type of three-dimensional memory is AND memory, which can be applied to multi-dimensional memory arrays and has high integration and high area utilization, and has the advantages of fast operation speed. Therefore, the development of three-dimensional memory has gradually become the current trend.

The present disclosure provides a three-dimensional memory having relatively low bit line capacitance (CBL) and/or background leakage current.

The three-dimensional memory disclosed herein includes a plurality of blocks, a bit line transistor structure, a first upper conductive layer, and a second upper conductive layer. The plurality of blocks are disposed on a substrate, wherein one of the plurality of blocks includes a first sub-block disposed in a first region of the substrate and a second sub-block disposed in a second region of the substrate. The bit line transistor structure is disposed on the substrate and between the first sub-block and the second sub-block, and includes a first bit line transistor structure disposed in the first region and a second bit line transistor structure disposed in the second region. The first upper conductive layer is disposed on the substrate and includes a plurality of regional bit lines, a plurality of regional source lines, and a conductive pattern. A plurality of regional bit lines extend along a first direction and include a first group of regional bit lines and a second group of regional bit lines, wherein the first group of regional bit lines and the second group of regional bit lines are separated from each other in the first direction. A plurality of regional source lines extend along the first direction, wherein two adjacent regional bit lines among the plurality of regional bit lines are disposed between two adjacent regional source lines. A conductive pattern is disposed between the first group of regional bit lines and the second group of regional bit lines in the first direction, and is disposed between two adjacent regional source lines in the second direction. A second upper conductive layer is disposed on the first upper conductive layer and includes a global bit line, wherein the global bit line is electrically connected to the first group of regional bit lines and the second group of regional bit lines through the conductive pattern.

Based on the above, the design of the three-dimensional memory disclosed in the present invention can be realized by forming a conductive pattern in the first upper conductive layer. In detail, the three-dimensional memory of an embodiment of the present invention includes a block divided into a first sub-block disposed in a first region and a second sub-block disposed in a second region, and a plurality of regional bit lines are divided into a first group of regional bit lines and a second group of regional bit lines, wherein the global bit line can be electrically connected to the first group of regional bit lines and the second group of regional bit lines through the conductive pattern. Based on this, the sector that needs to be driven by each bit line transistor structure can be reduced and the regional bit line can have a relatively short length, thereby reducing the bit line capacitance and background leakage current, thereby improving the operating speed of the three-dimensional memory of an embodiment of the present invention.

The following examples are listed and illustrated in detail, but the examples provided are not intended to limit the scope of the present disclosure. In addition, the drawings are for illustration purposes only and are not drawn in their original size. For ease of understanding, the same components will be indicated by the same symbols in the following description.

FIG1A is a partial three-dimensional schematic diagram of a memory of an embodiment of the present disclosure, FIG1B is a top view schematic diagram of a memory of an embodiment of the present disclosure, FIG1C is a partial schematic diagram of an embodiment of the memory of FIG1B , and FIG1D is a circuit diagram of a memory of an embodiment of the present disclosure.

1A to 1C, the three-dimensional memory 10 provided in the present disclosure may be a three-dimensional AND flash memory or a three-dimensional NOR flash memory with high capacity and high performance. In the present embodiment, the three-dimensional memory 10 is a three-dimensional NOR flash memory, but the present disclosure is not limited thereto. The three-dimensional memory 10 of the present embodiment includes a plurality of tiles 10T. Each tile 10T may store, for example, 16M bits of data. In this embodiment, the block 10T in the three-dimensional memory 10 is divided into two sub-tiles 10T1 and 10T2, wherein the sub-tile 10T1 and the sub-tile 10T2 can each store 8M bits of data, which will be described in detail in the subsequent embodiments. It is worth noting that FIG. 1A to FIG. 1C only show that the three-dimensional memory 10 includes one block 10T as an example, but the present disclosure is not limited to this.

The three-dimensional memory 10 includes a plurality of blocks 10T, for example, disposed on a substrate SB. The substrate SB may be, for example, a semiconductor substrate. In some embodiments, the material of the substrate SB may include silicon, doped silicon, germanium, silicon germanium, semiconductor compounds, other suitable semiconductor materials, or a combination thereof. For example, the substrate SB may be a silicon substrate, but the present disclosure is not limited thereto. In some embodiments, a plurality of doped regions may be formed in the substrate SB according to design requirements. For example, a plurality of doped regions including a P-type well region (not shown) and an N-type deep well region (not shown) may be formed in the substrate SB, but the present disclosure is not limited thereto. In other embodiments, a buried oxide layer (not shown) may be further formed on the substrate SB. In the present embodiment, the substrate SB may include a first region SB1 and a second region SB2, wherein the sub-block 10T1 is disposed in the first region SB1, and the sub-block 10T2 is disposed in the second region SB2, but the present disclosure is not limited thereto.

In some embodiments, the block 10T may include multiple memory blocks 10B. As shown in FIG1B , the sub-block 10T1 and the sub-block 10T2 each include memory blocks 10B1, 10B2, 10B3, 10B4 and memory blocks 10B5, 10B6, 10B7, 10B8, but the present disclosure is not limited thereto. That is, the three-dimensional memory 10 of the present embodiment may also include multiple memory blocks not shown in FIG1B .

In some embodiments, one of the memory blocks 10B may include a stacking structure SS and a plurality of vertical channel structures VC, wherein the memory blocks 10B may be defined by a plurality of separation structures ST, but the present disclosure is not limited thereto.

The plurality of partition structures ST are, for example, disposed on the substrate SB. In some embodiments, the plurality of partition structures ST may extend in the second direction d2 and may be used to define a plurality of memory blocks 10B of the three-dimensional memory 10. For example, as shown in FIG. 1C , in this embodiment, two adjacent partition structures ST may be used to define a memory block 10B1 and a memory block 10B5, but the present disclosure is not limited thereto.

The stacking structure SS may include a plurality of word lines WL and a plurality of insulating layers IL stacked alternately in sequence in a normal direction d3 of the substrate SB. For example, as shown in FIG. 1A and FIG. 1D , the stacking structure SS in the three-dimensional memory 10 of the present embodiment may include 32 word lines WL0, WL1, WL2, ... WLn ...., WL30, WL31 and 32 insulating layers, but the present disclosure is not limited thereto. The plurality of word lines WL may, for example, each extend on a plane defined by a first direction d1 and a second direction d2, wherein the first direction d1 is, for example, orthogonal to the second direction d2, and the first direction d1 and the second direction d2 are, for example, orthogonal to the normal direction d3 of the substrate SB. In the present embodiment, the word lines WL0-WL31 may have lengths in the second direction d2 that are gradually smaller in the normal direction d3 of the substrate SB, so that the plurality of word lines WL may be formed into a staircase structure having an array region AR and a staircase region SR. In some embodiments, the material of the plurality of word lines WL may include a suitable conductive material. For example, the material of the plurality of word lines WL may include tungsten, but the present disclosure is not limited thereto.

The corresponding word lines in the plurality of word lines WL may each be regarded as a layer of memory cell pages. In the present embodiment, a sector in the memory block 10B may include a layer of memory cell pages. Referring to FIG. 1B and FIG. 1D , each of the plurality of memory blocks 10B includes 32 sectors. Therefore, the sub-block 10T1 (including memory blocks 10B1, 10B2, 10B3, 10B4) and the sub-block 10T2 (including memory blocks 10B5, 10B6, 10B7, 10B8) may each include 128 sectors; however, the present disclosure is not limited thereto.

A plurality of vertical channel structures VC are, for example, disposed on a substrate SB, wherein each of the plurality of vertical channel structures VC extends, for example, in a normal direction d3 of the substrate SB. In some embodiments, the plurality of vertical channel structures VC are disposed in an array area AR of the substrate SB and penetrate the stacking structure SS in a normal direction d3 of the substrate SB. One of the plurality of vertical channel structures VC, for example, includes a cell string, wherein each memory cell in a memory cell string is electrically connected to a corresponding word line, but the present disclosure is not limited thereto. In the present embodiment, each of the plurality of vertical channel structures VC may include a channel layer CH, an insulating column IC, a source column SC, a drain column DC, a filling layer FL, and a charge trapping layer CTL, but the present disclosure is not limited thereto.

The channel layer CH has a ring-shaped structure in the normal direction d3 of the substrate SB, for example. In some embodiments, the channel layer CH may include a suitable semiconductor material. For example, the material of the channel layer CH may include polysilicon, but the present disclosure is not limited thereto.

The insulating column IC is, for example, surrounded by the channel layer CH, that is, the insulating column IC is, for example, disposed inside the channel layer CH and, for example, extends in the normal direction d3 of the substrate SB. In some embodiments, the material of the insulating column IC may include a suitable dielectric material. For example, the material of the insulating column IC may include silicon oxide, but the present disclosure is not limited thereto.

The source column SC and the drain column DC are also, for example, surrounded by the channel layer CH, that is, the source column SC and the drain column DC are, for example, disposed inside the channel layer CH, and, for example, each extend in the normal direction d3 of the substrate SB. In some embodiments, the source column SC and the drain column DC may each include a suitable semiconductor material. For example, the material of the source column SC and the drain column DC may include polysilicon or other metal materials, but the present disclosure is not limited thereto.

The filling layer FL is, for example, surrounded by the channel layer CH and is, for example, used to fill the interior of the channel layer CH. Specifically, the filling layer FL can be used to fill the area in the interior of the channel layer CH where the above-mentioned components are not provided, for example, as a support, but the present disclosure is not limited thereto. In some embodiments, the material of the filling layer FL may include a suitable dielectric material. For example, the material of the filling layer FL may include silicon oxide, but the present disclosure is not limited thereto.

The charge trapping layer CTL is, for example, disposed around the channel layer CH, and may be, for example, an external structure of the vertical channel structure VC. In some embodiments, the charge trapping layer CTL may include a composite structure. In the present embodiment, the charge trapping layer CTL may include three dielectric layers sequentially stacked on the side surface of the channel layer CH. For example, the charge trapping layer CTL may include a composite layer of oxide-nitride-oxide (ONO), but the present disclosure is not limited thereto. In other embodiments, the charge trapping layer CTL may include a composite layer of oxide-nitride-oxide-nitride-oxide (ONONO) or a composite layer including other structures.

Based on this, the memory cell can be defined by a vertical channel structure VC surrounded by a layer of word lines WL. For example, the memory cell MC shown in Figure 1D is defined by a vertical channel structure VC surrounded by word line WL0, but the present invention is not limited to this. In some embodiments, the memory cell can perform 1-bit operation or 2-bit operation through different operation methods. For example, when a voltage is applied to the source column SC and the drain column DC, since the source column SC and the drain column DC are electrically connected to the channel layer CH, electrons can be transmitted along the channel layer CH and stored in the charge capture layer CTL, so that a 1-bit operation can be performed on the memory cell. In addition, for the operation using Fowler-Nordheim tunneling, electrons or holes can be trapped in the charge trapping layer CTL between the source column SC and the drain column DC. For the operation using source side injection, channel-hot-electron injection or band-to-band tunneling hot carrier injection, electrons or holes can be locally trapped in the charge trapping layer CTL of one of two adjacent source columns SC and drain columns DC, so that single-bit cell (SLC; 1 bit) or multi-bit cell (MLC; greater than or equal to 2 bits) operation can be performed, but the present disclosure is not limited thereto.

In this embodiment, one of the memory blocks 10B may include at least two rows of vertical channel structures VC. For example, one of the memory blocks 10B1 and 10B2 includes two rows of vertical channel structures VC, wherein the vertical channel structures VC are arranged alternately in the second direction d2. In detail, taking the memory block 10B1 shown in FIG. 1C as an example, the memory block 10B1 includes a first row of vertical channel structures VC1 and a second row of vertical channel structures VC2, wherein the first row of vertical channel structures VC1 includes vertical channel structures VC11, VC12, VC13, and VC14 arranged along the second direction d2, and the second row of vertical channel structures VC2 includes vertical channel structures VC21, VC22, VC23, and VC24 arranged along the second direction d2, and the vertical channel structure VC11, vertical channel structure VC21, vertical channel structure VC12, vertical channel structure VC22, vertical channel structure VC13, vertical channel structure VC23, vertical channel structure VC14, and vertical channel structure VC24 are, for example, arranged alternately in this order in the second direction d2.

In this embodiment, the three-dimensional memory 10 further includes a bit line transistor structure BLTS, a source line transistor structure SLTS, a plurality of regional bit lines LBL, a plurality of regional source lines LSL, a conductive pattern TMP, a word line decoder XDEC, a control logic CL, a global bit line GBL, and a global source line GSL.

The bit line transistor structure BLTS is, for example, disposed on the substrate SB. In some embodiments, the bit line transistor structure BLTS may include a plurality of bit line transistors BLT (e.g., the bit line transistors BLT1 and BLT2 shown in FIG. 1A and the bit line transistors BLT1, BLT2, BLT3, BLT4, BLT5, BLT6, BLT7, and BLT8 shown in FIG. 1D). In this embodiment, the bit line transistor structure BLTS includes a first bit line transistor structure BLTS1 and a second bit line transistor structure BLTS2, wherein the first bit line transistor structure BLTS1 is disposed in the first region SB1 and disposed between the sub-block 10T1 and the sub-block 10T2, and the second bit line transistor structure BLTS2 is disposed in the second region SB2 and also disposed between the sub-block 10T1 and the sub-block 10T2. 1D, in this embodiment, the first bit line transistor structure BLTS1 may include 8 bit line transistors BLT1-BLT8. In addition, although not shown in FIG. 1D, the second bit line transistor structure BLTS2 may also include 8 bit line transistors, that is, the bit line transistor structure BLTS may include 16 bit line transistors, but the present disclosure is not limited thereto.

In this embodiment, as shown in FIG. 1B and FIG. 1D , the first bit line transistor structure BLTS1 can drive 128 segments in the sub-block 10T1 , and the second bit line transistor structure BLTS2 can drive 128 segments in the sub-block 10T2 , but the present disclosure is not limited thereto.

In this embodiment, taking the second bit line transistor structure BLTS2 as an example, as shown in FIG. 1A , the second bit line transistor structure BLTS2 can be electrically connected to a regional bit line LBL to be introduced later through a via window VB1, and can be electrically connected to a global bit line GBL to be introduced later through a via window VB2, which will be described in detail in the following embodiments.

The source line transistor structure SLTS is, for example, disposed on the substrate SB. In some embodiments, the source line transistor structure SLTS may include a plurality of source line transistors SLT (e.g., source line transistors SLT1, SLT2, SLT3, SLT4, SLT5, SLT6, SLT7, SLT8 shown in FIG. 1D ). In the present embodiment, the source line transistor structure SLTS is disposed on a side of the sub-block 10T1 that is far from the sub-block 10T2, but the present disclosure is not limited thereto.

In this embodiment, the source line transistor structure SLTS can be electrically connected to a regional source line LSL to be introduced later through a via VS, and can be electrically connected to a global source line GSL (as shown in FIG. 1D ) through another via (not shown), which will be described in detail in the following embodiments.

The plurality of regional bit lines LBL are, for example, disposed on the substrate SB and may extend, for example, in the first direction d1. In some embodiments, the plurality of regional bit lines LBL are each disposed on a corresponding vertical channel structure VC. It is worth noting that, in the present embodiment, the corresponding regional bit line LBL may be electrically connected to a drain column DC in the corresponding vertical channel structure VC through a plug PD. In some embodiments, the material of the plurality of regional bit lines LBL may be the same as or similar to the material of the plurality of word lines WL.

In this embodiment, the plurality of regional bit lines LBL include a first group of regional bit lines LBL1 and a second group of regional bit lines LBL2, wherein the first group of regional bit lines LBL1 is disposed in the first region SB1 and electrically connected to the first bit line transistor structure BLTS1, and the second group of regional bit lines LBL2 is disposed in the second region SB2 and electrically connected to the second bit line transistor structure BLTS2.

In the present embodiment, the first group of regional bit lines LBL1 and the second group of regional bit lines LBL2 are separated from each other in the first direction d1, but the present disclosure is not limited thereto. In other embodiments, the regional bit lines in the first group of regional bit lines LBL1 may be connected to the corresponding regional bit lines in the second group of regional bit lines LBL2 in the first direction d1, but the present disclosure is not limited thereto.

In the present embodiment, the regional bit lines in the first group of regional bit lines LBL1 and the regional bit lines in the second group of regional bit lines LBL2 are arranged corresponding to each other in the first direction d1. In detail, referring to FIG. 1C , in some embodiments, the first group of regional bit lines LBL1 may include regional bit lines LBL10, regional bit lines LBL11, regional bit lines LBL12, regional bit lines LBL13, regional bit lines LBL14, regional bit lines LBL15, regional bit lines LBL16, and regional bit lines LBL17, and the second group of regional bit lines LBL2 may include regional bit lines LBL20, regional bit lines LBL21, regional bit lines LBL22, and regional bit lines LBL23. L22, regional bit line LBL23, regional bit line LBL24, regional bit line LBL25, regional bit line LBL26 and regional bit line LBL27, wherein the regional bit line LBL10 and the regional bit line LBL20 are on the same straight line extending along the first direction d1 and are separated from each other, and the regional bit line LBL11 and the regional bit line LBL21 are on the same straight line extending along the first direction d1 and are separated from each other, and so on, which will not be repeated here.

A plurality of regional source lines LSL are, for example, disposed on the substrate SB, and may, for example, each extend in the first direction d1. In some embodiments, and a plurality of regional source lines LSL are each disposed on a corresponding vertical channel structure VC. It is worth noting that, in the present embodiment, the corresponding regional source line LSL may be electrically connected to a source column SC in the corresponding vertical channel structure VC through a plug PS. In some embodiments, the material of the plurality of regional source lines LSL may be the same as or similar to the material of the plurality of word lines WL.

The conductive pattern TMP is, for example, disposed on the substrate SB. From another perspective, the conductive pattern TMP, the plurality of regional bit lines LBL, and the plurality of regional source lines LSL are all part of the first upper conductive layer TM1, wherein the conductive pattern TMP, the plurality of regional bit lines LBL, and the plurality of regional source lines LSL are separated from each other. The conductive pattern TMP can be, for example, electrically connected to the global bit line GBL through the via window TV, so as to, for example, enable the plurality of regional bit lines LBL to be electrically connected to the global bit line GBL through the bit line transistor structure BLTS. That is, the plurality of regional bit lines LBL and the global bit line GBL can be electrically connected to each other through the via window VB1, the bit line transistor structure BLTS, the via window VB2, the conductive pattern TMP, and the via window TV.

In this embodiment, in order to allow the conductive pattern TMP to have a sufficient spatial arrangement, in addition to separating the first group of regional bit lines LBL1 and the second group of regional bit lines LBL2 from each other in the first direction d1, the plurality of regional bit lines LBL and the plurality of regional source lines LSL have the following design: two adjacent regional bit lines LBL are arranged between two adjacent regional source lines LSL.

In detail, referring to FIG. 1C , in some embodiments, the plurality of regional source lines LSL may each include a regional source line LSL0, a regional source line LSL1, a regional source line LSL2, a regional source line LSL3, a regional source line LSL4, a regional source line LSL5, a regional source line LSL6, and a regional source line LSL7. Taking the first group of regional bit lines LBL1 located in the first block SB1 as an example, two adjacent regional bit lines LBL10 and LBL11 are arranged between two adjacent regional source lines LSL0 and LSL1, two adjacent regional bit lines LBL12 and LBL13 are arranged between two adjacent regional source lines LSL2 and LSL3, two adjacent regional bit lines LBL14 and LBL15 are arranged between two adjacent regional source lines LSL4 and LSL5, and two adjacent regional bit lines LBL16 and LBL17 are arranged between two adjacent regional source lines LSL6 and LSL7. It is worth noting that the relationship between the second group of regional bit lines LBL2 and the regional source lines LSL in the second region SB2 is similar to the above-mentioned embodiment and will not be described in detail here. It is worth noting that since two adjacent regional bit lines LBL are arranged between two adjacent regional source lines LSL, the arrangement relationship between the source pillars SC and the drain pillars DC in the first column vertical channel structure VC1 and the second column vertical channel structure VC2 is opposite, as shown in FIG. 1C .

Through the above configuration, the conductive pattern TMP can be disposed between the first group of regional bit lines LBL1 and the second group of regional bit lines LBL2 that are separated from each other in the first direction d1, and can be disposed between two adjacent regional source lines LSL in the second direction d2. Based on this, the conductive pattern TMP can be used to electrically connect the first group of regional bit lines LBL1 and the second group of regional bit lines LBL2 to the global bit line GBL.

Specifically, referring to FIG. 1A and FIG. 1B , in some embodiments, taking the second group of regional bit lines LBL2 as an example, the conductive pattern TMP can be electrically connected to the global bit line GBL through the via window TV, and can be electrically connected to the second group of regional bit lines LBL2 through the via window VB2. Based on this, the second group of regional bit lines LBL2 can be electrically connected to the global bit line GBL through the setting of the conductive pattern TMP. That is, the second group of regional bit lines LBL2 and the global bit line GBL can be electrically connected to each other through the path of the via window VB1, the bit line transistor structure BLTS, the via window VB2, the conductive pattern TMP, and the via window TV. It is worth noting that the manner in which the first group of local bit lines LBL1 located in the first region SB1 is electrically connected to the global bit lines GBL through the conductive pattern TMP is similar to the above-mentioned embodiment and will not be described in detail herein.

The word line decoder XDEC is, for example, disposed on the substrate SB. In the present embodiment, the word line decoder XDEC includes a plurality of transistors (not shown), and is disposed between the stack structure SS and the substrate SB in the normal direction d3 of the substrate SB. The plurality of transistors included in the word line decoder XDEC may be, for example, complementary metal oxide semiconductor field effect transistors (CMOS). Therefore, this architecture may be referred to as a complementary metal oxide semiconductor field effect transistor under array (CMOS under array; CUA) architecture. In some embodiments, the plurality of transistors in the word line decoder XDEC may be electrically connected to a plurality of word lines WL to control the corresponding word lines WL. In detail, the word line decoder XDEC may be electrically connected to the corresponding memory cells via the word lines WL. In some embodiments, the word line decoder XDEC is configured to operate under the control of the control logic CL to be described later. For example, the word line decoder XDEC can receive word line address data from the outside through the control logic CL. The word line decoder XDEC can be used, for example, to decode the word line address to apply a voltage provided from a voltage generator (not shown) to the corresponding word line WL according to the decoded word line address.

In this embodiment, the word line decoder XDEC includes a word line decoder XDEC1 and a word line decoder XDEC2, wherein the word line decoder XDEC1 and the word line decoder XDEC2 can be electrically connected to a plurality of word lines WL in the sub-blocks 10T1 and 10T2 respectively.

The control logic CL is, for example, disposed on the substrate SB and, for example, electrically connected to the word line decoder XDEC. In some embodiments, the control logic CL may receive commands and address data from a controller (not shown), and control the word line decoder XDEC and other components not shown in response to corresponding commands. In addition, the control logic CL sends the above-mentioned word line address data to the word line decoder XDEC.

The global bit line GBL is, for example, disposed on the substrate SB. In the present embodiment, the global bit line GBL is electrically connected to the plurality of regional bit lines LBL, wherein the manner in which the global bit line GBL is electrically connected to the plurality of regional bit lines LBL may refer to the aforementioned embodiment, which will not be described in detail herein. In some embodiments, the material of the global bit line GBL may be the same as or similar to the material of the plurality of word lines WL. Please refer to FIG. 1D , in the present embodiment, the global bit line GBL may be electrically connected to the bit line transistor structure BLTS including 16 bit line transistors.

In some embodiments, as shown in FIG. 1D , the three-dimensional memory 10 may further include a global source line GSL. The global source line GSL is, for example, disposed on a substrate SB. In this embodiment, the global source line GSL is electrically connected to a plurality of regional source lines LSL, wherein the manner in which the global source line GSL is electrically connected to the plurality of regional source lines LSL may refer to the aforementioned embodiments, and will not be described in detail herein. In some embodiments, the material of the global bit line GBL may be the same or similar to the material of the plurality of word lines WL.

From another perspective, the global bit line GBL and the global source line GSL are part of the second upper conductive layer TM2, but the present disclosure is not limited thereto.

In some embodiments, the three-dimensional memory 10 may further include a peripheral circuit PC. The peripheral circuit PC may, for example, include a sense amplifier SA and a page buffer PB, wherein the sense amplifier SA and the page buffer PB are disposed on a substrate SB, but the present disclosure is not limited thereto. The sense amplifier SA is, for example, electrically connected to a global bit line GBL, and may, for example, be electrically connected to a block 10T through the global bit line GBL. In some embodiments, the sense amplifier SA may include a current-to-voltage converter (not shown) and an amplifier circuit (not shown). The current-to-voltage converter may, for example, be used to convert a current signal read from a memory cell of the block 10T into a voltage signal, and the amplifier circuit may, for example, be used to generate read data according to the voltage signal provided by the current-to-voltage converter. The page buffer PB is, for example, electrically connected to the sense amplifier SA, and may be, for example, electrically connected to the regional bit line LBL and the block 10T through the global bit line GBL. In some embodiments, the page buffer PB may include a plurality of page buffer units (not shown) each connected to the corresponding regional bit line LBL, and operates under the control of the control logic CL. For example, during a read operation, the page buffer PB reads data of a memory cell connected to a selected word line through the corresponding regional bit line LBL, and the data may be processed by the sense amplifier SA and output to an external host device through a data input/output unit (not shown) coupled to the page buffer PB.

In some embodiments, the three-dimensional memory 10 may further include a lower conductive layer LM. Referring to FIG. 1B , the lower conductive layer LM is disposed between the stacked structure SS and the word line decoder XDEC in the normal direction d3 of the substrate SB, and includes, for example, a plurality of conductive lines extending along the first direction d1. Therefore, in this embodiment, the stacked structure SS located in the first area SB1 and the stacked structure SS located in the second area SB2 may be electrically connected to the corresponding word line decoder XDEC through the arrangement of the lower conductive layer LM.

In general, in this embodiment, the block 10T included in the three-dimensional memory 10 is divided into a sub-block 10T1 disposed in the first area SB1 and a sub-block 10T2 disposed in the second area SB2 in the first direction d1, and a plurality of local bit lines LBL are also divided into a first group of local bit lines LBL1 and a second group of local bit lines LBL2 in the first direction d1, wherein the first group of local bit lines LBL1 and the second group of local bit lines LBL2 are connected to each other. The first bit line transistor structure BLTS1 and the vertical channel structure VC in the memory blocks 10B1, 10B2, 10B3, and 10B4 in the sub-block 10T1 are electrically connected, and the second set of regional bit lines LBL2 and the second bit line transistor structure BLTS2 and the vertical channel structure VC in the memory blocks 10B5, 10B6, 10B7, and 10B8 in the sub-block 10T2 are electrically connected.

Based on this, the segment that needs to be driven by each bit line transistor structure (i.e., the first bit line transistor structure BLTS1 and the second bit line transistor structure BLTS2) is reduced and the length of the plurality of regional bit lines LBL can be relatively short, thereby reducing the bit line capacitance (CBL) and the background leakage current, thereby improving the operation speed (e.g., reading speed) of the three-dimensional memory 10. In the present embodiment, the bit line capacitance and/or the background leakage current on the plurality of regional bit lines LBL in the three-dimensional memory 10 can be halved relative to the bit line capacitance and/or the background leakage current on the regional bit lines in the three-dimensional memory (blocks are not divided) of the prior art, but the present disclosure is not limited thereto.

Furthermore, by setting the conductive pattern TMP, the first group of regional bit lines LBL1 and the second group of regional bit lines LBL2 can be electrically connected to the global bit lines GBL respectively, so as to realize the design of the three-dimensional memory 10 of this embodiment.

Fig. 2 is a partial schematic diagram of another embodiment of the three-dimensional memory of Fig. 1B. It should be noted that the embodiment of Fig. 2 can respectively use the component numbers and partial contents of the embodiments of Fig. 1A to Fig. 1D, wherein the same or similar numbers are used to represent the same or similar components, and the description of the same technical contents is omitted.

2 , in the present embodiment, the first upper conductive layer TM1′ further includes a third group of regional bit lines LBL3, wherein the third group of regional bit lines LBL3 extends along the first direction d1 and crosses the first region SB1 and the second region SB2. Specifically, the third group of regional bit lines LBL3 is not cut off and has a length longer than the first group of regional bit lines LBL1 and the second group of regional bit lines LBL2. In some embodiments, the third group of regional bit lines LBL3 may be electrically connected to the first bit line transistor structure BLTS1 or the second bit line transistor structure BLTS2.

In the present embodiment, two adjacent regional bit lines in the third group of regional bit lines LBL3 are also disposed between two adjacent regional source lines. In detail, referring to FIG. 2 , in some embodiments, the third group of regional bit lines LBL3 may each include a regional bit line LBL30, a regional bit line LBL31, a regional bit line LBL32, and a regional bit line LBL33. The two adjacent regional bit lines LBL30 and LBL31 are disposed between two adjacent regional source lines LSL1 and LSL2, and the two adjacent regional bit lines LBL32 and LBL33 are disposed between two adjacent regional source lines LSL6 and LSL7.

In some embodiments, a pitch p _GBL between adjacent global bit lines GBL in the second direction d2 may be the same as a pitch p _TMP between adjacent conductive patterns TMP in the second direction d2, so that the global bit lines GBL may be electrically connected to the conductive pattern TMP through the via TV. For example, the pitch p _GBL between adjacent global bit lines GBL in the second direction d2 may be 0.64 micrometers, and the pitch p _TMP between adjacent conductive patterns TMP in the second direction d2 may be 0.64 micrometers, but the present disclosure is not limited thereto.

Please continue to refer to FIG. 2 . In the present embodiment, the regional source line LSL adjacent to the conductive pattern TMP includes an opening F, wherein the opening F faces the conductive pattern TMP. Specifically, the regional source lines LSL0, LSL1, LSL4, and LSL5 adjacent to the conductive pattern TMP each include an opening F, wherein the opening F faces and corresponds to the conductive pattern TMP in the second direction d2. The center line of the opening F may, for example, pass through the center of the conductive pattern TMP. In the present embodiment, the center line of the opening F is parallel to the second direction d2, but the present disclosure is not limited thereto. By designing the regional source line LSL with the opening F, it is possible, for example, to make the conductive pattern TMP formed by the exposure process have a more complete pattern.

Fig. 3 is a partial schematic diagram of another embodiment of the three-dimensional memory of Fig. 1B. It should be noted that the embodiment of Fig. 3 can use the component numbers and part of the content of the embodiment of Fig. 2, wherein the same or similar numbers are used to represent the same or similar components, and the description of the same technical content is omitted.

3 , in this embodiment, the regional source line LSL adjacent to the conductive pattern TMP includes an opening F, wherein the opening F faces the conductive pattern TMP. The features of the opening F can be referred to in the above embodiments, and will not be described in detail here.

In this embodiment, a gap O is provided between one of the first group of regional bit lines LBL1 not adjacent to the conductive pattern TMP and a corresponding one of the second group of regional bit lines LBL2 in the first direction d1, and the opening F included in the regional source line LSL may correspond to the gap O. In detail, referring to FIG. 1B and FIG. 3 , the first group of regional bit lines LBL1 not adjacent to the conductive pattern TMP includes regional bit lines LBL12, LBL13, LBL16, and LBL17, and the first group of regional bit lines LBL2 not adjacent to the conductive pattern TMP includes regional bit lines LBL22, LBL23, LBL26, and LBL27, wherein a gap O is provided between the regional bit line LBL12 and the regional bit line LBL22, between the regional bit line LBL13 and the regional bit line LBL23, between the regional bit line LBL16 and the regional bit line LBL26, and between the regional bit line LBL17 and the regional bit line LBL27. The opening F included in the regional source line LSL may correspond to the above-mentioned gap O in the second direction d2.

In some embodiments, the width d _F of the opening F in the first direction d1 may be substantially the same as the dimension d _O of the gap O in the first direction d1, but the present disclosure is not limited thereto.

In summary, the present disclosure can realize the design of the three-dimensional memory of the present embodiment by forming a conductive pattern in the first upper conductive layer. In detail, the three-dimensional memory of an embodiment of the present disclosure includes a block divided into a first sub-block disposed in a first region and a second sub-block disposed in a second region, and a plurality of regional bit lines divided into a first group of regional bit lines and a second group of regional bit lines, wherein the first group of regional bit lines is electrically connected to a first bit line transistor structure and a corresponding vertical channel structure in the first sub-block, and the second group of regional bit lines is electrically connected to a second bit line transistor structure and a corresponding vertical channel structure in the second sub-block. Based on this, the segment that needs to be driven in each bit line transistor structure can be reduced and the regional bit line can have a relatively short length, which can reduce the bit line capacitance and background leakage current, thereby improving the operating speed of the three-dimensional memory of an embodiment of the present disclosure.

10: Three-dimensional memory 10B, 10B1, 10B2, 10B3, 10B4, 10B5, 10B6, 10B7, 10B8: Memory block 10T: Block 10T1, 10T2: Sub-block AR: Array area BLT1, BLT2, BLT3, BLT4, BLT5, BLT6, BLT7, BLT8: Bit line transistor BLTS: Bit line transistor structure BLTS1: First bit line transistor structure BLTS2: Second bit line transistor structure CH: Channel layer CL: Control logic CT: Charge trap layer DC: Drain column FL: Filling layer GBL: Global bit line GSL: Global Source Line IC: Insulation Pillar IL: Insulation Layer LBL, LBL10, LBL11, LBL12, LBL13, LBL14, LBL15, LBL16, LBL17, LBL20, LBL21, LBL22, LBL23, LBL24, LBL25, LBL26, LBL27, LBL30, LBL31, LBL32, LBL33: Regional Bit Lines LBL1: First Group of Regional Bit Lines LBL2: Second Group of Regional Bit Lines LBL3: Third Group of Regional Bit Lines LM: Lower Conductive Layer LSL, LSL0, LSL1, LSL2, LSL3, LSL4, LSL5, LSL6, LSL7: Regional Source Lines MC: Memory Cells PB: Page buffer PC: Peripheral circuit PD, PS: Plug SA: Sense amplifier SB: Substrate SB1: First area SB2: Second area SC: Source column SLT1, SLT2, SLT3, SLT4, SLT5, SLT6, SLT7, SLT8: Source line transistor SLTS: Source line transistor structure SR: Step region SS: Stacking structure ST: Separation structure TM1: First upper conductive layer TM2: Second upper conductive layer TMP: Conductive pattern TV, VB1, VB2: Interlayer window VC, VC1, VC2, VC11, VC12, VC13, VC14, VC21, VC22, VC23, VC24: Vertical channel structure WL, WL0, WL1, WL2, WL30, WL31, WLn: character line XDEC, XDEC1, XDEC2: character line decoder d1: first direction d2: second direction d3: normal direction of base

FIG. 1A is a partial three-dimensional schematic diagram of a three-dimensional memory of an embodiment of the present disclosure. FIG. 1B is a top view schematic diagram of a three-dimensional memory of an embodiment of the present disclosure. FIG. 1C is a partial schematic diagram of an embodiment of the three-dimensional memory of FIG. 1B. FIG. 1D is a circuit diagram of a three-dimensional memory of an embodiment of the present disclosure. FIG. 2 is a partial schematic diagram of another embodiment of the three-dimensional memory of FIG. 1B. FIG. 3 is a partial schematic diagram of yet another embodiment of the three-dimensional memory of FIG. 1B.

10: Three-dimensional memory

BLT1, BLT2: bit line transistors

BLTS: Bit Line Transistor Structure

BLTS1: First bit line transistor structure

BLTS2: Second bit line transistor structure

CL: Control Logic

GBL: Global Bit Line

IL: Insulating layer

LBL, LBL1, LBL2, LBL10, LBL11, LBL20, LBL21: Regional bit lines

LBL1: The first set of regional bit lines

LBL2: The second set of regional bit lines

LSL, LSL0, LSL1: Regional source line

PB: Page Buffer

PC: Peripheral circuit

SA: Sense Amplifier

SLTS: Source Line Transistor Structure

SS: stack structure

TM1: first upper conductive layer

TMP: Conductive pattern

TV, VB1, VB2, VS: interlayer window

WL: character line

XDEC, XDEC1, XDEC2: character line decoder

d1: first direction

d2: second direction

d3: normal direction of the base

Claims (20)

A three-dimensional memory comprises: a plurality of blocks disposed on a substrate, wherein one of the plurality of blocks comprises a first sub-block disposed in a first region of the substrate and a second sub-block disposed in a second region of the substrate; a bit line transistor structure disposed on the substrate and located between the first sub-block and the second sub-block, comprising a first bit line transistor structure disposed in the first region and a second bit line transistor structure disposed in the second region; a first upper conductive layer disposed on the substrate, comprising: a plurality of regional bit lines extending along a first direction and comprising a first group of regional bit lines and a second group of regional bit lines, wherein the first group The regional bit lines and the second group of regional bit lines are separated from each other in the first direction; a plurality of regional source lines extending along the first direction, wherein two adjacent regional bit lines among the plurality of regional bit lines are arranged between two adjacent regional source lines; and a conductive pattern arranged between the first group of regional bit lines and the second group of regional bit lines in the first direction, and arranged between the two adjacent regional source lines in the second direction; and a second upper conductive layer arranged on the first upper conductive layer, comprising: a global bit line electrically connected to the first group of regional bit lines and the second group of regional bit lines through the conductive pattern. A three-dimensional memory as described in claim 1, wherein a via window is provided between the first upper conductive layer and the second upper conductive layer, and the global bit line is electrically connected to the conductive pattern through the via window. A three-dimensional memory as described in claim 1, wherein the plurality of regional bit lines further include a third group of regional bit lines, and the third group of regional bit lines spans the first region and the second region. A three-dimensional memory as described in claim 1, wherein the first sub-block and the second sub-block each include multiple memory blocks, and one of the multiple memory blocks includes a stacking structure and multiple vertical channel structures penetrating the stacking structure in the normal direction of the substrate. A three-dimensional memory as described in claim 4, wherein the stacking structure includes a plurality of word lines and a plurality of insulating layers stacked alternately in sequence in the normal direction of the substrate. A three-dimensional memory as described in claim 4, wherein one of the plurality of vertical channel structures comprises: a channel layer having a ring-shaped structure in the normal direction of the substrate; an insulating column disposed inside the channel layer; a source column and a drain column disposed inside the channel layer; a filling layer filling the inside of the channel layer; and a charge trapping layer surrounding the channel layer. A three-dimensional memory as described in claim 6, wherein the plurality of vertical channel structures include a first column of vertical channel structures and a second column of vertical channel structures, and the first column of vertical channel structures and the second column of vertical channel structures are arranged alternately in the second direction. A three-dimensional memory as described in claim 7, wherein the arrangement relationship between the source column and the drain column in the first column vertical channel structure and the second column vertical channel structure is opposite. A three-dimensional memory as described in claim 6, wherein the plurality of regional bit lines are electrically connected to the corresponding drain pillars through a first plug, and the plurality of regional source lines are electrically connected to the corresponding source pillars through a second plug. A three-dimensional memory as described in claim 1, wherein the second upper conductive layer further includes a global source line, and the global source line is electrically connected to the multiple regional source lines. The three-dimensional memory as described in claim 10 further includes a source line transistor structure, wherein the source line transistor structure is disposed on the substrate and is located on a side of the first sub-block away from the second sub-block, wherein the source line transistor structure is electrically connected to the global source line and the plurality of regional source lines. The three-dimensional memory as described in claim 4 further comprises: a word line decoder disposed between the stacking structure and the substrate in the normal direction of the substrate and electrically connected to the plurality of word lines; and a control logic disposed on the substrate and electrically connected to the word line decoder. The three-dimensional memory as described in claim 12 further includes a lower conductive layer, wherein the lower conductive layer is disposed between the stacking structure and the word line decoder in the normal direction of the substrate, and the stacking structure is electrically connected to the word line decoder through the lower conductive layer. The three-dimensional memory as described in claim 4 further comprises: a sense amplifier disposed on the substrate and electrically connected to the global bit line; and a page buffer disposed on the substrate and electrically connected to the sense amplifier. A three-dimensional memory as described in claim 1, wherein the pitch between the adjacent global bit lines in the second direction is the same as the pitch between the adjacent conductive patterns in the second direction. A three-dimensional memory as described in claim 1, wherein the regional source line adjacent to the conductive pattern includes an opening, and the opening faces the conductive pattern. A three-dimensional memory as described in claim 16, wherein the center line of the opening passes through the center of the conductive pattern, and the center line is parallel to the second direction. A three-dimensional memory as described in claim 16, wherein there is a gap in the first direction between one of the first set of regional bit lines that is not adjacent to the conductive pattern and a corresponding one of the second set of regional bit lines. A three-dimensional memory as described in claim 18, wherein the opening corresponds to the gap in the second direction. A three-dimensional memory as described in claim 18, wherein the width of the opening in the first direction is the same as the size of the gap in the first direction.