TWI738311B - Display driving circuit and driving method - Google Patents

Abstract

The present disclosure relates to a display driving circuit including a pixel circuit, a logic circuit, a temporary storage circuit, and a receiving circuit. The logic circuit is electrically connected to the pixel circuit. The logic circuit includes a first control terminal and a second control terminal. The first control terminal is configured to receive a clock signal. The temporary storage circuit is configured to output a data signal according to the clock signal. An output terminal of the temporary storage circuit is electrically connected to the second control terminal. The receiving circuit is electrically connected to the output terminal of the temporary storage circuit, and is configured to output the data signal received from the temporary storage circuit to the logic circuit. The logic circuit selectively transmits the data signal from the receiving circuit to the pixel circuit according to the signals received by the first control terminal and the second control terminal.

Description

Display driving circuit and driving method

The present disclosure relates to a display driving circuit and a driving method, especially a technology for transmitting data signals to a pixel circuit to generate expected brightness.

Flat display devices have become the mainstream of various display devices. For example, household televisions, personal computers and laptop computer monitors, mobile phones and digital cameras, etc., are all products that use a large number of flat-panel display devices. In flat-panel display devices, the light-emitting elements and their driving circuits are often packaged in the form of chiplets, making the overall structure more streamlined.

One aspect of the present disclosure relates to a display driving circuit, including a logic circuit, a temporary storage circuit, and a receiving circuit. The logic circuit is electrically connected to the pixel circuit. The logic circuit includes a first control terminal and a second control terminal. The first control terminal is used for receiving a clock signal. The temporary storage circuit is used for outputting the data signal according to the clock signal. The output terminal of the temporary storage circuit is electrically connected to the second control terminal. The receiving circuit is electrically connected to the output terminal of the temporary storage circuit, and is used for outputting the data signal received from the temporary storage circuit to the logic circuit. The logic circuit selectively transmits the data signal from the receiving circuit to the pixel circuit according to the signals received by the first control terminal and the second control terminal.

Another aspect of the present disclosure relates to a driving method including the following steps: receiving a clock signal through a logic circuit and a temporary storage circuit. Receive the data signal through the temporary storage circuit, and according to the clock signal, output the data signal to the logic circuit and the receiving circuit. The logic circuit selectively conducts the receiving circuit to the pixel circuit according to the data signal and the clock signal from the temporary storage circuit.

According to this, by selectively turning on the electrical connection between the receiving circuit and the pixel circuit through the logic circuit, the display driving circuit can be driven according to two signals such as the clock signal and the data signal, so that the external wiring of the display driving circuit is improved. streamline.

Hereinafter, a plurality of embodiments of the present invention will be disclosed in drawings. For clear description, many practical details will be described in the following description. However, it should be understood that these practical details should not be used to limit the present invention. That is to say, in some embodiments of the present invention, these practical details are unnecessary. In addition, in order to simplify the drawings, some conventionally used structures and elements are shown in the drawings in a simple and schematic manner.

In this text, when a component is referred to as “connected” or “coupled”, it can be referred to as “electrically connected” or “electrically coupled”. "Connected" or "coupled" can also be used to mean that two or more components cooperate or interact with each other. In addition, although terms such as “first”, “second”, etc. are used herein to describe different elements, the terms are only used to distinguish elements or operations described in the same technical terms. Unless the context clearly indicates, the terms do not specifically refer to or imply order or sequence, nor are they used to limit the present invention.

The present disclosure relates to a display driving circuit. Please refer to FIG. 1, which is a schematic diagram of the display device 200 to which the present disclosure is applied. In some embodiments, the display device 200 includes a display panel P, a display driving circuit 100 and a controller T. A pixel circuit 210 is provided on the display panel P, and the pixel circuit 210 includes a plurality of pixel units 211. Each pixel unit 211 includes a plurality of sub-pixel units 210R, 210G, and 210B. In some embodiments, the sub-pixel units 210R-210B are light-emitting diodes of different colors (eg, red, green, and blue light-emitting diodes arranged adjacently). The controller T transmits the data signal DATA to the display driving circuit 100, and the display driving circuit 100 drives the corresponding sub-pixel units in the pixel circuit 210 accordingly.

Please refer to FIGS. 1 and 2, which are schematic diagrams of the display driving circuit 100 according to some embodiments of the present disclosure. In some embodiments, the display driving circuit 100 is packaged in the form of a chiplet and disposed on the display panel P at a position corresponding to the pixel unit 211. The display driving circuit 100 includes a logic circuit 110, a temporary storage circuit 120 and a receiving circuit 130. The logic circuit 110 is electrically connected to the pixel circuit 210 and includes a first control terminal N1 and a second control terminal N2. The first control terminal N1 is used to receive the clock signal CLK from the controller T.

The temporary storage circuit 120 is used for receiving the clock signal CLK and the data signal from the controller T, and is triggered according to the pulse in the clock signal CLK to output the data signal DATA. The output terminal of the temporary storage circuit 120 is electrically connected to the second control terminal N2. That is, the second control terminal N2 of the logic circuit 110 receives the data signal DATA through the temporary storage circuit 120.

The receiving circuit 130 is electrically connected to the output terminal of the temporary storage circuit 120 and is used for outputting the data signal DATA received from the temporary storage circuit 120 to the logic circuit 110. The logic circuit 10 selectively transmits the data signal DATA from the receiving circuit 130 to the pixel circuit 210 according to the signals received by the first control terminal N1 and the second control terminal N2. The pixel circuit 210 can be driven according to the data signal DATA and the power supply voltage Vdd.

Please refer to FIG. 3, which is a schematic diagram of the clock signal CLK and the data signal DATA according to some embodiments of the present disclosure. In some embodiments, the data signal DATA is a digital signal including multiple pulses. For example: the data signal DATA sequentially includes the trigger signal OE and a plurality of data pulses P1~P9. Each data pulse P1~P9 is used to drive a different sub-pixel unit (for example, the data pulses P1~P3 respectively correspond to the sub-pixel unit 210R~210B). In addition, the receiving circuit 130 includes a plurality of cascade receiving registers 130R, 130G, and 130B for receiving data pulses corresponding to different sub-pixel units 210R-210B. After the data pulses in the data signal DATA are sequentially transferred to the logic circuit 110 through the receiving registers 130R~130B, the logic circuit 110 transfers the pulses in the data signal DATA to the sub-pixel units 210R~210B.

Please refer to Figures 4A~4D, which is a schematic diagram of the transmission method of the data signal DATA. In FIG. 4A, when the temporary storage circuit 120 is triggered by the clock signal CLK, it receives the first data pulse P1 in the data signal DATA. In FIG. 4B, when the temporary storage circuit 120 is triggered by the clock signal CLK again, the temporary storage circuit 120 receives the second data pulse P2 in the data signal DATA. At the same time, the temporary storage circuit 120 outputs the first data pulse P1 to the second control terminal N2 of the logic circuit 120 and the receiving register 130R in the receiving circuit 130.

In conclusion, in Figure 4C, when the temporary storage circuit 120 is triggered by the clock signal CLK again, the temporary storage circuit 120 receives the third data pulse P3 in the data signal DATA. At the same time, the register circuit 120 outputs the second data pulse P2 to the second control terminal N2 of the logic circuit 120 and the receiving register 130R in the receiving circuit 130. At this time, since the receiving register 130R will also be triggered by the clock signal CLK, the receiving register 130R will output the previously received first data pulse P1 to the receiving register 130G.

Similarly, in Figure 4D, when the temporary storage circuit 120 is triggered by the clock signal CLK again, the temporary storage circuit 120 will output the previously received third data pulse P3 to the second control terminal N2 of the logic circuit 120 and receive The receiving register 130R in the circuit 130. At this time, since the receiving register 130R and the receiving register 130G are also triggered by the clock signal CLK, the receiving register 130G will output the previously received first data pulse P1 to the receiving register 130B, and The receiving register 130R outputs the previously received second data pulse P2 to the receiving register 130G.

The display driving circuit 100 of the present disclosure only needs to receive two signals such as the clock signal CLK and the data signal DATA to drive the pixel circuit 210. Therefore, the wiring in the display device 200 can be reduced, thereby reducing the manufacturing process and packaging. Cost and improve the overall volume of the display device 200.

In some embodiments, during the period when the temporary storage circuit 120 outputs the data signal DATA to the receiving circuit 130, the logic circuit 110 turns off the electrical connection between the receiving circuit 130 and the pixel circuit 210. That is, the logic circuit 1410 does not transfer the data signal DATA from the receiving circuit 130 to the pixel circuit 210 at this time. After the temporary storage circuit 120 outputs all the pulses in the data signal DATA to the receiving circuit 130, the logic circuit 110 turns on the electrical connection between the receiving circuit 130 and the pixel circuit 210 to drive the pixel circuit 210 according to the data signal DATA.

In some embodiments, the logic circuit 110 includes a first logic element 111 and a plurality of second logic elements 112. The first logic element 111 is used for receiving the clock signal CLK and the data signal DATA through the first control terminal N1 and the second control terminal N2. In some embodiments, the first logic element 111 includes a NOR gate, which means that when the signals received by the first control terminal N1 and the second control terminal N2 are both "0", the first logic Component 111 will output "1".

The two input terminals of the second logic element 112R-112B are respectively electrically connected to the output terminal of the first logic element 111 and the receiving register 130R-130B. The output terminals of the second logic elements 112R-112B are electrically connected to the sub-pixel units 210R-210B. In some embodiments, the second logic elements 112R-112B include AND gates, which means that when the first logic element 111 outputs "1" and the data signal DATA output by the receiving registers 130R-130B is also When it is “1”, the second logic elements 112R-112B will output “1” to drive the pixel circuit 210 to emit light.

Please refer to FIG. 5, which is a schematic diagram of the driving method of some embodiments of the present disclosure. In step S501, the display driving circuit 100 receives the clock signal CLK from the controller T. The clock signal CLK is input to the input terminals of the logic circuit 110 and the temporary storage circuit 120, respectively.

In step S502, the temporary storage circuit 120 receives the data signal DATA from the controller T, and outputs the data signal DATA to the logic circuit 110 and the receiving circuit 130 according to the clock signal CLK.

In step S503, the receiving circuit 130 sequentially stores the data pulses in the data signal DATA through the receiving registers 130R-130B serially connected in sequence. The receiving registers 130R-130B are also used to output data pulses in the data signal DATA to the logic circuit 110 in response to the clock signal CLK.

The logic circuit 110 selectively turns on the receiving circuit 130 to the pixel circuit 210 according to the data signal DATA and the clock signal CLK from the temporary storage circuit 120. As shown in FIG. 5, in step S504, while the temporary storage circuit 120 outputs the pulse in the data signal DATA to the receiving circuit 130, the logic circuit 110 turns off the electrical connection between the receiving circuit 130 and the pixel circuit 210, The data signal DATA output by the temporary storage circuit 120 is not transmitted to the pixel circuit 210 through the logic circuit 110.

In step S505, after the temporary storage circuit 120 outputs all the pulses of the data signal DATA to the receiving circuit 130, the logic circuit 110 turns on the electrical connection between the receiving circuit 130 and the pixel circuit 210, so that the data signal output by the temporary storage circuit 120 The DATA can be transferred to the pixel circuit 210 via the logic circuit 110, and then the sub-pixel units 210R-210B in the pixel circuit 210 are driven.

In some embodiments, the data signal DATA includes a plurality of pulses in a binary system. For example, if the controller T wants to drive the pixel circuit 210 to generate the brightness of the gray scale "64", the controller T will convert the "64" into the binary code "01000000". The controller T can determine whether to end the transmission of the data signal DATA in advance according to the binary code.

Please refer to Fig. 6, which is the judgment method in some embodiments of the present disclosure. In step S601, the controller T receives an image signal. In step S602, the controller T converts the image signal into the data signal DATA according to the configuration of the display driving circuit 100 (ie, the chiplet on the display panel P). The data signal DATA is a binary command used to drive the sub-pixel units 210R-210B.

For example, referring to FIG. 7, in some embodiments, the display device 200 includes a plurality of display driving circuits 100A-100C. If one display driving circuit 100A is used to drive nine sub-pixel units 210A, and in the first frame of the picture, the pixel brightness corresponding to the nine sub-pixel units 210A is "32, 64, 120...", then the controller T After receiving the image signal IMG, the nine brightness levels will be converted into binary commands "00001000, 01000000, 01111000...". Each binary instruction contains eight bit instructions. The controller T transmits each bit signal in sequence to form the data signal DATA. Taking pixel brightness of "32, 64, 120..." as an example, since it contains eight bit commands after being converted to binary commands, the controller T will send eight bit commands in sequence to form a data signal DATA. For example: the first bit of data sent by the controller T will be the first bit command in the pixel brightness "32, 64, 120..." "0000100"0", 0100000"0", 0111100"0"... ". That is, the first bit of data is "000...", "0" means that the sub-pixel unit does not need to emit light, and "1" means that the sub-pixel unit emits light. Similarly, the fifth bit data is "0000"1"000, 0100"0"000, 0111"1"000..." (ie "101..."). For the convenience of explanation, the octets of the aforementioned binary system are called bit[0], bit[1], bit[2], bit[3], bit[4 in the order from right to left. ], bit[5], bit[6], bit[7].

In step S603, after the controller T generates the data signal DATA, the controller T can first determine the pulse (ie, "1") distribution status when the bit data in the data signal DATA is converted to the binary system. According to the pulse distribution, since the non-pulse signal (ie, "0" does not need to be transmitted), once the temporary storage circuit 120 receives all the pulses in the data signal DATA (or bit data), the display driving circuit 100 will It can be confirmed that all commands of the data signal DATA (or bit data) have been received, and the electrical connection between the receiving circuit 130 and the pixel circuit 210 is turned on.

In some embodiments, the controller T can determine that all the bit data in the data signal DATA is converted to a maximum value after the binary system, and determine the pulse position of the maximum value in all the data data (that is, the command The order of "1" in the bit data) is used as the "pulse distribution status". For example, during the display of one frame, if the maximum pixel brightness in the nine sub-pixel units 210A corresponding to the same display driving circuit 100A is "31", the conversion to the binary system is "00011111". In this case, the controller T will be able to confirm that among the nine bits of data (used to drive the pixel unit 210A), none of bits [6] to bit [7] have pulses (because the maximum value is 31). Accordingly, the controller T only needs to transmit bit[0]～bit[5] in the bit data. This means that the subsequent signal will not need to be sent any more, and the subsequent drive can be directly carried out. The logic circuit 110 transmits the data signal DATA received by the receiving circuit 130 to the corresponding sub-pixel unit to drive light emission.

In one embodiment, the operation of the controller T to transmit bit data according to the pulse distribution of the data signal DATA can be subdivided into steps S604 to S610. In step S604, the controller T first determines whether the maximum value in the same set of bit data in the data signal DATA is greater than "32 (ie, binary "00100000")". If it is less than "32", it means that the pulses in the data signal DATA are all located between bit[0] to bit[4]. In step S605, the controller T only needs to transmit bit[0] to bit[4] in the data signal DATA (such as: 0, 0, 0, 0, 0, 1), because after bit[4] The signals of are all "0".

Similarly, in step S606, the controller T further determines whether the maximum value in the same set of bit data in the data signal DATA is greater than "64 (ie, binary "01000000")". If it is less than "64", it means that the pulses in the data signal DATA are all located between bit[0] and bit[5]. In step S607, the controller T only needs to transmit bit[0] to bit[5] in the data signal DATA (such as: 0, 0, 0, 0, 0, 0, 1), because bit[5 The signals after] are all "0".

Similarly, in step S608, the controller T further determines whether the maximum value in the same group of bit data in the data signal DATA is greater than "128 (ie, binary "10000000")". If it is less than "128", it means that the pulses in the data signal DATA are all located between bit[0] and bit[6]. In step S609, the controller T only needs to transmit bit[0] to bit[6] in the data signal DATA (such as: 0, 0, 0, 0, 0, 0, 0, 1), because bit The signals after [6] are all "0". If it is greater than "128", in step S610, the controller T will transmit bit[0] to bit[7] in the transmission data signal DATA.

In the foregoing embodiments, "the controller T is connected to a single display driving circuit 100, and the pixel circuit 210 is driven" is taken as an example for description. In some other embodiments, please refer to FIG. 7, a plurality of display driving circuits 100A-100C are cascade connected to each other to receive the data signal DATA. That is, the data signal DATA transmitted by the controller T is used to control the sub-pixel units corresponding to the plurality of display driving circuits 100. For example, the controller T will sequentially transmit the data signal DATA to the display driving circuit 100 in each horizontal row. As shown in Fig. 7, each display driving circuit 100A-100C corresponds to 9 sub-pixel units. The sub-pixel units are arranged along the horizontal direction of the display panel P (or the pixel circuit 210). Therefore, the data signal DATA includes 27 bits, which respectively control the 27 sub-pixel units in each horizontal row. Please refer to FIG. 8. In other embodiments, the pixel units 211 (that is, including the sub-pixel units 210R-210B) corresponding to the plurality of cascaded display driving circuits 100 can also be arranged arbitrarily, not horizontally. Arrangement or rectangular arrangement is limited.

Please refer to FIG. 9, which is a schematic diagram of the data signal DATA and the clock signal CLK according to some embodiments of the present disclosure. As mentioned earlier, when the data signal DATA is a binary system, the controller T will sequentially send bit[0], bit[1], bit[2], and bit[2] corresponding to the brightness of all sub-pixel units. bit[3], bit[4], bit[5], bit[6], bit[7]. For example: when the number of sub-pixel units in the same row driven by the controller T is nine, the zeroth bit data B0 of the data signal DATA is the bit[0] of these nine sub-pixel units (ie, multiple bits The instructions P1～P9 are bit[0] of the nine sub-pixel units respectively). The first bit data B1 of the data signal DATA is bit[1] of these nine sub-pixel units, and so on.

As shown in Figure 9, the temporary storage circuit 120 will sequentially receive multiple bit data in the data signal DATA transmitted from the controller T (e.g., the zeroth bit data B0, the first bit data B1, the first bit data B1, and the first bit data). Two-bit data B2, third-bit data B3...). The interval time between the temporary storage circuit 120 receiving the bit data (ie, the zeroth interval time L0, the first interval time L1, the second interval time L2, and the third interval time L3 shown in Figure 9) are The pixel circuit 210 is driven based on the bit data. As mentioned above, the multiple bit instructions P1 to P9 in the zeroth bit data B0 are instructions for converting the brightness of multiple sub-pixel units into binary bit[0].

In conclusion, the interval time (ie, the zeroth interval time L0) during which the temporary storage circuit 120 receives the zeroth bit data B0 and the first bit data B1 is shorter than the temporary storage circuit 120 receives the first bit data B1 and the second bit The interval time of the metadata B2 (ie, the first interval time L1). That is, after the pixel circuit 210 receives the zeroth bit data B0 corresponding to bit[0], its light-emitting time will be less than the light-emitting time of the first bit data B1 corresponding to bit[1]. Because the brightness value corresponding to bit[1] is "2", which is greater than the brightness value corresponding to bit[0] is "1", it will have a longer light-emitting time. Similarly, the light-emitting time after the pixel circuit 210 receives the seventh bit data corresponding to bit [7] will be the longest.

In addition, please refer to FIG. 2. In one embodiment, the logic circuit 110 turns on the electrical connection between the receiving circuit 130 and the pixel circuit 210 as follows: "The signals received by the two input terminals of the first logic element 111 are both Is 0, and the signal received by the second logic element 112 from the receiving circuit 130 is 1". In order to prevent the temporary storage circuit 120 from completely outputting all the bit data in the data signal DATA to the receiving circuit 130, the logic circuit 110 mistakenly turns on the electrical connection between the receiving circuit 130 and the pixel circuit 210 in advance. In an embodiment, the interval Dt between a plurality of pulses of the clock signal CLK can be controlled between 1 and 49 nanoseconds. Accordingly, since the interval Dt of the clock signal CLK is smaller than the response/reaction time of the pixel circuit 210, even if the logic circuit 110 briefly turns on the electrical connection between the receiving circuit 130 and the pixel circuit 210, it will not let The pixel circuit 210 is directly driven.

In other embodiments, the interval Dt between a plurality of pulses of the clock signal CLK can be controlled between 1 to 14 nanoseconds. Accordingly, when the response/reaction time of the pixel circuit 210 is 15 nanoseconds, it is possible to prevent the logic circuit 110 from turning on the electrical connection between the receiving circuit 130 and the pixel circuit 210 by mistake in advance. In other embodiments, the interval Dt between a plurality of pulses of the clock signal CLK can be controlled between 1 and 9 nanoseconds.

The various elements, method steps, or technical features in the foregoing embodiments can be combined with each other, and are not limited to the order of description or presentation of figures in the present disclosure.

Although the content of the present invention has been disclosed in the above embodiments, it is not intended to limit the content of the present invention. Anyone who is familiar with the art can make various changes and modifications without departing from the spirit and scope of the content of the present invention. Therefore, the present invention The scope of protection of the content shall be subject to the scope of the attached patent application.

100: Display drive circuit

100A~100C: display drive circuit

110: Logic Circuit

120: Temporary storage circuit

130: receiving circuit

200: display device

210: pixel circuit

211: Pixel Unit

210R: Sub-pixel unit

210G: Sub-pixel unit

210B: Sub-pixel unit

P: display panel

T: Controller

111: first logic element

112: second logic element

130R: Receive register

130G: Receive register

130B: Receive register

N1: The first control terminal

N2: second control terminal

CLK: Clock signal

DATA: data signal

Vdd: supply voltage

P1~P9: Data pulse

B0~B3: bit data

L0~L3: interval time

Dt: interval

FIG. 1 is a schematic diagram of a display device according to some embodiments of the present disclosure. FIG. 2 is a schematic diagram of a display driving circuit according to some embodiments of the present disclosure. FIG. 3 is a schematic diagram of the waveforms of the clock signal and the data signal according to some embodiments of the present disclosure. 4A to 4D are schematic diagrams of the operation of the display driving circuit according to some embodiments of the present disclosure. FIG. 5 is a flowchart of the steps of the driving method according to some embodiments of the present disclosure. FIG. 6 is a flowchart of the steps of the driving method according to some embodiments of the present disclosure. FIG. 7 is a schematic diagram of a display device according to some embodiments of the present disclosure. FIG. 8 is a schematic diagram of a display device according to some embodiments of the present disclosure. FIG. 9 is a schematic diagram of the waveforms of the clock signal and the data signal according to some embodiments of the present disclosure.

Domestic deposit information (please note in the order of deposit institution, date and number) without Foreign hosting information (please note in the order of hosting country, institution, date, and number) without

100: Display drive circuit

110: Logic Circuit

120: Temporary storage circuit

130: receiving circuit

210: pixel circuit

210R: Sub-pixel unit

210G: Sub-pixel unit

210B: Sub-pixel unit

111: first logic element

112: second logic element

130R: Receive register

130G: Receive register

130B: Receive register

N1: The first control terminal

N2: second control terminal

CLK: Clock signal

DATA: data signal

Vdd: supply voltage

Claims (18)

A display driving circuit, including: A logic circuit electrically connected to a pixel circuit, wherein the logic circuit includes a first control terminal and a second control terminal, and the first control terminal is used for receiving a clock signal; A temporary storage circuit for outputting a data signal according to the clock signal, wherein an output terminal of the temporary storage circuit is electrically connected to the second control terminal; and A receiving circuit is electrically connected to the output terminal of the temporary storage circuit and used to output the data signal received from the temporary storage circuit to the logic circuit, wherein the logic circuit is based on the first control terminal and the The signal received by the second control terminal selectively transmits the data signal from the receiving circuit to the pixel circuit. The display driving circuit according to claim 1, wherein the logic circuit turns off the electrical connection between the receiving circuit and the pixel circuit while the temporary storage circuit outputs the data signal to the receiving circuit; After the storage circuit outputs the data signal to the receiving circuit, the logic circuit turns on the electrical connection between the receiving circuit and the pixel circuit. The display driving circuit according to claim 2, wherein the pixel circuit includes a plurality of sub-pixel units, and the receiving circuit includes a plurality of receiving registers connected in series, and a plurality of pulses in the data signal sequentially pass through After the receiving registers are transferred to the logic circuit, the logic circuit transfers the pulses in the data signal to the sub-pixel units. The display driving circuit according to claim 3, wherein the logic circuit includes: A first logic element for receiving the clock signal and the data signal through the first control terminal and the second control terminal; and A plurality of second logic elements, two input terminals of the second logic elements are electrically connected to an output terminal of the first logic element and the receiving registers, and the plurality of output terminals of the second logic elements are electrically connected Sexually connected to these sub-pixel units. The display driving circuit according to claim 4, wherein the first logic element includes a NOR gate. The display driving circuit according to claim 5, wherein the second logic element includes a gate. The display driving circuit according to claim 3, wherein the temporary storage circuit is used to sequentially receive a zeroth bit data, a first bit data, and a second bit data, and the temporary storage circuit receives the first bit data An interval time between the zero bit data and the first bit data is shorter than an interval time for the temporary storage circuit to receive the first bit data and the second bit data. The display driving circuit according to claim 3, wherein the interval between the pulses of the clock signal is between 1 and 49 nanoseconds. The display driving circuit according to claim 8, wherein the interval between the pulses of the clock signal is between 1 to 14 nanoseconds. The display driving circuit according to claim 3, wherein the sub-pixel units are arranged along the horizontal direction of the pixel circuit. The display driving circuit according to claim 3, wherein the receiving registers output the data signal received from the register circuit to the logic circuit in response to the clock signal. A driving method, including: Receive a clock signal through a logic circuit and a temporary storage circuit; Receiving a data signal through the temporary storage circuit, and outputting the data signal to the logic circuit and a receiving circuit according to the clock signal; and The logic circuit selectively conducts the receiving circuit to a pixel circuit according to the data signal and the clock signal from the temporary storage circuit. The driving method described in claim 12 further includes: When the temporary storage circuit outputs a plurality of pulses in the data signal to the receiving circuit, the electrical connection between the receiving circuit and the pixel circuit is turned off; and After the temporary storage circuit outputs the pulses of the data signal to the receiving circuit, the electrical connection between the receiving circuit and the pixel circuit is turned on. The driving method described in claim 13, further comprising: Sequentially receiving the pulses of the data signal through a plurality of receiving registers in the receiving circuit; and The receiving registers transmit the pulses to a plurality of sub-pixel units in the pixel circuit through the logic circuit. The driving method according to claim 12, wherein the data signal includes a plurality of pulses in a binary system, and the driving method further includes: Determine the distribution of a pulse when the data signal is converted to a binary system; and According to the pulse distribution condition, after the temporary storage circuit receives all the pulses in the data signal, the electrical connection between the receiving circuit and the pixel circuit is turned on. The driving method according to claim 12, wherein the temporary storage circuit is used to sequentially receive a zeroth bit data, a first bit data, and a second bit data, and the temporary storage circuit receives the zeroth bit data An interval time between bit data and the first bit data is shorter than an interval time for the temporary storage circuit to receive the first bit data and the second bit data. The driving method according to claim 12, wherein the interval between the plurality of pulses of the clock signal is between 1 and 49 nanoseconds. The driving method according to claim 17, wherein the interval between the plurality of pulses of the clock signal is between 1 to 14 nanoseconds.

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