TWI734655B - A method for improving the tracking performance of clock data recovery circuitand a system using the same - Google Patents

Abstract

A CDR system comprises a phase detector and a APWC module. The phase detector is configured to sample a data signal to derive a plurality of sampling values. The APWC module is configured to provide a pulse width control signal to the phase detector according to a data transiting rate derived from the sampling values. Wherein the phase detector adjusts the pulse width of the output signal according to the pulse width control signal.

Description

Method for improving tracking performance of clock data recovery circuit and its applicable system

The present invention relates to a control method of a clock data recovery circuit and its applicable system, in particular to a method and system for improving the tracking performance of the clock data recovery circuit.

Clock data recovery (CDR) circuits are often used in high-speed transmission applications, usually for recovering the phase and/or frequency information of the input data signal, for example, by capturing the rising/falling edge of the data signal. The conventional CDR circuit, as shown in Figure 1, includes, for example, a phase detector (PD), a charge pump (CP), a loop filter (LF), and a voltage-controlled oscillator ( Voltage-controlledoscillator, VCO).

Generally speaking, most clock data recovery circuits applied to high-speed transmission use Bang-Bang (BB) phase detectors to perform phase detection and/or correction of the CDR circuit. When the BBPD-CDR is applied to different data types, if the following ability of the BBPD-CDR is insufficient (for example, the ability to follow the frequency), it will lead to insufficient jitter tolerance. And affect the stability of the clock recovery loop. Although various coding formats (Coding Format) can be used to reduce the impact, it will cause additional coding overhead. Therefore, how to improve the tracking ability of the clock data recovery circuit will be a major goal of technology research and development in this field.

The present invention provides a clock data recovery system, which includes a phase detector and an adaptive pulse width control (APWC) module. The phase detector is used to sample a data signal to obtain a complex sample value. The APWC module is used for providing a bandwidth adjustment signal to the phase detector according to a data transition rate obtained from the sampling values. The phase detector adjusts the pulse width of the output signal according to the bandwidth adjustment signal.

The present invention provides a control method of a clock data recovery circuit, which includes: sampling a data signal by a phase detector and obtaining a plurality of sample values; and calculating a data transition rate of the data signal according to the sample values; And adjust the output pulse width of the phase detector according to the data transition rate.

In one embodiment, the phase detector includes a pulse width adjustment module; the pulse width adjustment module selects an input adjustment clock signal according to the data transition rate.

In one embodiment, the input of the pulse width adjustment module further includes a clock signal, and the adjusted clock signal lags the clock signal.

In one embodiment, the amplitude that the adjusted clock signal lags behind the clock signal is between 0.5 UI and 1.5 UI.

In one embodiment, when the data transition rate is in a first interval, the phase detector output is a first pulse width; and when the data transition rate is in a second interval, the phase The output of the detector is a second pulse width; wherein when the data transition rate is in a third interval, the output of the phase detector is a third pulse width.

In an embodiment, the first interval is between 100% and 50%; the second interval is between 50% and 30%; and the third interval is less than 30%.

As described above, the first pulse width adjustment module receives the clock signal and the first adjustment clock signal and outputs the adjustment signal, thereby providing an appropriate pulse width. When the charge pump charges or discharges according to the appropriate pulse width, the jitter generation or influence of the clock data recovery circuit will be reduced. This achieves the purpose of improving the stability of the clock data recovery circuit loop.

The following will clearly illustrate the spirit of the present disclosure with diagrams and detailed descriptions. Anyone with ordinary knowledge in the technical field who understands the embodiments of the present disclosure can change and modify the techniques taught in the present disclosure. It does not depart from the spirit and scope of this disclosure.

Regarding the "first", "second", etc. used in this text, they do not specifically refer to order or sequence, nor are they used to limit the present invention. They are only used to distinguish elements or operations described in the same technical terms. Regarding the "include", "include", "have", "contain", etc. used in this article, they are all open terms, which means including but not limited to.

Regarding the terms used in this article, unless otherwise specified, each term usually has the usual meaning of each term used in this field, in the content disclosed here, and in the special content. Some terms used to describe the present disclosure will be discussed below or elsewhere in this specification to provide those skilled in the art with additional guidance on the description of the present disclosure.

In the drawings, the thickness of layers, panels, regions, or spaces, etc., are exaggerated for clarity. Throughout the specification, the same reference numerals denote the same elements. It should be understood that when an element such as a layer, board, region or space is referred to as being "on" or "connected to" another element, it can be interpreted as being directly on or with another element. Connected, or can be interpreted as having or presence of intermediate elements between the element and another element. As used herein, "connected" or "coupled" can refer to physical and/or electrical connections. Furthermore, in order to simplify the drawings and highlight the content to be presented in the drawings, the conventional structures or elements in the drawings may be drawn in a simple schematic manner or presented in an omitted manner.

Please refer to FIG. 2. FIG. 2 illustrates the clock data recovery system 10 using the control method of the clock data recovery circuit disclosed in the present invention. The clock data recovery system 10 includes a phase detector PD, a charge pump CP, a loop filter LF, a voltage controlled oscillator VCO, and an adaptive pulse width control (APWC) module APWCM. Specifically, the phase detector PD is, for example, an impact phase detector, and is preferably half-rate or multi-rate (such as but not limited to 1/4-rate or 1/ 9-rate) collision type (BB) phase detector PD. After the adaptive pulse width control module APWCM receives the data transition rate DTR provided by the phase detector PD from the phase detector PD, the adaptive pulse width control module APWCM provides bandwidth adjustment according to the data transition rate DTR The signal PMS is sent to the phase detector PD. The phase detector PD adjusts the bandwidth of the output signal of the phase detector PD according to the bandwidth adjustment signal PMS.

It should be noted that the definition of the data transition rate DTR is, for example, the number of data transitions in the unit data length. For example, in the unit data length, the number of transitions from low level (binary "0") to high level (binary "1") or high level to low level. The calculation of the data transition rate DTR can be calculated by the phase detector PD and provided to the adaptive pulse width control module APWCM, or it can be calculated by the adaptive pulse width control module APWCM. For example, the adaptive pulse width control module APWCM can calculate the number of data transitions based on the data transmitted by the phase detector PD. The present invention is not limited to the calculation method of the data transition rate DTR.

In one embodiment, the adaptive pulse width control module APWCM can adjust the bandwidth of the phase detector PD and divide it into three states according to the data transition rate DTR. Specifically, as shown in Table 1 below, when the data transition rate is in the first interval, the output of the phase detector PD is the first pulse width; when the data transition rate is in the second interval, the phase detector The PD output is the second pulse width; when the data transition rate is in the third interval, the PD output of the phase detector is the third pulse width. In a preferred embodiment, the first interval is the data transition rate in the range of 100% to 50%; the second interval is the data transition rate in the range of 50% to 30%; the third interval is the data transition rate Less than 30% of the range. In a preferred embodiment, the first pulse wave width is 0.5 UI; the second pulse wave width is 1 UI; and the third pulse wave width is 1.5 UI. It should be noted that the foregoing embodiment only illustrates that the data transition rate can be divided into several intervals and the corresponding pulse wave width is provided according to the interval to which the data transition rate belongs. The present invention is not limited to the number and range of the interval sum of the data transition rate and is not limited to the width of the pulse wave width provided. Any similar concepts that provide different pulse widths based on the data transition rate should belong to the scope of the present invention. Table 1. Correspondence between data transition rate and pulse width. Data transition rate Pulse width The first interval (100%~50%) First pulse width (0.5 UI) The second interval (50%~30%) Second pulse width (1 UI) The third interval (＜30%) Third pulse width (1.5 UI)

In one embodiment, taking a data packet with a data length of 9UI as an example, the number of state transitions in a data packet with a length of 9UI is at most 9 times and at least 2 times. It can be divided into three sections and given different pulse widths for different sections. For example, the number of transitions in the first interval can be between 9 and 6, and the first pulse width can be 0.5UI. If the bandwidth of the system 10 is restored according to the clock data, it can be proportional to the number of transitions of the data. Calculated with the pulse width of charging and discharging, the loop bandwidth change in this interval is 4.5 to 3. The number of transitions in the second interval can be between 5 and 4, and the second pulse width can be 1UI, the loop bandwidth variation in this interval is 5 to 4; the number of transitions in the third interval can be 3 To 2 times, and the third pulse width can be 1.5UI, the loop bandwidth change in this interval is 4.5 to 3. Preferably, the product of the number of transitions in each interval and the pulse width (the amount of change in loop bandwidth) is preferably substantially equal or similar. With this setting, when the data transition rate or the number of data transitions is low, you can still have a good frequency tracking ability by adjusting the value of the pulse width, thereby optimizing the jitter tolerance of the clock data recovery system.

In one embodiment, referring to FIG. 3, a phase detector 100 is illustrated, including a first sampling element 111, a second sampling element 112, a first comparison element 121, a first pulse width adjustment module 131, and a first output Component 141. The first sampling element 111 samples the data signal DS corresponding to the first clock signal CLK1 and outputs a first sampling value D1. The second sampling element 112 samples the data signal DS corresponding to the second clock signal CLK2 and outputs a second sampling value D2. Specifically, the first sampling element 111 and/or the second sampling element 112 can be, but not limited to, a flip-flop or other elements that perform sampling based on a clock signal. In addition, the sampling elements 111 and 112 respectively correspond to the definitions of the clock signals CLK1 and CLK2, for example, but not limited to, edge-triggered based on the upper edge points and/or the lower edge points of the clock signals CLK1 and CLK2. The data signal DS and the sampling values D1 and D2 are, for example, but not limited to, serial digital signals and bit values in serial digital signals.

The first comparison element 121 is coupled to the first sampling element 111 and the second sampling element 112 and receives the first sampling value D1 and the second sampling value D2. Specifically, the first comparison element 121 is, for example, but not limited to, a comparator or a logic gate, and is preferably an exclusive OR (XOR) logic gate. When the first sample value D1 and the second sample value D2 are different, the first comparison element 121 outputs the first comparison signal CS1. For example, if the value of the first sample value D1 is a binary value "1", and the value of the second sample value D2 is a binary value "0", then the first sample value D1 and the second sample value D2 are different. The definition of the first comparison signal CS1 is, for example, a comparison result of the first sample value D1 and the second sample value D2. For example, when the first sample value D1 and the second sample value D2 are different, the first comparison signal CS1 is a binary value "1". Conversely, when the first sample value D1 and the second sample value D2 are the same, the first comparison signal CS1 is a binary value "0". It should be noted that the above examples are only used to illustrate the embodiments and not to limit the present invention.

3 and 4, the first pulse width adjustment module 131 receives the third clock signal CLK3 and the first adjustment clock signal ACK1. For example, the first pulse width adjustment module 131 can be implemented by, but not limited to, a logic circuit or a switch circuit. There is a time interval TS between the positive edge point P3 of the third clock signal CLK3 and the positive edge point PA1 of the first adjusted clock signal ACK1. Specifically, the pulse width (PW) of the first clock signal CLK1, the second clock signal CLK2, and the third clock signal CLK3 are the same as each other. In addition, the positive edge point P1 of the first clock signal CLK1, the positive edge point P2 of the second clock signal CLK2, and the positive edge point P3 of the third clock signal CLK3 lag each other in sequence by a lagging width DW. Preferably, the backward width DW is 0.5 UI. For example, the positive edge point P2 of the second clock signal CLK2 lags behind the positive edge point P1 of the first clock signal CLK1 by an amplitude of 0.5 UI, and the positive edge point P3 of the third clock signal CLK3 lags behind the second clock signal The amplitude of the positive edge point P2 of the signal CLK2 is also 0.5 UI. It should be noted that the lag width DW that the clock signals CLK1 to CLK3 lag behind each other in the present invention is not limited to 0.5 UI. On the other hand, the present invention is not limited to the number of clock signals. In other words, the present invention can have clock signals CLK1-CLKX, the number of which is X clock signals, and X is any positive integer greater than 3. In one embodiment, when the phase detector 100 is applied to a clock data recovery circuit with a 1/N rate structure, X is equal to twice N. The first adjusted clock signal ACK1 may be one of the clock signals CLK1-CLKX that is behind the third clock signal CLK3. The width of the time interval TS is preferably 0.5 UI, 1 UI or 1.5 UI. For example, each of the clock signals CLK1-CLKX sequentially lags behind by 0.5 UI, and the third clock signal CLK3 has a positive edge point P3 and the first adjusted clock signal ACK1 has a positive edge point PA1. When the time interval TS is 0.5 UI, the first adjusted clock signal ACK1 can be the fourth clock signal CLK4. Next, the first pulse width adjustment module 131 outputs the first adjustment signal AS1 in the interval of the time interval TS. For example, as shown in FIG. 3, the first adjustment signal AS1 outputs a binary value "1" in the interval of the time interval TS, and outputs a binary value "0" in the remaining intervals. In this way, the first adjustment signal AS1 with a width equal to the time interval TS can be generated.

The first output element 141 is coupled to the first comparison element 121 and the first pulse width adjustment module 131 and receives the first comparison signal CS1 and the first adjustment signal AS1. Specifically, the first output element 141 is, for example, a logic circuit element. The first output element 141 performs a logical operation on the first comparison signal CS1 and the first adjustment signal AS1 and then outputs the first output signal OS1. In one embodiment, the logic operation is an AND logic operation. In this embodiment, for example, when the first comparison signal CS1 and the first adjustment signal AS1 are both binary values "1", the first output The signal OS1 is a binary value "1". In addition, in an embodiment, the first output signal OS1 output by the first output element 141 may be provided to a charge pump connected to the back end, for example. In this embodiment, the first output signal OS1 is, for example, an up signal or a down signal provided to the charge pump. The first output element 141 can adjust the first comparison signal CS1 according to the width of the first adjustment signal AS1. The clock data recovery circuit can provide suitable charging and/or discharging time of the charge pump through the above-mentioned phase detector 100 and reduce the integral response of the loop filter. Make the entire clock data recovery circuit reduce jitter generation by this setting.

In one embodiment, the present invention can be applied to a clock data recovery circuit with a 1/N rate structure where N is greater than 2 by increasing the number of phase detectors and clock signals. 5 and 6 illustrate a phase detector 300 applied to a 1/9 rate architecture and its related timing diagrams. When applied to a 1/9 rate architecture, there are 18 sets of clock signals CLK1-CLK18, 18 sets of sampling elements 111-1118, 18 sets of comparison elements 121-1218, 18 sets of pulse width adjustment modules 131-1318 and 18 sets of outputs Elements 141-1418. The clock signals CLK1-CLK18 lag behind each other in sequence, and the lagging amplitude is 0.5 UI, and the pulse width of each clock signal CLK1-CLK18 is 4.5 UI. The data signal DS is sampled by the sampling elements 111-1118 corresponding to the clock signals CLK1-CLK18, and the sampling values D1-D18 are provided to the comparison elements 121-1218 for comparison. It should be noted that each comparison element 121-1218 only inputs two adjacent sample values. For example, the sample values input by the comparison element 121 are D1 and D2. When the sample value reaches the end (sample value D18 in this embodiment), the next sample value is the first bit of the sample value (sample value D1 in this embodiment). For example, the sampling values input by the comparison element 1218 are D18 and D1. In addition, FIG. 5 simplifies the wiring connection in the drawing for clarity of the drawing. For example, the sampling element 113 drawn in FIG. 5 is only to illustrate the connection method of the sampling element 113, and it is not necessary to have two sampling elements 113. The rest of the process of the phase detector 300 is the same as the previous embodiment, and will not be repeated here. However, the present invention is not limited to the architecture used for the 1/9 rate. The present invention can be applied to various architectures by increasing and reducing the number of components.

Referring to FIG. 7, the present invention provides a control method of a clock data recovery circuit, including: step S1 samples a data signal by a phase detector and obtains a complex sample value; step S2 calculates a data signal based on the sample values Data transition rate; and step S3 adjusts the output pulse width of the phase detector according to the data transition rate.

The present invention has been described in the above-mentioned related embodiments, but the above-mentioned embodiments are only examples for implementing the present invention. It must be pointed out that the disclosed embodiments do not limit the scope of the present invention. On the contrary, modifications and equivalent arrangements included in the spirit and scope of the patent application are all included in the scope of the present invention.

10: Clock data recovery system 100, 300: Phase detector 111-1118: sampling element 121-1218: Compare components 131-1318: Pulse width adjustment module 141-1418: output components DS: Data signal CLK1-CLK18: clock signal D1-D18: sampled value CS1-CS18: Control signal AS1-AS18: adjust signal OS1-OS18: output signal S1, S2, S3: steps PD: Phase detector CP: charge pump LF: Loop filter VCO: Voltage Controlled Oscillator APWCM: adaptive pulse width control module

FIG. 1 is a schematic diagram of the structure of a conventional clock data recovery circuit.

FIG. 2 is a schematic diagram of the structure of a clock data recovery circuit in an embodiment of the present invention.

FIG. 3 is a schematic diagram of a phase detector in an embodiment of the invention.

FIG. 4 is a signal timing diagram of the phase detector in an embodiment of the present invention.

FIG. 5 is a schematic diagram of a phase detector in an embodiment of the invention.

FIG. 6 is a signal timing diagram of the phase detector in an embodiment of the present invention.

FIG. 7 is a flowchart of a control method of the clock data recovery circuit in an embodiment of the present invention.

10: Clock data recovery system

PD: Phase detector

CP: charge pump

LF: Loop filter

VCO: Voltage Controlled Oscillator

APWCM: adaptive pulse width control module

Claims (12)

A clock data recovery system, including: A phase detector for sampling a data signal to obtain a complex sample value; as well as The adaptive pulse width control (APWC) module is used to provide a bandwidth adjustment signal to the phase detector according to a data transition rate obtained from the sampling values; The phase detector adjusts the pulse width of the output signal according to the bandwidth adjustment signal. The clock data recovery system according to claim 1, wherein the phase detector includes a pulse width adjustment module; the pulse width adjustment module selects an input adjustment clock signal according to the data transition rate. The clock data recovery system according to claim 2, wherein the input of the pulse width adjustment module further includes a clock signal, and the adjusted clock signal lags behind the clock signal. The clock data recovery system according to claim 3, wherein the adjusted clock signal lags behind the clock signal by an amplitude between 0.5 UI and 1.5 UI. The clock data recovery system according to claim 1, wherein when the data transition rate is in a first interval, the phase detector output is a first pulse width; wherein when the data transition rate is in a first interval In the second interval, the output of the phase detector is a second pulse width; wherein when the data transition rate is in a third interval, the output of the phase detector is a third pulse width. The clock data recovery system according to claim 5, wherein the first interval is between 100% and 50%; the second interval is between 50% and 30%; and the third interval is less than 30%. A control method of a clock data recovery circuit, including: A data signal is sampled by a phase detector, and a complex sample value is obtained; Based on the sampled values, calculate a data transition rate; and Adjust the pulse width of the output signal of the phase detector according to the data transition rate. The control method according to claim 7, wherein the phase detector includes a pulse width adjustment module; the pulse width adjustment module selects an input adjustment clock signal according to the data transition rate. The control method according to claim 8, wherein the input of the pulse width adjustment module further includes a clock signal, and the adjusted clock signal lags the clock signal. The control method according to claim 9, wherein the amplitude of the adjusted clock signal behind the clock signal is between 0.5 UI and 1.5 UI. The control method according to claim 7, wherein when the data transition rate is in a first interval, the phase detector output is a first pulse width; wherein when the data transition rate is in a second interval When the phase detector output is a second pulse width; when the data transition rate is in a third interval, the phase detector output is a third pulse width. The control method according to claim 11, wherein the first interval is between 100% and 50%; the second interval is between 50% and 30%; and the third interval is less than 30%.

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