[go: up one dir, main page]

TWI732367B - Multi-level noise shaping system, method and non-transitory computer-readable medium - Google Patents

Multi-level noise shaping system, method and non-transitory computer-readable medium Download PDF

Info

Publication number
TWI732367B
TWI732367B TW108143895A TW108143895A TWI732367B TW I732367 B TWI732367 B TW I732367B TW 108143895 A TW108143895 A TW 108143895A TW 108143895 A TW108143895 A TW 108143895A TW I732367 B TWI732367 B TW I732367B
Authority
TW
Taiwan
Prior art keywords
signal
output
input
adder
delay
Prior art date
Application number
TW108143895A
Other languages
Chinese (zh)
Other versions
TW202123218A (en
Inventor
林義雄
陳浩銘
Original Assignee
香港商吉達物聯科技股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 香港商吉達物聯科技股份有限公司 filed Critical 香港商吉達物聯科技股份有限公司
Priority to TW108143895A priority Critical patent/TWI732367B/en
Publication of TW202123218A publication Critical patent/TW202123218A/en
Application granted granted Critical
Publication of TWI732367B publication Critical patent/TWI732367B/en

Links

Images

Landscapes

  • Compression, Expansion, Code Conversion, And Decoders (AREA)

Abstract

The present invention provides a multi-level noise shaping system comprises a digital signal processor, a delay feedback circuit, a multi-level quantizer and a controller. The digital signal processor outputs an input-output frequencies ratio signal according to input frequency and output frequency. The delay feedback circuit’s input connect to the digital signal processor to accept the input-output frequencies ratio signal, and outputs an oscillating signal. The multi-level quantizer’s input connect to delay feedback circuit to accept the oscillating signal, and output a multi-bits signal. The controller’s input connect to the multi-level quantizer to accept the multi-bits signal, the controller output a hold signal or a sampling single according to a codeword mapping table.

Description

多位階雜訊重塑式轉換系統、方法及非暫存性電腦可讀取紀錄媒體Multi-level noise reshaping conversion system, method and non-temporary computer readable recording medium

本發明提供一種多位階雜訊重塑式轉換系統、方法及非暫存性電腦可讀取紀錄媒體，尤指一種可進行取樣補點的多位階雜訊重塑式轉換系統、方法及非暫存性電腦可讀取紀錄媒體。The present invention provides a multi-level noise reshaping conversion system, method and non-temporary computer readable recording medium, in particular to a multi-level noise reshaping conversion system, method and non-temporary The storage computer can read the recording medium.

一般在聆聽音樂或看電影時都會注意到兩個引數取樣率和位元率，將把模擬音訊訊號轉成數字音訊訊號的過程稱作取樣，通過波形取樣的方法記錄1秒鐘長度的聲音需要多少個數據點。例如：44.1KHz取樣率的聲音就是要花費44000個數據點來描述1秒鐘的聲音波形，原則上取樣率越高，聲音質量越好。Generally speaking, when listening to music or watching movies, you will notice the two parameters sampling rate and bit rate. The process of converting an analog audio signal into a digital audio signal is called sampling, and the sound of 1 second is recorded by the method of waveform sampling. How many data points are needed. For example, a sound with a sampling rate of 44.1KHz takes 44,000 data points to describe a sound waveform for 1 second. In principle, the higher the sampling rate, the better the sound quality.

上述的取樣率是指將聲音(模擬訊號)轉換成數字訊號時的取樣頻率，也就是單位時間內取樣多少點資料，而位元率是指每秒傳送的位元(bit)數。單位為 bps(Bit Per Second)，位元率越高，傳送的資料越大，音質越好。The above-mentioned sampling rate refers to the sampling frequency when the sound (analog signal) is converted into a digital signal, that is, how many points of data are sampled per unit time, and the bit rate refers to the number of bits transmitted per second. The unit is bps (Bit Per Second). The higher the bit rate, the larger the transmitted data and the better the sound quality.

取樣率和位元率如同座標軸上的橫縱座標。橫座標的取樣率表示了每秒鐘的取樣資料點；縱座標的位元率表示了用數字量來量化模擬量的時候的精度。The sampling rate and bit rate are like the horizontal and vertical coordinates on the coordinate axis. The sampling rate of the abscissa indicates the sampled data points per second; the bit rate of the ordinate indicates the accuracy when using digital quantities to quantify analog quantities.

取樣定理表明取樣頻率必須大於被取樣訊號頻寬的兩倍，也就是假設訊號的頻寬是100Hz，那麼為了避免混疊現象取樣頻率必須大於200Hz，換句話說，就是取樣頻率必須至少是訊號中最大頻率分量頻率的兩倍，否則就不能從訊號取樣中恢復原始訊號。The sampling theorem states that the sampling frequency must be greater than twice the bandwidth of the signal being sampled, that is, assuming that the bandwidth of the signal is 100Hz, the sampling frequency must be greater than 200Hz in order to avoid aliasing. In other words, the sampling frequency must be at least in the signal The maximum frequency component is twice the frequency, otherwise the original signal cannot be recovered from the signal sampling.

一般取樣到的訊號常常會帶來一些誤差，誤差主要來自於兩個方面，與連續類比訊號頻譜有關的取樣頻率，以及量化時所用的字元長度。Generally, the sampled signal often brings some errors. The errors mainly come from two aspects, the sampling frequency related to the spectrum of the continuous analog signal, and the character length used in quantization.

本發明提供一種多位階雜訊重塑式轉換系統，配合一取樣迴路設置，包括一訊號處理器、一延遲回授迴路、一多位階量化器以及一控制器。該訊號處理器依據輸入訊號頻率與輸出訊號頻率的比值輸出一輸入-輸出頻率比例訊號，該延遲回授迴路的輸入端連接至該訊號處理器以接收該輸入-輸出頻率比例訊號，並通過一或複數個延遲器輸出一波峰為該輸入訊號頻率與該輸出訊號頻率比值的震盪訊號，該多位階量化器的輸入端連接至該延遲回授迴路以接收該震盪訊號，並依據該震盪訊號輸出一多位元量化訊號，該多位元量化訊號係依據下面的公式獲得：

Figure 02_image001
； 其中，
Figure 02_image003
為第n階段輸入的震盪訊號，M為該多位階量化器預設的位階數值，
Figure 02_image005
為一floor函數，
Figure 02_image007
為所輸出第n階段的該多位元量化訊號，該控制器的輸入端連接至該多位階量化器以接收該多位元量化訊號，將該多位元量化訊號依據代碼映射表輸出一保持訊號，並經由取樣迴路取得訊號後儲存，當該多位元量化訊號等於
Figure 02_image009
時依據代碼映射表輸出一取樣訊號，使取樣迴路進行取樣。 The present invention provides a multi-level noise reshaping conversion system, which is configured with a sampling loop and includes a signal processor, a delay feedback loop, a multi-level quantizer and a controller. The signal processor outputs an input-output frequency ratio signal according to the ratio of the input signal frequency to the output signal frequency. The input end of the delay feedback loop is connected to the signal processor to receive the input-output frequency ratio signal, and pass an input-output frequency ratio signal. Or a plurality of delayers output a peak as an oscillating signal of the ratio of the input signal frequency to the output signal frequency, the input of the multi-level quantizer is connected to the delay feedback loop to receive the oscillating signal, and output according to the oscillating signal A multi-bit quantized signal, the multi-bit quantized signal is obtained according to the following formula:
Figure 02_image001
; among them,
Figure 02_image003
Is the oscillating signal input in the nth stage, M is the preset level value of the multi-level quantizer,
Figure 02_image005
Is a floor function,
Figure 02_image007
For the output of the multi-bit quantized signal of the nth stage, the input of the controller is connected to the multi-level quantizer to receive the multi-bit quantized signal, and the multi-bit quantized signal is output and held according to the code mapping table Signal and store it after obtaining the signal through the sampling loop, when the multi-bit quantized signal is equal to
Figure 02_image009
When outputting a sampling signal according to the code mapping table, the sampling loop can perform sampling.

更進一步地，該延遲回授迴路包含一第一加法器、一第二加法器、以及一延遲模組；其中該第一加法器的輸入端連接至該訊號處理器以及該延遲模組並於該第一加法器的輸出端輸出一第一訊號；其中該第二加法器的輸入端連接至該第一加法器的輸出端以及該多位階量化器的輸出端並於該第二加法器的輸出端輸出一第二訊號；其中該延遲模組的輸入端連接至該第二加法器的輸出端並於該延遲回授迴路的輸出端輸出一延遲補償訊號。Furthermore, the delay feedback loop includes a first adder, a second adder, and a delay module; wherein the input of the first adder is connected to the signal processor and the delay module and is connected to the signal processor and the delay module. The output terminal of the first adder outputs a first signal; wherein the input terminal of the second adder is connected to the output terminal of the first adder and the output terminal of the multi-level quantizer and is connected to the output terminal of the second adder The output terminal outputs a second signal; wherein the input terminal of the delay module is connected to the output terminal of the second adder and outputs a delay compensation signal at the output terminal of the delay feedback loop.

更進一步地，該延遲模組包括一第一延遲器、一係數乘法器、以及一第二延遲器；其中該第一延遲器的輸入端係連接至該第二延遲器的輸出端並於該第一延遲器的輸出端輸出一第一延遲訊號；該係數乘法器的輸入端係連接至該第二延遲器的輸出端並於該係數乘法器的輸出端輸出一係數加乘訊號；該第二延遲器的輸入端係連接至該第一加法器的輸出端並於該第二延遲器的輸出端輸出一第二延遲訊號；該第一加法器的輸入端連接至該訊號處理器、該係數乘法器的輸出端、以及該第二延遲器的輸出端並於該第一加法器的輸出端輸出該第一訊號。Furthermore, the delay module includes a first delay, a coefficient multiplier, and a second delay; wherein the input of the first delay is connected to the output of the second delay and connected to the The output terminal of the first delay device outputs a first delay signal; the input terminal of the coefficient multiplier is connected to the output terminal of the second delay device and outputs a coefficient multiplication signal at the output terminal of the coefficient multiplier; The input end of the second delayer is connected to the output end of the first adder and outputs a second delay signal at the output end of the second delayer; the input end of the first adder is connected to the signal processor, the The output terminal of the coefficient multiplier and the output terminal of the second delay device output the first signal at the output terminal of the first adder.

更進一步地，該第二加法器輸出的該第二訊號依據下面的公式獲得：

Figure 02_image011
其中，
Figure 02_image013
為第n階段輸出的該第二加法訊號，
Figure 02_image015
為第n階段輸入的該多位元量化訊號，
Figure 02_image017
為第n階段輸入的該第一訊號。 Furthermore, the second signal output by the second adder is obtained according to the following formula:
Figure 02_image011
among them,
Figure 02_image013
Is the second addition signal output at the nth stage,
Figure 02_image015
Is the multi-bit quantized signal input in the nth stage,
Figure 02_image017
This is the first signal input at the nth stage.

更進一步地，該第一加法器輸出的該第一訊號依據下面的公式獲得：

Figure 02_image019
其中，
Figure 02_image017
為第n階段輸出的該第一訊號，
Figure 02_image021
為第n階段輸入的該輸入-輸出頻率比例訊號，
Figure 02_image023
為第
Figure 02_image025
階段輸入的該係數加乘訊號，
Figure 02_image027
為第
Figure 02_image029
階段輸入的該第二加法訊號。 Furthermore, the first signal output by the first adder is obtained according to the following formula:
Figure 02_image019
among them,
Figure 02_image017
Is the first signal output at the nth stage,
Figure 02_image021
Is the input-output frequency ratio signal input in the nth stage,
Figure 02_image023
For the first
Figure 02_image025
The multiplication signal of the coefficient input in the stage,
Figure 02_image027
For the first
Figure 02_image029
The second addition signal input in the stage.

更進一步地，該係數乘法器的該係數加乘訊號依據下面的公式獲得：

Figure 02_image031
其中，
Figure 02_image023
為第
Figure 02_image025
階段輸出的該係數加乘訊號，
Figure 02_image033
為第
Figure 02_image025
階段輸入的該第二加法訊號。 Furthermore, the coefficient multiplication signal of the coefficient multiplier is obtained according to the following formula:
Figure 02_image031
among them,
Figure 02_image023
For the first
Figure 02_image025
The multiplication signal of the coefficient output at the stage,
Figure 02_image033
For the first
Figure 02_image025
The second addition signal input in the stage.

更進一步地，該輸入-輸出頻率比例訊號最小值為0，最大值為1。Furthermore, the minimum value of the input-output frequency ratio signal is 0, and the maximum value is 1.

更進一步地，該多位元量化訊號為一整數構成之階梯波。Furthermore, the multi-bit quantized signal is a step wave composed of an integer.

本發明的另一目的，在於提供一種多位階雜訊重塑式轉換方法，包括：一輸入訊號頻率與一輸出訊號頻率輸入至一訊號處理器；該訊號處理器依據輸入訊號頻率與輸出訊號頻率的比值輸出一輸入-輸出頻率比例訊號；該輸入-輸出頻率比例訊號輸入至一延遲回授迴路，並通過一或複數個延遲器輸出一波峰為該輸入訊號頻率與該輸出訊號頻率比值的震盪訊號；該震盪訊號輸入一多位階量化器；該多位階量化器依據該震盪訊號輸出一多位元量化訊號，該多位元量化訊號係依據下面的公式獲得：

Figure 02_image035
； 其中，
Figure 02_image003
為第n階段輸入的震盪訊號，M為該多位階量化器預設的位階數值，
Figure 02_image005
為一floor函數，
Figure 02_image037
為所輸出第n階段的該多位元量化訊號；該多位元量化訊號輸入一控制器；該控制器將該多位元量化訊號依據代碼映射表輸出一保持訊號，並經由取樣迴路取得訊號後儲存，當該多位元量化訊號等於
Figure 02_image009
時依據代碼映射表輸出一取樣訊號，使取樣迴路進行取樣。 Another object of the present invention is to provide a multi-level noise reshaping conversion method, including: an input signal frequency and an output signal frequency are input to a signal processor; the signal processor is based on the input signal frequency and the output signal frequency The ratio of output is an input-output frequency ratio signal; the input-output frequency ratio signal is input to a delay feedback loop, and through one or more delays, a peak is output as the oscillation of the ratio of the input signal frequency to the output signal frequency The oscillating signal is input to a multi-level quantizer; the multi-level quantizer outputs a multi-bit quantized signal according to the oscillating signal, and the multi-bit quantized signal is obtained according to the following formula:
Figure 02_image035
; among them,
Figure 02_image003
Is the oscillating signal input in the nth stage, M is the preset level value of the multi-level quantizer,
Figure 02_image005
Is a floor function,
Figure 02_image037
The multi-bit quantized signal for the output nth stage; the multi-bit quantized signal is input to a controller; the controller outputs a hold signal according to the code mapping table for the multi-bit quantized signal, and obtains the signal through a sampling loop After storage, when the multi-bit quantized signal is equal to
Figure 02_image009
When outputting a sampling signal according to the code mapping table, the sampling loop can perform sampling.

更進一步地，該延遲回授迴路包含一第一加法器、一第二加法器、以及一延遲模組；其中該第一加法器的輸入端連接至該訊號處理器以及該延遲模組並於該第一加法器的輸出端輸出一第一訊號；其中該第二加法器的輸入端連接至該第一加法器的輸出端以及該多位階量化器的輸出端並於該第二加法器的輸出端輸出一第二訊號；其中該延遲模組的輸入端連接至該第二加法器的輸出端並於該延遲回授迴路的輸出端輸出一延遲補償訊號。Furthermore, the delay feedback loop includes a first adder, a second adder, and a delay module; wherein the input of the first adder is connected to the signal processor and the delay module and is connected to the signal processor and the delay module. The output terminal of the first adder outputs a first signal; wherein the input terminal of the second adder is connected to the output terminal of the first adder and the output terminal of the multi-level quantizer and is connected to the output terminal of the second adder The output terminal outputs a second signal; wherein the input terminal of the delay module is connected to the output terminal of the second adder and outputs a delay compensation signal at the output terminal of the delay feedback loop.

更進一步地，該延遲模組包括一第一延遲器、一係數乘法器、以及一第二延遲器；其中該第一延遲器的輸入端係連接至該第二延遲器的輸出端並於該第一延遲器的輸出端輸出一第一延遲訊號；該係數乘法器的輸入端係連接至該第二延遲器的輸出端並於該係數乘法器的輸出端輸出一係數加乘訊號；該第二延遲器的輸入端係連接至該第一加法器的輸出端並於該第二延遲器的輸出端輸出一第二延遲訊號；更進一步地，該第一加法器的輸入端連接至該訊號處理器、該係數乘法器的輸出端、以及該第二延遲器的輸出端並於該第一加法器的輸出端輸出該第一訊號。Furthermore, the delay module includes a first delay, a coefficient multiplier, and a second delay; wherein the input of the first delay is connected to the output of the second delay and connected to the The output terminal of the first delay device outputs a first delay signal; the input terminal of the coefficient multiplier is connected to the output terminal of the second delay device and outputs a coefficient multiplication signal at the output terminal of the coefficient multiplier; The input terminal of the second delay device is connected to the output terminal of the first adder and outputs a second delay signal at the output terminal of the second delay device; further, the input terminal of the first adder is connected to the signal The processor, the output terminal of the coefficient multiplier, and the output terminal of the second delay device output the first signal at the output terminal of the first adder.

更進一步地，該第二加法器輸出的該第二訊號依據下面的公式獲得：

Figure 02_image011
其中，
Figure 02_image013
為第n階段輸出的該第二加法訊號，
Figure 02_image015
為第n階段輸入的該多位元量化訊號，
Figure 02_image017
為第n階段輸入的該第一訊號。 Furthermore, the second signal output by the second adder is obtained according to the following formula:
Figure 02_image011
among them,
Figure 02_image013
Is the second addition signal output at the nth stage,
Figure 02_image015
Is the multi-bit quantized signal input in the nth stage,
Figure 02_image017
This is the first signal input at the nth stage.

更進一步地，該第一加法器輸出的該第一訊號依據下面的公式獲得：

Figure 02_image019
其中，
Figure 02_image017
為第n階段輸出的該第一訊號，
Figure 02_image021
為第n階段輸入的該輸入-輸出頻率比例訊號，
Figure 02_image023
為第
Figure 02_image025
階段輸入的該係數加乘訊號，
Figure 02_image027
為第
Figure 02_image029
階段輸入的該第二加法訊號。 Furthermore, the first signal output by the first adder is obtained according to the following formula:
Figure 02_image019
among them,
Figure 02_image017
Is the first signal output at the nth stage,
Figure 02_image021
Is the input-output frequency ratio signal input in the nth stage,
Figure 02_image023
For the first
Figure 02_image025
The multiplication signal of the coefficient input in the stage,
Figure 02_image027
For the first
Figure 02_image029
The second addition signal input in the stage.

更進一步地，該係數乘法器的該係數加乘訊號依據下面的公式獲得：

Figure 02_image031
其中，
Figure 02_image023
為第
Figure 02_image025
階段輸出的該係數加乘訊號，
Figure 02_image033
為第
Figure 02_image025
階段輸入的該第二加法訊號。 Furthermore, the coefficient multiplication signal of the coefficient multiplier is obtained according to the following formula:
Figure 02_image031
among them,
Figure 02_image023
For the first
Figure 02_image025
The multiplication signal of the coefficient output at the stage,
Figure 02_image033
For the first
Figure 02_image025
The second addition signal input in the stage.

更進一步地，該輸入-輸出頻率比例訊號最小值為0，最大值為1。Furthermore, the minimum value of the input-output frequency ratio signal is 0, and the maximum value is 1.

更進一步地，該多位元量化訊號為一整數構成之階梯波。Furthermore, the multi-bit quantized signal is a step wave composed of an integer.

本發明的另一目的，在於提供一種非暫存性電腦可讀取記錄媒體，係用於儲存一程式，當一訊號處理晶片載入該程式後將可執行如上述的方法。Another object of the present invention is to provide a non-transitory computer-readable recording medium for storing a program. When a signal processing chip loads the program, the above-mentioned method can be executed.

本發明比起習知技術具有以下優勢功效：Compared with the conventional technology, the present invention has the following advantages:

1.本發明可以使取樣迴路之取樣更加精確。1. The present invention can make the sampling of the sampling loop more accurate.

2.本發明可以使取樣迴路在升頻時取樣率更佳。2. The present invention can make the sampling rate of the sampling loop better when the frequency is increased.

有關本發明之詳細說明及技術內容，現就配合圖式說明如下。再者，本發明中之圖式，為說明方便，其比例未必照實際比例繪製，該等圖式及其比例並非用以限制本發明之範圍，在此先行敘明。The detailed description and technical content of the present invention will now be described in conjunction with the drawings as follows. Furthermore, for the convenience of description, the figures in the present invention are not necessarily drawn according to actual proportions. These figures and their proportions are not intended to limit the scope of the present invention, and are described here first.

以下係舉一具體實施例就本發明的技術內容提出詳細的說明，請一併參閱「圖1」及「圖2」，係揭示本發明多位階雜訊重塑式轉換系統與延遲回授迴路的方塊示意圖，如圖所示：The following is a specific embodiment to provide a detailed description of the technical content of the present invention. Please refer to "Figure 1" and "Figure 2" together to disclose the multi-level noise reshaping conversion system and delay feedback loop of the present invention. Schematic diagram of the block, as shown:

本發明提供一種多位階雜訊重塑式轉換系統100，配合一取樣迴路50設置，該多位階雜訊重塑式轉換系統100主要包括一訊號處理器10、一連接至該訊號處理器10的延遲回授迴路20、一連接至該延遲回授迴路20的多位階量化器30、以及一連接至該多位階量化器30的控制器40，該控制器40的輸出端與該取樣迴路50的前饋路徑連結。The present invention provides a multi-level noise reshaping conversion system 100, which is configured with a sampling loop 50. The multi-level noise reshaping conversion system 100 mainly includes a signal processor 10 and a signal processor 10 connected to the signal processor 10. Delay feedback loop 20, a multi-level quantizer 30 connected to the delay feedback loop 20, and a controller 40 connected to the multi-level quantizer 30, the output of the controller 40 and the sampling loop 50 Feed forward path link.

於本發明多位階雜訊重塑式轉換系統100中所述的控制器、量化器、模組、單元或迴路的組合及其對應執行的功能，可以由單一晶片或複數個晶片的組合協同執行，該等晶片配置的數量非屬本發明所欲限定的範圍。此外，所述的晶片可以為但不限定於處理器(Processor)、中央處理器(Central Processing Unit, CPU)、微處理器(Microprocessor)、數位訊號處理器(Digital Signal Processor, DSP)、特殊應用積體電路(Application Specific Integrated Circuits, ASIC)、可程式化邏輯裝置(Programmable Logic Device, PLD) 等可將資訊或訊號做處理轉換用途或特殊用途的其他類似裝置或這些裝置的組合，於本發明中不予以限制。 The combination of the controller, quantizer, module, unit, or loop described in the multi-level noise reshaping conversion system 100 of the present invention and their corresponding functions can be executed by a single chip or a combination of multiple chips. The number of these chip configurations is not within the scope of the present invention. In addition, the chip may be, but is not limited to, a processor (Processor), a central processing unit (CPU), a microprocessor (Microprocessor), a digital signal processor (DSP), special applications Integrated circuits (Application Specific Integrated Circuits, ASIC), Programmable Logic Device (Programmable Logic Device, PLD) and other similar devices or combinations of these devices that can process information or signals for conversion purposes or special purposes, in the present invention There is no restriction in it.

所述的控制器40內包含資料儲存單元，該資料儲存單元可以為但不限定於快取記憶體(Cache memory)、動態隨機存取記憶體(DRAM)、持續性記憶體(Persistent Memory)等可以做為儲存資料和取出資料用途之裝置或其組合，於本發明中不予以限制。The controller 40 includes a data storage unit, and the data storage unit may be, but is not limited to, cache memory, dynamic random access memory (DRAM), persistent memory, etc. It can be used as a device for storing data and fetching data, or a combination thereof, which is not limited in the present invention.

前述的該延遲回授迴路20包含一第一加法器22、一第二加法器24、以及一延遲模組26，其中，所述的該訊號處理器10輸出端連接至該第一加法器22的第一輸入端，該第一加法器22的輸出端連接至該第二加法器24的輸入端，該第一加法器22的輸出端連接至該多位階量化器30的輸入端，該多位階量化器30的輸出端連接至該第二加法器24的輸入端，該第二加法器24的輸出端連接至該延遲模組26的輸入端，該延遲模組26的輸出端連接至該第一加法器22的輸入端。The aforementioned delay feedback loop 20 includes a first adder 22, a second adder 24, and a delay module 26, wherein the output terminal of the signal processor 10 is connected to the first adder 22 The output of the first adder 22 is connected to the input of the second adder 24, the output of the first adder 22 is connected to the input of the multi-level quantizer 30, the output of the first adder 22 is connected to the input of the second adder 24. The output terminal of the level quantizer 30 is connected to the input terminal of the second adder 24, the output terminal of the second adder 24 is connected to the input terminal of the delay module 26, and the output terminal of the delay module 26 is connected to the The input terminal of the first adder 22.

所述的第一加法器22、第二加法器24可以為但不限定於加法器(Adder)電路、半加器(Half Adder)、全加器(Full adder)、波紋進位加法器、超前進位加法器實現、或其它用於執行加法運算的數位電路、邏輯閘、裝置或這些裝置的組合，於本發明中不予以限制。The first adder 22 and the second adder 24 can be, but are not limited to, an adder (Adder) circuit, a half adder (Half Adder), a full adder (Full adder), a ripple carry adder, and a super advance. The implementation of a bit adder, or other digital circuits, logic gates, devices or combinations of these devices used to perform addition operations are not limited in the present invention.

前述的該延遲模組26包括一第一延遲器262、第二延遲器264、以及一係數乘法器266。該第二延遲器264的輸出端連接至該第一延遲器262的輸入端，該第二延遲器264的輸出端連接至該係數乘法器266的輸入端，該第二延遲器264的輸入端連接至該第二加法器24的輸出端，該第一延遲器262的輸出端連接至該第一加法器22的第二輸入端，該係數乘法器266的輸出端連接至該第一加法器22的第三輸入端。The aforementioned delay module 26 includes a first delay 262, a second delay 264, and a coefficient multiplier 266. The output terminal of the second delay 264 is connected to the input terminal of the first delay 262, the output terminal of the second delay 264 is connected to the input terminal of the coefficient multiplier 266, and the input terminal of the second delay 264 Connected to the output terminal of the second adder 24, the output terminal of the first delay 262 is connected to the second input terminal of the first adder 22, and the output terminal of the coefficient multiplier 266 is connected to the first adder 22's third input terminal.

所述的第一延遲器262、第二延遲器264可以為但不限定於積分器(Integrator)、計數器(Counter)等可以做為訊號延遲或積分用途之電路或其組合，於本發明中不予以限制。The first delay 262 and the second delay 264 can be, but are not limited to, integrators, counters, etc., which can be used as circuits for signal delay or integration, or a combination thereof. Be restricted.

所述的係數乘法器266可以為但不限定於乘法器(Multiplier)電路、加法器(Adder)、反向放大器(Reversing Amplifier)等可以做為加乘放大訊號用途之電路或其組合，於本發明中不予以限制。The coefficient multiplier 266 can be, but is not limited to, a multiplier (Multiplier) circuit, an adder (Adder), a reversing amplifier (Reversing Amplifier), etc., which can be used as a circuit for multiplying and amplifying signals or a combination thereof. There is no limitation in the invention.

上述為本發明多位階雜訊重塑式轉換系統之結構與連結內容，以下將描述本發明多位階雜訊重塑式轉換系統中訊號之傳遞進行詳述。The above is the structure and connection content of the multi-level noise reshaping conversion system of the present invention. The signal transmission in the multi-level noise reshaping conversion system of the present invention will be described in detail below.

該訊號處理器10依據所需轉換的輸入訊號頻率與預期輸出訊號頻率的比值輸出一輸入-輸出頻率比例訊號至該延遲回授迴路20，其中，該比值分母為輸出訊號頻率，分子為輸入訊號頻率，而輸入-輸出頻率比例訊號於本實施態樣中最小值為0，最大值為1。於其他實施態樣中，該比例數值可根據實際情況進行調整，於本發明中不予以限制。The signal processor 10 outputs an input-output frequency ratio signal to the delayed feedback loop 20 according to the ratio of the input signal frequency to be converted to the expected output signal frequency, wherein the denominator of the ratio is the output signal frequency and the numerator is the input signal Frequency, and the input-output frequency ratio signal in this embodiment has a minimum value of 0 and a maximum value of 1. In other implementation aspects, the ratio value can be adjusted according to actual conditions, and is not limited in the present invention.

當該輸入-輸出頻率比例訊號輸入至該延遲回授電路20，通過一或複數個延遲器輸出一震盪訊號至該多位階量化器30。When the input-output frequency ratio signal is input to the delay feedback circuit 20, an oscillating signal is output to the multi-level quantizer 30 through one or more delays.

具體而言，所述的延遲回授電路20之內部元件詳述如下，當該輸入-輸出頻率比例訊號進入該延遲回授模組20的第一加法器22，該第一加法器22輸出一第一訊號至該第二加法器24與該多位階量化器30，該第二加法器24輸出一第二訊號至該延遲模組26的第二延遲器264，該第二延遲器264輸出一第二延遲訊號至該第一延遲器262與該係數乘法器266，該第一延遲器262輸出一第一延遲訊號至該第一加法器22，該係數乘法器266輸出一係數加乘訊號至該第一加法器22。Specifically, the internal components of the delay feedback circuit 20 are detailed as follows. When the input-output frequency ratio signal enters the first adder 22 of the delay feedback module 20, the first adder 22 outputs a The first signal to the second adder 24 and the multi-level quantizer 30, the second adder 24 outputs a second signal to the second delay 264 of the delay module 26, and the second delay 264 outputs a The second delay signal is sent to the first delay 262 and the coefficient multiplier 266, the first delay 262 outputs a first delay signal to the first adder 22, and the coefficient multiplier 266 outputs a coefficient addition signal to The first adder 22.

其中，該第一訊號所構成之連續訊號為該震盪訊號，該震盪訊號的波峰為該輸入訊號頻率與該輸出訊號頻率比值，而該第一延遲訊號與該係數加乘訊號為該延遲模組26的一延遲補償訊號。Wherein, the continuous signal formed by the first signal is the oscillating signal, the peak of the oscillating signal is the ratio of the frequency of the input signal to the frequency of the output signal, and the first delay signal and the coefficient multiplication signal are the delay module A delay compensation signal of 26.

前述的該第一加法器22輸出的該第一訊號、第二加法器24輸出的該第二訊號、係數乘法器266的該係數加乘訊號依據相關的公式獲得，依序如下：The aforementioned first signal output by the first adder 22, the second signal output by the second adder 24, and the coefficient multiplication signal of the coefficient multiplier 266 are obtained according to related formulas, and the sequence is as follows:

該第一加法器22輸出的該第一訊號依據下面的公式獲得：

Figure 02_image039
； 其中，
Figure 02_image017
為第n階段輸出的該第一訊號，
Figure 02_image021
為第n階段輸入的該輸入-輸出頻率比例訊號，
Figure 02_image023
為第
Figure 02_image025
階段輸入的該係數加乘訊號，
Figure 02_image027
為第
Figure 02_image029
階段輸入的該第二加法訊號。上述公式可藉由反向器、反向器的組合或邏輯閘、邏輯閘的組合達成上述公式之運算內容，於本發明中不予以限制。 The first signal output by the first adder 22 is obtained according to the following formula:
Figure 02_image039
; among them,
Figure 02_image017
Is the first signal output at the nth stage,
Figure 02_image021
Is the input-output frequency ratio signal input in the nth stage,
Figure 02_image023
For the first
Figure 02_image025
The multiplication signal of the coefficient input in the stage,
Figure 02_image027
For the first
Figure 02_image029
The second addition signal input in the stage. The above formula can be achieved by a combination of inverters and inverters or a combination of logic gates and logic gates, which is not limited in the present invention.

該第二加法器24輸出的該第二訊號依據下面的公式獲得：

Figure 02_image011
其中，
Figure 02_image013
為第n階段輸出的該第二加法訊號，
Figure 02_image015
為第n階段輸入的該多位元量化訊號，
Figure 02_image017
為第n階段輸入的該第一訊號。該第二加法器24於接收該第一訊號時，可藉由加法器本身的減法輸入端輸入，使訊號相減或反向，亦可藉由增加反向器或反向器的組合使該訊號得以相減或反向，於本發明中不予以限制。 The second signal output by the second adder 24 is obtained according to the following formula:
Figure 02_image011
among them,
Figure 02_image013
Is the second addition signal output at the nth stage,
Figure 02_image015
Is the multi-bit quantized signal input in the nth stage,
Figure 02_image017
This is the first signal input at the nth stage. When the second adder 24 receives the first signal, it can subtract or invert the signal by inputting the subtraction input of the adder itself, or it can be increased by adding an inverter or a combination of inverters. The signal can be subtracted or reversed, which is not limited in the present invention.

該係數乘法器266的該係數加乘訊號依據下面的公式獲得：

Figure 02_image031
其中，
Figure 02_image023
為第
Figure 02_image025
階段輸出的該係數加乘訊號，
Figure 02_image033
為第
Figure 02_image025
階段輸入的該第二加法訊號。 The coefficient multiplication signal of the coefficient multiplier 266 is obtained according to the following formula:
Figure 02_image031
among them,
Figure 02_image023
For the first
Figure 02_image025
The multiplication signal of the coefficient output at the stage,
Figure 02_image033
For the first
Figure 02_image025
The second addition signal input in the stage.

當前述經由該延遲回授電路20輸出之震盪訊號輸入一多位階量化器30後，該多位階量化器30輸出一多位元量化訊號至一控制器40，該多位元量化訊號係依據下面的公式獲得：

Figure 02_image035
； 其中，
Figure 02_image017
為第n階段輸入的第一訊號，該第一訊號所構成之連續訊號為該震盪訊號，M為該多位階量化器預設的位階數值，
Figure 02_image041
為一floor函數，
Figure 02_image015
為所輸出第n階段的該多位元量化訊號，該多位元量化訊號為一整數構成之階梯波，當該多位元量化訊號輸入過小時，亦可產生一方波，於本發明中不予以限制。 When the aforementioned oscillating signal output by the delayed feedback circuit 20 is input to a multi-level quantizer 30, the multi-level quantizer 30 outputs a multi-bit quantized signal to a controller 40, and the multi-bit quantized signal is based on the following The formula is obtained:
Figure 02_image035
; among them,
Figure 02_image017
Is the first signal input in the nth stage, the continuous signal formed by the first signal is the oscillating signal, and M is the preset level value of the multi-level quantizer,
Figure 02_image041
Is a floor function,
Figure 02_image015
Is the outputted multi-bit quantized signal of the nth stage. The multi-bit quantized signal is a step wave composed of an integer. When the input of the multi-bit quantized signal is too small, a square wave can also be generated. In the present invention, Be restricted.

當該控制器40收到由該延遲回授電路20輸出該多位元量化訊號後，將該多位元量化訊號依據代碼映射表(如下)輸出一保持訊號至該取樣迴路50，該取樣迴路50根據該保持訊號將當下訊號或前一尚未取樣訊號將其儲存至該資料儲存單元。When the controller 40 receives the multi-bit quantized signal output by the delay feedback circuit 20, the multi-bit quantized signal outputs a hold signal to the sampling loop 50 according to the code mapping table (below). 50 According to the holding signal, the current signal or the previous unsampled signal is stored in the data storage unit.

具體而言，當該多位元量化訊號為0時，輸出保持訊號並將該尚未取樣訊號儲存

Figure 02_image009
次，當該多位元量化訊號為1時，輸出保持訊號並將該尚未取樣訊號儲存
Figure 02_image043
次，依此類推，直至該多位元量化訊號等於
Figure 02_image009
時依據代碼映射表輸出一取樣訊號至該取樣迴路50，並經由該取樣迴路取出當下訊號或尚未取樣訊號。 Specifically, when the multi-bit quantized signal is 0, output the hold signal and store the unsampled signal
Figure 02_image009
Second, when the multi-bit quantized signal is 1, output the hold signal and store the unsampled signal
Figure 02_image043
Times, and so on, until the multi-bit quantized signal is equal to
Figure 02_image009
According to the code mapping table, a sampling signal is output to the sampling loop 50, and the current signal or the unsampled signal is taken out through the sampling loop.

其中，取樣迴路50第一次收到取樣訊號會擷取當下訊號，之後將尚未取樣訊號進行重複儲存，直到下一次的取樣訊號，取出上述重複儲存的尚未取樣訊號的第一次儲存的尚未取樣訊號，而不會對其餘重複儲存的尚未取樣訊號進行取出。Among them, the sampling circuit 50 captures the current signal the first time it receives the sampled signal, and then repeatedly stores the unsampled signal until the next sampled signal, and retrieves the unsampled first stored unsampled signal of the repeatedly stored unsampled signal. Signal without taking out the remaining repeatedly stored unsampled signals.

多位元量化訊號 Multi-bit quantized signal 保持或取樣 Hold or sample 0 0 保持並儲存尚未取樣訊號

Figure 02_image045
次 Keep and store unsampled signals
Figure 02_image045
Times 1 1 保持並儲存尚未取樣訊號
Figure 02_image047
Keep and store unsampled signals
Figure 02_image047
 : : : : : : : :
Figure 02_image049
Figure 02_image049
 保持並儲存尚未取樣訊號1次 Keep and store the unsampled signal once
Figure 02_image045
Figure 02_image045
 取出當下訊號 Take out the current signal

以下係舉一具體實施例就本發明的技術內容提出詳細的說明，請參閱「圖3」，係揭示本發明多位階雜訊重塑式轉換系統流程示意圖，本發明多位階雜訊重塑式轉換方法如圖所示：The following is a specific embodiment to provide a detailed description of the technical content of the present invention. Please refer to "FIG. 3", which shows a schematic diagram of the process flow of the multi-level noise reshaping conversion system of the present invention. The conversion method is shown in the figure:

訊號處理器依據輸入訊號頻率與輸出訊號頻率的比值輸出一輸入-輸出頻率比例訊號至該延遲回授迴路(步驟S201)。The signal processor outputs an input-output frequency ratio signal to the delay feedback loop according to the ratio of the input signal frequency to the output signal frequency (step S201).

上述該比值分母為輸出訊號頻率，分子為輸入訊號頻率，而輸入-輸出頻率比例訊號於本實施態樣中最小值為0，最大值為1。於其他實施態樣中，該比例數值可根據實際情況進行調整，於本發明中不予以限制。The denominator of the ratio is the frequency of the output signal, and the numerator is the frequency of the input signal. The input-output frequency ratio signal in this embodiment has a minimum value of 0 and a maximum value of 1. In other embodiments, the ratio value can be adjusted according to actual conditions, and is not limited in the present invention.

延遲回授電路接收該輸入-輸出頻率比例訊號轉成一震盪訊號(S202)。The delay feedback circuit receives the input-output frequency ratio signal and converts it into an oscillating signal (S202).

具體而言，當該輸入-輸出頻率比例訊號進入該延遲回授模組20的第一加法器22，該第一加法器22輸出一第一訊號至該第二加法器24與該多位階量化器30，該第二加法器24輸出一第二訊號至該延遲模組26的第二延遲器264，該第二延遲器264輸出一第二延遲訊號至該第一延遲器262與該係數乘法器266，該第一延遲器262輸出一第一延遲訊號至該第一加法器22，該係數乘法器266輸出一係數加乘訊號至該第一加法器22。Specifically, when the input-output frequency ratio signal enters the first adder 22 of the delay feedback module 20, the first adder 22 outputs a first signal to the second adder 24 and the multi-level quantization 30, the second adder 24 outputs a second signal to the second delay 264 of the delay module 26, the second delay 264 outputs a second delay signal to the first delay 262 and the coefficient multiplication 266, the first delay 262 outputs a first delay signal to the first adder 22, and the coefficient multiplier 266 outputs a coefficient multiplication signal to the first adder 22.

其中，該第一訊號所構成之連續訊號為該震盪訊號，該震盪訊號的波峰為該輸入訊號頻率與該輸出訊號頻率比值，而該第一延遲訊號與該係數加乘訊號為該延遲模組26的一延遲補償訊號。Wherein, the continuous signal formed by the first signal is the oscillating signal, the peak of the oscillating signal is the ratio of the frequency of the input signal to the frequency of the output signal, and the first delay signal and the coefficient multiplication signal are the delay module A delay compensation signal of 26.

前述的該第一加法器22輸出的該第一訊號、第二加法器24輸出的該第二訊號、係數乘法器266的該係數加乘訊號依據相關的公式獲得，依序如下：The aforementioned first signal output by the first adder 22, the second signal output by the second adder 24, and the coefficient multiplication signal of the coefficient multiplier 266 are obtained according to related formulas, and the sequence is as follows:

該第一加法器22輸出的該第一訊號依據下面的公式獲得：

Figure 02_image051
其中，
Figure 02_image017
為第n階段輸出的該第一訊號，
Figure 02_image021
為第n階段輸入的該輸入-輸出頻率比例訊號，
Figure 02_image023
為第
Figure 02_image025
階段輸入的該係數加乘訊號，
Figure 02_image027
為第
Figure 02_image029
階段輸入的該第二加法訊號。上述公式可藉由反向器、反向器的組合或邏輯閘、邏輯閘的組合達成上述公式之運算內容，於本發明中不予以限制。 The first signal output by the first adder 22 is obtained according to the following formula:
Figure 02_image051
among them,
Figure 02_image017
Is the first signal output at the nth stage,
Figure 02_image021
Is the input-output frequency ratio signal input in the nth stage,
Figure 02_image023
For the first
Figure 02_image025
The multiplication signal of the coefficient input in the stage,
Figure 02_image027
For the first
Figure 02_image029
The second addition signal input in the stage. The above formula can be achieved by a combination of inverters and inverters or a combination of logic gates and logic gates, which is not limited in the present invention.

該第二加法器24輸出的該第二訊號依據下面的公式獲得：

Figure 02_image011
其中，
Figure 02_image013
為第n階段輸出的該第二加法訊號，Y[n]為第n階段輸入的該多位元量化訊號，
Figure 02_image017
為第n階段輸入的該第一訊號。該第二加法器24於接收該第一訊號時，可藉由加法器本身的減法輸入端輸入，使訊號相減或反向，亦可藉由增加反向器或反向器的組合使該訊號得以相減或反向，於本發明中不予以限制。 The second signal output by the second adder 24 is obtained according to the following formula:
Figure 02_image011
among them,
Figure 02_image013
Is the second addition signal output in the nth stage, Y[n] is the multi-bit quantized signal input in the nth stage,
Figure 02_image017
This is the first signal input at the nth stage. When the second adder 24 receives the first signal, it can subtract or invert the signal by inputting the subtraction input of the adder itself, or it can be increased by adding an inverter or a combination of inverters. The signal can be subtracted or reversed, which is not limited in the present invention.

該係數乘法器266的該係數加乘訊號依據下面的公式獲得：

Figure 02_image031
其中，
Figure 02_image023
為第
Figure 02_image025
階段輸出的該係數加乘訊號，
Figure 02_image033
為第
Figure 02_image025
階段輸入的該第二加法訊號。 The coefficient multiplication signal of the coefficient multiplier 266 is obtained according to the following formula:
Figure 02_image031
among them,
Figure 02_image023
For the first
Figure 02_image025
The multiplication signal of the coefficient output at the stage,
Figure 02_image033
For the first
Figure 02_image025
The second addition signal input in the stage.

多位階量化器將該震盪訊號轉成一多位元量化訊號至一控制器(S203)。The multi-level quantizer converts the oscillating signal into a multi-bit quantized signal to a controller (S203).

該多位元量化訊號係依據下面的公式獲得：

Figure 02_image035
； 其中，
Figure 02_image017
為第n階段輸入的第一訊號，該第一訊號所構成之連續訊號為該震盪訊號，M為該多位階量化器預設的位階數值，
Figure 02_image041
為一floor函數，
Figure 02_image015
為所輸出第n階段的該多位元量化訊號，該多位元量化訊號為一整數構成之階梯波，當該多位元量化訊號輸入過小時，亦可產生一方波，於本發明中不予以限制。 The multi-bit quantized signal is obtained according to the following formula:
Figure 02_image035
; among them,
Figure 02_image017
Is the first signal input in the nth stage, the continuous signal formed by the first signal is the oscillating signal, and M is the preset level value of the multi-level quantizer,
Figure 02_image041
Is a floor function,
Figure 02_image015
Is the outputted multi-bit quantized signal of the nth stage. The multi-bit quantized signal is a step wave composed of an integer. When the input of the multi-bit quantized signal is too small, a square wave can also be generated. In the present invention, Be restricted.

控制器根據該代碼映射表輸出保持訊號或取樣訊號至一取樣迴路，經由該取樣迴路儲存訊號或進行取樣 (S204)。The controller outputs the hold signal or the sampling signal to a sampling loop according to the code mapping table, and stores the signal or performs sampling through the sampling loop (S204).

當該控制器40收到由該延遲回授電路20輸出該多位元量化訊號後，將該多位元量化訊號依據代碼映射表(如下)輸出一保持訊號至該取樣迴路50，該取樣迴路50根據該保持訊號將當下訊號或前一尚未取樣訊號將其儲存至該資料儲存單元。When the controller 40 receives the multi-bit quantized signal output by the delay feedback circuit 20, the multi-bit quantized signal outputs a hold signal to the sampling loop 50 according to the code mapping table (below). 50 According to the holding signal, the current signal or the previous unsampled signal is stored in the data storage unit.

具體而言，當該多位元量化訊號為0時，輸出保持訊號並將該尚未取樣訊號儲存

Figure 02_image009
次，當該多位元量化訊號為1時，輸出保持訊號並將該尚未取樣訊號儲存
Figure 02_image043
次，依此類推，直至該多位元量化訊號等於
Figure 02_image009
時依據代碼映射表輸出一取樣訊號至該取樣迴路50，並經由該取樣迴路取出當下訊號或尚未取樣訊號。 Specifically, when the multi-bit quantized signal is 0, output the hold signal and store the unsampled signal
Figure 02_image009
Second, when the multi-bit quantized signal is 1, output the hold signal and store the unsampled signal
Figure 02_image043
Times, and so on, until the multi-bit quantized signal is equal to
Figure 02_image009
According to the code mapping table, a sampling signal is output to the sampling loop 50, and the current signal or the unsampled signal is taken out through the sampling loop.

其中，取樣迴路50第一次收到取樣訊號會擷取當下訊號，之後將尚未取樣訊號進行重複儲存，直到下一次的取樣訊號，取出上述重複儲存的尚未取樣訊號的第一次儲存的尚未取樣訊號，而不會對其餘重複儲存的尚未取樣訊號進行取出。Among them, the sampling circuit 50 captures the current signal the first time it receives the sampled signal, and then repeatedly stores the unsampled signal until the next sampled signal, and retrieves the unsampled first stored unsampled signal of the repeatedly stored unsampled signal. Signal without taking out the remaining repeatedly stored unsampled signals.

多位元量化訊號 Multi-bit quantized signal 保持或取樣 Hold or sample 0 0 保持並儲存尚未取樣訊號

Figure 02_image045
次 Keep and store unsampled signals
Figure 02_image045
Times 1 1 保持並儲存尚未取樣訊號
Figure 02_image047
Keep and store unsampled signals
Figure 02_image047
 : : : : : : : :
Figure 02_image049
Figure 02_image049
 保持並儲存尚未取樣訊號1次 Keep and store the unsampled signal once
Figure 02_image045
Figure 02_image045
 取出當下訊號 Take out the current signal

本發明之方法亦可記錄於電腦可讀取記錄媒體，所述的「電腦可讀取記錄媒體」包括(但不限於)攜帶型或非攜帶型儲存裝置、光儲存器件，及能夠儲存、含有或攜載指令及/或資料之各種其他媒體。電腦可讀取記錄媒體可包括非暫存性媒體，其中可儲存資料並且不包括載波及/或無線地或經由有線連接傳播之暫時電子信號。The method of the present invention can also be recorded on a computer-readable recording medium. The "computer-readable recording medium" includes (but is not limited to) portable or non-portable storage devices, optical storage devices, and capable of storing and containing Or various other media that carry instructions and/or information. The computer-readable recording medium may include a non-transitory storage medium in which data can be stored and does not include carrier waves and/or temporary electronic signals transmitted wirelessly or via wired connections.

非暫存性媒體之實例可包括(但不限於)磁碟或磁帶、諸如緊密光碟(CD)或數位化通用光碟(DVD)之光學儲存媒體、快閃記憶體、記憶體或記憶體器件。Examples of non-transitory media may include, but are not limited to, magnetic disks or tapes, optical storage media such as compact discs (CD) or digital versatile discs (DVD), flash memory, memory, or memory devices.

電腦可讀取記錄媒體可具有儲存於其上之代碼及/或機器可執行指令，該等代碼及/或機器可執行指令可表示程序、函數、子程式、程式、常式、次常式、模組、軟體套件、類別，或指令、資料結構或程式語句之任何組合。一個碼段可藉由傳遞及/或接收資訊、資料、引數、參數或記憶體內容耦接至另一碼段或硬體電路。資訊、引數、參數、資料等可經由包括記憶體共用、訊息傳遞、符記傳遞、網路傳輸或類似者之任何合適方式傳遞、轉遞或傳輸。The computer-readable recording medium may have codes and/or machine-executable instructions stored thereon, and these codes and/or machine-executable instructions may represent programs, functions, subroutines, programs, routines, subroutines, Modules, software packages, categories, or any combination of commands, data structures, or program statements. A code segment can be coupled to another code segment or hardware circuit by transmitting and/or receiving information, data, parameters, parameters, or memory content. Information, parameters, parameters, data, etc. can be transferred, transferred or transmitted via any suitable means including memory sharing, message transfer, token transfer, network transfer or the like.

此外，可由硬體、軟體、韌體、中間軟體、微碼、硬體描述語言或其任何組合實施實施例。當實施於軟體、韌體、中間軟體或微碼中時，用以執行必要任務之程式碼或碼段(例如電腦程式產品)可儲存於電腦可讀或機器可讀媒體中。處理器可執行必要任務。In addition, the embodiments may be implemented by hardware, software, firmware, middleware, microcode, hardware description language, or any combination thereof. When implemented in software, firmware, middleware, or microcode, the code or code segments (such as computer program products) used to perform the necessary tasks can be stored in a computer-readable or machine-readable medium. The processor can perform the necessary tasks.

綜上所述，本發明多位階雜訊重塑式轉換系統、方法及非暫存性電腦可讀取紀錄媒體可以使取樣迴路之取樣更加精確，再者，可以使取樣迴路在升頻時取樣率更佳。In summary, the multi-level noise reshaping conversion system, method, and non-temporary computer-readable recording medium of the present invention can make the sampling of the sampling loop more accurate. Furthermore, the sampling loop can sample during up-frequency. The rate is better.

以上已將本發明做一詳細說明，惟以上所述者，僅為本發明之一較佳實施例而已，當不能以此限定本發明實施之範圍，即凡依本發明申請專利範圍所作之均等變化與修飾，皆應仍屬本發明之專利涵蓋範圍內。The present invention has been described in detail above, but what is described above is only a preferred embodiment of the present invention, and should not be used to limit the scope of implementation of the present invention, that is, everything made in accordance with the scope of the patent application of the present invention is equal Changes and modifications should still fall within the scope of the patent of the present invention.

100       多位階雜訊重塑式轉換系統 10         訊號處理器 20         延遲回授迴路 22       第一加法器 24       第二加法器 26       延遲模組 262     第一延遲器 264     第二延遲器 266     係數乘法器 30       多位階量化器 40       控制器 50       取樣迴路 步驟S201-204 100 Multi-level noise reshaping conversion system 10 Signal processor 20 Delayed feedback loop 22 First adder 24 The second adder 26 Delay module 262 First retarder 264 Second delay 266 Coefficient multiplier 30 Multi-level quantizer 40 Controller 50 Sampling circuit Steps S201-204

圖1，本發明多位階雜訊重塑式轉換系統的方塊示意圖。FIG. 1 is a block diagram of the multi-level noise reshaping conversion system of the present invention.

圖2，本發明延遲回授迴路的方塊示意圖。Figure 2 is a block diagram of the delayed feedback loop of the present invention.

圖3，本發明多位階雜訊重塑式轉換系統的流程示意圖Figure 3, a schematic flow diagram of the multi-level noise reshaping conversion system of the present invention

100       多位階雜訊重塑式轉換系統 10         訊號處理器 20         延遲回授迴路 30       多位階量化器 40       控制器 50       取樣迴路 100 Multi-level noise reshaping conversion system 10 Signal processor 20 Delayed feedback loop 30 Multi-level quantizer 40 Controller 50 Sampling circuit

Claims (17)

一種多位階雜訊重塑式轉換系統，配合一取樣迴路設置，該多位階雜訊重塑式轉換系統包括：一訊號處理器，依據輸入訊號頻率與輸出訊號頻率的比值輸出一輸入-輸出頻率比例訊號；一延遲回授迴路，該延遲回授迴路的輸入端連接至該訊號處理器以接收該輸入-輸出頻率比例訊號，並通過一或複數個延遲器輸出一波峰為該輸入訊號頻率與該輸出訊號頻率比值的震盪訊號；一多位階量化器，該多位階量化器的輸入端連接至該延遲回授迴路以接收該震盪訊號，並依據該震盪訊號輸出一多位元量化訊號，該多位元量化訊號係依據下面的公式獲得：
Figure 108143895-A0305-02-0020-1
 其中，X[n]為第n階段輸入的該震盪訊號，M為該多位階量化器預設的位階數值，floor( )為一floor函數，Y[n]為所輸出第n階段的該多位元量化訊號；以及一控制器，連結至該取樣迴路的前饋路徑，該控制器的輸入端連接至該多位階量化器以接收該多位元量化訊號，將該多位元量化訊號依據代碼映射表輸出一保持訊號，並經由取樣迴路取得訊號後儲存至一資料儲存單元，當該多位元量化訊號等於2M-1時依據代碼映射表輸出一取樣訊號至該取樣迴路，使該取樣迴路進行取樣。 A multi-level noise reshaping conversion system, which is configured with a sampling loop. The multi-level noise reshaping conversion system includes: a signal processor, which outputs an input-output frequency according to the ratio of the input signal frequency to the output signal frequency Proportional signal; a delayed feedback loop, the input of the delayed feedback loop is connected to the signal processor to receive the input-output frequency proportional signal, and output a peak of the input signal frequency through one or more delays The output signal frequency ratio oscillation signal; a multi-level quantizer, the input end of the multi-level quantizer is connected to the delay feedback loop to receive the oscillation signal, and output a multi-bit quantized signal according to the oscillation signal, the The multi-bit quantized signal is obtained according to the following formula:
Figure 108143895-A0305-02-0020-1
 Among them, X[n] is the oscillating signal input at the nth stage, M is the preset level value of the multi-level quantizer, floor() is a floor function, and Y[n] is the output of the nth stage Bit quantized signal; and a controller connected to the feedforward path of the sampling loop, the input of the controller is connected to the multi-level quantizer to receive the multi-bit quantized signal, and the multi-bit quantized signal is based on The code mapping table outputs a holding signal, and the signal is obtained through the sampling circuit and then stored in a data storage unit. When the multi-bit quantized signal is equal to 2 M -1, a sampling signal is output to the sampling circuit according to the code mapping table to make the The sampling loop performs sampling. 如申請專利範圍第1項所述的多位階雜訊重塑式轉換系統，其中該延遲回授迴路包含一第一加法器、一第二加法器、以及一延遲模組；其中該第一加法器的輸入端連接至該訊號處理器以及該延遲模組並於該第 一加法器的輸出端輸出一第一訊號；其中該第二加法器的輸入端連接至該第一加法器的輸出端以及該多位階量化器的輸出端並於該第二加法器的輸出端輸出一第二訊號；其中該延遲模組的輸入端連接至該第二加法器的輸出端並於該延遲回授迴路的輸出端輸出一延遲補償訊號。 According to the multi-level noise reshaping conversion system described in claim 1, wherein the delay feedback loop includes a first adder, a second adder, and a delay module; wherein the first adder The input end of the converter is connected to the signal processor and the delay module and is connected to the The output terminal of an adder outputs a first signal; wherein the input terminal of the second adder is connected to the output terminal of the first adder and the output terminal of the multi-level quantizer and is connected to the output terminal of the second adder A second signal is output; wherein the input terminal of the delay module is connected to the output terminal of the second adder and a delay compensation signal is output at the output terminal of the delay feedback loop. 如申請專利範圍第2項所述的多位階雜訊重塑式轉換系統，其中該延遲模組包括一第一延遲器、一係數乘法器、以及一第二延遲器；其中該第一延遲器的輸入端係連接至該第二延遲器的輸出端並於該第一延遲器的輸出端輸出一第一延遲訊號；其中該係數乘法器的輸入端係連接至該第二延遲器的輸出端並於該係數乘法器的輸出端輸出一係數加乘訊號；其中該第二延遲器的輸入端係連接至該第一加法器的輸出端並於該第二延遲器的輸出端輸出一第二延遲訊號；其中該第一加法器的輸入端連接至該訊號處理器、該係數乘法器的輸出端、以及該第二延遲器的輸出端並於該第一加法器的輸出端輸出該第一訊號。 The multi-level noise reshaping conversion system described in claim 2, wherein the delay module includes a first delay, a coefficient multiplier, and a second delay; wherein the first delay The input terminal of is connected to the output terminal of the second delay device and outputs a first delay signal at the output terminal of the first delay device; wherein the input terminal of the coefficient multiplier is connected to the output terminal of the second delay device And output a coefficient multiplication signal at the output terminal of the coefficient multiplier; wherein the input terminal of the second delay device is connected to the output terminal of the first adder and outputs a second delay device at the output terminal of the second delay device. Delay signal; wherein the input terminal of the first adder is connected to the signal processor, the output terminal of the coefficient multiplier, and the output terminal of the second delayer, and the first adder is output at the output terminal of the first adder Signal. 如申請專利範圍第2項所述的多位階雜訊重塑式轉換系統，其中該第二加法器輸出的該第二訊號依據下面的公式獲得：A2[n]=Y[n]-X[n]；其中，A2[n]為第n階段輸出的該第二加法訊號，Y[n]為第n階段輸入的該多位元量化訊號，X[n]為第n階段輸入的該第一訊號。 For the multi-level noise reshaping conversion system described in item 2 of the scope of patent application, the second signal output by the second adder is obtained according to the following formula: A2[n]=Y[n]-X[ n]; where A2[n] is the second addition signal output in the nth stage, Y[n] is the multi-bit quantized signal input in the nth stage, and X[n] is the second addition signal input in the nth stage One signal. 如申請專利範圍第3項所述的多位階雜訊重塑式轉換系統，其中該第一加法器輸出的該第一訊號依據下面的公式獲得：X[n]=S[n]-T[n-1]+A2[n-2]； 其中，X[n]為第n階段輸出的該第一訊號，S[n]為第n階段輸入的該輸入-輸出頻率比例訊號，T[n-1]為第n-1階段輸入的該係數加乘訊號，A2[n-2]為第n-2階段輸入的該第二加法訊號。 The multi-level noise reshaping conversion system described in item 3 of the scope of patent application, wherein the first signal output by the first adder is obtained according to the following formula: X[n]=S[n]-T[ n-1]+A2[n-2]; Among them, X[n] is the first signal output in the nth stage, S[n] is the input-output frequency ratio signal input in the nth stage, and T[n-1] is the input signal in the n-1 stage The coefficient addition signal, A2[n-2] is the second addition signal input in the n-2th stage. 如申請專利範圍第3項所述的多位階雜訊重塑式轉換系統，其中該係數乘法器的該係數加乘訊號依據下面的公式獲得：T[n-1]=2×A2[n-1]；其中，T[n-1]為第n-1階段輸出的該係數加乘訊號，A2[n-1]為第n-1階段輸入的該第二加法訊號。 For the multi-level noise reshaping conversion system described in item 3 of the scope of patent application, the coefficient multiplication signal of the coefficient multiplier is obtained according to the following formula: T[n-1]=2×A2[n- 1]; where T[n-1] is the coefficient multiplication signal output in the n-1 stage, and A2[n-1] is the second addition signal input in the n-1 stage. 如申請專利範圍第1項所述的多位階雜訊重塑式轉換系統，其中該輸入-輸出頻率比例訊號最小值為0，最大值為1。 For the multi-level noise reshaping conversion system described in item 1 of the scope of patent application, the minimum value of the input-output frequency ratio signal is 0 and the maximum value is 1. 如申請專利範圍第1項所述的多位階雜訊重塑式轉換系統，其中該多位元量化訊號為一整數構成之階梯波。 In the multi-level noise reshaping conversion system described in item 1 of the scope of patent application, the multi-bit quantized signal is a step wave composed of an integer. 一種多位階雜訊重塑式轉換方法，包括：一輸入訊號頻率與一輸出訊號頻率輸入至一訊號處理器；該訊號處理器依據輸入訊號頻率與輸出訊號頻率的比值輸出一輸入-輸出頻率比例訊號；該輸入-輸出頻率比例訊號輸入至一延遲回授迴路，並通過一或複數個延遲器輸出一波峰為該輸入訊號頻率與該輸出訊號頻率比值的震盪訊號；該震盪訊號輸入一多位階量化器；該多位階量化器依據該震盪訊號輸出一多位元量化訊號，該多位元量化訊號係依據下面的公式獲得：
Figure 108143895-A0305-02-0022-2
 其中，X[n]為第n階段輸入的震盪訊號，M為該多位階量化器預設的位階數值，floor( )為一floor函數，Y[n]為所輸出第n階段的該多位元量化訊號； 該多位元量化訊號輸入一控制器；以及該控制器將該多位元量化訊號依據代碼映射表輸出一保持訊號，並經由取樣迴路取得訊號後儲存至一資料儲存單元，當該多位元量化訊號等於2M-1時依據代碼映射表輸出一取樣訊號至該取樣迴路的前饋路徑，使該取樣迴路進行取樣。 A multi-level noise reshaping conversion method includes: an input signal frequency and an output signal frequency are input to a signal processor; the signal processor outputs an input-output frequency ratio according to the ratio of the input signal frequency to the output signal frequency Signal; the input-output frequency ratio signal is input to a delay feedback loop, and a peak is output through one or more delays as an oscillation signal of the ratio of the input signal frequency to the output signal frequency; the oscillation signal inputs a multi-level Quantizer; the multi-level quantizer outputs a multi-bit quantized signal according to the oscillating signal, and the multi-bit quantized signal is obtained according to the following formula:
Figure 108143895-A0305-02-0022-2
 Among them, X[n] is the oscillating signal input at the nth stage, M is the preset level value of the multi-level quantizer, floor() is a floor function, and Y[n] is the output of the nth stage. The multi-bit quantized signal; the multi-bit quantized signal is input to a controller; and the controller outputs a holding signal according to the code mapping table for the multi-bit quantized signal, and obtains the signal through the sampling loop and stores it in a data storage unit. When the multi-bit quantized signal is equal to 2 M -1, a sampling signal is output to the feedforward path of the sampling loop according to the code mapping table, so that the sampling loop performs sampling. 如申請專利範圍第9項所述的多位階雜訊重塑式轉換方法，其中該延遲回授迴路包含一第一加法器、一第二加法器、以及一延遲模組；其中該第一加法器的輸入端連接至該訊號處理器以及該延遲模組並於該第一加法器的輸出端輸出一第一訊號；其中該第二加法器的輸入端連接至該第一加法器的輸出端以及該多位階量化器的輸出端並於該第二加法器的輸出端輸出一第二訊號；其中該延遲模組的輸入端連接至該第二加法器的輸出端並於該延遲回授迴路的輸出端輸出一延遲補償訊號。 In the multi-level noise reshaping conversion method described in claim 9, wherein the delay feedback loop includes a first adder, a second adder, and a delay module; wherein the first adder The input end of the adder is connected to the signal processor and the delay module and outputs a first signal at the output end of the first adder; wherein the input end of the second adder is connected to the output end of the first adder And the output terminal of the multi-level quantizer outputs a second signal at the output terminal of the second adder; wherein the input terminal of the delay module is connected to the output terminal of the second adder and is connected to the delay feedback loop The output terminal outputs a delay compensation signal. 如申請專利範圍第10項所述的多位階雜訊重塑式轉換方法，其中該延遲模組包括一第一延遲器、一係數乘法器、以及一第二延遲器；其中該第一延遲器的輸入端係連接至該第二延遲器的輸出端並於該第一延遲器的輸出端輸出一第一延遲訊號；其中該係數乘法器的輸入端係連接至該第二延遲器的輸出端並於該係數乘法器的輸出端輸出一係數加乘訊號；其中該第二延遲器的輸入端係連接至該第一加法器的輸出端並於該第二延遲器的輸出端輸出一第二延遲訊號；其中該第一加法器的輸入端連接至該訊號處理器、該係數乘法器的輸出端、以及該第二延遲器的輸出端並於該第一加法器的輸出端輸出該第一訊號。 According to the multi-level noise reshaping conversion method described in claim 10, the delay module includes a first delayer, a coefficient multiplier, and a second delayer; wherein the first delayer The input terminal of is connected to the output terminal of the second delay device and outputs a first delay signal at the output terminal of the first delay device; wherein the input terminal of the coefficient multiplier is connected to the output terminal of the second delay device And output a coefficient multiplication signal at the output terminal of the coefficient multiplier; wherein the input terminal of the second delay device is connected to the output terminal of the first adder and outputs a second delay device at the output terminal of the second delay device. Delay signal; wherein the input terminal of the first adder is connected to the signal processor, the output terminal of the coefficient multiplier, and the output terminal of the second delayer, and the first adder is output at the output terminal of the first adder Signal. 如申請專利範圍第10項所述的多位階雜訊重塑式轉換方法，其中該第二加法器輸出的該第二訊號依據下面的公式獲得： A2[n]=Y[n]-X[n]；其中，A2[n]為第n階段輸出的該第二加法訊號，Y[n]為第n階段輸入的該多位元量化訊號，X[n]為第n階段輸入的該第一訊號。 In the multi-level noise reshaping conversion method described in item 10 of the scope of patent application, the second signal output by the second adder is obtained according to the following formula: A2[n]=Y[n]-X[n]; where A2[n] is the second addition signal output in the nth stage, Y[n] is the multi-bit quantized signal input in the nth stage, X[n] is the first signal input in the nth stage. 如申請專利範圍第11項所述的多位階雜訊重塑式轉換方法，其中該第一加法器輸出的該第一訊號依據下面的公式獲得：X[n]=S[n]-T[n-1]+A2[n-2]；其中，X[n]為第n階段輸出的該第一訊號，S[n]為第n階段輸入的該輸入-輸出頻率比例訊號，T[n-1]為第n-1階段輸入的該係數加乘訊號，A2[n-2]為第n-2階段輸入的該第二加法訊號。 The multi-level noise reshaping conversion method described in item 11 of the scope of patent application, wherein the first signal output by the first adder is obtained according to the following formula: X[n]=S[n]-T[ n-1]+A2[n-2]; where X[n] is the first signal output in the nth stage, S[n] is the input-output frequency ratio signal input in the nth stage, T[n -1] is the coefficient multiplication signal input in the n-1 stage, and A2[n-2] is the second addition signal input in the n-2 stage. 如申請專利範圍第11項所述的多位階雜訊重塑式轉換方法，其中該係數乘法器的該係數加乘訊號依據下面的公式獲得：T[n-1]=2×A2[n-1]；其中，T[n-1]為第n-1階段輸出的該係數加乘訊號，A2[n-1]為第n-1階段輸入的該第二加法訊號。 The multi-level noise reshaping conversion method described in item 11 of the scope of patent application, wherein the coefficient multiplication signal of the coefficient multiplier is obtained according to the following formula: T[n-1]=2×A2[n- 1]; where T[n-1] is the coefficient multiplication signal output in the n-1 stage, and A2[n-1] is the second addition signal input in the n-1 stage. 如申請專利範圍第9項所述的多位階雜訊重塑式轉換方法，其中該輸入-輸出頻率比例訊號最小值為0，最大值為1。 In the multi-level noise reshaping conversion method described in item 9 of the scope of patent application, the minimum value of the input-output frequency ratio signal is 0 and the maximum value is 1. 如申請專利範圍第9項所述的多位階雜訊重塑式轉換方法，其中該多位元量化訊號為一整數構成之階梯波。 In the multi-level noise reshaping conversion method described in item 9 of the scope of patent application, the multi-bit quantized signal is a step wave composed of an integer. 一種非暫存性電腦可讀取記錄媒體，係用於儲存一程式，當一訊號處理晶片載入該程式後將可執行如申請專利範圍第9至16項中任一項所述的方法。 A non-temporary computer-readable recording medium is used to store a program. When a signal processing chip is loaded into the program, the method described in any one of the 9th to 16th patent applications can be executed.
TW108143895A 2019-12-02 2019-12-02 Multi-level noise shaping system, method and non-transitory computer-readable medium TWI732367B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
TW108143895A TWI732367B (en) 2019-12-02 2019-12-02 Multi-level noise shaping system, method and non-transitory computer-readable medium

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW108143895A TWI732367B (en) 2019-12-02 2019-12-02 Multi-level noise shaping system, method and non-transitory computer-readable medium

Publications (2)

Publication Number Publication Date
TW202123218A TW202123218A (en) 2021-06-16
TWI732367B true TWI732367B (en) 2021-07-01

Family

ID=77516939

Family Applications (1)

Application Number Title Priority Date Filing Date
TW108143895A TWI732367B (en) 2019-12-02 2019-12-02 Multi-level noise shaping system, method and non-transitory computer-readable medium

Country Status (1)

Country Link
TW (1) TWI732367B (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115705020B (en) * 2021-08-17 2025-06-06 漳州立达信光电子科技有限公司 Sampling rate microcontroller system

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070296502A1 (en) * 2004-08-27 2007-12-27 Zongshan Zhou Method For Double Sampling Loop Negative Feedback And Double Sampling Negative Feedback Amplifier
CN102045064A (en) * 2009-10-20 2011-05-04 群联电子股份有限公司 Phase-locked loop and voltage-controlled oscillator thereof
TW201939900A (en) * 2018-03-13 2019-10-01 群聯電子股份有限公司 Phase-locked loop circuit calibration method, memory storage device and connection interface circuit

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070296502A1 (en) * 2004-08-27 2007-12-27 Zongshan Zhou Method For Double Sampling Loop Negative Feedback And Double Sampling Negative Feedback Amplifier
US7403068B2 (en) * 2004-08-27 2008-07-22 Zongshan Zhou Method for double sampling loop negative feedback and double sampling negative feedback amplifier
CN102045064A (en) * 2009-10-20 2011-05-04 群联电子股份有限公司 Phase-locked loop and voltage-controlled oscillator thereof
TW201939900A (en) * 2018-03-13 2019-10-01 群聯電子股份有限公司 Phase-locked loop circuit calibration method, memory storage device and connection interface circuit

Also Published As

Publication number Publication date
TW202123218A (en) 2021-06-16

Similar Documents

Publication Publication Date Title
US7936293B2 (en) Delta-sigma modulator
CN102291150B (en) A sigma-delta modulator
TWI699092B (en) A residue generation system, an analog-to-digital converter, and a method for generating a residue signal
CN107276590B (en) Signal processing method and system
TWI732367B (en) Multi-level noise shaping system, method and non-transitory computer-readable medium
TW202005287A (en) Electronic circuit for implementing modulator configured to perform noise shaping in digital domain
CN109547028B (en) Digital-to-analog conversion device, electronic musical instrument, information processing device, and digital-to-analog conversion method
US10659074B2 (en) Delta-sigma modulator, electronic device, and method for controlling delta-sigma modulator
US8271567B2 (en) Methods and systems for compression, storage, and generation of digital filter coefficients
JP3636130B2 (en) Trellis type noise shaping modulator
CN103875185A (en) Multi-level sigma-delta adc with reduced quantization levels
US20170331467A1 (en) Systems, apparatus, and methods for providing continuous-time signal differentiation and integration
US20040174279A1 (en) Method and apparatus for efficient conversion of signals using look-up table
CN116195182A (en) Systems and methods for compensating for feedback delay in digital class-D modulators
US20170149417A1 (en) Pulse width modulator and non-transitory computer readable medium for storing program for pulse width modulator
US6392398B1 (en) Sampling function generator
US20150145585A1 (en) Sample Rate Converter and Rate Estimator Thereof and Rate Estimation Method Thereof
JP5219722B2 (en) Modulation method, modulator, and A / D converter
JP6043129B2 (en) Serial data receiving circuit and receiving method, audio signal processing circuit, electronic device, and audio system
TWI822030B (en) Noise shaping digital automatic gain control system
JP2009303009A (en) Peak level detection apparatus
CN110235373B (en) D/A conversion device, method, storage medium, electronic musical instrument and information processing device
TW202205813A (en) Sampling rate fine tuning system
TWI782637B (en) Incremental analog-to-digital converter and circuit system using the same
US20070216466A1 (en) Systems and methods for creating and using a conditioning signal

Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees