TWI728698B - Lcd driving circuit - Google Patents

Abstract

A shift register circuit includes: a first transistors for outputting a driving voltage to a node based on a previous-stage scan signal; a second transistor for outputting a current-stage scan signal based on a clock signal; a compensation circuit for compensating the driving voltage based on the previous-stage scan signal and an ITP signal; and a pull-down circuit for adjusting the driving voltage and the current-stage scan signal based on the current-stage scan signal. A first reference voltage source is coupled to the pull-down circuit and a second reference voltage source is coupled to the compensation circuit. The first reference voltage source and the second reference voltage source have different voltage levels.

Description

Liquid crystal display (LCD) drive circuit

The present invention relates to a liquid crystal display (LCD) driving circuit.

Liquid crystal display (LCD) has the advantages of low radiation, low power consumption, light weight, less damage to eyesight, long life, high resolution, etc., and has gradually become the mainstream of displays. In recent years, through the continuous improvement of LCD technology, LCD response speed and contrast have been continuously improved, the viewing angle has gradually increased, and the large screen and super large screen technology have also achieved breakthroughs.

With regard to the liquid crystal display (LCD) drive circuit, an integrated touch solution has been proposed, which directly integrates the touch function into the panel production process to increase the added value of the product.

In terms of current technology, a cell touch panel is one of the more mature technologies. However, during touch sensing, if the potential of the Q point inside the GOA (Gate on Array) circuit drops due to leakage, as a result, when the touch sensing ends and the clock signal starts, there will be It may cause the problem that the GOA circuit cannot be downloaded.

Therefore, it has been proposed to add an additional circuit under the GOA circuit architecture. The additional circuit can provide charge to the Q point inside the GOA circuit during touch sensing, avoiding the above-mentioned problems.

However, in the additional circuit added, it is usually necessary to increase the capacitance to prevent the Integrated Test Procedure (ITP) signal from being unable to provide charge to the Q point within the sensing time due to leakage. However, in addition, increasing the capacitor requires an additional large GOA circuit area, which is not conducive to narrow frame design.

According to an example of this case, a liquid crystal display (LCD) driving circuit is proposed, which includes a plurality of stages of shift register circuits. Each shift register circuit includes: a first transistor receives a previous scan signal, and outputs a driving voltage to a node according to the previous scan signal; a second transistor is coupled to the first transistor With the node, the second transistor outputs a scan signal of the current stage according to a clock signal; a compensation circuit is coupled to the node for compensation according to the scan signal of the previous stage and an integrated test timing (ITP) signal The driving voltage; and a pull-down circuit, which is coupled to the node and the second transistor, and adjusts the driving voltage and the second transistor according to the current scan signal, or the previous scan signal, or a later scan signal Scan signal at this level. Wherein, a first reference voltage source is coupled to the pull-down circuit, and a second reference voltage source is coupled to the compensation circuit, and the potentials of the first reference voltage source and the second reference voltage source are different.

In order to have a better understanding of the above and other aspects of the present invention, the following specific examples are given in conjunction with the accompanying drawings to describe in detail as follows:

100: shift temporary storage circuit

T1~T21: Transistor

110: Compensation circuit

120: pull-down circuit

G(N): Scan signal

Q(N): drive voltage

Q: Node

CLK: clock signal

VSS, VSS2: Reference voltage source

200, 400, 500: shift temporary storage circuit

210, 410, 510: Compensation circuit

220,420,520: pull-down circuit

230,430,530: control circuit

ITP: Integrated test timing signal

G(N-1)~G(N+4): scan signal

P(N-1)~P(N): pull-down signal

F(N-1)~F(N): forward signal

LC: Control signal

C: Capacitance

Figure 1 shows the driving circuit of a liquid crystal display (LCD) according to an embodiment of the present invention Schematic diagram of shift register circuit.

FIG. 3 shows a waveform diagram of a shift register circuit according to an embodiment of the invention.

FIG. 4 is a detailed circuit diagram of the shift register circuit of the liquid crystal display driving circuit according to an embodiment of the present invention.

FIG. 5 is a detailed circuit diagram of the shift register circuit of the liquid crystal display driving circuit according to an embodiment of the present invention.

The technical terms in this specification refer to the customary terms in the technical field. If there are descriptions or definitions for some terms in this specification, the explanation of the part of the terms is based on the description or definitions in this specification. Each embodiment of the present disclosure has one or more technical features. Under the premise of possible implementation, those skilled in the art can selectively implement some or all of the technical features in any embodiment, or selectively combine some or all of the technical features in these embodiments.

The liquid crystal display (LCD) driving circuit of an embodiment of the present invention includes a plurality of stages of shift register circuits. FIG. 1 is a schematic diagram of a shift register circuit of a liquid crystal display (LCD) driving circuit according to an embodiment of the invention. As shown in FIG. 1, the shift register circuit 100 includes an input transistor T1, an output transistor T2, a compensation circuit 110 and a pull-down circuit 120.

The input transistor T1 (also called the input terminal) receives the previous scan signal G(N-1) output from the previous shift register circuit, and based on the previous output from the previous shift register circuit The level scan signal G(N-1) is used to output the driving voltage Q(N) to the node Q, where N is a positive integer. The input transistor T1 can be a diode connection method, Wherein, the source and the gate are coupled together, and receive the previous scan signal G(N-1), and the drain outputs the driving voltage Q(N) to the node Q.

The output transistor T2 (also called the driving terminal or the output terminal) is coupled to the input transistor T1 and the node Q. One end (for example, the source) of the output transistor T2 receives the clock signal CLK, and outputs the scanning signal G(N) of the current level according to the clock signal CLK. The clock signal CLK may be a periodic pulse signal. The control terminal (for example, the gate) of the output transistor T2 is coupled to the node Q, and the other terminal (for example, the drain) of the output transistor T2 outputs the scan signal G(N) of the current stage.

The compensation circuit 110 is coupled to the node Q for compensating the driving voltage Q(N) according to the previous scan signal (or previous scan signals) and the integrated test sequence (ITP) signal. The compensation circuit 110 can further selectively reduce the leakage of the driving voltage Q(N). In the description of the embodiments of this case, the previous scan signal (or the previous scan signals) can be collectively referred to as the previous scan signal; similarly, the next scan signal (or the subsequent scan signals) can be collectively referred to as the subsequent scan signal. The rest can be deduced by analogy.

The pull-down circuit 120 is coupled to the node Q and the output transistor T2, and is based on the scan signal G(N) of the current stage, or the scan signal of the previous stage (or the scan signal of the previous stage), or the scan signal of the next stage (or the next stage). Scan signal) to adjust the driving voltage Q(N) and the current level scan signal G(N).

In addition, as shown in FIG. 1, a first reference voltage source (such as VSS) is coupled to the pull-down circuit 120, and a second reference voltage source (such as VSS2) is coupled to the compensation circuit 110, wherein the first reference voltage source and The potential of the second reference voltage source is different. or Yes, in other possible embodiments of this case, the first reference voltage source (such as VSS) is for example but not limited to -11V, and the second reference voltage source (such as VSS2) is for example but not limited to -8V. Or, 0<VSS-VSS2<-3V.

Please refer to FIG. 2, which shows a detailed circuit diagram of the shift register circuit of the liquid crystal display driving circuit according to an embodiment of the present invention. As shown in FIG. 2, the shift register circuit 200 includes an input transistor T1, an output transistor T2, a front transmission transistor T7, a compensation circuit 210, a pull-down circuit 220, and a control circuit 230.

FIG. 3 shows a waveform diagram of a shift register circuit according to an embodiment of the invention.

The compensation circuit 210 includes: transistors T3 to T5. The compensation circuit 210 may further optionally include: a transistor T6.

The transistor T3 is used to control when the ITP signal can be input to the shift register circuit 200. The transistor T3 has a source and a gate receiving the previous-stage forwarding signal F(N-1) sent by the previous-stage shift register circuit; and a drain coupled to the gate of the transistor T5.

The transistor T4 is used to control when the ITP signal stops inputting to the shift register circuit 200. The transistor T4 has a drain electrode coupled to the transistor T3; a gate electrode receiving the scan signal G(N+2); and a drain electrode coupled to the second reference voltage source VSS2.

The transistor T5 has: the source receives 1TP; the gate is coupled to the drain of the transistor T3; and the drain is coupled to the node Q. Wherein, if the compensation circuit 210 does not include the transistor T6, the drain of the transistor T5 is coupled to the node Q; and If the compensation circuit 210 includes the transistor T6, the drain of the transistor T5 is coupled to the node Q through the transistor T6.

The transistor T6 is used to avoid the leakage current of the driving voltage Q(N). Transistor T6 is a diode connection. The source and gate of the transistor T6 are coupled to the drain of the transistor T5, and the drain of the transistor T6 is coupled to the node Q.

The operation of the compensation circuit 210 is as follows. When the front-level forward signal F(N-1) is logic high, the transistor T3 is turned on to pull the gate voltage of the transistor T5 to logic high, so that the transistor T5 is also turned on, so that the ITP signal can pass through Transistor T5 is sent to node Q. If the scan signal G(N+2) is logic high, the transistor T4 is turned on to pull the gate voltage of the transistor T5 to logic low, so that the transistor T5 is turned off, making the ITP signal unable to pass through the transistor T5 is sent to node Q.

Through the above operations, the compensation circuit 210 can compensate the driving voltage Q(N) on the node Q.

The front power transmitting transistor T7 is coupled to the node Q. One end (for example, the source) of the front transmission transistor T7 receives the clock signal CLK, the control terminal (for example, the gate) of the front transmission transistor T7 is coupled to the node Q, and the other end (for example, the drain) of the front transmission transistor T7 The forwarding signal F(N) is output. The forwarding signal F(N) and the scanning signal G(N) of this stage are basically the same signal, but the forwarding signal F(N) has a better waveform. The front transmitting transistor T7 outputs the forwarding signal F(N) according to the clock signal CLK and the driving voltage Q(N).

The pull-down circuit 220 includes transistors T8 to T13.

The transistor T8 has a source coupled to the node Q; a gate receiving the pull-down signal P(N); and a drain coupled to the second reference voltage source VSS2.

The transistor T9 has a source coupled to the node Q; a gate receiving the pull-down signal P(N-1); and a drain coupled to the second reference voltage source VSS2.

The transistor T10 has a source coupled to the node Q; a gate receiving the scan signal G(N+4); and a drain coupled to the second reference voltage source VSS2.

The transistor T11 has a source receiving the scan signal G(N); a gate receiving the pull-down signal P(N); and a drain coupled to the first reference voltage source VSS.

The transistor T12 has a source receiving the scan signal G(N); a gate receiving the pull-down signal P(N-1); and a drain coupled to the first reference voltage source VSS.

The transistor T13 has a source receiving the scanning signal G(N); a gate receiving the scanning signal G(N+2); and a drain coupled to the first reference voltage source VSS.

Please note that in other possible embodiments of the present case, the gates of the transistors T8 to T13 may receive scan signals of other levels or pull-down signals of other levels, which is also within the spirit of the present case.

The operation principle of the pull-down circuit 220 is as follows. Taking the transistor T8 as an example, when the pull-down signal P(N) is logic high, the transistor T8 is turned on to pull down the driving voltage Q(N). The operation of the remaining transistors can be deduced by analogy.

That is to say, the pull-down circuit 220 includes two groups of transistors, where one group of transistors (such as transistors T8~T10) pulls down the driving voltage Q(N), and the other group of transistors (such as transistors) pulls down the driving voltage Q(N). The crystals T11~T13) pull down the scan signal G(N).

The control circuit 230 is coupled to the pull-down circuit 220. Control circuit 230 The pull-down signal P(N) is generated according to the control signal LC and the driving voltage Q(N). The pull-down circuit 220 can pull down the driving voltage Q(N) or the scan signal G(N) according to the pull-down signal P(N), and/or the scan signal of the current stage/or the scan signal of other stages. Wherein, the control signal LC can be a DC voltage with a fixed high voltage level during a frame, or can be a pulse signal that is periodically enabled. In addition, the phases of the control signal LC and the clock signal CLK are different.

The control circuit 230 includes transistors T14 to T21.

The transistor T14 has a source and a gate receiving the control signal LC; and a drain coupled to the gate of the transistor T15.

The transistor T15 has: a source receiving the control signal LC; a gate, a drain coupled to the transistor T14; and a drain outputting a pull-down signal P(N).

The transistor T16 has a gate electrode coupled to the transistor T15; the gate electrode receives the scan signal Q(N-1); and the drain electrode is coupled to the first reference voltage source VSS.

The transistor T17 has a gate electrode coupled to the transistor T15; the gate electrode receives the scan signal Q(N); and the drain electrode is coupled to the first reference voltage source VSS.

The transistor T18 has a source coupled to a gate of the transistor T15; the gate receives the scan signal Q(N+1); and the drain is coupled to the first reference voltage source VSS.

The transistor T19 has: the source receives the pull-down signal P(N); the gate receives the scan signal Q(N-1); and the drain is coupled to the first reference voltage source VSS.

Transistor T20 has: the source receives the pull-down signal P(N); the gate is connected The scan signal Q(N) is received; and the drain is coupled to the first reference voltage source VSS.

The transistor T21 has a source receiving the pull-down signal P(N); a gate receiving the scan signal Q(N+1); and a drain coupled to the first reference voltage source VSS.

The operation of the control circuit 230 is as follows. When the control signal 1LC is logic high so that the transistor T14 is turned on, the transistor T15 is also turned on, so that the pull-down signal P(N) is logic high.

When any one of the transistor T16, T17, or T18 is on, the gate voltage of the transistor T15 is pulled down, so that the transistor T15 becomes off, and the pull-down signal P(N) becomes floating.

When any one of the transistors T19, T20, or T21 is turned on, the pull-down signal P(N) is pulled down. When the pull-down signal P(N) is pulled down to logic low, the transistor T8 turns off and does not pull down the driving voltage Q(N).

That is to say, the control circuit 230 includes two groups of transistors, where one group of transistors (such as transistors T16~T18) makes the pull-down signal P(N) floating, and the other group of transistors ( For example, transistors T19~T21) pull down the pull-down signal P(N).

Please refer to FIG. 4, which illustrates a detailed circuit diagram of the shift register circuit of the liquid crystal display driving circuit according to an embodiment of the present invention. As shown in FIG. 4, the shift register circuit 400 includes an input transistor T1, an output transistor T2, a front transmission transistor T7, a compensation circuit 410, a pull-down circuit 420, and a control circuit 430.

The compensation circuit 410, the pull-down circuit 420, and the control circuit 430 are basically the same or similar to the compensation circuit 210, the pull-down circuit 220, and the control circuit in FIG. 2 Road 230. However, the transistors T8 to T10 of the pull-down circuit 420 are coupled to the first reference voltage source VSS.

Please refer to FIG. 5, which illustrates a detailed circuit diagram of the shift register circuit of the liquid crystal display driving circuit according to an embodiment of the present invention. As shown in FIG. 5, the shift register circuit 500 includes: an input transistor T1, an output transistor T2, a front transmission transistor T7, a compensation circuit 510, a pull-down circuit 520, and a control circuit 530.

The compensation circuit 510, the pull-down circuit 520, and the control circuit 530 are basically the same or similar to the compensation circuit 210, the pull-down circuit 220, and the control circuit 230 in FIG. 2. However, the compensation circuit 510 additionally includes a capacitor C, which is coupled between the gate of the transistor T5 and the gate of the transistor T6.

It can be seen from the above that the shift register circuit of the embodiment of the present application uses a dual ground voltage source (Dual VSS) design, and the leakage amount of the leakage path of the driving voltage is reduced when the ITP is sensed. Therefore, the shift register circuit of this embodiment does not need an external large capacitor. In this way, the circuit area can be reduced and the effect of a narrow frame can be achieved.

In summary, although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention. Those with ordinary knowledge in the technical field to which the present invention belongs can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to those defined by the attached patent application scope.

100: shift temporary storage circuit

T1~T2: Transistor

110: Compensation circuit

120: pull-down circuit

G(N-1)~G(N): scan signal

Q(N): drive voltage

Q: Node

CLK: clock signal

VSS, VSS2: Reference voltage source

Claims (12)

A liquid crystal display (LCD) drive circuit includes a plurality of stages of shift temporary storage circuits, each shift temporary storage circuit includes: a first transistor receives a previous stage scan signal, and outputs a driving voltage according to the previous stage scan signal To a node; a second transistor is coupled to the first transistor and the node, and the second transistor outputs a local scan signal according to a clock signal; a compensation circuit is coupled to the node for Compensate the driving voltage according to the previous scan signal and an integrated test timing (ITP) signal; and a pull-down circuit, coupled to the node and the second transistor, and based on the current scan signal, or the previous Stage scan signal, or a later stage scan signal to adjust the driving voltage and the current stage scan signal; wherein, a first reference voltage source is coupled to the pull-down circuit, and a second reference voltage source is coupled to the compensation circuit , The first reference voltage source and the second reference voltage source have different potentials. The liquid crystal display (LCD) driving circuit according to claim 1, wherein 0<VSS-VSS2<-3V, VSS is the first reference voltage source and VSS2 is the second reference voltage source. The liquid crystal display (LCD) driving circuit according to claim 1, wherein the compensation circuit includes: a third transistor having: a source and a gate to receive a front-end forwarding signal; and a drain; A fourth transistor having: a source coupled to the drain of the third transistor; a gate receiving the subsequent scan signal; and a drain coupled to the second reference voltage source; and a The fifth transistor has: a source receiving the ITP signal; a gate coupled to the drain of the third transistor; and a drain coupled to the node. The liquid crystal display (LCD) driving circuit according to claim 3, wherein the compensation circuit further comprises: a sixth transistor having: a source and a gate coupled to the drain of the fifth transistor , And a drain coupled to the node. The liquid crystal display (LCD) drive circuit of claim 4, wherein the compensation circuit further comprises: a capacitor coupled between the gate of the fifth transistor and the gate of the sixth transistor . The liquid crystal display (LCD) driving circuit according to claim 3, wherein, when the preceding-stage forwarding signal is logic high, the third transistor is turned on, so that the fifth transistor is also turned on, so that the The ITP signal is sent to the node through the fifth transistor; and if the subsequent scan signal is logic high, the fourth transistor is turned on, so that the fifth transistor is turned off, so that the ITP signal cannot It is sent to the node through the fifth transistor. The liquid crystal display (LCD) driving circuit according to claim 1, wherein each shift register circuit further comprises: a seventh transistor coupled to the node, and the seventh transistor depends on the clock signal and the The driving voltage is used to output a forward signal of the current level. The liquid crystal display (LCD) driving circuit according to claim 1, wherein the pull-down circuit includes: a first transistor group to pull down the driving voltage; and a second transistor group to scan the current stage The signal is pulled down. The liquid crystal display (LCD) driving circuit according to claim 8, wherein the first transistor group is coupled to the second reference voltage source, and the second transistor group is coupled to the first reference voltage source. The liquid crystal display (LCD) driving circuit according to claim 8, wherein the first transistor group is coupled to the first reference voltage source, and the second transistor group is coupled to the first reference voltage source. The liquid crystal display (LCD) drive circuit according to claim 1, wherein each shift register circuit further comprises: a control circuit coupled to the pull-down circuit, the control circuit generating a control signal according to a control signal and the drive voltage The pull-down signal of the current level, so that the pull-down circuit pulls down the driving voltage and the scan signal of the current level according to the pull-down signal of the current level, the scan signal of the current level and the scan signals of other levels. The liquid crystal display (LCD) drive circuit according to claim 11, wherein the control circuit includes: a third transistor group controls whether the pull-down signal of the current stage is floating; and a fourth transistor group controls Under this level pull-down signal Pull, the third transistor group and the fourth transistor group are coupled to the first reference voltage source.

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