CN112419991A

CN112419991A - Liquid Crystal Display (LCD) driving circuit

Info

Publication number: CN112419991A
Application number: CN202011097819.6A
Authority: CN
Inventors: 郑诗婷; 陈柄霖
Original assignee: AU Optronics Corp
Current assignee: AUO Corp
Priority date: 2020-02-14
Filing date: 2020-10-14
Publication date: 2021-02-26
Anticipated expiration: 2040-10-14
Also published as: TWI728698B; TW202131301A; CN112419991B

Abstract

The shift register circuit includes: a first transistor that outputs a driving voltage to a node based on a previous stage scan signal; a second transistor that outputs a primary stage scan signal based on a clock pulse signal; a compensation circuit that outputs a primary stage scan signal based on the previous stage scan signal. The first-level scanning signal and an integrated test timing signal are used to compensate the driving voltage; and a pull-down circuit is used to adjust the driving voltage and the current-level scanning signal according to the current-level scanning signal. A first reference voltage source is coupled to the pull-down circuit, and a second reference voltage source is coupled to the compensation circuit. The potentials of the first reference voltage source and the second reference voltage source are different.

Description

Liquid Crystal Display (LCD) driving circuit

Technical Field

The invention relates to a Liquid Crystal Display (LCD) driving circuit.

Background

Liquid Crystal Displays (LCDs) have the advantages of low radiation, low power consumption, light weight, less damage to vision, long lifetime, high resolution, etc., and are becoming the mainstream of displays. In recent years, through continuous improvement of LCD technology, the response speed and contrast of the LCD are continuously improved, the visual angle is gradually increased, and large screens and ultra-large screen technology are also broken through.

For a Liquid Crystal Display (LCD) driving circuit, an integrated touch solution is proposed to directly integrate a touch function into a panel manufacturing process, thereby increasing the added value of the product.

In the prior art, an embedded touch panel (cell touch panel) is one of the more mature technologies. However, if the voltage of the Q point in the GOA (Gate on Array) circuit is lowered due to the leakage during the touch sensing, the GOA circuit may not be able to download when the clock signal is activated after the touch sensing is finished.

Therefore, it has been proposed to add an additional circuit under the GOA circuit architecture. The added extra circuit can provide charge to the Q point in the GOA circuit during touch sensing, so that the problems are avoided.

However, in the added extra circuit, a large capacitor is usually added to avoid the problem that the Integrated Test Procedure (ITP) signal cannot provide charge to the Q-point in the sensing time due to the leakage current. However, the capacitor needs to be enlarged to occupy a larger area of the GOA circuit, which is not favorable for the narrow frame design.

Disclosure of Invention

According to an example of the present disclosure, a Liquid Crystal Display (LCD) driving circuit is provided, which includes a multi-stage shift register circuit. Each shift register circuit includes: a first transistor (T1) receiving a previous scan signal G (N-1) and outputting a driving voltage Q (N) to a node Q according to the previous scan signal G (N-1); a second transistor (T2) coupled to the first transistor T1 and the node Q, the second transistor outputting a local scan signal g (n) according to a clock signal; a compensation circuit coupled to the node Q for compensating the driving voltage Q (N) according to the pre-scan signal and an integrated test timing (ITP) signal; and a pull-down circuit coupled to the node Q and the second transistor for adjusting the driving voltage Q (N) and the current-stage scanning signal G (N) according to the current-stage scanning signal G (N), the previous-stage scanning signal, or a next-stage scanning signal. Wherein, a first reference voltage source is coupled to the pull-down circuit, a second reference voltage source is coupled to the compensation circuit, and the first reference voltage source and the second reference voltage source have different potentials.

The invention is described in detail below with reference to the drawings and specific examples, but the invention is not limited thereto.

Drawings

FIG. 1 is a diagram of a shift register circuit of a Liquid Crystal Display (LCD) driving circuit according to an embodiment of the invention.

FIG. 2 is a detailed circuit diagram of a shift register circuit of a liquid crystal display driving circuit according to an embodiment of the invention.

FIG. 3 is a waveform diagram of a shift register circuit according to an embodiment of the present invention.

FIG. 4 is a detailed circuit diagram of a shift register circuit of a liquid crystal display driving circuit according to an embodiment of the invention.

FIG. 5 is a detailed circuit diagram of a shift register circuit of a liquid crystal display driving circuit according to an embodiment of the invention.

Wherein, the reference numbers:

100 shift register circuit

T1-T21 transistors

110 compensating circuit

120 pull-down circuit

G (N) scanning signals

Q (N) a driving voltage

Q is node

CLK clock pulse signal

VSS, VSS2 reference voltage source

200,400,500 shift register circuit

210,410,510 compensating circuit

220,420,520 Pull-Down Circuit

230,430,530 control circuit

ITP integrating test timing signals

G (N-1) to G (N +4): scanning signal

P (N-1) -P (N) is a pull-down signal

F (N-1) -F (N) forward signals

LC control signal

C is capacitor

Detailed Description

The invention will be described in detail with reference to the following drawings, which are provided for illustration purposes and the like:

the technical terms in the specification refer to the common terms in the technical field, and if the specification explains or defines a part of the terms, the explanation of the part of the terms is based on the explanation or definition in the specification. Various embodiments of the present disclosure may have one or more technical features. In the present invention, the present invention provides a method for implementing a mobile communication system, which is capable of providing a mobile communication system with a plurality of mobile communication devices.

A Liquid Crystal Display (LCD) driving circuit according to an embodiment of the present invention includes a multi-stage shift register circuit. FIG. 1 is a diagram of a shift register circuit of a Liquid Crystal Display (LCD) driving circuit according to an embodiment of the invention. As shown in fig. 1, the shift register circuit 100 includes: an input transistor T1, an output transistor T2, a compensation circuit 110 and a pull-down circuit 120.

The input transistor T1 (also referred to as an input terminal) receives a previous stage scan signal G (N-1) output from a previous stage shift register circuit, and outputs a driving voltage Q (N) to a node Q according to the previous stage scan signal G (N-1) output from the previous stage shift register circuit, where N is a positive integer. The input transistor T1 may be diode connected, in which the source and the gate are coupled together and receive the previous stage scanning signal G (N-1), and the drain outputs the driving voltage Q (N) to the node Q.

The output transistor T2 (also referred to as a driving terminal or an output terminal) is coupled to the input transistor T1 and the node Q. One end (e.g., the source) of the output transistor T2 receives the clock signal CLK, and outputs the present-stage scan signal g (n) according to the clock signal CLK, wherein the clock signal CLK may be a periodic pulse signal. The control terminal (e.g., gate) of the output transistor T2 is coupled to the node Q, and the other terminal (e.g., drain) of the output transistor T2 outputs the present-stage scan signal g (n).

The compensation circuit 110 is coupled to the node Q for compensating the driving voltage Q (n) according to the previous stage scan signal (or the previous stages scan signal) and the ITP signal. The compensation circuit 110 can further selectively reduce the leakage of the driving voltage q (n). In the description of the embodiment, the previous stage scan signal (or the previous stages of scan signals) may be collectively referred to as a previous stage scan signal; similarly, the next stage scan signal (or the next stages of scan signals) may be collectively referred to as the next stage scan signal, and so on.

The pull-down circuit 120 is coupled to the node Q and the output transistor T2, and adjusts the driving voltage Q (n) and the scan signal g (n) according to the scan signal g (n) of the current stage, or the scan signal of the previous stage (or the scan signals of the previous stages), or the scan signal of the next stage (or the scan signals of the next stages).

In addition, as shown in fig. 1, a first reference voltage source (e.g., VSS) is coupled to the pull-down circuit 120, and a second reference voltage source (e.g., VSS2) is coupled to the compensation circuit 110, wherein the first reference voltage source and the second reference voltage source have different potentials. Alternatively, in other embodiments of the present disclosure, the first reference voltage source (e.g., VSS) is, for example but not limited to-11V, and the second reference voltage source (e.g., VSS2) is, for example but not limited to-8V. Alternatively, 0< VSS-VSS2< -3V.

Referring to fig. 2, a detailed circuit diagram of a shift register circuit of a liquid crystal display driving circuit according to an embodiment of the invention is shown. As shown in fig. 2, the shift register circuit 200 includes: an input transistor T1, an output transistor T2, a forwarding transistor T7, a compensation circuit 210, a pull-down circuit 220 and a control circuit 230.

The compensation circuit 210 includes: transistors T3-T5. The compensation circuit 210 may further optionally include: and a transistor T6.

The transistor T3 is used to control when the ITP signal can be input to the shift register circuit 200. The transistor T3 has: the source and the grid receive a previous stage of forward signals F (N-1) sent by a previous stage of shift register circuit; and a drain coupled to the gate of transistor T5.

The transistor T4 is used to control when the ITP signal stops being input to the shift register circuit 200. The transistor T4 has: a source coupled to the drain of the transistor T3; the grid electrode receives a scanning signal G (N + 2); and a drain coupled to a second voltage reference source VSS 2.

The transistor T5 has: a source receives the ITP; a gate coupled to the drain of the transistor T3; and a drain coupled to node Q. Wherein, if the compensation circuit 210 does not include the transistor T6, the drain of the transistor T5 is coupled to the node Q; and if the compensation circuit 210 includes the transistor T6, the drain of the transistor T5 is coupled to the node Q through the transistor T6.

The transistor T6 is used to avoid the leakage current of the driving voltage q (n). The transistor T6 is diode connected. The source and gate of the transistor T6 are coupled to the drain of the transistor T5, and the drain of the transistor T6 is coupled to the node Q.

The operation of the compensation circuit 210 is as follows. When the previous stage forwarding signal F (N-1) is logic high, the transistor T3 is turned on to pull the gate voltage of the transistor T5 to logic high, thereby turning on the transistor T5 and enabling the ITP signal to be sent to the node Q through the transistor T5. If the scan signal Q (N +2) is logic high, the transistor T4 is turned on to pull the gate voltage of the transistor T5 to logic low, thereby turning off the transistor T5 and preventing the ITP signal from being transmitted to the node Q through the transistor T5.

Through the above operation, the compensation circuit 210 can compensate the driving voltage Q (n) on the node Q.

The forwarding transistor T7 is coupled to the node Q. One terminal (e.g., the source) of the forwarding transistor T7 receives the clock signal CLK, the control terminal (e.g., the gate) of the forwarding transistor T7 is coupled to the node Q, and the other terminal (e.g., the drain) of the forwarding transistor T7 outputs a forwarding signal f (n), wherein the forwarding signal f (n) is substantially the same as the current-stage scan signal g (n), but the forwarding signal f (n) has a preferred waveform. The forwarding transistor T7 outputs a forwarding signal f (n) according to the clock signal CLK and the driving voltage q (n).

The pull-down circuit 220 includes transistors T8-T13.

The transistor T8 has: the source is coupled to the node Q; the grid electrode receives a pull-down signal P (N); and a drain coupled to a second voltage reference source VSS 2.

The transistor T9 has: the source is coupled to the node Q; the grid electrode receives a pull-down signal P (N-1); and a drain coupled to a second voltage reference source VSS 2.

The transistor T10 has: the source is coupled to the node Q; the grid electrode receives a scanning signal G (N + 4); and a drain coupled to a second voltage reference source VSS 2.

The transistor T11 has: the source electrode receives a scanning signal G (N); the grid electrode receives a pull-down signal P (N); and a drain coupled to the first reference voltage source VSS.

The transistor T12 has: the source electrode receives a scanning signal G (N); the grid electrode receives a pull-down signal P (N-1); and a drain coupled to the first reference voltage source VSS.

The transistor T13 has: the source electrode receives a scanning signal G (N); the grid electrode receives a scanning signal G (N + 4); and a drain coupled to the first reference voltage source VSS.

It is noted that in other embodiments, the gates of the transistors T8-T13 may receive the scan signal of other stages or the pull-down signal of other stages, which is also within the spirit of the present invention.

The operation principle of the pull-down circuit 220 is as follows. Taking the transistor T8 as an example, when the pull-down signal p (n) is logic high, the transistor T8 is turned on to pull down the driving voltage q (n). The operation of the remaining transistors may be repeated.

That is, the pull-down circuit 220 includes two transistor groups, one of the transistor groups (e.g., the transistors T8-T10) pulls down the driving voltage Q (N), and the other transistor group (e.g., the transistors T11-T13) pulls down the scan signal G (N).

The control circuit 230 is coupled to the pull-down circuit 220. The control circuit 230 generates the pull-down signal p (n) according to the control signal LC and the driving voltage q (n). The pull-down circuit 220 may pull down the driving voltage q (n) or the scan signal g (n) according to the pull-down signal p (n), and/or the scan signal of the present stage and/or the scan signal of the other stage. The control signal LC may be a dc voltage with a fixed high voltage level during a frame (frame), or may be a pulse signal that is periodically enabled. In addition, the phase of the control signal LC is different from that of the clock pulse signal CLK.

The control circuit 230 includes transistors T14-T20.

The transistor T14 has: the source and the grid receive a control signal LC; and a drain coupled to the gate of transistor T15.

The transistor T15 has: the source electrode receives a control signal LC; a gate coupled to the drain of the transistor T14; and a drain outputting a pull-down signal P (N).

The transistor T16 has: a source coupled to the gate of the transistor T15; the grid electrode receives a scanning signal Q (N-1); and a drain coupled to the first reference voltage source VSS.

The transistor T17 has: a source coupled to the gate of the transistor T15; the grid electrode receives a scanning signal Q (N); and a drain coupled to the first reference voltage source VSS.

The transistor T18 has: a source coupled to the gate of the transistor T15; the grid electrode receives a scanning signal Q (N + 1); and a drain coupled to the first reference voltage source VSS.

The transistor T19 has: the source electrode receives a pull-down signal P (N); the grid electrode receives a scanning signal Q (N-1); and a drain coupled to the first reference voltage source VSS.

The transistor T20 has: the source electrode receives a pull-down signal P (N); the grid electrode receives a scanning signal Q (N); and a drain coupled to the first reference voltage source VSS.

The transistor T21 has: the source electrode receives a pull-down signal P (N); the grid electrode receives a scanning signal Q (N + 1); and a drain coupled to the first reference voltage source VSS.

The operation of the control circuit 230 is as follows. When the control signal LC is at logic high to turn on the transistor T14, the transistor T15 is also turned on, so that the pull-down signal p (n) is at logic high.

When any one of the transistors T16, T17, and T18 is turned on, the gate voltage of the transistor T15 is pulled down, so that the transistor T15 is turned off, and the pull-down signal p (n) is floated.

When any one of the transistors T19, T20 or T21 is turned on, the pull-down signal P (N) is pulled down. When the pull-down signal p (n) is pulled down to logic low, the transistor T8 turns off, and the driving voltage q (n) is not pulled down.

That is, the control circuit 230 includes two transistor groups, one of the transistor groups (e.g., the transistors T16-T18) makes the pull-down signal P (N) floating, and the other transistor group (e.g., the transistors T19-T21) pulls down the pull-down signal P (N).

Referring now to fig. 4, a detailed circuit diagram of a shift register circuit of a liquid crystal display driving circuit according to an embodiment of the invention is shown. As shown in fig. 4, the shift register circuit 400 includes: an input transistor T1, an output transistor T2, a forwarding transistor T7, a compensation circuit 410, a pull-down circuit 420 and a control circuit 430.

The compensation circuit 410, the pull-down circuit 420, and the control circuit 430 are substantially the same as or similar to the compensation circuit 210, the pull-down circuit 220, and the control circuit 230 of fig. 2. However, the transistors T8-T10 of the pull-down circuit 420 are coupled to the first voltage reference VSS.

Referring now to fig. 5, a detailed circuit diagram of a shift register circuit of a liquid crystal display driving circuit according to an embodiment of the invention is shown. As shown in fig. 5, the shift register circuit 500 includes: an input transistor T1, an output transistor T2, a forwarding transistor T7, a compensation circuit 510, a pull-down circuit 520 and a control circuit 530.

The compensation circuit 510, the pull-down circuit 520, and the control circuit 530 are substantially the same as or similar to the compensation circuit 210, the pull-down circuit 220, and the control circuit 230 of fig. 2. However, the compensation circuit 510 further includes a capacitor C coupled between the gate of the transistor T5 and the gate of the transistor T6.

As can be seen from the above, the shift register circuit of the embodiment utilizes a Dual-grounded voltage source (Dual VSS) design, so that the leakage amount of the leakage path of the driving voltage is reduced during the ITP induction. Therefore, the shift register circuit of the embodiment of the invention does not need to be externally connected with a large capacitor. Therefore, the circuit area can be reduced, and the effect of narrow frame can be achieved.

The present invention may be embodied in other specific forms without departing from the spirit or essential attributes thereof, and it should be understood that various changes and modifications can be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.

Claims

1. a liquid crystal display (LCD) drive circuit, is characterized in that, comprises multistage shift register circuit, and each shift register circuit comprises:

a first transistor receives a previous-stage scanning signal, and outputs a driving voltage to a node according to the previous-stage scanning signal;

A second transistor is coupled to the first transistor and the node, and the second transistor outputs a level scan signal according to a clock pulse signal;

a compensation circuit, coupled to the node, for compensating the driving voltage according to the pre-stage scan signal and an integrated test timing (ITP) signal; and

a pull-down circuit, coupled to the node and the second transistor, and adjusting the driving voltage and the current-stage scan signal according to the current-stage scan signal, or the previous-stage scan signal, or a post-stage scan signal;

Wherein, a first reference voltage source is coupled to the pull-down circuit, and a second reference voltage source is coupled to the compensation circuit, and the potentials of the first reference voltage source and the second reference voltage source are different.

2. The liquid crystal display (LCD) driving circuit of claim 1, wherein 0<VSS-VSS2<-3V, VSS is the first reference voltage source and VSS2 is the second reference voltage source.

3. The liquid crystal display (LCD) driving circuit of claim 1, wherein the compensation circuit comprises:

a third transistor, having: a source and a gate receiving a pre-stage forwarding signal; and a drain;

a fourth transistor having: a source coupled to the drain of the third transistor; a gate receiving the post-stage scan signal; and a drain coupled to the second reference voltage source; and

A fifth transistor has: a source receiving the ITP signal; a gate coupled to the drain of the third transistor; and a drain coupled to the node.

4. The liquid crystal display (LCD) driving circuit of claim 3, wherein the compensation circuit further comprises:

A sixth transistor has a source and a gate coupled to the drain of the fifth transistor, and a drain coupled to the node.

5. The liquid crystal display (LCD) driving circuit of claim 4, wherein the compensation circuit further comprises:

A capacitor is coupled between the gate of the fifth transistor and the gate of the sixth transistor.

6. The liquid crystal display (LCD) driving circuit according to claim 3, wherein,

When the pre-stage forwarding signal is logic high, the third transistor is turned on, so that the fifth transistor is also turned on, so that the ITP signal is sent to the node through the fifth transistor; and

If the post-stage scan signal is logic high, the fourth transistor is turned on, so that the fifth transistor is turned off, so that the ITP signal cannot be sent to the node through the fifth transistor.

7 . The liquid crystal display (LCD) driving circuit of claim 1 , wherein each shift register circuit further comprises: a seventh transistor coupled to the node, the seventh transistor being connected to the clock signal according to the clock pulse signal. 8 . This driving voltage is used to output a first-stage forwarding signal.

8 . The liquid crystal display (LCD) driving circuit of claim 1 , wherein the pull-down circuit comprises: a first transistor group for pulling down the driving voltage; and a second transistor group for pulling down the current level scan signal pull-down.

9. The liquid crystal display (LCD) driving circuit of claim 8, wherein the first transistor group is coupled to the second reference voltage source, and the second transistor group is coupled to the first transistor group reference voltage source.

10. The liquid crystal display (LCD) driving circuit of claim 8, wherein the first transistor group is coupled to the first reference voltage source, and the second transistor group is coupled to the first transistor group reference voltage source.

11. The liquid crystal display (LCD) driving circuit of claim 1, wherein each shift register circuit further comprises: a control circuit coupled to the pull-down circuit, the control circuit according to a control signal and the driving voltage to generate a first-level pull-down signal, so that the pull-down circuit pulls down the driving voltage and the current-level scan signal according to the current-level pull-down signal, the current-level scan signal and the other-level scan signals.

12. The liquid crystal display (LCD) driving circuit of claim 11, wherein the control circuit comprises: a third transistor group to control whether the pull-down signal of the current stage is floating; and a fourth transistor group The pull-down signal of this stage is pulled down, and the third transistor group and the fourth transistor group are coupled to the first reference voltage source.