TWI724834B - Semiconductor device having floating conductive layer - Google Patents

Abstract

A semiconductor device includes a substrate having a first conductivity type, a high-pressure well formed in the substrate and having a second conductivity type, a source well formed in the substrate on one side of the high-pressure well, a drain well formed in the high-pressure well, an isolation layer formed above the high-pressure well between the source well and the drain well, a gate layer formed on the substrate and continuously extending from above an edge portion of the source well to an edge portion of the isolation layer, a source region formed in the source well near the gate layer, a drain region formed in the drain well, and at least one floating conductive layer formed on the isolation layer. The distance between the floating conductive layer and the drain region is less than the distance between the floating conductive layer and the source region.

Description

Semiconductor device with floating conductor layer

The present invention relates to a semiconductor device, and more particularly to a semiconductor device having a floating conductor layer.

Ultra-high voltage (ultra-HV) semiconductor devices are widely used in display components, portable components and other diverse applications. The goals pursued by ultra-high voltage semiconductor devices include high breakdown voltage (breakdown voltage), low characteristic on-resistance (Ron), and high reliability in both room temperature and high temperature environments.

However, as the application of ultra-high voltage semiconductor devices expands, seeking a higher breakdown voltage has become the current research focus.

The present invention provides a semiconductor device with a floating conductor layer, which can increase the breakdown voltage to more than 500V by reducing the characteristic on-resistance (Ron).

The semiconductor device of the present invention includes a substrate having a first conductivity type, a high-voltage well having a second conductivity type, a source well having a first conductivity type, a drain well having a second conductivity type, an isolation layer, and a gate layer , The source region, the drain region and at least one floating conductor layer. The high-pressure well is formed in the substrate, the source well is formed in the base on one side of the high-pressure well, the drain well is formed in the high-pressure well, the isolation layer is formed above the high-pressure well between the source well and the drain well, and the gate layer is formed Above the substrate and continuously extending from the edge portion of the source well to the edge portion of the isolation layer, the source region is formed in the source well beside the gate layer, and the floating conductor layer is formed above the isolation layer. The distance between the floating conductor layer and the drain region is smaller than the distance between the floating conductor layer and the source region.

In order to make the above-mentioned features and advantages of the present invention more comprehensible, the following specific embodiments are described in detail in conjunction with the accompanying drawings.

The following content provides many different implementations or examples for implementing different features of the present invention. Moreover, these embodiments are only exemplary, and are not used to limit the scope and application of the present invention. Furthermore, for the sake of clarity, the relative size (such as length, thickness, spacing, etc.) and relative position of each region or structural element may be reduced or enlarged. In addition, similar or identical element symbols are used in the various drawings to indicate similar or identical elements or features.

FIG. 1 is a schematic top view of a semiconductor device according to an embodiment of the present invention, and FIG. 2 is a schematic cross-sectional view of the semiconductor device along the line II-II' in FIG. 1.

1 and 2, the semiconductor device 10 of this embodiment includes a substrate 100 having a first conductivity type, a high-voltage well 102 having a second conductivity type, a source well 104 having a first conductivity type, and a source well 104 having a second conductivity type. Type drain well 106, isolation layer 108, gate layer 110, source region 112, drain region 114 and at least one floating conductor layer 116. In one embodiment, the first conductivity type is P type, and the second conductivity type is N type. In another embodiment, the first conductivity type is N-type, and the second conductivity type is P-type. The substrate 100 is a semiconductor substrate, for example, formed of a silicon bulk material, an epitaxial layer (epitaxial layer), or a silicon-on-insulator (SOI) material. In this embodiment, the semiconductor device 10 can be a Lateral Diffused MOSFET device, and can be applied to mixed-mode circuit design or analog circuit design, such as: LED lighting, energy saving Electric lamps, ballasts, motor drivers, etc. The high-pressure well 102 is formed in the substrate 100, the source well 104 is formed in the base 100 on the side of the high-pressure well 102, and the drain well 106 is formed in the high-pressure well 102. In one embodiment, the source well 104 and the high pressure well 102 are adjacent to each other. The source region 112 is formed in the source well 104 next to the gate layer 110, and the source region 104 includes a first heavily doped region 118 with a first conductivity type and a second heavily doped region with a second conductivity type. The impurity region 120, the second heavily doped region 120 is formed between the first heavily doped region 118 and the gate layer 110.

The isolation layer 108 is formed above the high-pressure well 102 between the source well 104 and the drain well 106, and a field oxide (FOX) layer 122 or the like is provided outside the active region or the OD region The isolation structure and the isolation layer 108 can be made in the same thermal oxidation step. However, the present invention is not limited to this. The isolation structure can also be changed to a local silicon oxide layer (LOCOS) or a shallow trench isolation structure (STI). ). In one embodiment, the isolation layer 108 partially overlaps the drain well 106 and is separated from the source well 104.

The gate layer 110 is formed above the substrate 100 and continuously extends from above the edge portion 104a of the source well 104 to above the edge portion 108a of the isolation layer 108, and a gate is generally provided between the gate layer 110 and the substrate 100 An oxide layer (not shown), a spacer (not shown) may be formed on the sidewall of the gate layer 110. The material of the gate layer 110 may be polysilicon or other suitable conductive materials.

The floating conductor layer 116 is formed above the isolation layer 108, and the distance s1 between the floating conductor layer 116 and the drain region 114 is smaller than the distance s2 between the floating conductor layer 116 and the source region 112; also In other words, the position of the floating conductor layer 116 is closer to the drain region 114 and far from the source well 104. Since an electrically floating floating conductor layer 116 is provided above the isolation layer 108, an ultra-high voltage (such as 500V or more) is applied to the drain region 114, and the electric field distribution under the isolation layer 108 will be as shown in FIG. The existence of the conductive layer 116 maintains a small fixed electric field and then increases to the source region 112, which can prevent the voltage surge from occurring and reduce Ron, so that the breakdown voltage is further increased. In comparison, the electric field distribution without a floating conductor layer obviously has a sudden rise area 400. In one embodiment, the distance s1 between the floating conductor layer 116 and the drain region 114 can be kept at least 1 µm, in one embodiment it is above 4 µm, in another embodiment it is above 8 µm, and With a floating conductor layer 116 with a width w1 degree of about 4 µm, the breakdown voltage can reach more than 500V. In one embodiment, the width w1 of the floating conductive layer 116 is 0.025 to 0.8 times the width w2 of the isolation layer 108 (see FIG. 1). In an embodiment, the thickness t1 of the floating conductor layer 116 is 0.2 to 0.3 times, for example, 0.22 to 0.3 times, of the thickness t2 of the isolation layer 108. The material of the floating conductor layer 116 includes polysilicon or metal (for example, aluminum); if it is polysilicon, the floating conductor layer 116 can be formed at the same time as the gate layer 110, so additional steps can be avoided. However, the present invention is not limited to this.

In FIG. 2, the semiconductor device 10 may further include a drift region 124 formed in the high-pressure well 102 under the isolation layer 108. In this embodiment, the drift region 124 includes a top region 126 having a first conductivity type and a grade region 128 having a second conductivity type. The gradient region 128 is formed between the isolation layer 108 and the top region 126 . In an embodiment, the gradient region 128 may extend out of the isolation layer 108 and be connected to the gate layer 110. Moreover, the drift region 124 may be located directly under the floating conductor layer 116 or partially overlapped with the floating conductor layer 116.

3 is a schematic cross-sectional view of a semiconductor device according to another embodiment of the present invention, in which the component symbols of the previous embodiment are used to denote the same or similar components, and the description of the same components can refer to the related descriptions of the previous embodiment The content will not be repeated here.

In FIG. 3, formed above the isolation layer 108 are two floating conductor layers 300a and 300b, wherein the distance s1 between the floating conductor layer 300b and the drain region 114 is smaller than the floating conductor layer 300a and the source region 112 The distance s2 between the two, and the distance s1 can be kept above 1 µm, for example, above 8 µm. In other words, the floating conductor layers 300a and 300b are regarded as a whole, so even if the floating conductor layers 300a and 300b are not coupled to each other, they are closer to the drain region 114 and far from the source well 104 as a whole. Although FIG. 3 shows two floating conductor layers 300a and 300b, the present invention is not limited to this, and the number of floating conductor layers can also be greater than two, such as three, four, etc. The width w3 of the floating conductor layers 300a and 300b can be 0.025 to 0.37 times the width w2 of the isolation layer 108.

Several experiments are listed below to more specifically verify the efficacy of the semiconductor device of the present invention. However, without going beyond the scope of the present invention, the materials used, quantity and size ratio, parameters, measurement methods, etc. can be appropriately changed. Therefore, the present invention should not be interpreted restrictively based on the experiments described below.

<Experimental example 1>

Fabricate the semiconductor device as shown in Figure 2, where the standard dose (STD) of the N-type high pressure well (102) is 3.5E12/cm ² , and the standard dose (STD) of the P-type top zone (126) is 8E12/cm ² , And the distance (s1) between the fixed floating conductor layer and the drain region is 8 µm. Then, the widths of the floating conductor layer of polysilicon were 4μm, 6μm and 8μm, and the breakdown voltage (BVD) curve was measured when the dose ratio of the N-type high-voltage well was changed. The results are shown in Fig. 5.

<Experimental example 2>

Fabricate the semiconductor device shown in Figure 2, where the thickness of the polysilicon floating conductor layer is about 1300 Å, the thickness of the silicon oxide isolation layer is about 6000 Å, and the standard dose (STD) of the N-type high pressure well (102) is 3.5E12/cm ² , The standard dose (STD) of the P-type top region (126) is 8E12/cm ² , and the distance (s1) between the fixed floating conductor layer and the drain region is 8 μm. Then, the widths of the floating conductor layer of polysilicon were 4μm, 6μm and 8μm, and the change curve of breakdown voltage was measured when the dose ratio of the P-type top region was changed.

<Comparative Example 1>

The semiconductor device as shown in Figure 2 was fabricated, but there was no floating conductor layer, and the remaining conditions were the same as in Experimental Example 1. The change curve of the breakdown voltage was measured when the dose ratio of the N-type high-voltage well was changed. The results are shown in Figure 5.

<Comparative Example 2>

The semiconductor device as shown in Figure 2 was fabricated, but there was no floating conductor layer, and the remaining conditions were the same as in Experimental Example 2. The change curve of the breakdown voltage was measured when the dose ratio of the P-type top region was changed. The results are shown in Figure 6.

It can be obtained from Fig. 5 that the breakdown voltage of Experimental Example 1 with a floating conductor layer increases with the increase of the dose of the N-type high voltage well, which means that the charge of n is greater than the charge of p (Qn>Qp) can increase the breakdown voltage; from Fig. 6 It can be obtained that the breakdown voltage of Experimental Example 2 with a floating conductor layer increases as the dose of the P-type top region decreases, which also means that Qn>Qp can increase the breakdown voltage. In contrast, Comparative Examples 1 to 2 with no floating conductor layer did not show the above trend.

<Ron Analysis>

Obtain the dose of N-type high-voltage well +7% and the dose of P-type top region -9% for the N-type high voltage well with a breakdown voltage of more than 500V in Experimental Examples 1~2 (the width of the floating conductor layer is 4µm), and there is no floating conductor layer. Ron, where the doses of the N-type high pressure well and the P-type top zone are both standard values, are shown in Fig. 7. It can be obtained from the Ron measured three times in Fig. 7 that if there is a floating conductor layer, if the dose of the N-type high pressure well is +7% of the standard dose or the dose of the P-type top zone is -9% of the standard dose, Both can improve Ron by more than 5%. Therefore, according to the inference, adjusting the dose of the N-type high-pressure well and the dose of the P-type top zone at the same time can also further reduce Ron.

In summary, the present invention provides a floating conductor layer above the isolation layer, so that when an ultra-high voltage (such as 500V or more) is applied to the drain region, the electric field distribution can maintain a fixed electric field due to the existence of the floating conductor layer. , And then increase to the source region, so it can avoid the voltage surge and reduce Ron, and then increase the breakdown voltage, which is beneficial to the application of ultra-high voltage components.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the relevant technical field can make some changes and modifications without departing from the spirit and scope of the present invention. The scope of protection of the present invention shall be determined by the scope of the attached patent application.

10: Semiconductor device

100: substrate

102: high pressure well

104: Source Well

104a, 108a: edge part

106: Kick Well

108: isolation layer

110: gate layer

112: source region

114: Drain Region

116, 300a, 300b: floating conductor layer

118: The first heavily doped region

120: second heavily doped region

122: Field Oxide

124: Drift Zone

126: Top Zone

128: gradient zone

400: Sudden rise area

s1, s2: distance

t1, t2: thickness

w1, w2, w3: width

FIG. 1 is a schematic top view of a semiconductor device according to an embodiment of the invention. FIG. 2 is a schematic cross-sectional view of the semiconductor device along the line II-II' of FIG. 1. FIG. 3 is a schematic cross-sectional view of a semiconductor device according to another embodiment of the invention. 4 is a diagram of the electric field distribution under the isolation layer of the semiconductor device of FIG. 2. Figure 5 is a graph showing the breakdown voltage curves of Experimental Example 1 and Comparative Example 1 with the dose ratio of the N-type high-pressure well. Fig. 6 is a graph showing the breakdown voltage curve of Experimental Example 2 and Comparative Example 2 with the variation of the dose ratio of the P-type top zone. Fig. 7 is a Ron curve diagram of experimental example 1, experimental example 2, and no floating conductor layer and the doses of the N-type high pressure well and the P-type top zone are all standard values.

10: Semiconductor device

100: substrate

102: high pressure well

104: Source Well

104a, 108a: edge part

106: Kick Well

108: isolation layer

110: gate layer

112: source region

114: Drain Region

116: floating conductor layer

118: The first heavily doped region

120: second heavily doped region

122: Field Oxide

124: Drift Zone

126: Top Zone

128: gradient zone

s1, s2: distance

t1, t2: thickness

w1: width

Claims (7)

A semiconductor device includes: a substrate with a first conductivity type; a high-voltage well with a second conductivity type and formed in the substrate; a source well with the first conductivity type and formed In the substrate on one side of the high-pressure well; a drain well having the second conductivity type and formed in the high-pressure well; an isolation layer formed between the source well and the drain Above the high pressure well between the pole wells; a gate layer formed above the substrate and continuously extending from above an edge portion of the source well to above an edge portion of the isolation layer; a source A pole region is formed in the source well beside the gate layer; a drain region is formed in the drain well; at least one floating conductor layer is formed above the isolation layer, and the floating The distance between the conductive layer and the drain region is smaller than the distance between the floating conductive layer and the source region; and a drift region is formed in the high-voltage well below the isolation layer, wherein The drift region includes: a top region having the first conductivity type; and a gradient region having the second conductivity type formed between the isolation layer and the top region, wherein the gradient region Extend the isolation layer and connect with the gate layer. The semiconductor device according to claim 1, wherein the at least one floating conductor layer includes two or more floating conductor layers. The semiconductor device according to claim 1, wherein the distance between the floating conductor layer and the drain region is 1 μm or more. The semiconductor device according to claim 1, wherein the width of the at least one floating conductor layer is 0.025 to 0.8 times the width of the isolation layer. The semiconductor device according to claim 1, wherein the thickness of the at least one floating conductor layer is 0.22 to 0.3 times the thickness of the isolation layer. The semiconductor device according to claim 1, wherein the material of the floating conductor layer includes polysilicon or metal. The semiconductor device according to claim 1, wherein the drift region is located directly under the floating conductor layer.

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