TWI718975B - Method and device for increasing read/write speed of memory data - Google Patents

Abstract

A method for increasing read/write speed of memory data includes executing a read operation in a memory region when a write operation is executing in the memory region. After data of a page in the memory region is read, the method doesn’t need to send a write command to mark the page as a read state. So the method can increase read/write speed and reduce a delay time in data transmission.

Description

Method and device for improving reading and writing speed of memory data

The invention relates to a data reading and writing device, in particular to a method and device for improving the reading and writing speed of memory data.

FIG. 1 shows a conventional data reading and writing device 10, which includes a writing circuit 12, a memory circuit 14, and a reading circuit 16. The writing circuit 12 may be a field programmable gate array (FPGA). The memory circuit 14 may be a dynamic random access memory (DRAM). The reading circuit 16 may be a host, such as a central processing unit (CPU). As shown in FIG. 1, the memory circuit 14 has a plurality of memory regions 142, 144, 146, and 148, and the writing circuit 12 sequentially writes data into the plurality of memory regions 142, 144, 146, and 148 . When the writing circuit 12 completes the writing operation of the memory block 142, the writing circuit 12 will change the flag data of the status register (not shown in the figure) corresponding to the memory block 142 to "1" to change the memory block 142. Block 142 is marked as written. At this time, the writing circuit 12 will also send a signal to the reading circuit 16 to inform the reading circuit 16 that the memory block 142 can be read. The state register can be provided in the writing circuit 12. As shown in FIG. 2, when the writing circuit 12 starts to write the memory block 144, the software 162 of the reading circuit 16 also starts to read the data in the memory block 142. After all the data in the memory block 142 has been read, the read circuit 16 will send a clear command S1 to the write circuit 12 to change the tag data corresponding to the memory block 142 to "0" to change the memory block 142 Mark as read status. The conventional data reading and writing device 10 must wait for the entire memory block 142 to complete the writing operation before reading the data in the memory block 142. Therefore, it takes a long time for the writing circuit 12 to write data to the reading circuit 16 to obtain data. The read and write time (the read and write speed is slower), resulting in a greater delay in data transfer.

In addition, the traditional memory blocks 142, 144, 146, and 148 each have multiple pages. Taking the memory block 142 as an example, the memory block 142 has multiple pages P0~Pn, as shown in FIG. 3 . Each page P0~Pn has a mask area A1 and a data area A2. After the writing circuit 12 writes the data into the data area A2 of the page P0, the writing circuit 12 will also write the data "1" into the marking area A1 of the page P0 to indicate that the page P0 has completed the writing operation. Similarly, when the writing circuit 12 writes data into the data area A2 of the pages P1 to Pn, the marking area A1 of the pages P1 to Pn will also be written with the data "1". After the reading circuit 16 reads the data in the data area A2 of the page P0, the reading circuit 16 will send a write command to change the data in the mark area A1 of the page P0 from "1" to "0". That is to say, whenever the reading circuit 16 reads a page of data, a write operation must be performed to write the data "0" into the marked area A1, which results in a longer read and write time and a delay in data transmission.

The purpose of the present invention is to provide a method and device for improving the reading and writing speed of memory data.

According to the present invention, a method for improving the read and write speed of memory data includes detecting a first mark area and a second mark in a first page of a memory block when the write operation is performed on the first page of the memory block Area data, judging whether to write a first data into the page based on the detected data, and when writing the first data into the page, change the first mark area and the second mark area at the same time Data to change the page to the written state; and when the first page is read, the data of a first mark area and a second mark area in the first page are detected, according to the detected data The measured data determines whether to read the first data in the page and when reading the first data, the data in the first marking area and the second marking area are not changed.

According to the present invention, a device for increasing the speed of reading and writing memory data includes a memory circuit, a writing circuit, and a reading circuit. The memory circuit has a plurality of memory blocks, each memory block has a plurality of pages, and each page has a first marking area, a second marking area and a data area. When the writing circuit performs a writing operation on the first page of the plurality of pages, it detects that the first mark area of the first page has a first cycle data or a second cycle data and detects the first The second mark area of the page has an even-numbered data or an odd-numbered data, and according to the detected data, it is determined whether to write a first data into the data area of the first page, and the writing circuit is in the data area of the first page. When the first data is written into the data area, the data of the first marking area and the second marking area are changed at the same time. When performing a reading operation on the first page, the reading circuit detects that the first mark area has the first cycle data or the second cycle data and detects that the second mark area has the even data or the odd number Data, and determine whether to read the first data in the data area based on the detected data, the reading circuit does not change the first mark area and the second mark area when reading the first data data.

When the method and device of the present invention perform a write operation on a memory block, the memory block can be read at the same time, and after the data of the page in the memory area is read, there is no need to send a write The instruction marks the page as read status, so the read and write speed can be increased, and the delay time of data transmission can be reduced.

4 shows the device 20 for improving the reading and writing speed of memory data according to the present invention, which includes a writing circuit 22, a memory circuit 24, and a reading circuit 26. The writing circuit 22 may be, but is not limited to, a field programmable logic gate array (FPGA). The memory circuit 24 may be, but is not limited to, dynamic random access memory (DRAM). The reading circuit 26 may be a host, such as a central processing unit (CPU). The memory circuit 24 has a plurality of memory blocks 242, 244, 246, and 248. The writing circuit 22 can perform a writing operation to write data into the memory circuit 24, and the software 262 of the reading circuit 26 can perform a reading operation to read the data in the memory circuit 24. The writing circuit 22 and the reading circuit 26 can write and read the same memory block at the same time. Therefore, the device 20 of the present invention can shorten the read and write time (improve the read and write speed) and reduce the delay of data transmission. Taking the memory block 242 as an example, before the writing circuit 22 writes to the memory block 242, it first judges the memory through the mark data of the state register (not shown) corresponding to the memory block 242. Whether the block is in the read state "0". If the judgment is yes, the writing circuit 22 starts to write the memory block 242. When the write operation of the memory block 242 is completed, the write circuit 22 will change the flag data of the status register (not shown in the figure) corresponding to the memory block 242 to "1" to mark the memory block 242 as written Into state. The state register can be provided in the writing circuit 12. When the writing circuit 22 writes the memory block 242, the software 262 of the reading circuit 26 can also read the data of the memory block 242 at the same time. After all the data in the memory block 242 is read, the read circuit 26 will send a clear command S1 to the write circuit 22 to change the mark data corresponding to the memory block 242 to "0" to mark the memory block 242 The status has been read.

FIG. 5 shows an embodiment of the memory block 242 in FIG. 4, which includes a plurality of pages P0~Pn, and each page P0~Pn has a first mark area AR, a second mark area AOE, and a data area AD. The writing circuit 22 can determine whether the pages P0 to Pn have written data through the data in the first marking area AR and the second marking area AOE. For example, the writing circuit 22 can judge whether the current write operation has written data to the page P0 through the data in the first mark area AR of the page P0, and the writing circuit 22 can judge through the data in the second mark area AOE of the page P0. It is judged whether the current write operation is odd (odd) or even (even) times.

5 to 7 are used to illustrate the write operation and read operation of the memory block 242 in FIG. 4. Assuming that when the device 20 is just started, the memory block 242 is marked as a read state, and the first marked area AR of all pages P0~Pn in the memory block 242 has the first round data "0", and The second mark area AOE all have even data "0", as shown in FIG. 5. When the writing circuit 22 performs a writing operation on the page P0, the writing circuit 22 first detects the data in the first marking area AR and the second marking area AOE of the page P0. When the first cycle data "0" of the first mark area AR and the even data "0" of the second mark area AOE and the second cycle data "1" and the odd data "1" stored by the writing circuit 22 are detected At the same time, the writing circuit 22 determines that the page P0 has not been written with data, and therefore writes the first data D11 into the data area AD of the page P0, and simultaneously writes the second cycle data "1" and the odd data "1" into the first A marking area AR and a second marking area AOE. When it is detected that the data in the first mark area AR and the second mark area AOE is completely or partially the same as the data stored in the writing circuit 22, the writing circuit 22 determines that the page P0 has been written with data, so it is not written The first data D1 to page P0, and the writing operation of page P0 is ended.

Referring to FIG. 6, after the writing operation of page P0 is completed, the writing circuit 22 then performs a writing operation on page P1, and the writing operation of page P1 is the same as that of page P0, so it will not be repeated. When the writing circuit 22 performs a writing operation on the page P1 to write the second data D12 into the data area AD of the page P1, the reading circuit 26 also reads the first data D11 of the data area AD of the page P0 at the same time. During the reading operation, the reading circuit 26 first detects the data in the first marking area AR and the second marking area AOE of the page P0. When the second cycle data "1" of the first mark area AR and the odd data "1" of the second mark area AOE and the second cycle data "1" and the odd data "1" stored by the reading circuit 26 are detected At the same time, the reading circuit 22 determines that the first data D11 in the data area AD of the page P0 has not been read, and thus reads the first data D11 in the page P0. When it is detected that the data in the first mark area AR and the second mark area AOE is completely different or partly different from the data stored in the reading circuit 22, the reading circuit 22 determines that the data in the page P0 has been read, so no more Read the first data of page P0, and end the read operation of page P0. Referring to FIG. 7, after reading the first data D11, the reading circuit 26 of the present invention will not send a write command to change the data "1" of the first mark area AR and the second mark area AOE in the page P0. Since the reading circuit 26 of the present invention does not need to perform a writing operation, the device 20 of the present invention can further shorten the reading and writing time (improving the reading and writing speed) and reduce the delay of data transmission.

4, when the write circuit 22 performs all the memory blocks 242, 244, 246, and 248 in the memory circuit 24 and completes the write operation, it represents the end of the first write cycle, and then the write circuit 22 can Write to the first memory area 242 to start the second write cycle. At the same time, the second cycle data "1" and the odd data "1" stored in the write circuit 22 will be changed to the first cycle data " 0" and even data "0". Similarly, after the reading circuit 26 has performed all the memory blocks 242, 244, 246, and 248 in the memory circuit 24 and completed the reading operation, it represents the end of the first reading cycle. Then, the reading circuit 26 can start reading data from the first memory area 242 to enter the second reading cycle, and at the same time, the second cycle data "1" and the odd data "1" stored in the reading circuit 26 will be separately Change to the first cycle data "0" and the even data "0".

8 and 9 are used to illustrate the operation of the memory block 242 in the second cycle. As shown in FIG. 8, when the first cycle ends, the first mark area AR of all pages P0~Pn in the memory block 242 are all changed to the second cycle data "1", and the second mark area AOE is all changed to odd numbers Data "1". When the writing circuit 22 performs the second cycle of writing operation on the page P0, the writing circuit 22 will also first detect the data in the first marking area AR and the second marking area AOE of the page P0. When the second cycle data "1" of the first mark area AR and the odd data "1" of the second mark area AOE and the first cycle data "0" and even data "0" stored in the writing circuit 22 are detected At the same time, the writing circuit 22 determines that the page P0 has not been written with data, and thus writes the first data D21 into the data area AD of the page P0. At the same time, the writing circuit 22 will also write the first cycle data "0" and the even data "0" into the first mark area AR and the second mark area AOE, respectively.

Referring to FIG. 9, after the writing circuit 22 completes the writing operation of the page P0, the writing circuit 22 then performs the writing operation on the page P1. Since the writing operation of page P1 is the same as that of page P0, it will not be repeated here. When the writing circuit 22 performs a writing operation on the page P1 to write the second data D22 into the data area AD of the page P1, the reading circuit 26 also performs a second cycle of reading operation at the same time to read the data area AD of the page P0 The first information D21. During the reading operation, the reading circuit 26 first detects the data in the first marking area AR and the second marking area AOE of the page P0. When detecting the first cycle data "0" of the first mark area AR and the even data "0" of the second mark area AOE and the first cycle data "0" and the even data "0" stored by the reading circuit 26 At the same time, the reading circuit 22 determines that the first data D21 in the data area AD of the page P0 has not been read, and thus reads the first data D21 in the page P0. Similarly, after reading the first data D21, the reading circuit 26 will not send a write command to change the data in the first marking area AR and the second marking area AOE in the page P0.

FIG. 10 shows another embodiment of the memory block 242 in FIG. 4. The difference between the memory block 242 in FIG. 10 and FIG. 5 is that the first mark area AR of the memory block 242 in FIG. 10 has two bytes (16 bits) to store the first cycle data "00" and the second The cyclic data "FF", the second mark area AOE also has two bytes to store the even data "00" and the odd data "FF". When at least one of the two bytes of the first mark area AR is abnormal or malfunctioning, causing the data presented by the two bytes to be not "00" or "FF", for example, the data of the two bytes is not "00" or "FF". The data is "03" or "AA". At this time, the writing circuit 22 and the reading circuit 26 can determine that the first mark area AR has the first mark area according to the data "03" or "AA" of the two bytes is closer to "00" or "FF". Cycle data "00" or second cycle data "FF". For example, the writing circuit 22 and the reading circuit 26 can compare the detected data "03" or "AA" with a preset value "88". Assuming that the detected data is "03", the value "0" of the first byte in the data "03" and the value "3" of the second byte are respectively smaller than the first value in the preset value "8" and the second value "8", so it is judged that the data "03" is closer to the first cycle data "00". In this way, the writing circuit 22 and the reading circuit 26 will determine that the first marking area AR has the first cycle data "00". Assuming that the detected data is "AA", the value "A" of the first byte in the data "AA" and the value "A" of the second byte are respectively greater than the first value in the default value "8" and the second value "8", so it is determined that the data "AA" is closer to the first cycle data "FF", the writing circuit 22 and the reading circuit 26 will determine that the first marking area AR has the second cycle data " FF". Similarly, when at least one bit of the two byte groups of the second mark area AOE is abnormal or faulty, the same method can also be used to determine that the second mark area AOE has even-numbered data "00" or odd-numbered data "FF". . The aforementioned way of judging data that is closer to "00" or "FF" is just for explaining the present invention, and it does not limit the present invention to only use this way to make judgments. In the embodiment of FIG. 10, both the first mark area AR and the second mark area AOE have multiple bits. Therefore, even if some of the bits are damaged, the present invention can still operate normally and extend the service life of the memory circuit 24.

In FIGS. 5 to 10, the first marking area AR and the second marking area AOE have one bit or two bytes (multiple bits) as an example for illustration, but the present invention is not limited to this. The number of bits in the first mark area AR and the second mark area AOE can be changed. For example, the first mark area AR and the second mark area AOE can also use two bits, three bits, one byte group, or It consists of three bytes. In addition, the number of bits in the first marking area AR and the second marking area AOE is not necessarily the same. For example, the first marking area AR may have two bits, and the second marking area AOE may have three bits.

The above description of the preferred embodiments of the present invention is for the purpose of clarification, and is not intended to limit the present invention to the disclosed form accurately. Modifications or changes are possible based on the above teachings or learning from the embodiments of the present invention Yes, the embodiments are selected and described in order to explain the principles of the present invention and allow those familiar with the technology to use the present invention in various embodiments in practical applications. The technical ideas of the present invention are intended to be derived from the scope of subsequent patent applications and their equality. Decided.

10: Data reading and writing device 12: Write circuit 14: Memory circuit 142: memory block 144: memory block 146: memory block 148: memory block 16: Reading circuit 162: Software 20: device 22: Write circuit 24: Memory circuit 242: memory block 244: memory block 246: memory block 248: memory block 26: read circuit 262: software

Figure 1 shows a conventional data reading and writing device. Figure 2 shows the reading and writing operations of the data reading and writing device of Figure 1. Figure 3 shows the memory block in Figure 1. Figure 4 shows the device of the present invention for improving the speed of reading and writing memory data. 5 to 9 are used to illustrate the write operation and read operation of the memory block in FIG. 4. FIG. 10 shows another embodiment of the memory block in FIG. 4.

20: device

22: Write circuit

24: Memory circuit

242: memory block

244: memory block

246: memory block

248: memory block

26: read circuit

262: software

Claims (11)

A method to increase the speed of reading and writing memory data, including: When writing a first page of a memory block marked as read, the following steps are performed: Detecting that a first mark area of the first page has a first cycle data or a second cycle data; Detecting that a second mark area of the first page has an even-numbered data or an odd-numbered data; When the first marked area has the first cycle data and the second marked area has the even-numbered data, write a first data into a data area of the first page, and the second cycle data and the odd-numbered data Data is written into the first marking area and the second marking area respectively; and When the first mark area has the second cycle data and the second mark area has the odd data, the first data, the first cycle data, and the even data are written into the data area and the first mark respectively Zone and the second marking zone; and After the writing operation of the first page is completed, when reading the first page, the following steps are performed: Detecting that the first marking area has the first cycle data or the second cycle data; Detecting that the second marking area has the even-numbered data or the odd-numbered data; and When the first mark area has the first cycle data and the second mark area has the even data, or when the first mark area has the second cycle data and the second mark area has the odd data, read Get the first data in the data area; Wherein, after reading the first data, no data is written to the first marking area and the second marking area. Such as the method of claim 1, wherein the first mark area has a plurality of bits for storing the first cycle data or the second cycle data. For example, the method of claim 2, further comprising determining that the first marking area has the first cycle data when the value of the plurality of bits is less than a preset value, and determining the first cycle data when the value is greater than the preset value The marked area has the second cycle data. Such as the method of claim 1, wherein the second mark area has a plurality of bits for storing the even-numbered data or the odd-numbered data. For example, the method of claim 4 further includes determining that the second marking area has the even-numbered data when the value of the plurality of bits is less than a preset value, and determining the second marking area when the value is greater than the preset value Have the odd data. A device for improving the reading and writing speed of memory data, including: A memory circuit having a plurality of memory blocks, wherein each memory block has a plurality of pages, and each page has a first marking area, a second marking area and a data area; A write circuit connected to the memory circuit for detecting that the first marking area has a first cycle data or a second cycle data and detecting that the second marking area has an even data or an odd data, wherein When the first mark area has the first cycle data and the second mark area has the even data, the writing circuit writes the second cycle data, the odd data, and a first data into the first mark respectively Area, the second mark area, and the data area, and when the first mark area has the second cycle data and the second mark area has the odd data, the write circuit sends the first cycle data, the even data Data and the first data are respectively written into the first marking area, the second marking area and the data area; and A reading circuit connected to the memory circuit for detecting that the first marking area has the first cycle data or the second cycle data and detecting that the second marking area has the even-numbered data or the odd-numbered data, wherein When the first mark area has the first cyclic data and the second mark area has the even-numbered data or the first mark area has the second cyclic data and the second mark area has the odd-numbered data, the read The fetch circuit reads the first data in the data area, and after reading the first data, does not write any data to the first mark area and the second mark area. Such as the device of claim 6, wherein the writing circuit and the reading circuit simultaneously perform writing and reading operations on the same memory block. Such as the device of claim 6, wherein the first mark area has a plurality of bits for storing the first cycle data or the second cycle data. For example, the device of claim 8, wherein when the writing circuit and the reading circuit detect that the value of the plurality of bits is less than a preset value, it is determined that the first marking area has the first cycle data, and the writing circuit When the input circuit and the read circuit detect that the value is greater than the preset value, it is determined that the first mark area has the second cycle data. Such as the device of claim 6, wherein the second mark area has a plurality of bits for storing the even-numbered data or the odd-numbered data. For example, in the device of claim 10, when the writing circuit and the reading circuit detect that the value of the plurality of bits is less than a preset value, it is determined that the second mark area has the even-numbered data, and the writing circuit And when the reading circuit detects that the value is greater than the preset value, it determines that the second mark area has the odd data.

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