TWI717192B - Electrostatic discharge blocking circuits - Google Patents

Abstract

An electrostatic discharge blocking circuit including an internal circuit, a schottky diode and an electrostatic discharge (ESD) releasing element is provided. The schottky diode is coupled between a specific node and the internal circuit. The ESD releasing element is coupled between the specific circuit and a power terminal. When an ESD event occurs, the ESD releasing element is turned on to release an ESD current from the specific node to the power terminal.

Description

Electrostatic discharge resistance isolation circuit

The present invention relates to an electrostatic discharge resistance isolation circuit, in particular to an electrostatic discharge resistance isolation circuit with an electrostatic discharge release element.

The electrostatic discharge (ESD) event of the integrated circuit refers to the discharge process of the electrostatic charge with high voltage through the integrated circuit chip. Although the amount of such electrostatic charge is usually not large, due to the high voltage, the instantaneous energy released is also considerable. If it is not handled properly, it will often cause the integrated circuit to burn out.

Therefore, ESD has become one of the important reliability considerations in semiconductor products. There are two types of ESD tests that are familiar to ordinary people, the human body model (HBM) and the machine model (MM). Generally, commercial integrated circuits must have a certain degree of HBM and MM tolerance before they can be sold. Otherwise, integrated circuits are easily damaged by accidental ESD events. Therefore, how to manufacture an efficient ESD protection device/component to protect the integrated circuit is a topic that the industry has been continuously discussing and researching.

The invention provides an electrostatic discharge resistance isolation circuit, which includes an internal circuit, a Schottky diode and an electrostatic discharge release element. The Schottky diode is coupled between a specific node and the internal circuit. The electrostatic discharge component is coupled between a specific node and a power terminal. When an electrostatic discharge event occurs at a specific node, the electrostatic discharge release element is turned on to discharge an electrostatic discharge current from the specific node to the power terminal.

In order to make the purpose, features and advantages of the present invention more comprehensible, embodiments are specifically listed below, in conjunction with the accompanying drawings, for detailed description. The specification of the present invention provides different examples to illustrate the technical features of different embodiments of the present invention. Wherein, the configuration of each element in the embodiment is for illustrative purposes, and is not intended to limit the present invention. In addition, the part of the repetition of the drawing symbols in the embodiments is for simplifying the description and does not mean the relevance between different embodiments.

Figure 1 is a schematic diagram of the structure of the electrostatic discharge resistance isolation circuit of the present invention. As shown in the figure, the electrostatic discharge resistance isolation circuit 100 includes an internal circuit 110, a schottky diode 120 and an electrostatic discharge discharge element 130. Internal circuit 110 is coupled between _a cathode of Schottky diode of the power supply terminal PT 120. The Schottky diode 120 is coupled between a specific node ND and the internal circuit 110 to block an electrostatic discharge current from entering the internal circuit 110 from the specific node ND. In this schematic diagram, the anode of the Schottky diode 120 is coupled to a specific node ND, and the cathode thereof is coupled to the internal circuit 110. ESD release element 130 is coupled between the node ND ₁ and the specific power supply terminal PT, to release the ESD current.

When an ESD event occurs at a particular node ND, and the power supply terminal coupled to the PT _1, the electrostatic discharge circuit 100 enters a blocking protection mode. In the protection mode, the electrostatic discharge discharge element 130 is turned on to discharge an electrostatic discharge current from the specific node ND to the power terminal PT ₁ . In this schematic diagram, due to the high AC resistance of the Schottky diode 120, the Schottky diode 120 does not conduct in the initial stage of the electrostatic discharge event to prevent the electrostatic discharge current from entering Internal circuit 110. In addition, since the trigger voltage of the ESD discharge element 130 is lower than the total trigger voltage of the Schottky diode 120 plus the internal circuit 110, the path of the ESD discharge element 130 will be earlier than the path of the Schottky diode 120 Conduction.

When the electrostatic discharge event does not occur, the electrostatic discharge isolation circuit 100 operates in a normal mode. In the normal mode, since the Schottky diode 120 has a low DC resistance, when a specific node ND receives an external signal or voltage, the Schottky diode 120 can be quickly turned on. To transmit the signal or voltage of the specific node ND to the internal circuit 110. In this schematic diagram, the internal circuit 110 operates according to the signal or voltage of a specific node ND. The invention does not limit the structure of the internal circuit 110. Any circuit that needs ESD protection can be used as the internal circuit 110.

Figure 2 is a possible embodiment of the electrostatic discharge resistor isolation circuit of the present invention. In this embodiment, the specific node ND is used as an input node to provide a signal or voltage to the internal circuit 110. In a possible embodiment, the specific node ND receives and provides the voltage VPP ₁ or VPP ₂ to the internal circuit 110. In addition, the internal circuit 110 is further coupled to a power terminal PT ₂ . The power terminal PT _{2 is} used to receive the operating voltage VDD. In this embodiment, the power source terminal PT ₁ for receiving the operating voltage VSS. The operating voltage VDD is greater than the operating voltage VSS. In some embodiments, the operating voltage VSS may be a negative value.

The internal circuit 110 starts to operate according to the operating voltages VDD and VSS. In this embodiment, the operating voltages VDD and VSS are used as the operating voltages of the internal circuit 110, so the operating voltages VDD and VSS must be respectively stabilized at a fixed value. For example, the operating voltage VDD may be maintained at 3.3V, and the operating voltage VSS may be maintained at 0V. When the operating voltages VDD and VSS are unstable, the internal circuit 110 may not work normally.

Relative to the operating voltages VDD and VSS, the voltage of the specific node ND does not maintain a fixed value. For example, in a first period (such as a writing period), the voltage of the specific node ND is equal to the voltage VPP ₁ , and in a second period (such as a reading period), the voltage of the specific node ND is equal to the voltage VPP ₂ . In a possible embodiment, the voltage VPP _{1 is} greater than the voltage VPP ₂ .

The invention does not limit the structure of the internal circuit 110. In one possible embodiment, the internal circuit 110 is a one-time programmable memory (OTP memory), and has an access circuit 211 and a memory array 212.

The access circuit 211 is used to access the memory array 212. The present invention does not limit the structure of the access circuit 211. In a possible embodiment, the access circuit 211 performs a write operation on the memory array 212 according to the voltage VPP ₁ to write the value 1 or the value 0 into the memory array 212. In another possible embodiment, the access circuit 211 performs a read operation on the memory array 212 according to the voltage VPP ₂ to retrieve data stored in the memory array 212.

The memory array 212 has a plurality of memory cells (not shown). The present invention does not limit the structure of the memory cell. In a possible embodiment, each memory cell of the memory array 212 has at least one transistor, and each transistor has a floating gate. During the write operation, the access circuit 211 provides the voltage VPP ₁ to the corresponding memory cell to accumulate charge on the floating gate of the memory cell. In this example, when the floating gate of the memory cell has sufficient charge, it means that the memory cell stores a first value (such as 1 or 0). When the floating gate of the memory cell has no charge, it means that the memory cell stores a second value (such as 0 or 1).

In another possible embodiment, each memory cell of the memory array 212 has at least one transistor. In this example, the access circuit 211 may use the voltage VPP _{1 to} break down the gate oxide layer of the transistor of the corresponding memory cell. When the gate oxide layer of the transistor of the memory cell is broken down, it means that the memory cell stores the first value. When the gate oxide layer of the transistor of the memory cell is not broken down, it means that the memory cell stores the second value.

In other embodiments, each memory cell of the memory array 212 has at least one fuse. In this example, the access circuit 211 may use the voltage VPP ₁ to blow the fuse of the corresponding memory cell. When the fuse of the transistor of the memory cell is blown, it means that the memory cell stores the first value. When the fuse of the transistor of the memory cell is not blown, it means that the memory cell stores the second value.

When an electrostatic discharge event occurs at a specific node ND and the power terminal PT _{1 is} coupled to the ground, the electrostatic discharge release element 130 is turned on to discharge the electrostatic discharge current from the specific node ND to the power terminal PT ₁ . In this embodiment, since the Schottky diode 120 blocks the electrostatic discharge current from flowing into the internal circuit 110, it can prevent the access circuit 211 and the memory array 212 from being damaged.

Figure 3 is another possible embodiment of the electrostatic discharge resistor isolation circuit of the present invention. In this embodiment, the specific node ND serves as a power terminal for receiving the operating voltage VDD. The internal circuit 110 starts to operate according to the operating voltages VDD and VSS. In one possible embodiment, the internal circuit 110 includes a P-type transistor 313, N-type transistors 314 and 315.

The source of the P-type transistor 313 is coupled to the cathode of the Schottky diode 120. The drain of the P-type transistor 313 is coupled to the drain of the N-type transistor 314. The source of the N-type transistor 314 is coupled to the power terminal PT ₁ . The gate of the N-type transistor 314 is coupled to the gate of the P-type transistor 313 and the drain of the N-type transistor 315. The gate and source of the N-type transistor 315 are coupled to the power terminal PT ₁ .

When an ESD event occurs at a particular node ND, and the power terminal PT ₁ is coupled to ground by a high impedance Schottky diode 120, the ESD current can be blocked into the internal circuit 110, to avoid ESD current Damage P-type transistor 313, N-type transistor 314 and 315. Furthermore, since the on-voltage of the ESD discharge element 130 is lower than the total on-voltage of the Schottky diode 120 plus the internal circuit 110, the path of the ESD discharge element 130 is longer than that of the Schottky diode 120. The early turn-on is used to discharge the electrostatic discharge current from the specific node ND to the power terminal PT ₁ via the electrostatic discharge release element 130.

In this embodiment, the electrostatic discharge release element 130 includes an N-type transistor 311. The drain of the N-type transistor 311 is coupled to a specific node ND, and its gate and source are coupled to the power terminal PT ₁ . When an electrostatic discharge event occurs at a specific node ND, the parasitic bi-carrier transistor 312 of the N-type transistor 311 is turned on, thus turning on the N-type transistor 311, so that the electrostatic discharge current flows from the specific node ND into the power terminal PT ₁ .

Figure 4 is another embodiment of the electrostatic discharge resistor isolation circuit of the present invention. In this embodiment, the specific node ND serves as an output node for outputting the signal of the internal circuit 110. Since the internal circuit 110 may output a negative voltage, the electrostatic discharge resistance isolation circuit 100 further includes a Schottky diode 411. In other embodiments, if the level of the signal or voltage output by the internal circuit 110 only changes between a positive level and a ground level (such as 0V), the Schottky diode 411 can be omitted .

In this embodiment, the Schottky diode 411 is connected in parallel with the Schottky diode 120. As shown in the figure, the cathode of the Schottky diode 120 is coupled to the anode of the Schottky diode 411 and the output stage 413. The anode of the Schottky diode 120 and the cathode of the Schottky diode 411 are coupled to a specific node ND. When the internal circuit 110 outputs the positive level, the Schottky diode 411 is turned on. Therefore, the level of the specific node ND is the positive level. However, when the internal circuit 110 outputs a negative voltage, the Schottky diode 120 is turned on. Therefore, the level of the specific node ND is a negative level.

The invention does not limit the structure of the internal circuit 110. Any circuit that can output a signal or voltage can be used as the internal circuit 110. In this embodiment, the internal circuit 110 includes an output stage 413. The output stage 413 in accordance with the operating voltage VDD or VSS outputs a control signal S _C. For example, when the control signal S _C to a first level (e.g., high level), the output stage 413 outputs the operation voltage VSS. In a possible embodiment, the operating voltage VSS is a negative voltage or a ground voltage. When the control signal S _C is a quasi second (e.g., low), the output stage 413 outputs the operation voltage VDD. In a possible embodiment, the operating voltage VDD is a positive voltage.

In this embodiment, the output stage 413 includes a P-type transistor 414 and an N-type transistor 415. The source of the P-type transistor 414 is coupled to the power terminal PT ₂ . The gate of the P-type transistor 414 is coupled to the gate of the N-type transistor 415 and receives the control signal S _C. The drain of the N-type transistor 415 is coupled to the drain of the P-type transistor 414. The source of the N-type transistor 415 is coupled to the power terminal PT ₁ .

When an electrostatic discharge event does not occur, the electrostatic discharge isolation circuit 100 operates in a normal mode. In the normal mode, when the power source terminal PT ₁ and PT ₂ receives the operation voltage VSS and the VDD, the output stage 413 in accordance with a control signal S _C output operation voltage VSS or VDD. For example, when the control signal S _C is turned on a P-type transistor 414, 414 an electrical output P-type crystal operating voltage VDD. Therefore, the voltage of the specific node ND is approximately equal to the operating voltage VDD. However, when the control signal S _C is turned on N-type transistor 415, N-type electric crystal 415 outputs the operation voltage VSS. Therefore, the voltage of the specific node ND is approximately equal to the operating voltage VSS.

When an electrostatic discharge event occurs at the specific node ND and the power terminal PT _{1 is} coupled to the ground, the electrostatic discharge release element 130 is turned on to discharge the electrostatic discharge current from the specific node ND to the power terminal PT ₁ . In this embodiment, the electrostatic discharge release element 130 includes an N-type transistor 412. Since the characteristics of the N-type transistor 412 are similar to those of the N-type transistor 311 in FIG. 3, details are not repeated here.

Figure 5 is another embodiment of the operating circuit of the present invention. In this embodiment, the specific node ND is used as an input node to provide a signal or voltage to the internal circuit 110. Since the level of the signal or voltage received by the specific node ND may be positive or negative, in this embodiment, the electrostatic discharge resistance isolation circuit 100 further includes a Schottky diode 511.

The Schottky diode 511 is connected in parallel with the Schottky diode 120. As shown in the figure, the cathode of the Schottky diode 120 and the anode of the Schottky diode 511 are coupled to the input stage 513, and the anode of the Schottky diode 120 and the cathode of the Schottky diode 511 are coupled to the input stage 513. Coupled to a specific node ND. When the specific node ND receives a positive signal or voltage, the Schottky diode 120 is turned on to transmit the signal or voltage of the specific node ND to the internal circuit 110. However, when the specific node ND receives a negative signal or voltage, the Schottky diode 511 is turned on to transmit the negative signal or voltage to the internal circuit 110.

The invention does not limit the structure of the internal circuit 110. Any circuit that can receive external signals or voltages can be used as the internal circuit 110. In this embodiment, the internal circuit 110 includes an input stage 513. The input stage 513 operates according to the voltage of the specific node ND. For example, when the level of the signal or voltage of the specific node ND is equal to a first level (such as a positive level), the input stage 513 outputs the operating voltage VSS. When the level of the signal or voltage of the specific node ND is equal to a second level (such as a negative level), the input stage 513 outputs the operating voltage VDD. In other embodiments, when the signal or voltage level of the specific node ND is equal to a ground level (such as 0V), the input stage 513 also outputs the operating voltage VDD. In some embodiments, when the signal or voltage of the specific node ND is changed between a positive level and a ground level, the jotteki diode 511 can be omitted.

In this embodiment, the input stage 513 includes a P-type transistor 514 and an N-type transistor 515. The source of the P-type transistor 514 is coupled to the power terminal PT ₂ . The gate of the P-type transistor 514 is coupled to the gate of the N-type transistor 515 and the cathode of the Schottky diode 120. The drain of the N-type transistor 515 is coupled to the drain of the P-type transistor 514. The source of the N-type transistor 515 is coupled to the power terminal PT ₁ . In other embodiments, the drain of the N-type transistor 515 is not coupled to the drain of the P-type transistor 514. In this example, the drain of the N-type transistor 515 is used to output the operating voltage VSS, and the drain of the P-type transistor 514 is used to output the operating voltage VDD.

When an electrostatic discharge event occurs at the specific node ND and the power terminal PT _{1 is} coupled to the ground, the electrostatic discharge release element 130 is turned on to discharge the electrostatic discharge current from the specific node ND to the power terminal PT ₁ . In this embodiment, the electrostatic discharge release element 130 includes an N-type transistor 512. Since the characteristics of the N-type transistor 512 are similar to those of the N-type transistor 311 in FIG. 3, details are not described herein again.

Unless otherwise defined, all vocabulary (including technical and scientific vocabulary) herein belong to the general understanding of persons with ordinary knowledge in the technical field of the present invention. In addition, unless clearly stated, the definition of a word in a general dictionary should be interpreted as consistent with the meaning in the article in its related technical field, and should not be interpreted as an ideal state or an overly formal voice.

Although the present invention has been disclosed as above in preferred embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the relevant technical field can make some changes and modifications without departing from the spirit and scope of the present invention. . For example, the system, device, or method of the embodiment of the present invention can be implemented in a physical embodiment of hardware, software, or a combination of hardware and software. Therefore, the protection scope of the present invention shall be subject to those defined by the attached patent application scope.

100: Electrostatic discharge resistance isolation circuit

110: Internal circuit

120,411,511: Schottky diode

130: Electrostatic discharge discharge element

PT ₁ , PT ₂ : power supply

ND: specific node

VPP ₁ ,VPP ₂ : Voltage

VDD, VSS: operating voltage

211: Access Circuit

212: Memory Array

313,414,514: P-type transistor

312: Dual carrier transistor

413: output stage

513: input stage

311,314,315,412,415,512,515: N-type transistor

Figure 1 is a schematic diagram of the structure of the electrostatic discharge resistance isolation circuit of the present invention. Figure 2 is a possible embodiment of the electrostatic discharge resistor isolation circuit of the present invention. Figure 3 is another embodiment of the electrostatic discharge resistance isolation circuit of the present invention. Figure 4 is another embodiment of the electrostatic discharge resistor isolation circuit of the present invention. Figure 5 is another embodiment of the electrostatic discharge resistor isolation circuit of the present invention.

100: Electrostatic discharge resistance isolation circuit

110: Internal circuit

120: Schottky diode

130: Electrostatic discharge discharge element

PT ₁ : Power terminal

ND: specific node

Claims (10)

An electrostatic discharge resistance isolation circuit, comprising: an internal circuit; a first Schottky diode coupled between a specific node and the internal circuit; and an electrostatic discharge element coupled between the specific node and a Between the first power terminal; wherein when an electrostatic discharge event occurs at the specific node, the electrostatic discharge release element is turned on to release an electrostatic discharge current from the specific node to the first power terminal, wherein when the static electricity When the discharge event does not occur and the specific node receives an external signal or an external voltage, the first Schottky diode transmits the external signal or the external voltage to the internal circuit. The electrostatic discharge resistor isolation circuit of claim 1, wherein the internal circuit is a one-time programmable memory, and when the one-time programmable memory performs a write operation, the voltage of the specific node is equal to a first A voltage. When the one-time programmable memory performs a read operation, the voltage of the specific node is equal to a second voltage, and the first voltage is greater than the second voltage. The electrostatic discharge resistance isolation circuit according to claim 1, wherein when the electrostatic discharge event does not occur, the voltage of the specific node and the voltage of the first power terminal are used as the operating voltage of the internal circuit. The electrostatic discharge resistance isolation circuit of claim 1, wherein the internal circuit is further coupled to a second power terminal, and when the electrostatic discharge event does not occur, the voltage of the second power terminal is equal to a first operating voltage, and the first The voltage of the power terminal is equal to a second operating voltage, and the internal circuit operates according to the first and second operating voltages. The electrostatic discharge resistance isolation circuit described in claim 4, wherein the internal The circuit includes an output stage that provides the first or second operating voltage to the specific node. The electrostatic discharge resistance isolation circuit according to claim 5, further comprising: a second Schottky diode connected in parallel with the first Schottky diode; wherein the cathode of the first Schottky diode and the The anode of the second Schottky diode is coupled to the output stage, and the anode of the first Schottky diode and the cathode of the second Schottky diode are coupled to the specific node. The electrostatic discharge resistance isolation circuit according to claim 4, wherein the internal circuit includes an input stage, and the first Schottky diode transmits the signal of the specific node to the input stage. The electrostatic discharge resistance isolation circuit according to claim 7, further comprising: a second Schottky diode connected in parallel with the first Schottky diode; wherein the cathode of the first Schottky diode and the The anode of the second Schottky diode is coupled to the input stage, and the anode of the first Schottky diode and the cathode of the second Schottky diode are coupled to the specific node. The electrostatic discharge resistance isolation circuit according to claim 1, wherein when the electrostatic discharge event triggers the electrostatic discharge discharge element, the first Schottky diode is not conductive. The electrostatic discharge resistance isolation circuit according to claim 1, wherein the electrostatic discharge release element is an N-type transistor, the N-type transistor having a first end, a second end and a control end, the first end Coupled to the specific node, the second terminal and the control terminal are coupled to the first power terminal.

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