TWI714865B - Wafer structure - Google Patents

Abstract

The present invention provides a wafer structure, which includes a plurality of dies, a plurality of dicing channels, and a plurality of process patterns, the dicing channel is adjacent to the first side and the second side of the die, and the process patterns are concentrated in the dicing channel adjacent to the first side , Or concentrated in the die, or concentrated in the cutting lane of the adjacent first side and the adjacent second side of the cutting lane. Therefore, the width of the cutting lane without the process pattern can be increased after the width of the cutting lane is reduced. The number of dies that can be produced on a wafer.

Description

Wafer structure

The present invention relates to a wafer structure, in particular to a wafer structure in which the process patterns are concentrated on a part of the dicing lane or the crystal grains.

With the development of electronic products and technological evolution, integrated circuit (IC) design companies and foundries want to increase the number of dies that can be produced on a wafer, and one of the common methods is Reduce the width of the scriber line, but during the manufacturing process of the die, it is often necessary to rely on the process pattern on the scriber line to check its correctness. However, the capacity of the manufacturing equipment has its limits, and the process pattern cannot be reduced beyond the capacity of the manufacturing equipment , Resulting in the limitation of the reduction of the cutting path. Based on the above problems, the State Intellectual Property Office of the People’s Republic of China applied for publication number "CN103176350A" and authorized announcement number "CN101533229B", and Japan Patent Office patent application publication number "JP 2005-283609", etc., all proposed related technologies. The effect is not obvious.

Furthermore, after the wafer is cut to divide the die, if the dicing lane has a process pattern but not completely cut, there will be a phenomenon of residual process pattern on the edge of the die, and the residual process pattern may cause the die There is a short circuit between the input/output channels, or a short circuit problem occurs when the die is assembled with other accessories (for example: flexible circuit board, FPC). In addition, the general process pattern is designed to be located in the cutting channel around the die. Therefore, the problem of the process pattern must be considered during the cutting process, which affects the selection of cutting process parameters and makes the cutting process complicated.

Therefore, the present invention provides a wafer structure that reduces the width of the dicing path, and even reaches the limit width of the dicing process, so as to increase the number of dies that can be produced on a wafer, and further simplify the dicing process and improve the residual of the process pattern. The short-circuit phenomenon.

The object of the present invention is to provide a wafer structure whose process pattern is concentrated on the dicing lane on one side of the adjacent die, thereby simplifying the cutting process and reducing the width of the dicing lane adjacent to the other side of the die to increase The number of dies that can be produced on a wafer.

The object of the present invention is to provide a wafer structure in which the process patterns are concentrated on the dicing lanes on the first side of adjacent dies and part of the dicing lanes on the second side of the adjacent dies, while reducing the size of the dicing lines that do not have the process pattern The width of the cutting channel to increase the number of dies that a wafer can produce.

The object of the present invention is to provide a wafer structure whose process pattern is different from the different sides of the die adjacent to the input/output portion of the die, so as to prevent the process pattern remaining in the dicing channel from affecting the die after the wafer is cut. The input/output section can avoid short circuits.

The purpose of the present invention is to provide a wafer structure in which the process pattern is concentrated on the die, which simplifies the cutting process and reduces the width of the dicing path, so as to increase the number of die produced by a wafer and avoid the process pattern remaining In the cutting channel, the short-circuit phenomenon caused by the residual process pattern is improved.

The present invention discloses a wafer structure, which includes a plurality of dies, a plurality of dicing channels, and a plurality of process patterns. The dies have a plurality of first sides and a plurality of second sides; the dicing channels are adjacent to the ones of the dies. The first side and the second sides, and the widths of the cutting lanes adjacent to the second sides are smaller than the widths of the cutting lanes adjacent to the first sides; the process patterns are located adjacent to the The cutting lanes on the first side.

The present invention discloses a wafer structure, which includes a plurality of dies, a plurality of dicing channels, and a plurality of process patterns. The dies have a plurality of first sides and a plurality of second sides; the dicing channels are adjacent to the ones of the dies. The first side and the second sides; the process patterns are located at 5% of the cutting paths adjacent to the second sides and the cutting paths adjacent to the first sides; where none The width of the cutting lanes adjacent to the second sides of the process patterns is smaller than the width of the cutting lanes with the process patterns.

The present invention discloses a wafer structure, which includes a plurality of dies, a plurality of dicing channels, and a plurality of process patterns. The dies have a plurality of first sides and a plurality of second sides; the dicing channels are adjacent to the ones of the dies. The first side and the second sides; the process patterns are located in the dies.

In the specification and subsequent patent applications, certain words are used to refer to specific elements. However, those with ordinary knowledge in the technical field of the present invention should understand that manufacturers may use different terms to refer to the same element, and, The scope of this specification and subsequent patent applications does not use differences in names as a way of distinguishing elements, but uses differences in the overall technology of elements as a criterion for distinguishing. The "include" mentioned in the entire specification and subsequent patent applications is an open term, so it should be interpreted as "include but not limited to".

In order to enable your reviewer to have a better understanding and understanding of the features of the present invention and the effects achieved, I would like to illustrate with examples. The description is as follows:

Please refer to the first figure, which is a schematic diagram of an embodiment of the wafer structure of the present invention. As shown in the figure, a wafer structure 10 includes a plurality of dies 20 and a plurality of dicing lanes 30 and 32, wherein the dicing lane 30 is a transverse (or first direction) X dicing lane, and the dicing lane 32 is a longitudinal (or first) (Two directions) Y cutting lanes. According to the drawing, the cutting lanes 30 in the first direction X are adjacent to the upper and lower sides of the die 20, and the cutting lanes 32 in the second direction Y are adjacent to the The left and right sides of the die 20, so the cutting lanes 30 and 32 surround the periphery of the die. Furthermore, the dies 20 of the wafer structure 10 in the embodiment of the first figure are rectangular. The embodiments of the present invention will be described below in conjunction with a region 12 of the wafer structure 10.

Please refer to the second figure, which is an enlarged view of the area 12 of the wafer structure 10 shown in the first figure. As shown in the figure, the die 20 has a first side 21, a second side 22, a third side 23, and a fourth side 24, wherein the first side 21 and the third side 23 are short of the die 20 The second side 22 and the fourth side 24 are the long sides of the die 20. The die 20 may include a plurality of input/output parts (or referred to as input/output channels) 25, and the input/output parts 25 are arranged along the second side 22 or the fourth side 24 of the die 20, and the first In the embodiment shown in FIG. 2, the input/output parts 25 are arranged along the second side 22 and the fourth side 24 of the die 20. Therefore, the input/output parts 25 may be located on the two long sides of the die 20.

Referring to the second figure again, the process pattern 40 is concentrated in the cutting lanes 32 of the first side 21 of the adjacent die 20. In the embodiment of the second figure, the process pattern 40 may not be located at the second edge of the adjacent die 20. In the cutting lanes 30 of the side 22 and the fourth side 24, in other words, the process patterns 40 can all be located in the cutting lanes 32 adjacent to the first side (short side) 21. Therefore, the input/output parts 25 and The process patterns 40 are adjacent to different sides of the die 20. In this way, after the cutting process, even if the process pattern 40 is not completely cut and remains, it will not affect the electrical connection state of the input/output parts 25, such as the process The residue of the pattern 40 is located in the cutting lane 32 adjacent to the first side (short side) 21, because the cutting lane 30 adjacent to the second side (long side) 22 and the fourth side (long side) 24 does not have a manufacturing process The residue of the pattern 40 will not cause a short circuit between the input/output parts 25, and will not affect the electrical properties of the die 20 and other accessories (for example, the wires of the test device or the flexible circuit board (FPC)) assembly Connection Status. The above-mentioned process pattern includes an alignment pattern, a width measurement pattern, a thickness measurement pattern, or an electrical test element.

Furthermore, the width of the cutting lane 32 in the second direction Y in the embodiment of the second figure is the first width W1, and the width of the cutting lane 30 in the first direction X is the second width W2, and as shown in the figure, due to the There is no need to provide the process pattern 40 in the cutting lane 30 in one direction X, so the second width W2 can be smaller than the first width W1. In other words, the width of the cutting lane 30 on the second side 22 of the adjacent die 20 is smaller than that of the adjacent die The width of the cutting lane 32 of the first side 21 of 20. In addition, if the process pattern 40 located in the cutting lane 32 in the second direction Y has a maximum width W3, since there is no need to provide the process pattern 40 in the cutting lane 30 in the first direction X, the second width W2 of the cutting lane 30 can be smaller than The maximum width W3, therefore, the width of the cutting lane 30 adjacent to the second side 22 without the process pattern 40 may be smaller than the width of the process pattern 40. Furthermore, in order to simplify the cutting process without changing the tool multiple times during the cutting process, the width of the cutting lane 30 of the second side 22 and the fourth side 24 of the adjacent die 20 can be the same as the second width W2, and adjacent The widths of the cutting lanes 32 of the first sides 21 and the third sides 23 may be the same width W3. However, the second figure shows only an implementation structure, so the width of the cutting lane 30 adjacent to the second side 22 and the fourth side 24 can be different. As can be seen from the above description, since the process pattern 40 is concentrated on the cutting lanes 32 on the first side 21 of the adjacent die 20, the width of the cutting lanes 30 on the adjacent second side 22 can be reduced. The space occupied by the dicing lanes 30 on the wafer is reduced, so the saved space can be used to form additional dies 20, thereby increasing the number of dies 20 that can be produced from one wafer.

Please refer to the third figure, which is an enlarged schematic view of a second embodiment of the wafer structure of the present invention. The third figure is an enlarged view of the region 12 of the wafer structure 10 shown in the first figure. As shown in the figure, the difference between the embodiment in the third figure and the embodiment in the second figure is that the widths of the cutting lanes 30, 34, and 36 in the first direction X in the third diagram can be different widths. The width is the narrower second width W2. In addition, the width of the cutting lanes 34 and 36 can be changed to the wider first width W1 of the cutting lane 32 in the second direction Y for setting the process patterns 42, 43.

Furthermore, the number of cutting lanes 34 and 36 in the first direction X with the first width W1 may account for less than 5% of the total number of cutting lanes in the first direction X, and preferably 2%. In other words, if the first There are 100 cutting lanes in the direction X. The second embodiment of the present invention allows at most 5 cutting lanes to be provided with process patterns 42, 43, and preferably allows only 2 or less cutting lanes to be provided with process patterns. Therefore, in addition to the process patterns 41 concentrated on the cutting lane 32 adjacent to the first side 21, there are also some process patterns 42, 43 located below 5% (or preferably less than 2%) of the cutting lane on the adjacent second side 22 Cutting lanes 34, 36, so that the width W2 of the cutting lane 30 without the adjacent second side 22 of the process patterns 41, 42, 43 is smaller than the width of the cutting lanes 32, 34, 36 with the process patterns 41, 42, 43 W1. In addition, the width of the process patterns 41, 42, 43 is the maximum width W3, and the second width W2 may be smaller than the maximum width W3.

In the first and second embodiments of the wafer structure of the present invention, the process patterns required by the wafer are centrally arranged in the cutting lane 32 on the short side of the adjacent die 20, so that the long side of the adjacent die 20 is cut No process pattern is required for all or at least 95% (or preferably 98%) of the channel, so the width of the cutting channel on the long side of the adjacent die 20 can be effectively reduced to reduce the cutting of the long side of the adjacent die 20 The track occupies the space of the wafer, and the saved space can be used to form additional dies 20, thereby increasing the number of dies 20 that can be produced from one wafer. The first and second embodiments are particularly effective when applied to a rectangular die 20 with a large difference between the long and short sides. For example, if the second side (long side) 22 and the first side (short side) of the die 20 are When the ratio of 21 differs by more than 5 times (preferably more than 10 times) (for example, the drive IC of the display panel or the touch control IC generally meets this length and width condition), the first and second embodiments of the present invention are used to change the process pattern Centrally arranged in the dicing lane on the short side of the adjacent die 20, the effect of saving the wafer area occupied by the dicing lane is particularly good. Refer to the fourth figure, which is an enlarged schematic view of a third embodiment of the wafer structure of the present invention. The fourth figure is an enlarged view of the region 12 of the wafer structure 10 shown in the first figure. As shown in the figure, the difference between the embodiment in the fourth figure and the embodiments in the second and third figures is that the process patterns 44 are all located in the die 20 and are not placed in any dicing lanes 30, 38. Therefore, the second direction The width of the Y cutting lane 38 and the width of the cutting lane 30 in the first direction X can be the same as the narrower second width W2, and all the cutting lanes 30 in the first direction X and all the cutting lanes 38 in the second direction Y can be As shown in the fourth figure, the width is the same, so that the cutting process does not need to be changed and the cutting process is further simplified. In this way, the second width W2 of the cutting lanes 30 and 38 can be smaller than a fourth width W4 of the process pattern 44. Since the process pattern 44 is concentrated in the die 20, the width of the dicing lanes 30, 38 can be reduced, and the space occupied by the dicing lanes 30, 38 can be reduced, thereby increasing the production capacity of a wafer The number of die 20 is shown. Furthermore, because there is no process pattern 44 in all the cutting lanes 30 and 38, there is no need to consider the problems of the process pattern 44 in the cutting process, and simplify the selection of cutting process parameters, and simplify the cutting procedure and reduce the width of the cutting lane. Reach the minimum limit width of the cutting process. The minimum limit width of the cutting process may vary according to the capabilities of the manufacturing equipment, which is not limited by the technology of the present invention.

Referring again to the fourth figure, in addition to the process pattern 44 inside the die 20, it also contains a number of electronic components 50. The process pattern 44 is located in a useless area in the die 20 that has no electronic components 50 or other circuits originally designed, so the process pattern 44 can be A useless area located at any position in the die 20, and the electronic component 50 is located in the electronic component area of the die 20 where various components are to be designed, so the electronic component 50 is located outside the useless area. Furthermore, the die 20 may further include the input/output part 25. However, the shape of the pattern of the electronic component 50 formed in the die 20, the formation position of the input/output part 25, and the formation position of the process pattern 44 are not fourth. Limited by the embodiment of the figure. The aforementioned unused area can be an unused area of a specific layer of the wafer (for example, an unused area in a polysilicon layer or a metal layer), which is used to place single-layer process patterns such as alignment patterns, width measurement patterns, or thickness measurement patterns. Or, when designing the circuit of the die 20, a specific area of the die 20 can be reserved as a useless area in advance. This useless area can span the multi-layer structure of the wafer, so it can be used to place multi-layer electrical test components and other process patterns . In addition, according to the above description, according to the requirements of the process, in addition to the process pattern 44 can be concentrated in the die 20, part of the process pattern 44 can also be distributed in part of the cutting lanes 30 or 38, which can still reduce the occupation of the cutting lanes 30, 38. Space for wafers.

In summary, the present invention discloses a wafer structure including a plurality of dies, a plurality of dicing channels, and a plurality of process patterns. The dies have a plurality of first sides and a plurality of second sides; the dicing channels are adjacent to the dies The first sides and the second sides of, and the width of the cutting lanes adjacent to the second sides is smaller than the width of the cutting lanes adjacent to the first sides; the process patterns are located at the same The cutting lanes adjacent to the first sides.

The present invention discloses a wafer structure, which includes a plurality of dies, a plurality of dicing channels, and a plurality of process patterns. The dies have a plurality of first sides and a plurality of second sides; the dicing channels are adjacent to the ones of the dies. The first side and the second sides; the process patterns are located at 5% of the cutting paths adjacent to the second sides and the cutting paths adjacent to the first sides; where none The width of the cutting lanes adjacent to the second sides of the process patterns is smaller than the width of the cutting lanes with the process patterns.

The present invention discloses a wafer structure, which includes a plurality of dies, a plurality of dicing channels, and a plurality of process patterns. The dies have a plurality of first sides and a plurality of second sides; the dicing channels are adjacent to the ones of the dies. The first side and the second sides; the process patterns are located in the dies.

10‧‧‧Wafer structure 12‧‧‧Region 20‧‧‧Die 21‧‧‧First side 22‧‧‧Second side 23‧‧‧Third side 24‧‧‧Fourth side 25‧‧‧ Input/output section 30‧‧‧cutting road 32‧‧‧cutting road 34‧‧‧cutting road 36‧‧‧cutting road 38‧‧‧cutting road 40‧‧‧process pattern 41‧‧‧process pattern 42‧‧‧ Process pattern 43‧‧‧Process pattern 44‧‧‧Process pattern 50‧‧Electronic component W1‧‧‧First width W2‧‧‧Second width W3‧‧‧Maximum width W4‧‧‧Fourth width X‧‧ ‧First direction Y‧‧‧Second direction

Figure 1: It is a schematic diagram of an embodiment of the wafer structure of the present invention; Figure 2: It is an enlarged schematic view of the first embodiment of a wafer structure of the present invention; Figure 3: It is a schematic view of the first embodiment of the wafer structure of the present invention An enlarged schematic view of a second embodiment of a wafer structure; and the fourth figure: it is an enlarged schematic view of a third embodiment of a wafer structure of the present invention.

12‧‧‧Region

20‧‧‧grain

21‧‧‧First side

22‧‧‧Second side

23‧‧‧The third side

24‧‧‧The fourth side

25‧‧‧Input/Output

30‧‧‧Cut Road

32‧‧‧Cut Road

40‧‧‧Process drawing

W1‧‧‧First width

W2‧‧‧Second width

W3‧‧‧Maximum width

X‧‧‧First direction

Y‧‧‧Second direction

Claims (18)

A wafer structure comprising: a plurality of dies having a plurality of first sides and a plurality of second sides; a plurality of dicing channels, adjacent to the first sides and the second sides of the dies, adjacent to the The width of the cutting lanes on the second side is smaller than the width of the cutting lanes adjacent to the first sides; and the plurality of manufacturing process patterns are located at less than 5% of the cutting lanes among the cutting lanes adjacent to the second side And the cutting lanes adjacent to the first sides. In the wafer structure described in claim 1, wherein the first sides are the short sides of the dies, and the second sides are the long sides of the dies. As for the wafer structure described in claim 1, wherein all the process patterns are located in the scribe lanes adjacent to the first sides. For the wafer structure described in claim 1, wherein the dies have a plurality of input/output parts, the input/output parts are arranged along the second sides, and the input/output parts are connected to the The process patterns are adjacent to different sides of the die. In the wafer structure described in claim 1, wherein the width of the scribe lanes adjacent to the second sides is smaller than the maximum width of the process patterns. As for the wafer structure described in claim 1, wherein the widths of the scribe lanes adjacent to the second sides are the same width. In the wafer structure described in item 6 of the scope of patent application, the widths of the scribe lanes adjacent to the first sides are the same width. A wafer structure comprising: a plurality of crystal grains having a plurality of first sides and a plurality of second sides; A plurality of cutting lanes, adjacent to the first sides and the second sides of the dies; and a plurality of manufacturing process patterns, located in the cutting lanes of less than 5% of the cutting lanes adjacent to the second sides and adjacent The cutting lanes of the first sides; wherein the width of the cutting lanes adjacent to the second sides without the process patterns is smaller than the width of the cutting lanes with the process patterns. As for the wafer structure described in claim 8, wherein the first sides are the short sides of the dies, and the second sides are the long sides of the dies. In the wafer structure described in item 8 of the scope of patent application, the dies have a plurality of input/output parts, and the input/output parts are arranged along the second sides. In the wafer structure described in item 8 of the scope of patent application, the width of the scribe lanes adjacent to the second sides without the process patterns is smaller than the maximum width of the process patterns. A wafer structure comprising: a plurality of dies having a plurality of first sides and a plurality of second sides; a plurality of dicing channels, the first sides and the second sides adjacent to the dies; and a plurality of process patterns , Located in these crystal grains. For the wafer structure described in item 12 of the scope of patent application, the dies respectively include a plurality of electronic components, and the process patterns are located in a useless area of the dies where the electronic components are not provided. For the wafer structure described in item 13 of the scope of patent application, the useless area is a useless area of one layer of the wafer structure. In the wafer structure described in claim 13, wherein the unused area is an unused area spanning the multilayer structure of the wafer structure. For the wafer structure described in claim 12, wherein the width of the scribe lanes is smaller than the maximum width of the process patterns. For the wafer structure described in item 12 of the scope of patent application, the widths of the scribe lanes adjacent to the second sides are the same width. As for the wafer structure described in claim 12, the widths of the scribe lanes adjacent to the first sides are the same width.

Images