TWI707343B - Programming method for nand flash memory - Google Patents

Abstract

A programming method for NAND flash memory includes obtaining a program saturation voltage V _wstof a NAND flash memory, applying a first program voltage V ₁to the NAND flash memory in which a practical application range of the first program voltage V ₁is V _wst± 5V, and then applying a second program voltage V ₂to the NAND flash memory in which the second program voltage V ₂is greater than the first program voltage V ₁.

Description

NAND flash memory writing method

The present invention relates to the operation of a flash memory, and particularly relates to a writing method of a NAND flash memory.

NAND flash memory has been widely used in various devices, such as the memory cards of digital cameras, the memory of MP players, the memory devices of universal serial bus (USB) and other daily home appliances or 3C products.

However, with the increase in applications, NAND flash memory currently encounters many problems that need to be resolved. For example, the reliability of memory cells often deteriorates due to the narrower read voltage margin (RV margin). For example, FIG. 1A shows the starting voltage (Vth) distribution pattern of a NAND flash memory in an ideal state during operation, where the data of 0 and 1 are determined based on the value of Vth. For the writing (programming) of NAND flash memory, a voltage is applied to it so that the voltage stored in the memory cell exceeds the voltage at voltage determination point II in Figure 1, and the memory indicates that 0 has been written; if it is If no voltage is applied or the voltage stored in the memory cell is still lower than the voltage determination point III after the voltage is applied, it means that 1 is still in the erased state. At this time, there is still a lot of space between the judgment points I and III, so the ideal read voltage tolerance 100 range is large.

However, in actual operation, NAND flash memory will encounter read disturbance (Read Disturbance), write disturbance (Program Disturbance), proximity effect interference (interference), storage electronics loss (De-trap) interference, and extreme resistance values. Effect (Drain side pattern), random telegraph noise (random telegraph noise, RTN), etc., cause the Vth distribution pattern of NAND flash memory during operation as shown in Figure 1B, where the write state (0) and erase The distribution of the state (1) becomes wider, which causes the read voltage tolerance 102 to become narrow, and reliability problems are likely to occur.

In addition, the write performance of the NAND flash memory is reduced due to the use of a smaller incremental write pulse (Incremental Step Pulse Program, ISPP). Moreover, if a larger ISPP step is used for writing to improve performance, as shown in Figure 2, when the ISPP is finally completed, a larger Vt distribution and over-programming are likely to occur.

The invention provides a writing method for NAND flash memory, which can increase writing efficiency and reliability at the same time.

The writing method of the NAND flash memory of the present invention includes first obtaining a programmed saturation voltage (V _wst ) value of the NAND flash memory, and then applying the first writing voltage V ₁ to the NAND flash memory Body, wherein the optimal application range of the first written voltage V ₁ is between V _wst ± 5V, and then the second write voltage V _{2 is} applied to the NAND flash memory, wherein the second The writing voltage V _{2 is} greater than the first writing voltage V ₁ .

In an embodiment of the present invention, if the first writing voltage V _{1 is} less than V _wst , the second writing voltage V ₂ is V _wst .

In an embodiment of the present invention, the first writing voltage V ₁ is V _wst , and the second writing voltage V ₂ is V _wst +1V.

In an embodiment of the present invention, if the first writing voltage V _{1 is} greater than V _wst , the second writing voltage V ₂ is V ₁ +1V.

In an embodiment of the present invention, the above-mentioned NAND flash memory includes a substrate, a floating gate located on the substrate, a control gate located on the floating gate, the substrate and the floating gate The gate oxide layer between the gates and the inter-gate dielectric layer between the control gate and the floating gate, and the programmed saturation voltage V _wst is adjusted by at least one of the following parameters : The material of the floating gate, the thickness of the gate oxide layer, the thickness of the dielectric layer between the gates, and the area between the control gate and the floating gate.

In an embodiment of the present invention, obtaining the programmed saturation voltage value V _wst includes: applying different voltage pulses to the NAND flash memory to obtain a starting voltage value that changes with the increase of the voltage pulse, And the voltage pulse at which the starting voltage value stops rising is used as the programmed saturation voltage value V _wst .

In an embodiment of the present invention, after the above-mentioned second writing voltage, an additional writing voltage may be applied to the NAND flash memory, and the voltage of the additional writing voltage is greater than the second writing voltage The voltage V ₂ .

Based on the above, the present invention obtains the programmed saturation voltage value of the NAND flash memory in advance, and uses this voltage value as the programming reference. Therefore, only two write voltages can be used to complete the writing to improve the efficiency of the device. , And avoid overwriting, thereby increasing the reliability of NAND flash memory.

In order to make the above-mentioned features and advantages of the present invention more comprehensible, the following specific embodiments are described in detail in conjunction with the accompanying drawings.

Hereinafter, some embodiments are listed in conjunction with the accompanying drawings for detailed description, but the embodiments provided are not intended to limit the scope of the present invention. In addition, the drawings are for illustrative purposes only and are not drawn according to the original size. To facilitate understanding, the same elements in the following description will be described with the same symbols. In addition, the terms "include", "have" and so on used in the text are all open terms; that is, include but are not limited to. Moreover, the directional terms mentioned in the text, such as "上", "下", etc., are only used to refer to the directions of the drawings. Therefore, the directional terms used are used to illustrate, but not to limit the present invention.

FIG. 3 is a flowchart of a NAND flash memory writing according to an embodiment of the invention.

Please refer to FIG. 3, step 300 is first performed to obtain a programmed saturation voltage (V _wst ) value of the NAND flash memory. In this embodiment, the method of obtaining the programmed saturation voltage V _wst is, for example, applying different voltage pulses to the above-mentioned NAND flash memory to obtain the starting voltage value that changes with the increase of the voltage pulse, and the starting voltage The voltage pulse at which the value stops rising is used as the programmed saturation voltage value V _wst . In other words, the programmed saturation voltage value V _wst is the lowest voltage value to reach the programmed saturation phenomenon, and it is usually input from a word line to the NAND flash memory.

Since the NAND flash memory is basically as shown in FIG. 4, it includes a substrate 400, a floating gate 402 on the substrate 400, a control gate 404 on the floating gate 402, a substrate 400 and a floating gate. The gate oxide layer 406 between 402 and the inter-gate dielectric layer 408 between the control gate 404 and the floating gate 406. In addition, there is usually an isolation structure 410 in the substrate 400. Once the material or size of the above structure changes, the programmed saturation voltage value V _wst will also change; in other words, the above-mentioned programmed saturation voltage value V _wst can be adjusted by changing the material or size of the above structure, for example, change the following At least one parameter: the material of the floating gate 402, the thickness of the gate oxide layer 406, the thickness of the inter-gate dielectric layer 408, and the area between the control gate 404 and the floating gate 406 (ie coupling ratio) . However, the present invention is not limited to this. Even other NAND flash memories with different structures from those shown in FIG. 4 can be written using the process of the present invention.

Next, proceed to step 302 to apply the first write voltage V ₁ to the NAND flash memory, where the first write voltage V ₁ is V _wst plus or minus 5V.

Then, proceed to step 304 to apply the second writing voltage V ₂ to the NAND flash memory, wherein the second writing voltage V _{2 is} greater than the first writing voltage V ₁ .

In one embodiment, if the first writing voltage V ₁ is less than V _wst , the second writing voltage V ₂ is V _wst . In another embodiment, if the first writing voltage V ₁ is V _wst , the second writing voltage V ₂ is V _wst +1V. In still another embodiment, if the first writing voltage V ₁ is greater than V _wst , the second writing voltage V ₂ is V ₁ +1V. From the viewpoint of high writing speed, the condition that the first writing voltage V ₁ is V _wst and the second writing voltage V ₂ is V _wst +1V can achieve the highest writing speed and avoid excessive writing The input voltage stresses the component.

FIG. 5A is a waveform diagram of a write operation according to FIG. 3. FIG. 5B is a schematic diagram corresponding to the Vth distribution pattern of FIG. 5A. In FIG. 5A, the first write voltage V ₁ is V _wst and the second write voltage V ₂ is V _wst +1V. Fig. 5B shows the initial write state without pulse application, the write state after the first write voltage V _{1 is} applied (indicated by the dotted line), and the write state after the second write voltage V _{2 is} applied (located at the bottom of the figure). right). Due to the limitation of the natural structure, the first writing voltage V ₁ can generate the programmed saturation V _wst . Therefore, the Vth distribution pattern of the writing state is not only narrowed, nor overwriting occurs. Similarly, this writing method can also be used to avoid overwriting problems caused by tail bits.

After step 304, an additional write voltage can be applied to the NAND flash memory, and the voltage of this additional write voltage can be slightly greater than the second write voltage V ₂ ; or, this additional write voltage can be omitted. Write voltage.

In summary, the present invention first obtains the programmed saturation voltage value of the individual NAND flash memory before writing, and uses this voltage value as the voltage reference for applying pulses during the writing operation. Therefore, only two write voltages can be used to complete the write, which greatly improves the efficiency of the device, and the voltage of the first gun (first write voltage) is set to a voltage value that can reach the programmed saturation to prevent excessive Writing occurs, thereby increasing the reliability of the NAND flash memory.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the technical field can make some changes and modifications without departing from the spirit and scope of the present invention. The scope of protection of the present invention shall be determined by the scope of the attached patent application.

100, 102: Read voltage tolerance 300, 302, 304: Step 400: Substrate 402: Floating gate 404: Control gate 406: Gate oxide layer 408: Inter-gate dielectric layer 410: Isolation structure I, II , III: Voltage judgment point V ₁ , V ₂ : Voltage value V _wst : Programmable saturation voltage value

FIG. 1A is a schematic diagram of the Vth distribution pattern of a NAND flash memory in operation in an ideal state. FIG. 1B is a schematic diagram of the Vth distribution pattern of a NAND flash memory under the influence of various interferences during operation. Figure 2 is a schematic diagram of a conventional Vth distribution pattern for writing with a large ISPP. FIG. 3 is a writing flow chart of a NAND flash memory according to an embodiment of the invention. 4 is a schematic cross-sectional view of a NAND flash memory according to the embodiment of the invention. FIG. 5A is a waveform diagram of a write operation according to FIG. 3. FIG. 5B is a schematic diagram corresponding to the Vth distribution pattern of FIG. 5A.

300, 302, 304: steps

Claims (6)

A method for writing NAND flash memory, wherein the NAND flash memory comprises: a substrate, a floating gate located on the substrate, a control gate located on the floating gate, The gate oxide layer between the floating gates and the inter-gate dielectric layer between the control gate and the floating gates, the writing method includes: obtaining the NAND flash memory A programmed saturation voltage value V _{wst of} V _wst , wherein the programmed saturation voltage value V _wst is adjusted by at least one of the following parameters: the material of the floating gate; the thickness of the gate oxide layer; the gate The thickness of the inter-dielectric layer; and the area sandwiched between the control gate and the floating gate; applying a first write voltage V ₁ to the NAND flash memory, wherein the first The application range of the writing voltage V ₁ is between V _wst ± 5V; the second writing voltage V _{2 is} applied to the NAND flash memory, wherein the second writing voltage V _{2 is} greater than the first writing Input voltage V ₁ ; and in the step of applying the first write voltage V ₁ to the NAND flash memory and in the step of applying the second write voltage V ₂ to the NAND flash memory Between the steps, a voltage of 0V is applied to the NAND flash memory. The writing method according to the first item of the scope of patent application, wherein the first writing voltage V ₁ is V _wst , and the second writing voltage V ₂ is V _wst +1V. The writing method according to the first item of the scope of patent application, wherein the first writing voltage V _{1 is} less than V _wst , and the second writing voltage V ₂ is V _wst . The writing method according to the first item of the scope of patent application, wherein the first writing voltage V _{1 is} greater than V _wst , and the second writing voltage V ₂ is V ₁ +1V. As for the writing method described in the first item of the scope of patent application, wherein obtaining the programmed saturation voltage value V _wst includes: applying different voltage pulses to the NAND flash memory to obtain the increase in the voltage pulse A changed starting voltage value, and the voltage pulse at which the starting voltage value stops rising is used as the programmed saturation voltage value V _wst . The application of the method of writing patentable scope of item 1, wherein further comprising, after the second write voltage V _2: the additional write a voltage is applied to the NAND flash memory, and the additional The voltage of the writing voltage of is greater than the second writing voltage V ₂ .

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