TWI897507B - Memory device and operating method for memory device - Google Patents

Abstract

A memory device and an operating method for the memory device are provided. The memory device is a three-dimensional NAND flash memory device with high-performance and high-capacity. The memory device includes a common source line, at least one bit line and at least one memory string. During an erasing operation, an erasing voltage is applied to at least one of the common source line and the at least one bit line. In a first period of the erasing operation, a voltage value of the erasing voltage is raised, and a voltage value of a word line voltage is a first voltage value. In a second period after the first period of the erasing operation, the voltage value of the erasing voltage is a target voltage value, and the voltage value of the word line voltage is raised from the first voltage value to a second voltage value.

Description

Memory device and operating method for memory device

The present disclosure relates to a memory device and an operating method for the memory device, and more particularly to a memory device and an operating method for reducing erase bias loss during an erase operation performed on at least one storage string of the memory device.

Typically, a memory device performs an erase operation on a memory string. If the memory device is a 3D NAND flash memory device, the memory device may perform a gate-induced drain leakage (GIDL)-assisted erase operation on the memory string. Multiple data stored in the memory string are erased based on the channel potential of the channel within the memory string. The channel potential is generated by an external erase voltage.

However, during a GIDL-assisted erase operation, the erase bias between the external erase voltage and the channel potential is lost due to at least one factor. This at least one factor includes at least one of a declining lateral electric field, the bitline junction, and the common source line junction. In other words, the channel potential is always lower than the external erase voltage. Therefore, the reliability of the GIDL-assisted erase operation is affected by at least one factor.

The present disclosure provides a memory device and an operating method that can reduce erase bias loss when performing an erase operation on at least one memory string of the memory device.

In one embodiment of the present disclosure, a memory device includes a common source line, at least one bit line, and at least one memory string. The at least one memory string is coupled between the common source line and the at least one bit line. During an erase operation, an erase voltage is applied to at least one of the common source line and the at least one bit line, and a word line voltage is applied to a plurality of memory cells in the at least one memory string. During a first period of the erase operation, the erase voltage is raised to a target voltage value, and the word line voltage is at a first voltage value. In a second period following the first period of the erase operation, a voltage value of the erase voltage is a target voltage value, and a voltage value of the word line voltage is raised from a first voltage value to a second voltage value.

In one embodiment of the present disclosure, an operating method is applied to operate a memory device. The memory device includes a common source line, at least one bit line, and at least one memory string. The at least one memory string is coupled between the common source line and the at least one bit line. The operating method includes: during an erase operation, applying an erase voltage to a common source line and at least one of the at least one bit line, and applying a word line voltage to a plurality of memory cells of the at least one memory string; during a first period of the erase operation, increasing the erase voltage to a target voltage, and applying the word line voltage to a first voltage; and during a second period following the first period of the erase operation, applying the erase voltage to the target voltage, and increasing the word line voltage from the first voltage to a second voltage.

Based on the above, during the first period of the erase operation, the erase voltage is raised, and the word line voltage is at a first voltage value. During the second period following the first period of the erase operation, the erase voltage is set to a target voltage value, and the word line voltage is raised from the first voltage value to a second voltage value. It should be noted that during the second period, the raised word line voltage raises the channel potential of the at least one memory string. Therefore, the channel potential can be compensated during the second period. This reduces the erase bias loss between the erase voltage and the channel potential. Therefore, the present disclosure provides a stable and enhanced GIDL-assisted erase operation.

To make the above content clearer and easier to understand, several embodiments are described in detail below with reference to the accompanying drawings.

The present disclosure can be understood by referring to the following detailed description in conjunction with the accompanying drawings, as described below. It should be noted that for the purposes of clarity and ease of understanding, the various drawings of the present disclosure depict portions of electronic devices, and some elements in the various drawings may not be drawn to scale. Furthermore, the number and size of each device depicted in the drawings are for illustrative purposes only and are not intended to limit the scope of the present disclosure.

Please refer to Figure 1, which is a schematic diagram of a memory device according to an embodiment of the present disclosure. The memory device 100 can be a 3D NAND flash memory device. In this embodiment, the memory device 100 includes a common source line CSL, bit lines BL<1>~BL<n>, and memory strings STR1~STRn. The memory strings STR1~STRn are respectively coupled between the common source line CSL and the bit lines BL<1>~BL<n>. For example, the memory string STR1 is coupled between the common source line CSL and the bit line BL<1>. The memory string STRn is coupled between the common source line CSL and the bit line BL<n>.

Taking memory string STR1 as an example, memory string STR1 includes memory cells MC1-MCm. Memory cells MC1-MCm are connected in series. String select transistors SST and ground select transistors GST are connected to memory cells MC1-MCm, respectively.

In this embodiment, during an erase operation, an erase voltage VERA is applied to the common source line CSL and at least one of the bit lines BL<1> through BL<n>. During the erase operation, a word line voltage VWL is applied to the memory cells in the memory strings STR1 through STRn. In this embodiment, the erase operation is a block erase operation. Gate-induced drain leakage (GIDL) assists the erase operation.

In this embodiment, word line voltage VWL is applied to word lines connected to memory strings STR1 to STRn. Taking memory string STR1 as an example, word line voltage VWL is applied to word lines connected to memory cells MC1 to MCm in memory string STR1.

In this embodiment, during an erase operation, an erase voltage VERA is applied to the common source line CSL and the bit lines BL<1> to BL<n>, but the present disclosure is not limited thereto. In some embodiments, during an erase operation, the erase voltage VERA is applied to the common source line CSL. In some embodiments, during an erase operation, the erase voltage VERA is applied to the bit lines BL<1> to BL<n>.

Please refer to Figures 1, 2, and 3. Figure 2 is a waveform diagram according to an embodiment of the present disclosure. Figure 3 is a waveform diagram of an erase voltage, a channel potential, and a word line voltage according to an embodiment of the present disclosure. In this embodiment, during the first period T1 of the erase operation, the voltage value of the erase voltage VERA is increased to a target voltage value VT. During the first period T1 of the erase operation, the voltage value of the word line voltage VWL is a first voltage value V1. For example, during the first period T1 of the erase operation, the voltage value of the erase voltage VERA is gradually increased from an initial voltage value Vini to a target voltage value VT. At the start of the first period T1, the word line voltage VWL decreases from the initial voltage Vini to the first voltage V1, but the present disclosure is not limited thereto. When the erase voltage VERA reaches the target voltage VT, the first period T1 ends and the second period T2 begins.

In a second period T2 following the first period T1 of the erase operation, the voltage value of the erase voltage VERA is the target voltage value VT, and the voltage value of the word line voltage VWL is increased from the first voltage value V1 to the second voltage value V2.

During an erase operation, a channel potential VEB is generated in the channel structure of each memory string STR1-STRn. For example, each channel structure can be a channel pillar in a circuit under array (CUA) structure, but the present disclosure is not limited thereto. During a first period T1, the channel potential VEB in each channel structure increases substantially as the erase voltage VERA increases. After the erase voltage VERA reaches a target voltage VT, an erase bias loss LS is generated between the erase voltage VERA and the channel potential VEB. The erase bias loss LS is generated based on at least one of a decreasing lateral electric field, a bit line junction, and a common source line junction.

In this embodiment, the voltage difference Vch between the target voltage value VT and the first voltage value V1 can be determined based on the different designs or processes of the memory strings STR1 to STRn. The erase bias loss LS is changed based on the design or process. For example, in order to reduce the erase bias loss LS, the voltage difference Vch is in the range of 20 volts to 26 volts. The voltage difference of the first voltage value V1 minus the second voltage value V2 is designed to be in the range of 0 volts to -6 volts. The initial voltage value Vini and the second voltage value V2 are 0 volts. The target voltage value VT is 20 volts. The first voltage value V1 is in the range of 0 volts to -6 volts. More specifically, the voltage difference between the first voltage value V1 and the second voltage value V2 is designed to be within a range of -3 volts to -4 volts. Therefore, the first voltage value V1 is within a range of -3 volts to -4 volts. For example, if the memory string STR1 includes 200 memory cells (i.e., "m" = 200), the first voltage value V1 is -3 volts. For example, if the memory string STR1 includes 800 memory cells (i.e., "m" = 800), the first voltage value V1 is -4 volts.

It should be noted that during the second period T2, the word line voltage VWL is increased from the first voltage value V1 to the second voltage value V2. Due to the capacitive coupling effect, the word line voltage VWL can raise the channel potential VEB. Therefore, the channel potential VEB can be compensated during the second period T2. This reduces the erase bias loss LS between the erase voltage VERA and the channel potential VEB. Consequently, the memory device 100 provides a stable and enhanced GIDL-assisted erase operation.

In this embodiment, during the second period T2, the channel potential VEB is raised to be substantially equal to the target voltage value VT. Therefore, the erase bias loss LS is substantially equal to 0V.

In this embodiment, during the second period T2, the channel potential VEB continues to rise slowly. Therefore, when entering the second period T2 of the erase operation, the voltage value of the erase voltage VERA is the target voltage value VT. The voltage value of the word line voltage VWL is increased from the first voltage value V1 to the second voltage value V2 after the delay time td. Therefore, the rising voltage value of the word line voltage VWL (i.e., "V2-V1") can be reduced. If the delay time td is increased, the rising voltage value can be reduced. However, the operation time of the erase operation will be longer. Therefore, the delay time td is a trade-off parameter for the erase operation. In this embodiment, the delay time length td is greater than 0 seconds and less than 400 microseconds.

In this embodiment, taking memory string STR1 as an example, memory string STR1 further includes a string select transistor SST and a ground select transistor GST. String select transistor SST is coupled between the memory cell on the first side of memory string STR1 (i.e., memory cell MC1) and bit line BL<1>. Ground select transistor GST is coupled between the memory cell on the second side of memory string STR1 (i.e., memory cell MCm) and the common source line CSL. In this embodiment, string select transistor SST and ground select transistor GST are controlled to participate in the erase operation.

In this embodiment, during an erase operation, a first select signal SS1 is applied to the string select transistor SST. A second select signal SS2 is applied to the ground select transistor GST. In this embodiment, the first select signal SS1 is applied to the gate electrode of the string select transistor SST. The second select signal SS2 is applied to the gate electrode of the ground select transistor GST.

During the first period T1 of the erase operation, before a first time point tp1, the voltage value of the first select signal SS1 is equal to the initial voltage value Vini. The first select signal SS1 begins to float at the first time point tp1. The voltage value of the first select signal SS1 begins to rise at the first time point tp1 as the voltage value of the erase voltage VERA increases. Therefore, after the first time point tp1, the voltage difference Vch1 between the voltage values of the erase voltage VERA and the first select signal SS1 remains constant.

During the first period T1 of the erase operation, before the second time point tp2, the voltage value of the second select signal SS2 is equal to the initial voltage value Vini. The voltage value of the second select signal SS2 begins to float at the second time point tp2. At the second time point tp2, the voltage value of the second select signal SS2 begins to rise as the voltage value of the erase voltage VERA rises. Therefore, after the second time point tp2, the voltage difference Vch2 between the voltage values of the erase voltage VERA and the second select signal SS2 remains constant.

It should be noted that to prevent the electronic characteristics of the string select transistor SST and the ground select transistor GST from being disturbed by the erase voltage VERA during the erase operation, the voltage differences Vch1 and Vch2 need to be limited to below a critical interference voltage. The electronic characteristics of the string select transistor SST can be the critical voltage value of the string select transistor SST. The electronic characteristics of the ground select transistor GST can be the critical voltage value of the ground select transistor GST. In addition, the voltage difference Vch1 is related to the voltage withstand capability of the string select transistor SST. The voltage difference Vch2 is related to the voltage withstand capability of the ground select transistor GST. For example, if the voltage withstand capability of the ground select transistor GST is higher than that of the string select transistor SST, the second time point tp2 will be later than the first time point tp1. Therefore, during the second period T2 of the erase operation, the voltage value of the first select signal SS1 is higher than the voltage value of the second select signal SS2. For example, during the second period T2, the target voltage value VT is 20 volts. The voltage value of the first select signal SS1 is 13 volts. The voltage value of the second select signal SS2 is 10 volts. Therefore, the voltage difference Vch1 is 7 volts. The voltage difference Vch2 is 10 volts.

In some embodiments, during an erase operation, the erase voltage VERA is applied only to the bit lines BL<1> to BL<n>. Therefore, the first select signal SS1 is applied based on the waveform in FIG2. The second select signal SS2 is equal to the erase voltage VERA.

In some embodiments, during the erase operation, the erase voltage VERA is applied only to the common source line CSL. Therefore, the second select signal SS2 is applied based on the waveform in Figure 2. The first select signal SS1 is equal to the erase voltage VERA.

In this embodiment, the common source line CSL extends along direction Y. The bit lines BL<1> through BL<n> extend along direction X and are arranged along direction Y. Each memory string STR1 through STRn extends along direction Z. Taking memory string STR1 as an example, the memory cells MC1 through MCm of memory string STR1 are arranged along direction Z. Directions X, Y, and Z are different from each other.

In this embodiment, the memory device 100 further includes a control circuit 110. The control circuit 110 provides an erase voltage VERA, a word line voltage VWL, a first select signal SS1, and a second select signal SS2 during an erase operation.

Please refer to Figures 1, 4, and 5. Figure 4 is a waveform diagram according to an embodiment of the present disclosure. Figure 5 is a waveform diagram of the erase voltage, channel potential, and word line voltage according to an embodiment of the present disclosure. In this embodiment, during the first period T1 of the erase operation, the voltage value of the erase voltage VERA is increased to the target voltage value VT. For example, during the first period T1 of the erase operation, the voltage value of the erase voltage VERA is gradually increased from the initial voltage value Vini to the target voltage value VT. During the first period T1 of the erase operation, the voltage value of the word line voltage VWL is the first voltage value V1. The voltage value of the first voltage value V1 is equal to the initial voltage value Vini, but the present disclosure is not limited to this. When the voltage value of the erase voltage VERA reaches the target voltage value VT, the first period T1 ends and the second period T2 begins.

During a second period T2 following the first period T1 of the erase operation, the erase voltage VERA is at the target voltage VT, and the word line voltage VWL is increased from the first voltage V1 to the second voltage V2. In this embodiment, the word line voltage VWL is increased from the first voltage V1 to the second voltage V2 after a delay time td.

In this embodiment, the voltage difference Vch between the target voltage value VT and the first voltage value V1 can be determined based on the different designs or processes of the memory strings STR1-STRn. The erase bias loss LS is changed based on the design or process. The voltage difference between the first voltage value V1 and the second voltage value V2 is designed to be within the range of 0 volts to -6 volts. For example, the initial voltage value Vini and the first voltage value V1 are 0 volts. The target voltage value VT is 26 volts. The second voltage value V2 is higher than the first voltage value V1 and lower than or equal to 6 volts. More specifically, the voltage difference between the first voltage value V1 and the second voltage value V2 is designed to be in the range of -3 volts to -4 volts. Therefore, the second voltage value V2 is in the range of 3 volts to 4 volts.

In this embodiment, the first select signal SS1 begins to float at a first time point tp1. The voltage value of the first select signal SS1 begins to rise at the first time point tp1 as the voltage value of the erase voltage VERA increases. Therefore, after the first time point tp1, the voltage difference Vch1 between the voltage values of the erase voltage VERA and the first select signal SS1 remains constant. The voltage value of the second select signal SS2 begins to float at a second time point tp2. The voltage value of the second select signal SS2 begins to rise at the second time point tp2 as the voltage value of the erase voltage VERA increases. Therefore, after the second time point tp2, the voltage difference Vch2 between the voltage value of the erase voltage VERA and the voltage value of the second select signal SS2 is fixed. In addition, the voltage difference Vch1 is related to the voltage withstand capability of the string select transistor SST. The voltage difference Vch2 is related to the voltage withstand capability of the ground select transistor GST. For example, in the second period T2, the target voltage value VT is 23 volts. The voltage value of the first select signal SS1 is 16 volts. The voltage value of the second select signal SS2 is 7 volts. Therefore, the voltage difference Vch1 is 13 volts. The voltage difference Vch2 is 10 volts.

Please refer to Figures 1 and 6 , which are flowcharts illustrating an operating method according to an embodiment of the present disclosure. In this embodiment, operating method S100 is applicable to operating memory device 100. Operating method S100 includes steps S110 through S130. In step S110, during an erase operation, an erase voltage VERA is applied to a common source line CSL and at least one of bit lines BL<1> through BL<n>. During the erase operation, a word line voltage VWL is applied to memory cells in memory strings STR1 through STRn.

In step S120, during the first period T1 of the erase operation, the erase voltage VERA is raised to the target voltage VT. For example, during the first period T1 of the erase operation, the erase voltage VERA is gradually increased from the initial voltage Vini to the target voltage VT. At the start of the first period T1, the word line voltage VWL is at the first voltage V1.

In step S130, in a second period T2 after the first period T1 of the erase operation, the voltage value of the erase voltage VERA is the target voltage value VT, and the voltage value of the word line voltage VWL is increased from the first voltage value V1 to the second voltage value V2.

The detailed operations of steps S110 to S130 have been clearly described in the embodiments of FIG. 1 to FIG. 5 and will not be repeated here.

In summary, during the first period of an erase operation, the erase voltage is raised, and the word line voltage is at a first voltage. During a second period following the first period of the erase operation, the erase voltage is at a target voltage, and the word line voltage is raised from the first voltage to a second voltage. During the second period, the raised word line voltage raises the channel potential of at least one memory string. Therefore, the channel potential can be compensated during the second period. This reduces the erase bias loss between the erase voltage and the channel potential. Therefore, the present disclosure provides a stable and enhanced GIDL-assisted erase operation.

Although the present disclosure has been disclosed above with reference to the embodiments, they are not intended to limit the present disclosure. Anyone with ordinary skill in the art may make slight modifications and improvements without departing from the spirit and scope of the present disclosure. Therefore, the scope of protection of the present disclosure shall be determined by the scope of the attached patent application.

100: Memory device 110: Control circuit BL<1>~BL<n>: Bit lines CSL: Common source line GST: Ground select transistor LS: Erase bias loss MC1~MCm: Memory cells S100: Operation method S110~S130: Steps SS1: First select signal SS2: Second select signal SST: String select transistor STR1~STRn: Memory strings T1: First period T2: Second period td: Delay time tp1: First time point tp2: Second time point V1: First voltage value V2: Second voltage value Vch, Vch1, Vch2: Voltage difference VEB: Channel potential VERA: Erase voltage Vini: Initial voltage VT: Target voltage VWL: Word line voltage X, Y, Z: Direction

Figure 1 is a schematic diagram of a memory device according to an embodiment of the present disclosure. Figure 2 is a waveform diagram according to an embodiment of the present disclosure. Figure 3 is a waveform diagram of an erase voltage, a channel potential, and a word line voltage according to an embodiment of the present disclosure. Figure 4 is a waveform diagram according to an embodiment of the present disclosure. Figure 5 is a waveform diagram of an erase voltage, a channel potential, and a word line voltage according to an embodiment of the present disclosure. Figure 6 is a flow chart of an operating method according to an embodiment of the present disclosure.

100: Memory device

110: Control circuit

BL<1>~BL<n>: bit line

CSL: Common Source Line

GST: Ground Select Transistor

MC1~MCm: memory cells

SS1: First selection signal

SS2: Second selection signal

SST: string select transistor

STR1~STRn: Memory string

V1: First voltage value

V2: Second voltage value

VERA: Erase voltage

Vini: Initial voltage value

VT: Target voltage value

VWL: word line voltage

X, Y, Z: Direction

Claims (20)

A memory device includes: a common source line; at least one bit line; and at least one memory string, respectively coupled between the common source line and the at least one bit line. During an erase operation, an erase voltage is applied to at least one of the common source line and the at least one bit line, and a word line voltage is applied to a plurality of memory cells in the at least one memory string. During a first period of the erase operation, the erase voltage is raised to a target voltage and the word line voltage is at a first voltage. During a second period following the first period of the erase operation, the erase voltage is at the target voltage and the word line voltage is raised from the first voltage to a second voltage. The memory device of claim 1, wherein a voltage difference between the target voltage value and the first voltage value is in a range of 20 volts to 26 volts. The memory device of claim 1, wherein when entering the second period of the erase operation, the voltage value of the word line voltage is increased from the first voltage value to the second voltage value after a delay time. The memory device of claim 3, wherein the delay time length is greater than 0 seconds and less than 400 microseconds. The memory device of claim 1, wherein during the first period of the erase operation, the voltage value of the word line voltage is decreased from an initial voltage value to the first voltage value. The memory device of claim 1, wherein a voltage difference between the first voltage value and the second voltage value is in a range of 0 volts to -6 volts. The memory device of claim 1, wherein a voltage difference between the first voltage value and the second voltage value is in a range of -3 volts to -4 volts. The memory device of claim 1, wherein during the first period of the erase operation, the first voltage value is equal to an initial voltage value. The memory device as described in claim 1, wherein the first period of the erase operation further includes: a first selection signal applied to a string selection transistor begins to float at a first time point, wherein the string selection transistor is coupled between a first side memory cell among the memory cells of the at least one memory string and the at least one bit line, and a second selection signal applied to a ground selection transistor begins to float at a second time point later than the first time point, wherein the ground selection transistor is coupled between a second side memory cell among the memory cells of the at least one memory string and the common source line. In the memory device of claim 9, during the second period of the erase operation, a voltage value of the first selection signal is higher than a voltage value of the second selection signal. A memory device as described in claim 1, wherein: the common source line extends along a first direction, the at least one bit line extends along a second direction and is arranged along the first direction, the memory cells of the at least one memory string are arranged along a third direction, and the first direction, the second direction and the third direction are different from each other. A method for operating a memory device, wherein the memory device includes a common source line, at least one bit line, and at least one memory string, wherein the at least one memory string is coupled between the common source line and the at least one bit line, wherein the method includes: during an erase operation, applying an erase voltage to at least one of the common source line and the at least one bit line, and applying a word line voltage to The erase operation comprises: applying a voltage of the erase voltage to a target voltage value and applying a voltage of the word line voltage to the target voltage value; and applying a voltage of the erase voltage to the target voltage value and raising the voltage of the word line voltage from the first voltage value to a second voltage value in a second period after the first period of the erase operation. The operating method of claim 12, wherein a voltage difference between the target voltage value and the first voltage value is in a range of 20 volts to 26 volts. An operating method as described in claim 12, wherein the step of increasing the voltage value of the word line voltage from the first voltage value to the second voltage value includes: when entering the second period of the erase operation, increasing the voltage value of the word line voltage from the first voltage value to the second voltage value after a delay time. The operating method of claim 14, wherein the delay time length is greater than 0 seconds and less than 400 microseconds. The operating method as described in claim 12 further includes: during the first period of the erase operation, reducing the voltage value of the word line voltage from an initial voltage value to the first voltage value. The operating method of claim 12, wherein a voltage difference between the first voltage value and the second voltage value is in a range of 0 volts to -6 volts. The operating method of claim 12, wherein a voltage difference between the first voltage value and the second voltage value is in a range of -3 volts to -4 volts. The operating method of claim 12, wherein during the first period of the erase operation, the first voltage value is equal to an initial voltage value. An operating method as described in claim 12, wherein the first period of the erase operation further includes: a first selection signal being applied to a string selection transistor starting to float at a first time point, wherein the string selection transistor is coupled between a first side memory cell among the memory cells of the at least one memory string and the at least one bit line; and a second selection signal being applied to a ground selection transistor starting to float at a second time point later than the first time point, wherein the ground selection transistor is coupled between a second side memory cell among the memory cells of the at least one memory string and the common source line.